Aligned carbon nanotube–based electronics on glass wafer

Abstract

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by “head-to-head” comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)–based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a “90-nm” node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.

Carbon nanotube devices fabricated on glass wafer provide superior performance compared with silicon ones.

INTRODUCTION

Since its discovery, semiconducting carbon nanotube (CNT) has drawn much attention as an active channel material in field-effect transistors (FETs) due to its exceptional electrostatics from the ultrathin body and excellent electrical properties with high carrier mobility from ballistic transport (1–5). Through decades of development on CNT materials (4, 6–9), FET process (3, 10–12), and device structure (13–16), great efforts from the research community and industry have been paid to pursue CNT’s talent for surpassing conventional semiconductors. In the early days of individual CNT–based FETs, milestone progress (1, 3, 17, 18) has been made 10 times as energy-efficient (both gate-delay and energy-delay product) as conventional complementary metal oxide semiconductor (CMOS) FETs. Moreover, CNT-based transistors with gate lengths as short as 5 nm outperform silicon ones (3). Unfortunately, this superiority of CNTs over silicon only holds when normalized to a density of 125 CNTs/μm in the channel region, which calls for CNT materials to evolve from individual CNTs to array films.

In 2020, ideal materials (4) of aligned CNT (ACNT) arrays with high purity (s-CNT > 99.9999%) and suitable density (125 to 250 CNTs/μm) were developed for FETs and integrated circuits (ICs) (10, 11), resulting in the as-measured gate delay of ACNT-based circuits (4, 10) over that of silicon devices with a close gate length. However, this faster result is obtained at a higher supply voltage (4) of 2.6 V (silicon at 1.3 V), inducing higher power consumption, and the device’s off-state performance is measured by an ionic liquid gate (4), which is impractical for IC applications seeking further process improvements.

The latest breakthroughs involve optimizing the gate stack (10) and introducing an innovative full-contact scheme (11), helping the real performance of ACNT FETs better than their silicon counterparts in both on-state and off-state current density. The 90-nm CNT technology demonstrates superiority to the “45-nm” node silicon technology. However, these impressive advantages come at the cost of substantial gate-source voltage (V_gs) swing (2 V or wider), indicating a mismatch with the supply voltage (0.8 V of V_dd) and the need for higher V_dd with higher power consumption. For example, ACNT ring oscillators (ROs) require a higher supply voltage of 2.6 V (4) and even 3.8 V (10) to achieve higher oscillating frequencies. On the contrary, taking 45- to 180-nm nodes in silicon technology as an example, their V_dd for transistors and ROs are the same at 1 to 1.5 V.

In practical applications, especially for digital circuits, different voltages (V_gs, V_ds, and V_dd) of devices need to comply with well-defined constraints. As indicated in (18–20), V_gs and V_ds should have the same voltage range, i.e., from 0 V to V_dd of supply voltage. Therefore, on-state/off-state current (I_on/I_off) is defined at V_ds = V_dd and V_gs = V_dd/0 V. In addition, key device metrics of transconductance (g_m) and subthreshold swing (SS) are defined within the same voltage range. However, in the case of emerging nano-electronic transistors, where the threshold voltage (V_th) is not targeted and optimized, the V_gs swing would arbitrarily induce erroneous interpretation during benchmarking. Therefore, we should select (18, 21, 22) available V_ds values as the supply voltage V_dd from the transfer curves and normalize with the threshold voltage for the same V_gs range as the overdrive voltage (V_ov). Hence, a “head-to-head” comparison of comprehensive benchmarking metrics using this approach could evaluate the superiority of emerging CNTs fairly and effectively (23).

Inspired by silicon-on-insulator (SOI) technology (24, 25), which features high speed (20 to 25% faster for a given power consumption) and low power consumption (half to a third of the power of bulk Si counterparts) by mitigating latch-up effects, it is found that the performance of transistors could be further improved by the selection or optimization of substrates with better electrical properties. Furthermore, the preparation and assembly procedure (4, 6) for ACNT arrays is compatible (6) with any hydrophilic insulating substrates, like SOI technology, indicating an innovative and promising technological approach for the construction of ACNT-based transistors and ICs on the suitable substrate according to different application scenarios. Aiming at the simultaneous optimization of speed (on-state) and power (off-state) in a limited voltage range, from the substrate point of view, low-loss substrates could affect devices less to keep them fast and power efficient. To minimize losses from the substrates, small dielectric permittivity and low loss tangent are two key parameters that must be given priority during substrate selection. According to the substrate benchmarking results as shown in fig. S1 and table S1, it is believed that the glass wafer with the minimum ε_r and tan δ is a suitable one. The advantages of the glass wafer are multifaceted: (i) robust electrical isolation: high resistivity (up to 100 gigohm·cm) to suppress leakage currents and cross-talk, promoting power efficiency; (ii) minimized parasitic effects: ultralower dielectric permittivity (~3) and loss tangent (3.7 × 10⁻⁵) mitigate parasitic capacitance between circuits and substrate, improving performance at equivalent V_dd (or reducing power consumption at matched performance); (iii) economical scalability: low cost and availability with the large size for specific applications as large area electronics.

In this work, by developing a related process on low-loss glass wafer and upgrading the device structure for speed and power considerations, we report ACNT-based electronics on a glass wafer to pursue head-to-head superiority over silicon technology. Our developed ACNT FETs show better performance within a V_dd range of 1 V, outperforming previously reported ACNT FETs. In particular, a head-to-head comparison of a 250-nm gate length transistor with a 90-nm node silicon device is demonstrated, indicating an actual advantage of almost three to four generations, making previously reported potential (10, 11, 21) become a reality. In addition to DC performance, we also verify the circuit speed by ROs exhibiting a record gate delay of 9.86 ps into sub-10 ps, which is by far the fastest RO based on all nanomaterials and even better than silicon at a lower supply voltage. Furthermore, on the basis of the high-performance ACNT FETs, basic logic gates such as NAND, NOR, AND, and OR are successfully fabricated, indicating the potential of building a standard cell library for ICs.

RESULTS

Dense ACNT arrays with a density of 230 CNTs/μm are deposited directly onto a 4-inch glass wafer using the dimension-limited self-alignment (DLSA) method (4, 10, 11). The ACNTs on the glass wafer present a uniform and monolayer distribution, as shown in the scanning electron microscopy (SEM) image (Fig. 1A). Figure 1 (B and C) illustrates both a schematic representation and an SEM image of the top-gated ACNT FETs used in this work. On the basis of the previously reported process on silicon substrates, we develop all the fabrication processes on a glass wafer. Palladium (Pd) is used as the source/drain electrodes to form the ACNT-based p-type metal oxide semiconductor FET (MOSFET) by a doping-free process due to its ability to form an ohmic contact with CNTs, allowing for hole injection into the CNT valence band in a barrier-free manner (26, 27). Furthermore, our FETs adopt an atomic layer deposition (ALD)–grown HfO₂ film of only 5-nm thickness as the gate insulator for optimal gate control and a thick metal stack of titanium/gold (Ti/Au = 20/150 nm) as the gate electrode to minimize parasitic resistance. Here, we use the low-work-function metal Ti as the gate metal to fabricate enhancement-mode (E-mode) FETs by work-function engineering (10, 28) V_th with the lowest off-state current close to V_gs = 0 V (fig. S2). Different from previously reported ACNT-based FETs (4, 10, 11, 13, 29), the structure and process are adapted for speed and power considerations. A gate structure with air spacers (6, 30) of about 30-nm width is chosen for parasitic reduction (speed) and reverse tunneling suppression (power). We also upgrade the device structure to lower the parasitic effects by adopting thinner contacts with the thicker gate inducing less overlapping. We reduce the thickness of the source/drain electrodes to 30 nm, still ensuring efficient p-type ohmic contact, while the increase in resistance due to thinning could be compensated by using thicker external metal wires. A detailed description of the entire fabrication process is elaborated in fig. S3A and in Materials and Methods.

Fig. 1. Characterization of ACNT arrays and ACNT FETs on the glass wafer.

(A) Optical photograph of a 4-inch glass wafer covered with uniform ACNTs, and SEM image of ACNTs deposited on the glass wafer. Scale bar, 500 nm. (B) 3D schematic device structure of an ACNT FET with air spacers. (C) False-colored SEM image of the channel region of a 250-nm-L_g ACNT FET. Scale bar, 250 nm. (D) Transfer curves and transconductance of a 250-nm-L_g FET at a series of V_ds. (E) Output characteristics of a 250-nm-L_g FET with V_gs varying from −2 to 0 V with a step of 0.2 V. (F) Head-to-head comparison of the transfer characteristics between our 250-nm-L_g ACNT FET and a 90-nm node silicon high-performance standard MOSFET (35) in a picture.

Typical transfer curves with corresponding transconductance (g_m) and output curves for our p-type E-mode FETs with a gate length of 250 nm are shown in Fig. 1 (D and E). The maximum on-state current density (I_max) is over 1 mA/μm at the carrier density near the source (20) of 1.44 × 10¹³ cm⁻², while the peak transconductance (g_m) reaches nearly 1.3 mS/μm at a V_ds of −1.0 V. Besides on-state performance, the typical FET maintains a subthreshold slope (SS) of less than 100 mV/dec over a current range spanning ~3 orders of magnitude (fig. S4A), accompanied by a minimal leakage current of 100 pA/μm. Higher g_m/I_on ratio and low SS indicate a good on/off transition and hence gate control. We also show statistical results of our 250-nm-L_g FETs (fig. S4, B to F) and their scaling-down performance (fig. S4, G and H). Although this variation characterization may be insufficient, it demonstrates that the superiority of CNT FETs, as shown in Fig. 2, is not obtained by performance fluctuations. Limited by the imperfections of ACNT channel materials and fabrication processes, further FET downsizing tends to cause larger variations, calling for extensive research to improve the uniformity of both the ACNT materials and ACNT FETs.

Fig. 2. Benchmarking of our ACNT FETs with previously reported ACNT FETs and silicon MOSFETs.

(A and B) Comparisons of I_on-L_g (A) and g_m-L_g (B) dependence of our FETs with other ACNT FETs (4, 6–8, 10–12, 32) and silicon MOSFETs (from 250- to 45-nm nodes) (33–37). Note that I_on values are extracted at V_ds = V_dd and V_gs = V_th − 2/3V_dd (p-type) rather than the maximum current. (C and D) Benchmarking of I_on-V_dd (C) and g_m-V_dd (D) dependence of our FETs with other ACNT FETs and silicon MOSFETs. The better corner is located in the upper left. (E and F) Comprehensive comparisons of on-state and off-state performance including I_on versus I_off (E) and SS versus g_m (F). The better corner is located in the bottom right.

It seems that the typically demonstrated ACNT-based FET on the glass wafer could not outperform state-of-the-art CNT FETs (11), especially in terms of current density. However, the results of Fig. 1 (D and E) could balance almost all the key DC metrics from the on-state (I_on) to the off-state (I_off) with their transition (g_m and SS) in the same well-defined V_ds and V_gs voltage range as V_dd, which we replot in Fig. 1F, compared with the performance of 90-nm node silicon under the constraint V_gs = V_ds = V_dd = 1 V marked by a gray square according to Intel’s guidelines (18, 21, 22). It is obvious and direct to find out that the two curves of ACNT and silicon are almost identical. The current density and transconductance are 0.67 mA/μm and 1.3 mS/μm, respectively, indicating a g_m/I_on ratio of almost 2, which is very close to that of silicon. Not only is our ACNT FET’s absolute performance of the on-state current density slightly better than that of silicon with identical off-state current density but also the transition metrics of transconductance are better with comparable SS. Notably, the supply voltage V_dd for the 90-nm node silicon device is 1.2 V, which is higher than that of our ACNT transistors. Therefore, the power consumption would be lower at a lower supply voltage, or the current density would be better at the same supply voltage. At least, our 250-nm gate length transistor is as good as the 90-nm node silicon transistor in Fig. 1F, showing the three-generation superiority of ACNT over silicon technology, which is close to the four- to five-generation advantage (21) obtained by calculation using only the gate delay parameter in 2009. This demonstrated superiority over silicon is achieved from measurements without any theoretical speculation, calculations (3, 18, 21), normalizations (3, 8, 12, 31), de-embedding (6), or other special operations (4) not applicable in ICs.

We further benchmark our FETs with other high-performance ACNT FETs (4, 6–8, 10–12, 32) and silicon MOSFETs (33–37) in Fig. 2. The benchmark metrics include on-state performance (I_on and g_m) and their scaling characteristics with feature size (L_g) and supply voltage (V_dd), absolute on-state with off-state performance (I_on versus I_off), and transition on-state with off-state performance (g_m versus SS), collectively forming a comprehensive comparison framework. In addition, for clarity, we summarized all the parameters in tables S2 and S3 with benchmarking between current density and carrier density near the source as shown in fig. S5A and indicated in (20). In most previously reported CNT FETs, I_on and I_off denote the maximum and minimum currents over a wide V_gs range (I_max versus I_min instead of I_on versus I_off), which is less applicable to ICs. Therefore, as indicated (18, 21, 22) in Introduction, for a fair evaluation, we extract I_on and I_off at the supply voltage with the same range of V_gs (as shown by the shaded box in fig. S6).

The on-state performance (I_on and g_m) of our devices is substantially promoted by scaling the gate length, as shown in Fig. 2 (A and B). ACNT-based FETs in this work have the best on-state performance among all previously reported ACNT FETs. As for current density (transconductance), the best (worst) result in this work with 1-V supply from our 130-nm-L_g (250-nm-L_g) FET is even better than the 45-nm node silicon device, indicating still about a three (five)–generation advantage consistent with the result in Fig. 1F. Moreover, the on-state performance advantage over silicon is obtained at a lower supply voltage (1 versus 1.2 V), as shown in Fig. 2 (C and D), which also shows better supply scaling properties even down to around 0.4 V. Even in the well-defined voltage range, all the on-state performance of ACNT FETs in Fig. 2 (A to D) exceeds that of silicon by three to five generations, still with a power consumption advantage because of the lower supply voltage.

Besides the on-state performance, the off-state metrics (I_off and SS) that directly affect the power dissipation are also of great concern (38) and should be comprehensively benchmarked by groups of I_on versus I_off and SS versus g_m, as shown in Fig. 2 (E and F). In a well-defined voltage range, previously reported representative ACNT-based FETs (4, 10, 11) suffer from larger I_off and SS (see fig. S7). Notably, our FETs fabricated on the glass wafer have lower off-state current densities and SS at the same on-state current densities and better transconductances. Previous work (10) has a lower SS with close g_m than our FETs in the lower left corner of Fig. 2F; however, the supply voltage is too small, less than 0.4 V, which would not be applicable in ICs (14, 39). Compared with silicon, from a statistical result point of view, the I_on versus I_off (SS versus g_m) of our 250-nm-L_g FETs are between those of 130- and 90-nm node silicon MOSFETs (having slightly better g_m but worse SS than 90-nm node silicon), still indicating a two- to three-generation advantage, consistent with the result in Fig. 1F. However, we have to admit that, as the gate length scales down, the on-state performance could still maintain the two- to three-generation advantage, but the off-state performance of I_off and SS degrades notably, mainly due to the poor gate control induced by the relatively high interface trap density, which is key for further improvement in the future.

DC performance superiority alone would not ensure an actual (as-measured) speed advantage, which is also affected by parasitics from device structures and processes developed on specific substrates. To completely compare ACNT with silicon beyond only DC performance, standard circuit cells of ROs for speed characterization with the same device configuration should be fabricated and verified. Inverters made of pure p-type FETs for simplicity, as shown in Fig. 3A, which are the building blocks of ROs, are attached in a chain, and the output of the last stage inverter is looped back to the first with an additional inverter connected as a load to buffer the oscillating output signal. Benefiting from the low-loss glass substrate, a more compact layout could be designed, while the parasitic effects are less pronounced in our CNT ROs. The voltage transfer characteristics (VTCs) of a typical inverter are presented in Fig. 3B, with the supply voltage scaled down from 1 to 0.4 V within the range of transistors’ supply voltage. Despite small losses at high voltage levels (due to the load transistor in a pure p-type design), our inverter with a 1-V supply voltage exhibits correct functionality, along with a low-level noise margin (NM_L) of 0.41 V, a high-level noise margin (NM_H) of 0.22 V, and a voltage gain of ~12 (detailed in fig. S8).

Fig. 3. Characteristics of ACNT inverters and ROs.

(A) Circuit diagram and false-colored SEM image of an inverter consisting of pure p-type FETs. Scale bar, 4 μm. (B) VTC curve of our fabricated inverter under supply voltage ranging from 0.4 to 1.0 V. (C) 3D schematic and corresponding false-colored SEM image of the nine-stage RO on the glass substrate. Scale bar, 4 μm. (D) Circuit diagram of the nine-stage RO, consisting of nine p-type inverters in a series, followed by an extra inverter as the buffer stage. (E) Output power spectrum of a typical nine-stage RO. (F) Comparison of the gate delay versus supply voltage between our champion ROs and other reported ROs based on CNTs (4, 10, 29, 30) and silicon (33).

Figure 3 (C and D) shows the SEM image and schematic with a circuit diagram of our typical nine-stage RO. The output spectrum of our champion nine-stage RO is depicted in Fig. 3E. The oscillating frequency increases as the supply voltage scales up and reaches a peak value of 5.63 GHz, corresponding to a record stage delay of only 9.86 ps at V_dd 1.8 V. Typically, ACNT ROs fabricated on silicon wafers require a higher V_dd to oscillate and reach optimal performance, mainly due to (i) poorly optimized transistors unable to work in a well-defined voltage range and (ii) parasitics (dielectric permittivity) and energy loss (loss tangent) from the substrate, especially at higher frequencies. Thus, combined with the introduction of the corresponding parasitic reduction process/structure and the usage of a low-loss glass substrate, we successfully scale down the supply voltage to 1.4 V with a 9.95-ps gate delay, still satisfying less than 10 ps compared to ROs based on silicon (33), CNTs (4, 10, 29, 30, 40), and other nanomaterials (41, 42), as shown in Fig. 3F and fig. S9, indicating a speed advantage over other reported ROs even at lower supply voltages. However, despite the advantages in speed and power, the uniformity of our ACNT-based ROs still needs to be further improved by optimizing the uniformity of ACNT materials and processes, especially as the size of FETs decreases.

In addition to the performance verification, we further demonstrate digital circuits on the glass substrate. A series of logic gates, without loss of generality, are designed and fabricated successfully as shown in Fig. 4. Four typical kinds of gates such as NAND (Fig. 4, A to C), NOR (Fig 4, D to F), AND (Fig. 4, G to I), and OR (Fig. 4, J to L) with respective circuit diagrams and SEM images are measured and exhibit correct logic functionality. In principle, ACNT-based ICs on glass wafers could be realized by a standard cell library built from basic gates.

Fig. 4. Demonstration of logic gates constructed by p-type ACNT FETs on the glass wafer.

Circuit diagram (A, D, G, and J), false-colored SEM image (scale bar, 4 μm) (B, E, H, and K), and its functional measurements (C, F, I, and L) of a/an NAND, NOR, AND, OR gate.

DISCUSSION

We report ACNT-based electronics on a glass wafer, providing a suitable platform for device performance boosts. By developing a related process on glass wafer and upgrading the device structure for speed and power considerations, based on high-quality ACNT arrays, we fabricate 250-nm gate length FETs with a g_m/I_on ratio of as high as 2, approaching that of silicon, along with SS less than 100 mV/dec and an off-state current density of 100 pA/μm. Our ACNT-based FETs could balance on-state and off-state performance simultaneously while still within the supply voltage range that has almost identical transfer curves with 90-nm node silicon devices, directly indicating a three- to four-generation superiority without any calculations, normalizations, or other special operations. According to the benchmarking results, we find that the on-state performance (I_on and g_m) of ACNT-based FETs also has a gate length and supply voltage scaling advantage, especially in transconductance, with even five-generation superiority over the 45-nm node silicon devices. Combined with the introduction of a corresponding parasitic reduction process/structure and superior DC performance, the record as-measured gate delay of 9.86 to 9.95 ps into sub-10 ps at 1.8- to 1.4-V supply voltage is achieved, surpassing all other nanomaterials and even silicon technology with lower supply voltages. Furthermore, we successfully develop basic logic gates such as NAND, NOR, AND, and OR, which provide the basis of building a standard cell library for ICs.

The superiority of ACNT-based FETs over silicon devices has proven that ACNT-based electronics on the glass wafer would be a promising solution for further development in the future. This work also proposes an approach to enhance the performance of CNT devices, suggesting the possibility of more effective substrates or platforms for further enhancement. However, there are still several challenges that remain to be solved before the application of digital ICs. For example, n-type FETs with matched performance need to be developed to build CMOS architecture on glass. To date, the performance of ACNT-based n-type FETs still suffers from some engineering challenges, mainly due to the poor contact quality between low-work-function metal and dense CNTs (43). In addition, the performance advantage of our FETs lies in the relatively long gate length FETs, which only present performance equivalent to silicon devices at the 90-nm node. If the gate length is further scaled down for better performance, the results show degraded off-state performance due to poor gate control induced by relatively high interface trap density and exhibit large variations due to imperfect materials and fabrication processes. At this current stage, despite the superiority over Si FETs demonstrated in our work, CNT technology is so far not mature so that integration with mainstream silicon CMOS technology and more research can promote CNT technology as an applicable technology to meet the scalable contemporary applications in the future.

MATERIALS AND METHODS

Preparation of ACNT arrays by DLSA method

The main steps in the preparation of CNT arrays by the DLSA method are described as follows.

1) Preparation of the high-purity semiconducting CNT solution. The arc-discharged CNT powder (purchased from Carbon Solution Inc.) and poly[9-(1-octylonoyl)-9H-carbazole-2,7-diyl] (PCz) are dissolved together in 500 ml of toluene. The mixed solution is dispersed with a 7-mm probe tip for 30 min at 600 W (Sonics VCX-800), followed by 2 hours of 50,000g centrifugation (Sorvall LYNX6000, Thermo Fisher Scientific). Then, a dynamic liquid phase filtration process is carried out on the PCz-wrapped CNT solution, followed by rinsing off in 1,4-epoxybutane [tetrahydrofuran (THF)]. The filtered PCz-wrapped CNTs are redispered in 1,1,2-trichloroethane solvent for 5 min at 600 W (Sonics VCX-800). The above dispersion and centrifugation processes are repeated twice to obtain a high-purity CNT solution.

2) Assembly of CNT arrays onto the wafer. A 4-inch wafer is first directly and quickly inserted into the high-purity CNT 1,1,2-trichloroethane solution by a dip-coating mechanical apparatus. It is crucial that the PCz-dispersed CNTs are difficult to spontaneously attach to the wafer by static deposition, which is a prerequisite for the realization of the DLSA. Then, 40 μl of C₄H₈O₂ was dropped into the CNT solution close to the wafer. Because of the differences in density, C₄H₈O₂ will be located at the upper liquid level and will quickly disperse, forming a layer around the wafer. The possible formation of hydrogen bonds between the N atoms in the PCz molecules and the H atoms of the hydroxyl groups in C₄H₈O₂ allows the PCz-wrapped CNTs to migrate from the three-dimensional (3D) disorder in the lower solvent to the surface region and become confined to the 2D interface between C₄H₈O₂ and 1,1,2-trichloroethane solution. The wafer is withdrawn at a speed of 10 μm/s. After 3 hours, PCz-wrapped CNTs confined in the 2D interface will be assembled onto the wafer along the 1D contact line between the bilayer and the wafer surface due to the strong affinity of C₄H₈O₂ and the wafer. The ACNT films are repeatedly cleaned by toluene, THF, and N,N-dimethylformamide for 20 min for each solvent. Last, the as-deposited wafer is baked at 180°C for 30 min. During the whole aligning process, the CNT-PCz system undergoes a transition from 3D to 2D degrees of freedom, and then from 2D to 1D degrees of freedom. This transformative process gives rise to the name DLSA.

Polymer removal by annealing and yttrium oxide coating and decoating process

To remove the polymer wrapping around the CNTs, the glass wafer covered by ACNTs is first placed in a tube furnace (Thermo Fisher Scientific Linberg/Blue M MoldathERM 1100°C) and annealed at 350°C for 1 hour in an argon-hydrogen (Ar-H₂) atmosphere. During the annealing process, the N₂ and H₂ flow rates are 40 and 5 standard cubic centimeters per minute (sccm), respectively. Owing to the stronger electrostatic force between yttrium and polymers than that between polymers and CNTs, we then implement the yttrium oxide coating (YOCD) process to remove the residual polymer residue after annealing to some extent. YOCD consists of the following two steps: (i) deposition of a 10-nm yttrium film by electron beam evaporation (EBE) on ACNTs, followed by an oxidation process on a hot plate at 250°C for 30 min. (ii) Yttrium oxide is then eliminated by immersing the sample in a dilute hydrochloric acid solution (with a volume ratio of HCl to H₂O = 1:25).

Fabrication process of top-gated ACNT FETs and ICs

The manufacturing steps for ICs are similar to those for ACNT FETs. These processes involve iterative layers of patterning, deposition, and etching, including electron beam lithography (EBL) to pattern specific designs, etching to remove unwanted residues, and film deposition, including EBE and ALD, to form materials serving as contacts, metal wires, and gate insulators. Note that fabricating devices and circuits on nontraditional substrates, such as glass in our work, requires customized processes. For example, the distinct properties of glass wafers (surface roughness, chemical composition, optical properties, etc.) affect specific process parameters (processing temperature, exposure dose, film thickness, etc.). The difference lies in the complexity of the interconnection wires in ICs, so overexposed poly(methyl methacrylate) (PMMA) is introduced as a jumper between the upper and lower metal wires.

Top-gated ACNT FETs

The detailed fabrication process is depicted in fig. S3A. (i) Alignment marks (Ti/Au = 5/90 nm) are initially patterned by EBL, followed by the deposition of a Ti/Au = 5/90 nm metal layer using EBE. (ii) The active channel regions are then defined using EBL, and a reactive ion etch (RIE) process is used to etch unwanted CNTs. Pd thin films (30 nm) are patterned by EBL and deposited by EBE as source/drain contacts, forming good p-type ohmic contacts with ACNTs. (iii) A bilayer of Ti/Au films (5/90 nm) is introduced to form the external metal wires, compensating for the increase in resistance caused by the thin contact electrodes. (iv) The gate insulator is first patterned by EBL, followed by the deposition of HfO₂ (5 nm) by a 90°C ALD process. (v) The gate metal, along with other connecting wires and probing pads (Ti/Au = 20/150 nm), is finally patterned and deposited. Note that the Ti metal used here is to adjust V_th to the negative half axis of V_gs.

ACNT ICs

The detailed fabrication process is depicted in fig. S3B. (i) Marks (Ti/Au = 5/90 nm) for lithography alignment are first patterned and deposited by EBL and EBE. (ii) Unwanted CNTs are removed through RIE, followed by a standard lift-off process. (iii) A thin Pd film (30 nm) is deposited by EBE as contact electrodes. (iv) A 90°C ALD process is carried out to grow a 6-nm HfO₂ layer in the channel region as a high-k oxide dielectric layer. (v) Lower metal wires, consisting of Ti/Au stacked films (5/90 nm), are subsequently deposited to connect different adjacent FETs in the circuits. (vi) Overexposed PMMA (200 K) with a dose of 20,000 μC/cm² is patterned by EBL to electrically isolate the lower metal wires from the following upper metal wires. (vii) Ti/Au stacked films of 20/150 nm are finally deposited to form the gate electrodes, upper metal wires, and probing pads.

The fabrication method described above is feasible when considering CNT technology as a separate technology. When it is necessary to consider heterogeneous integration with silicon CMOS technology, metal Pd is not compatible, but there are some methods to solve this problem. (i) For simple CNT devices, they could be integrated above the top interconnect layer after finishing the silicon CMOS wafer and out of the foundry, i.e., by monolithic (sequential) integration to avoid the incompatibility issue. (ii) When it comes to complex CNT circuits and modules, co-fabrication of CNT electronics and silicon circuits in the same foundry is necessary. Switching to alternative contact metals like Pt or compatible alloys with silicon CMOS as contacts for CNT FETs is feasible. (iii) We can also use state-of-the-art packaging technology to realize heterogeneous integration. The CNT wafer and Si CMOS wafer with parallel fabrication can be flipped and bonded to construct the integrated 2.5D IC. This allows for the independent fabrication of CNT chips outside the CMOS foundry, free from the influence of Si CMOS chips or the foundry.

Measurement and characterization of FETs and ICs

Top-gated ACNT FETs

ACNT FETs are measured using a probe station (Cascade Summit 11000) combined with a semiconductor analyzer (Keithley 4200) to provide the necessary supply voltage (V_dd) and ground (GND) levels.

ACNT ICs

The probe station (Cascade Summit 11000) and the semiconductor analyzer (Keithley 4200) are also used to supply V_dd and GND for RO and basic logic gates. For ROs that do not require any input signals, a spectrum analyzer (Agilent N9020A) is used to capture the output spectrum. For basic logic gates that require two input signals, a signal generator (Agilent 81150A) is used to generate the input signals. The corresponding output waveforms are displayed on an oscilloscope (Agilent DSO7054A), and the corresponding currents during operation are measured by Keithley 4200.

Supplementary Materials

This PDF file includes:

Notes S1 to S9

Figs. S1 to S9

Tables S1 to S4

References