A Low-Noise Low-Power 0.001Hz–1kHz Neural Recording System-on-Chip with Sample-Level Duty-Cycling

Abstract

Advances in brain-machine interfaces and wearable biomedical sensors for healthcare and human-computer interactions call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Existing integrated wearable solutions for minimally invasive biopotential recordings are limited in detection range and accuracy due to trade-offs in bandwidth, noise, input impedance, and power consumption. This article presents a 16-channel wide-band ultra-low-noise neural recording system-on-chip (SoC) fabricated in 65nm CMOS for chronic use in mobile healthcare settings that spans a bandwidth of 0.001 Hz to 1 kHz through a featured sample-level duty-cycling (SLDC) mode. Each recording channel is implemented by a delta-sigma analog-to-digital converter (ADC) achieving 1.0 μV_rms input-referred noise over 1Hz–1kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode. In SLDC mode, the power supply is duty-cycled while maintaining consistently low input-referred noise levels at ultra-low frequencies (1.1μV_rms over 0.001Hz–1Hz) and 435 MΩ input impedance. The functionalities of the proposed SoC are validated with two human electrophysiology applications: recording low-amplitude electroencephalogram (EEG) through electrodes fixated on the forehead to monitor brain waves, and ultraslow-wave electrogastrogram (EGG) through electrodes fixated on the abdomen to monitor digestion.

I. INTRODUCTION

NOVEL wearable diagnostics and brain-machine interface devices are exponentially growing for assessing and measuring patient health and wellness [1]–[3]. Such innovations are important to monitor the patient’s key bio-markers needed to make subject-specific diagnoses outside the clinical setting and in the patient’s own environment. However, in order to make wearable and brain-machine interface devices truly user-centric and minimally obtrusive to day-to-day life, low-power high-precision recording systems are necessary to reduce the form factor and enable long-term usage of wearable devices and systems [4].

Additionally, compared to the widespread use of electrocardiography (ECG), long-term monitoring of electroencephalogram (EEG), electrooculogram (EOG), and electrogastrogram (EGG) biopotentials have not been explored and applied as extensively due to their small signal amplitudes, typically several hundreds of μV [5]–[9]. Such electrophysiological signals can further expand technologies in brain-computer interfaces and provide a wealth of information about patient health and wellness. The biopotential amplitudes vs. frequency resolutions are summarized in Fig. 1 (a). In particular, the EGG bandwidth is in the ultra-low frequency range of 0.033 to 0.066 Hz [10], [11], and can be as low as 0.017 Hz, as high as 0.17 Hz when there are abnormal gastric myoelectrical activities [12]. The bandwidth of interest for several other electrophysiological signals also starts from DC [6], [13]. However, most of the state-of-the-art electrophysiological interfaces focus on the regular frequency range that is 1 Hz to several kHz bandwidth [14]–[16]. Therefore, there is a need for a recording system to have a low noise floor in the low-frequency region.

Fig. 1.

(a) Biopotential amplitudes vs. frequency resolutions, (b) Overview of 16-channel wide-band low-noise neural recording system-on-chip.

Low-frequency biopotential recording applications also involve long measurement times. For EGG measurement, the minimum recording time to capture useful diagnostic data is roughly 30–60 min [10], [13]. Therefore, the consideration for low power consumption is paramount in long-duration diagnostic measurements or daily wearable monitoring devices. However, it is well-known that high circuit performance and low power consumption is a fundamental trade-off existing in all electronics. In order to balance this trade-off, an adaptive recording system is necessary to meet the requirements of various biopotential applications.

Adaptable systems that need to situationally rebalance the power-performance trade-offs generally employ one of these two strategies: 1) adjusting the supply voltage or bias current, 2) changing the recording sampling frequency. In the first case, lowering the supply voltage or reducing the current applied affects the transistors’ regions of operation, potentially causing unexpected malfunction. Additionally, this voltage scaling technique can significantly reduce channel-to-channel uniformity caused by magnified process variations.

To overcome the drawbacks of the aforementioned strategies, we propose a 16-channel ultra-low-noise ADC with the capability of two operation modes: continuous operation mode and sample-level duty-cycling (SLDC) operation mode. The continuous operation mode is intended for recording neural signals at a frequency range from 1 Hz to 1 kHz. Under this mode, the power supply is continuous for the entire duration of the measurement. Flicker noise is significantly reduced in this mode by the chopping technique. Additionally, the thermal noise floor is maintained at a low level by using a low-noise operational transconductance amplifier (OTA) design. This low-noise feature makes it a good candidate for small amplitude biopotential recording, such as EEG. The DC operating points of the OTA are defined by the short-time reset at the beginning of the system power-on, which enables fast system settling compared with the pseudo resistors OTA bias method. Therefore, the SLDC operation mode is introduced to scale down power consumption for recording biopotentials at less than 1-Hz bandwidth. In this mode, the correlated double sampling (CDS) technique helps to remove the low-frequency noise and maintains a higher input impedance compared with the chopping technique to improve signal integrity. Benefiting from the low-power feature, SLDC operation mode is suitable for relatively long-term narrow bandwidth biopotential measurements, and it has been functionally verified by EGG recordings.

This paper is organized as follows. Section II presents details of hardware implementation of the proposed neural recording SoC, including the system overview and the circuit architecture. In Section III, the operation protocol, the measurement methods of the benchtop and in vivo validations are described. The testing results and discussion are presented in Section IV, and Section V concludes the paper with a comprehensive summary.

II. HARDWARE IMPLEMENTATION

A. System Overview

The overview of the 16-channel neural-recording system-on-chip is shown in Fig. 1. Sixteen independent differential channels record biopotentials in parallel from 16 electrodes VIN0–VIN15 with respect to a reference voltage, VREF. A global analog bias generator is shared by all channels to keep the analog front-ends working properly. The digital control circuits are implemented to realize correct operation with different phase control orders from the serial peripheral interface (SPI). The SPI block interfaces the 16 channels to the data acquisition system. Thus, the data from all 16 channels can be time-multiplexed out with channel selection sweeps. The power supply VDD can be configured to select between continuous operation mode and SLDC operation mode. In the continuous operation mode, the VDD supply is a constant DC provided externally. For the SLDC operation mode, a field-programmable gate array (FPGA) programs the VDD supply duty cycle for ultra-low frequency biopotential recording, and one sample is acquired for each VDD power-on duty cycle. The single VDD supply provides power to the whole neural recording system (except for driven signal from the external control system), including 16 recording channels, a bias generator, digital control circuits, and the on-chip SPI. This configuration makes it possible to scale down power consumption through the SLDC mode while maintaining all the circuitry works at the same condition as the continuous operation mode during the power-on time period.

B. Circuit Architecture

Fig. 2 shows the circuit diagram of the delta-sigma ADC in each channel at the 16-channel neural recording system. Delta-sigma ADC has low-noise and low-power features. Although the recording bandwidth is relatively small due to the intrinsic oversampling operation method, most of the biopotentials are below 10 kHz, which makes the delta-sigma modulator a preferred ADC topology for biopotential recordings. The ADC works as follows: firstly, the RST switches connect the OTA’s inputs and outputs to make it have appropriate DC operating points, and also reset the input to V_CDS to enable CDS to remove low-frequency noise at the SLDC operation mode. After the reset phase, the differential biopotential signal is chopped by 2 alternating control signals, Φ1 and Φ2, and capacitively coupled to the OTA through the input capacitor C_in (4.4 pF). Consequently, the input signal is down-modulated by another pair of chopping switches and integrated by the following integrator. The outputs of the integrator are digitized by a comparator with feedback through a capacitive digital-to-analog converter (C-DAC) to the ADC input stage. A 1-b DAC is utilized because it is simple, compact, and inherently linear. Although it limits the dynamic range (DR), the DAC capacitors are carefully sized to meet the DR requirements for biopotential recordings. The DAC consists of two identical capacitors $C_{fb}$ (22 fF) to realize 3-state feedback: $V_{fb}^{+},V_{fb}^{-}$, and $\frac{1}{2}\left(V_{fb}^{+}-V_{fb}^{-}\right)$. The first two states are alternated during regular operation based on feedback from the comparator, whereas the third state is used during the reset phase to have the OTA inputs stay neutral. The digital output D of this ADC is buffered and passed to the global SPI with the channel selection signal SEL. The SPI interfaces with the FPGA on the testing board. The data is acquired by the PC through wire connection between the PC and FPGA. Sixteen channels are able to record biopotentials simultaneously and data can be time-multiplexed out in real time with digital control circuits.

Fig. 2.

ADC architecture of each channel and the interface with off-chip data acquisition system.

To reduce the input-referred noise while optimizing power consumption, the OTA is implemented as a current-reuse architecture as shown in Fig. 3(a), and a common-mode feedback circuit is designed to stabilize the fully-differential OTA as shown in Fig. 3(b). To keep the analog-front end at a low noise level, the OTA consumes most of the system power to reduce the thermal noise and is also sized properly to suppress the flicker noise. An active integrator is used in this design to suppress parasitic capacitance effects on the integration performance, by benefiting from the Miller Effect. Additionally, the schematic of the dynamic comparator is shown in Fig. 3(c). The comparator is built with the StrongARM latch topology to eliminate static power, get rail-to-rail output, and reduce the input-referred offset.

Fig. 3.

Schematics of core circuit implementation. (a) Current-reuse transconductance amplifier, (b) Common-mode feedback circuits for the amplifier, (c) StrongARM dynamic comparator.

III. MEASUREMENT METHODS

A. Operation Protocol

This neural recording system-on-chip is capable of operating at two modes: continuous operation mode and SLDC operation mode. The timing diagram in continuous operation mode is shown as Fig. 4: VDD continuously provides a power supply for the system. RST switches are turned on at the beginning of each recording period to make sure the OTA operates at proper DC operating points. The time period that RST switches are off is defined as recording time. Chopping signals Φ1 and Φ2 are alternatively turned on during the recording time, while a fast clock triggers the comparator that provides the sampled output. A comparator sampling frequency of 5 MHz and a chopping frequency of 10 kHz are chosen as proof-of-principle in this work to accommodate a typical 1 kHz signal bandwidth for biopotential signals of interest at an oversampling ratio (OSR) of 2,500.

Fig. 4.

Timing waveforms during the continuous operation mode: power supply, periodic reset, chopping signals, and sampling clock.

When the signal of interest lies in an ultra-low frequency range, the SLDC mode is enabled to save power by only sampling the input signal at a small fraction t of the total period (N + 1)t where the N and t are adjustable according to applications as shown in Fig. 5. The duty-cycling supply is controlled externally by FPGA programming. The power-on period length t should be sufficiently long to collect enough data points to meet desired accuracy for each sample, while the overall sampling frequency 1/((N + 1)t) should be sufficiently fast to meet OSR requirements. At the starting of each slow period when VDD is powered up, the RST signal will clean the residues left from the previous period and set the initial condition for each node. After the RST is released, the choppers are enabled at the chopping frequency same as continuous operation mode if needed for applications, and the sampling clock signal f_clk is also enabled during that time period. With a 5 MHz sampling frequency, 50 μs RST duration, a power-on period of t = 850 μs, and a power-off period of Nt = 49.15 ms, the sample-level duty-cycle switched-supply mode achieves a power saving of 98.4% compared with the continuous supply operation mode.

Fig. 5.

Timing waveforms during the SLDC operation mode: pulsed power supply, periodic reset, chopping signals, and intermittent sampling clock.

B. Electrical Evaluation

The proposed neural recording system was fabricated on TSMC 65-nm standard CMOS process, spanning a total area of 1mm². Fig. 6 shows the micrograph of the integrated circuit (IC) and the layout area breakdown for each channel. The IC includes 16 channels, peripheral shared blocks, and I/O pads, and each channel occupies 0.017 mm².

Fig. 6.

Chip micrograph and layout channel area breakdown.

Benchtop characterization of this recording system was performed as shown in Fig. 7. The neural recording SoC is on a testing board which sits an FPGA to acquire data and send it to the computer for processing. A function generator with a source impedance of 50 Ω is used to feed the SoC inputs with sinusoidal waves and sweep input amplitudes and frequencies. A source meter provides the VDD power and simultaneously measures the power consumption of the chip. An oscilloscope and a DC power supply are for function verification purpose. At the continuous operation mode, the VDD is a 1-V constant voltage supply. The chopping frequency is 10 kHz and the RST reset phase is 50 μs. In the validation testing example for the SLDC mode, t is set to 850 μs including the RST reset phase of 50 μs, and N × t is 49.15 ms.

Fig. 7.

Testbench setup for the SoC electrical evaluation.

C. EEG Validation

In order to double-validate the recording functionality of the continuous operation mode, two on-body EEG recordings were measured simultaneously: auditory steady-state response (ASSR) and alpha modulation. ASSR is an auditory evoked potential of the brain in response to a high-repetitive auditory stimulus. In clinical applications, ASSR is used to assess a subject’s hearing sensitivity to certain frequencies, creating subject-specific audiograms to evaluate hearing loss. Such tests are valuable especially for infants and non-responsive patients because it is capable of directly quantifying hearing sensitivity from the body rather than requiring the subject to partake in a behavioral test [20]. Alpha modulation measures the brain oscillation frequency of the alpha band which is between 8–12 Hz. This biomarker is known to be associated with a subject’s alertness, peacefulness, readiness, and meditation and can be elicited when a subject closes their eyes [21]. For the 1-minute recording, the subject simultaneously listened to a 40 Hz amplitude-modulated uniform white noise auditory stimulus using wireless earbuds for the ASSR registering EEG activity at 40 Hz and closed their eyes to elicit EEG activity in the alpha band (8–12 Hz). Three 3M Red Dot gel electrodes were used. The electrode configuration was: the reference electrode at the right mastoid process, the current injection electrode at the left forehead (FP1), and the sensing channel electrode at the right forehead (FP2). Fig. 8 illustrates the experimental setup and electrode configuration which follows the configurations used in M. S. Lee et al [22]. The power spectral density (PSD) is computed from the recorded data without applying any digital filter in Matlab. The study was approved by the UC San Diego Institutional Review Board. Prior to the human study, informed consent was obtained from the subject.

Fig. 8.

Experimental setup of the EEG recording system with the human subject.

D. EGG Validation

Electrogastrography (EGG) was used to validate the ultra-low frequency recording functionality of the SLDC operation mode in this work. A stationary EGG recording was performed with the subject remaining seated for the duration of the test in order to mitigate motion artifacts. Given the ultra-low frequency and low power nature of the gastric slow wave in the range of 0.017 to 0.17 Hz, a 1.5-hour recording period was used in order to adequately capture the slow wave. Similarly to the prior EEG study, standard 3M Red Dot gel electrodes were used. The electrodes were placed as shown in Fig. 9, with the reference electrode (1) placed between the xiphoid process and umbilicus, as referenced in prior work [9], [23], [24], and the ground (3) and channel electrodes (2) placed 4 cm apart. This single-channel configuration was intended to capture slow waves propagating from the fundus and corpus of the stomach [24]. The subject remained stationary for the first 25 minutes of the recording process to establish a baseline. The subject then ate a high-calorie meal and subsequently remained stationary for the remainder of the testing period.

Fig. 9.

EGG measurement. Top: the experimental setup of the neural recording system with the human subject. Bottom: the electrode configuration on a stomach sketch for EGG measurement.

To extract the EGG data, the recorded data was first bandpass filtered utilizing a Kaiser windowed FIR filter between 0.03 Hz and 0.25 Hz to reduce motion artifacts and isolate the gastric slow wave. The PSD was calculated via the Welch method. This methodology arises from prior work [9], [23], [25]. Prior to the human study, informed consent was obtained from the subject.

IV. RESULTS AND DISCUSSION

A. Noise Performance

As shown in Fig. 10, the measured average noise density over 1 Hz to 1 kHz bandwidth is $32\mathrm{n}\mathrm{V}/\sqrt{Hz}$ with a total power consumption of 5.56 μW for each channel. The input-referred noise (IRN) is $1.0\mu {\mathrm{V}}_{rms}$ at this bandwidth, which gives a Noise Efficiency Factor (NEF) of 2.93. The overall system achieves 53.3-dB peak signal-to-noise-and-distortion factor (SNDR) at 2.1-mV_pp 100-Hz input as shown in Fig. 11. Therefore, the neural recording system is able to resolve biopotentials at an effective least significant bit (LSB) of 5.4 μV_pp. A peak spurious-free dynamic range (SFDR) of 68 dB is achieved with the same input as shown in Fig. 12. As expected, the distortion for signals near full range is limited by the third harmonic, well above even harmonics caused by mismatch between differential paths. Calculated with the peak SNDR, the dynamic range (DR) is 57.4 dB. The peak signal-to-noise ratio (SNR) is 61.1 dB at 12 mV_pp, and then it drops down when the ADC is overloaded.

Fig. 10.

Measured noise spectral density in continuous operation mode.

Fig. 11.

Measured SNDR and SNR in continuous operation mode.

Fig. 12.

Measured SFDR in the continuous operation mode.

Owing to the absence of any sample-and-hold or other switched-capacitor circuits in the charge-redistribution OTA and integrator topology implementing a continuous-time first-order delta-sigma modulator, the ADC is free from kT/C sampling noise, but requires careful DC biasing which is accomplished by activating the RST switch at the onset of conversion, with its high-resistance state maintaining the DC operating point throughout conversion. The input-referred noise of the ADC is dominated by thermal noise in the OTA owing to the delta-sigma loop which pushes noise in the integrator and quantizer to higher frequencies out of the signal band. As illustrated in the noise model in Fig. 17, careful sizing of the capacitive division network at the input stage of the OTA minimizes the overhead in input referred noise relative to the intrinsic OTA input referred noise:

$$V_{n,ADC}^2\approx {\left(\frac{C_{in}+C_{DAC}+C_{OTA}}{C_{in}}\right)}^2{V}_{n,\mathit{OTA}}^2$$ (1)

by maximizing the input coupling capacitance $C_{in}$ relative to the DAC feedback capacitance $C_{DAC}$ and OTA input parasitic capacitance $C_{OTA}$. Other noise contributions, such as from the RST switch in high-resistance mode and the chopping switches in alternating low-resistance state, are negligible. Clock jitter is carefully controlled from an external source providing the 5 MHz master clock for all clock and control waveforms. Residual charge injection by the chopping and RST switches due to asymmetries in the differential signal paths could cause DC offset and degrade the ADC DR. Although we did not find this to be an issue with the current design, it can be mitigated by several techniques such as nested chopping, dynamic offset zeroing, dead-banding, etc. [26]–[28].

Fig. 17.

Simplified noise model of the OTA input stage of one channel of the neural recording SoC.

B. Energy Efficiency

Given the timing configuration for the SLDC mode, 98.4% power is saved and each channel consumes 0.09 μW on average. As shown in Fig. 13, the peak SNDR, SNR, and DR are 53.1 dB, 56.3 dB, and 56.2 dB, respectively. The system presents 1.1 μV_rms input-referred noise over 0.001 Hz to 1 Hz bandwidth, which gives a NEF of 12.9. Fig. 14 shows that a 2-mV_pp input achieves a SFDR of 71 dB at 0.1 Hz. Each of the 16 channels was characterized in the SLDC operation mode on the electrical testbench. Across-channel variations in SNDR and IRN are negligible as shown in Fig. 15.

Fig. 13.

Measured SNDR and SNR in the SLDC operation mode.

Fig. 14.

Measured SFDR in the SLDC operation mode.

Fig. 15.

Measured SNDR and input-referred noise across 16 channels in the SLDC mode.

Through the RST switches, CDS is performed at each start of system power-on, which reduces low-frequency noise during 800-μs effective recording time in SLDC mode. Therefore, chopping is disabled in the SLDC operation mode, and the system gives 435-MΩ input impedance at 0.1Hz. The input impedance was measured by inserting a resistance of comparable magnitude in between the voltage source driving the signal and the ADC measuring the signal, and observing the corresponding amplitude drop in the ADC output.

During the operation time, the power breakdown for each channel from simulations is shown in Fig. 16 (the power consumption of the driven signals from the external control system is not included). The OTA power dominates the total power consumption as expected. The global bias and the dynamic comparator consume a small part of the total power. The performance of this 16-channel neural recording system is summarized in Table I. From the comparison of key metrics with state-of-the-art neural interfaces, this system achieves low NEF and PEF in continuous operation mode. With the SLDC mode, the ultra-low frequency recording band is covered with a high input impedance while maintaining a reasonable NEF.

Fig. 16.

Power breakdown for each channel during operation.

TABLE I.

Comparison with Existing Neural Recording Systems

	ISSCC’21 [18]	ISCAS’21 [19]	VLSI’21 [17]		ISSCC’22 [15]		TBCAS’22 [16]		This Work
Technology (nm)	65	180	55		180		180		65
Number of Channel	1	1	16		1		1		16
On-chip Decimator	No	No	Yes		No		No		No
Supply Voltage (V)	0.8	1.0	1.2		0.7		1.2		1.0
Power / channel (μW)	1.68	1.8	61.2		5		4.3		0.09	5.56
Bandwidth (Hz)	500	0.1–500	0.5–1k	0.3–10k	1–200	1–10k	1–300	1–5k	0.001–1	1–1k
Input-referred Noise ($\mu {\text{V}}_{rms}$)	2.6	1.4	2.88±0.18	5.53±0.36	1.4	8.5	3.6	14.7	1.1	1.0
Noise Density $\left(\text{nV}/\sqrt{Hz}\right)$	118	64	91	55	99	85	208		1125	32
NEF	6.58	3.31	17.1 / 9.8b		10.4	8.9	15.5		12.9	2.93
PEF (NEF2VDD)	34.6	10.95	351 / 115b		75.7	55.8	288		166	8.6
SNDR	94.2	N/A	59.5		85.1		82.7	71.7	53.1	53.3
Effective LSB ($\mu {\text{V}}_{pp}$)a	10.6	N/A	192		39.3		13.9		5.4	5.4
Input Impedance (MΩ)	8	N/A	283 @ 1Hz		431 @ DC 147 @ 1 kHz		133 @ 300Hz		435@0.1Hz	20@100Hz
Area / channel (mm2)	0.056	N/A	0.0077		0.108		0.151		0.017

^a:Effective LSB = full scale input range / 2^ENOB

^b:On-chip decimator not included

C. Biopotential Recording

The neural recording system’s capabilities in biomedical and neuroscience application settings were validated through electrophysiological experiments using two different operation protocols for EEG and EGG biopotential recording. For EEG recording, the results in Fig. 18 show the expected alpha modulation and the 40 Hz ASSR peak based on the subject’s state and stimuli during the experiment. The noise floor is roughly −143 dB and the difference between the alpha peak and the noise floor is roughly 20 dB. The difference between the 40-Hz ASSR peak and the noise floor is 17 dB. The 60-Hz peak represents the power line noise from electrical outlets.

Fig. 18.

Power spectral density of the EEG recording showing alpha brain wave activity around 10 Hz and ASSR at 40 Hz, as well as 60 Hz line noise.

The results for EGG recording are shown in Fig. 19, depicting a period of elevated gastric power after meal consumption in the 0.033 to 0.066 Hz region, indicating that slow wave activity is present in the recording. An increase in gastric activity post-meal consumption is anticipated based on prior works [9], [11], [24], [29], and this is reflected in the time series shown above in Fig. 19. Prominent biopotential signals such as EEG exerts at a frequency range from 1 Hz to 1 kHz, and is recorded at low amplitudes of μV. Therefore, there is a strong need for a low-noise recording system that can yield high-accuracy biopotential recordings. By adopting low-noise OTA design, chopping technique, reasonably sized input capacitors, etc., the proposed neural recording SoC meets the requirement with the continuous operation mode. This operation has been further verified in our system for one of the lowest-amplitude electrophysiological signals, EEG, and was fully capable of capturing alpha modulation and ASSR.

Fig. 19.

EGG measurement results. Top: spectrogram of the EGG recording session between 0 to 0.15 Hz. Bottom: Normalized EGG Power vs. Time. The red vertical through-all line represents the time the subject starts eating the meal and the magenta line represents the time the subject stops eating their meal.

In addition, it is important not to ignore unique requirements of certain biopotential signals, such as EGG, which operate at ultra-low frequencies and require very long recording times. The SLDC mode enables very low-power operation for ultra-low frequency at 0.001 Hz to 1 Hz, which is highly favorable for EGG. The operation mode was further verified in an on-body EGG experiment and yielded promising results to capture and analyze gastric myoelectrical activities. While wet-contact electrodes were employed in this work, the impedance of other electrode types and in particular dry-contact electrodes may present challenges at these very low frequencies. The presence of large electrode DC offsets may saturate the ADC and degrade the performance, which is effectively mitigated by employing additional chopping servo-loops [17], [30], [31].

V. CONCLUSION

In this article, a 16-channel low-noise low-power neural recording system-on-chip is presented. Sixteen channels are able to measure biopotentials simultaneously to potentially cover large spatial recordings with high-density electrode arrays. A low NEF of 2.93 is achieved with a chopping-based delta-sigma ADC topology to resolve the frequency band from 1 Hz to 1 kHz in the continuous operation mode. The SLDC mode is proposed to scale down system power consumption by 98.4% for the bandwidth from 0.001 Hz to 1 Hz, while maintaining the same effective LSB and a high input impedance of 435 MΩ. The efficacy of the dual operations has been demonstrated in two on-body biopotential recording experiments, EEG and EGG. The combination of these two operation modes expands the system’s bandwidth coverage and enables versatile electrophysiological recordings on a single chip.

Biography

Jiajia Wu (Graduate Student Member, IEEE) received the B.S. degree in electronic information engineering from Zhejiang University, Hangzhou, China in 2016, and the M.S. degree in electrical and computer engineering in the University of California San Diego, La Jolla, CA, USA in 2020, where she is currently pursuing the Ph.D. degree.

Her current research interests include miniaturized silicon integrated bioinstrumentation for implantable brain-machine interfaces. She received the Best Paper Runner-up Award in BioCAS and the Runner-up Paper Award in WiCAS at the 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

Abraham Akinin (Member, IEEE) received the B.S. degree in biomedical engineering and physics from the University of Miami, Coral Gables, FL, USA, in 2010, and the M.S. and Ph.D. degrees in bioengineering from the University of California San Diego, La Jolla, CA, USA, in 2017 and 2020 respectively.

He is currently a postdoctoral researcher at the Lawrence Livermore National Laboratory where he is part of the Center for Bioengineering and the Implantable Microsystems Group in the Materials Engineering Division. From 2018 to 2020 he was Bioelectronics Design Engineer at Nanovision Biosciences, developing a scalable and power efficient retinal prosthesis. His research interests include cochlear implants, neural prostheses, integrated circuits for medical instrumentation, and implantable or wearable medical devices.

Jonathan Somayajulu (Graduate Student Member, IEEE) received the B.S. degree in Bioengineering: Biosystems from the University of California San Diego, CA, USA. He is currently working towards an MS in bioengineering at University of California, San Diego.

His research interests include digital signal processing and radio frequency engineering with applications towards electroencephalography and electrogastrography.

Min Suk Lee (Graduate Student Member, IEEE) received the B.S. degree in Bioeingeering: Biosystems from the University of California San Diego, CA. He is currently working toward the Ph.D. degree at the same university. He was a recipient of the Award of Excellence from the National Academy of Future Scientists and Technologists in 2015. He received the Oak Ridge Institute for Science Graduate Fellowship for the DEVCOM Army Research Lab: Humans in Complex Systems in 2020. He received the best Student Demonstration Award at BMB 2022 in San Diego, USA.

His research interests include medical device design, brain computer interface, and physiology relevant analysis.

Akshay Paul (Graduate Student Member, IEEE) is biomedical engineering with a PhD from the department of Bioengineering at the University of California San Diego, La Jolla, CA. He received his B.S. degree in biomedical engineering with a specialization in biomedical imaging and photonics from the University of California Irvine in 2015 and his M.S. degree and Ph.D. degree in bioengineering from the University of California San Diego in 2018 and 2023, respectively. Currently he is Senior Staff Engineer at NextSense, Mountain View, CA, and Institute for Neural Computation Associate at University of California San Diego, La Jolla, CA.

His research interests include addressing the challenges of mobile brain and body health monitoring through the development of unobtrusive bioinstrumentation. He was a Catalyst Foundation student fellow in 2018 and received the Oak Ridge (ORAU) Army Research fellowship in 2020.

Hongyu Lu (Graduate Student Member, IEEE) Hongyu Lu received the B.Eng. degree in electrical engineering from the University of Electronic Science and Technology of China, Chengdu, China, in 2019. He received the M.S. degree in electrical engineering from the University of California San Diego, La Jolla, CA, USA, in 2021, where he is currently working toward the Ph.D. degree.

His research interests include low-noise amplifiers, mixers and phase-locked loops.

Yongjae Park (Graduate Student Member, IEEE) received the B.S. (Summa cum laude) degree in electrical engineering from Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018, where he is currently pursuing the combined M.S and Ph.D degree. He was a visiting scholar in University of California San Diego, La Jolla, CA, USA from Aug 2022 to Jul 2023.

His current research interests include CMOS analog/mixed IC designs, especially low noise sensor front-end for bio-potential recording system and imaging system.

Seong-Jin Kim (Senior Member, IEEE) received his B.S. degree in electrical engineering from the Pohang University of Science and Technology, Pohang, South Korea, in 2001, and M.S. and Ph.D. degrees in electrical engineering from KAIST, Daejeon, South Korea, in 2003 and 2008, respectively.

From 2008 to 2012, he was a Research Staff Member at the Samsung Advanced Institute of Technology, Yongin, South Korea, where he was involved in the development of CMOS imagers for real-time acquisition of 3-D images. From 2012 to 2015, he was with the Institute of Microelectronics, A*STAR, Singapore, where he was involved in the design of analog-mixed signal circuits for various sensing systems. In 2015, he joined the department of electrical engineering, Ulsan National Institute of Science and Technology, Ulsan, South Korea, and now serves as an Associate Professor. He is a co-founder of SolidVue, a LiDAR startup company in South Korea. His current research interests include high-performance imaging devices, LiDAR systems, and biomedical interface circuits and systems. Dr. Kim has served on the Technical Program Committee at the IEEE International Solid-State Circuits Conference (ISSCC) since 2019 and is the Country Representative of South Korea for the ISSCC Far-East Region in 2021.

Patrick P. Mercier (Senior Member, IEEE) received the B.Sc. degree in electrical and computer engineering from the University of Alberta, Edmonton, AB, Canada, in 2006, and the S.M. and Ph.D.degrees in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, in 2008 and 2012, respectively.

He is currently a Professor in electrical and computer engineering with the University of California at San Diego (UCSD), La Jolla, CA, USA, where he is also the Co-Director of the Center for Wearable Sensors and the Site Director of the Power Management Integration Center. He has published over 180 peer-reviewed papers, including 25 ISSCC papers, 33 JSSC papers, and several articles in high-impact journals, such as Science, Nature Biotechnology, Nature Biomedical Engineering, Nature Electronics, Nature Communications, and Advanced Science. His research interests include the design of energy-efficient microsystems, focusing on the design of RF circuits, power converters, and sensor interfaces for miniaturized systems and biomedical applications.

Gert Cauwenberghs (Fellow, IEEE) is Professor of Bioengineering and Co-Director of the Institute for Neural Computation at UC San Diego, La Jolla CA. He received the Ph.D. degree in Electrical Engineering from California Institute of Technology, Pasadena in 1994, and was previously Professor of Electrical and Computer Engineering at Johns Hopkins University, Baltimore, MD, and Visiting Professor of Brain and Cognitive Science at Massachusetts Institute of Technology, Cambridge. He co-founded Cognionics Inc. and chairs its Scientific Advisory Board.

His research focuses on micropower biomedical instrumentation, neuron-silicon and brain-machine interfaces, neuromorphic engineering, and adaptive intelligent systems. He received the NSF Career Award in 1997, ONR Young Investigator Award in 1999, and Presidential Early Career Award for Scientists and Engineers in 2000. He is a Francqui Fellow of the Belgian American Educational Foundation, and a Fellow of the American Institute for Medical and Biological Engineering. He served IEEE in a variety of roles including as Distinguished Lecturer of the IEEE Circuits and Systems Society, as VP of Technical Activities on the Executive Committee of the IEEE Engineering in Medicine and Biology Society, on the Steering Committee of IEEE Brain, and as Editor-in-Chief of the IEEE Transactions on Biomedical Circuits and Systems.