Transformer-less high gain DC–DC converter design and analysis for fuel cell vehicles

Abstract

High-power converters with significant gains represent established configurations that hold appeal for applications in the industrial and commercial sectors, such as fuel cell electric vehicles (FCEV), energy backup systems, and automotive headlamps. Existing literature predominantly features topologies employing a single-duty ratio. However, this singular approach may not be dependable for operations with high-duty cycles, necessitating the incorporation of additional components to enhance voltage gain. To address this, the current study introduces the concept of time-sharing within the context of a high-gain non-isolated DC–DC converter. This innovative approach achieves substantially higher output voltage gains, approximately 13.33 times that of the input voltage. The analysis of the proposed converter is approached from various perspectives. Finally, it is examined within the MATLAB/Simulink environment, where the theoretical analysis is validated, and an efficiency of 97.4% is achieved.

Introduction

DC–DC converters are extensively used in renewable energy source integration with microgrids, electric vehicles, portable electronics, and energy storage systems^1–4. However, they have limited voltage gain. Theoretically, a basic boost converter can provide higher voltage gains at higher values of duty ratios. However, at higher duty ratios, components like inductors and capacitors restrict the voltage gain in practice due to the parasitic elements. Furthermore, the exceptionally high-duty cycle operation may cause a major rectifier diode reverse-recovery difficulty as well as large current ripples, increasing conduction losses and causing high EMI concerns.

Single switch high gain topologies are derived from the SEPIC converter in⁵, boost employed with the CUK converter in⁶ with an improved voltage gain and reduced part count. However, it has high voltage stress and also achieves high gain at a duty ratio above 0.5. SEPIC converter is extended with a switched capacitor network in⁷ for solar photovoltaic applications. It has low voltage stress and capacitors are charged and discharged in parallel-series combination to produce more output voltage. However, output magnitude depends on the number of capacitors it may increase cost and size. In⁸, the switch and transformer-less ultrahigh gain DC converter are suggested with the reduced part count. Nevertheless, it may achieve ultra-voltage with an extreme duty cycle.

Different hybrid high gain DC–DC converters are suggested such as switched-inductor⁹, switched-capacitor¹⁰ voltage multiplier based on capacitor and diode¹¹, voltage-doubler circuits¹², and the voltage-lift technique¹³. All of them can provide higher voltage gains with a suitable duty ratio of low voltage stress. Furthermore, each type has its own merits, such as a single switch, low semiconductor stress, and reduced current ripple. However, single-switch topologies suffer from voltage stress and high input current ripples. Moreover, high voltage conversions, generally cells based on switched inductor/capacitor, are used, increasing magnetic elements, size, and cost.

A quadratic boost converter without the issue of the extreme value of duty ratio is developed in¹⁴ for enhanced voltage gains. However, it increases the magnetic elements, and the voltage stress on the main switch is also restricted to the output voltage. The interleaved boost converter is extended using diode capacitor cells¹⁵, voltage multipliers¹⁶, voltage lift capacitors, and coupled inductors¹⁷. The significant features are low voltage stress, less input current ripple, and the average value of the current that flows through the power device is low. Nevertheless, the circuit is complex, and efficiency may decrease due to more conduction losses and leakage inductance. A boost converter with a voltage multiplier and coupled inductor was developed in¹⁸. In this circuit scheme, the current ripple is lesser. Also, the interleaved series-connected capacitor improves the output voltage. On the other hand, voltage multipliers (VMCs) and linked inductors may add to the complexity and increase voltage stress.

The proposed topologies in^19–21 are based on the two quasi-z source converters and extended with switched capacitor cells which lead to the deduction of the components, semiconductor stress, and improved voltage gain. However, it has more components, and its limitations in the operating duty cycle (d < 0.5) lead to source utilization may be reduced.

A high-gain DC converter based on diode-capacitor multipliers and coupled inductors is suggested in²². It can give higher output voltage gain at a lesser duty cycle and low power device stress. For grid applications, a hybrid input-based high gain step-up converter is proposed^23–25 without using a voltage multiplier or coupled inductors, which results in reduced components and size. However, active switches may suffer voltage stress problems. With the study made from the literature, the present paper covers the following aspects:

• A high-voltage gain DC–DC converter has been designed without using voltage multipliers, voltage doubler circuits, and DC-coupled inductors in this study.

• The converter is analyzed with different modes and voltage gains have been examined w.r.t duty ratios.

• A small-signal model has been presented for the proposed converter model.

• The analysis has been presented for different aspects and validated through simulation results.

The paper is structured as the suggested topology, and its functioning is described in “Proposed configuration and modes of operation” section. “Small-signal modeling” section deals with the small-signal modeling of the proposed topology. “Performance analysis of the suggested converter” section presents parameter design considerations, power loss calculations, stress analysis, and comparative assessment. “Results and discussions” section elaborates on the results and discussions, whereas “Conclusion” section encapsulates the conclusion.

Proposed configuration and modes of operation

The circuit topology of the suggested hybrid high-gain converter is depicted in Fig. 1a. It comprises switches (S₁–S₃), diodes (D₁–D₃), inductors (L₁, L₂), capacitors (C₀, C₁) and load (R). This configuration enhances the amplification by utilizing energy-storing components that get charged in parallel during the turn-on from the input source. Subsequently, the energy is released to the load in a consecutive arrangement during the turn-off.

Figure 1.

Illustrates the diagram of the suggested converter along with essential waveforms: (a) Proposed structure, (b) CCM, (c) DCM, and (d) The powertrain of fuel cell vehicles, incorporating the recommended converter.

To achieve a heightened step-up voltage and maximize the utilization of energy sources, the proposed design implements a time-sharing approach to control the switches. The theoretical representation of the converter's continuous discontinuous conduction mode (DCM) and conduction mode (CCM) can be observed in Fig. 1b and c respectively. Figure 1d illustrates the application of the suggested converter utilizing a fuel cell as the energy source in combination with a supercapacitor, as well as its integration into the powertrain of fuel cell vehicles. The suggested configuration is well-suited for fuel-cell electric vehicles, offering the following merits:

• Reduced component count, resulting in economical and space-efficient design

• Enhanced voltage gain

• Optimized utilization of energy sources through the incorporation of two distinct duty ratios

Modes of operation in CCM

Sate 1:

involves energizing the inductors and charging capacitor C₁ using the input voltage through power switches S₁, S₂, and D₁. Simultaneously, capacitor C₀ has released its stored energy to the load. The circuit configuration during this phase is depicted in Fig. 2a. The associated equations are provided below.

$$V_{L_1}=L_1\frac{d{i}_{L_1}}{\mathit{dt}}=V_{\mathit{in}}$$ 1

$$V_{L_2}=L_2\frac{d{i}_{L_2}}{\mathit{dt}}=V_{\mathit{in}}$$ 2

$$V_{C_1}=V_{\mathit{in}}$$ 3

State 2:

Switch S₃ is in the ON state, while power devices S₁ and S₂ are in the OFF state, and both diodes (D₁, D₃) are reverse biased, as shown in Fig. 2b. During this mode, the L₁ and L₂ are connected in series through S₃, and the voltage across the inductor follows the relationship specified below.

$$V_{L_1}=V_{L_2}=\frac{V_{\mathit{in}}+V_{C_1}}{2L}$$ 4

State 3:

During operation, the input port connects in series to the inductors, capacitor C_1, and load. The energy accumulated from earlier modes is delivered to the R through diode D₃, as illustrated in Fig. 2c. The voltage across the inductor is as follows below.

$$V_{L_1}=V_{L_2}==\frac{V_{\mathit{in}}+V_{C_1}-V_0}{2L}$$ 5

The equation for the output voltage in relation to the duty ratio is provided in Eq. (6).

$$V_0=\frac{2V_{\mathit{in}}}{\left(1-D_1-D_2\right)}$$ 6

where ‘D₁ and D₂ are the duty ratios of the corresponding switches.

Theoretical examination of the converter's voltage gain is carried out using Eq. (6), with the duty ratio D₁ varied across different values in relation to D₂. The associated graph is depicted in Fig. 3a. Interestingly, the gain remains constant regardless of changes in D₁ and D₂. These outcomes lead to the inference that the suggested converter is not bound by restrictions on D1 being greater than D₂ or D₂ being less than D₁, as it consistently yields uniform voltage gain values.

Figure 2.

Modes of operation: (a) state-1, (b) state-2 and (c) state-3.

Figure 3.

Voltage gain with a variation of duty ratio: (a) voltage gain vs D₁ and (b) voltage gain vs D₂.

DCM operation

Mode 1:

The mode-1 operation during DCM is the same as Mode. The current flows via inductor as (7)

$$i_{L_1}=i_{L_2}=\frac{V_{\mathit{in}}}{L}{D}_1{T}_S$$ 7

Mode 2:

The device S₃ is ON, and S₁, S₂ are kept OFF. The current flows via inductors as (8) and (9).

$$i_{L_1}=i_{L_2}=\frac{V_{\mathit{in}}+V_{C_1}}{2L}{D}_2{T}_S$$ 8

$$i_{L_1}=i_{L_2}=\frac{V_{\mathit{in}}}{L}{D}_2{T}_S$$ 9

Mode 3:

Now all switches are OFF in this mode. The series-connected DC sources, L₁, C₁, and L₂ will transfer energies to C₀ and the load. The magnitudes of i_L1 and i_L2 will decrease to zero.

$$i_L=\frac{V_0-V_{\mathit{in}}-V_{C_1}}{2L}{D}_C$$ 10

Mode 4:

In mode 4, the devices S₁ and S₂ are still in off condition. The energy in L₁ and L₂ becomes zero. Nevertheless, the energy stored in C_o is delivered to the load. From Eqs. (8–10), D_C (duty ratio in the off period in DCM as follows,

$$D_C=\frac{2V_{\mathit{in}}\left(D_1+D_2\right)}{V_0-2V_{\mathit{in}}}$$ 11

The capacitor current average value is below

$$I_C=\frac{\frac{1}{2}{D}_C{T}_s{i}_L-I_0{T}_s}{T_s}$$ 12

$$I_C=\frac{1}{2}{D}_C{i}_L-I_0$$ 13

From Eqs. (5), (6), and (8), Ico is as given below

$$I_C=\frac{{(D_1+D_2)}^2{V}_{\mathit{in}}^2{T}_s}{L(V_0-2V_{\mathit{in}})}-\frac{V_0}{R}$$ 14

Then, the time constant normalized value is given below

$$\tau =\frac{L{f}_s}{R}$$ 15

Thus, the voltage gain is (16)

$$M_{\mathit{DCM}}=\frac{V_0}{V_{\mathit{in}}}=1+\sqrt{1+\frac{{(D_1+D_2)}^2}{\tau }}$$ 16

The theoretical assessment of the converter's voltage gain is conducted in the Discontinuous Conduction Mode (DCM) using Eq. (16) while altering the duty ratio D₁ in relation to varying values of duty ratio D₂. The corresponding graph is presented in Fig. 3b. Remarkably, the gain remains unaffected irrespective of changes in D₁ and D₂. The results lead to the conclusion that the suggested converter does not impose any limitations on D₁ being greater than D₂ or D₂ being less than D₁, as it consistently produces identical voltage gain values.

Boundary operating condition between CCM and DCM

The voltage gain of the CCM and DCM is equal when the converter operates at the boundary point. The time constant normalized value is shown below in terms of duty ratios. It is theoretically tested using Eq. (17), and the corresponding plot is depicted in Fig. 4.

$${\tau }_B=\frac{(D_1+D_2){(1-D_1-D_2)}^2}{4}$$ 17

Figure 4.

The variation of time constant τB corresponding to duty ratio.

Small-signal modeling

A comprehensive presentation of the converter's small-signal analysis is available in²⁶. Typically, the state variables consist of a ($\tilde{X}$, $\tilde{D}$) and a perturbation ($\tilde{x}$,$\tilde{d}$). The state-space equations and transfer functions are provided in Eqs. (18–26).

$$\begin{array}{c}x=\tilde{X}+\tilde{x}\\ d=\tilde{D}+\tilde{d}\\ \end{array}$$ 18

The small-signal model is expressed as in (19)

$$\begin{array}{c}\dot{\tilde{x}}=A\tilde{x}+B\tilde{u}\\ \tilde{y}=C\tilde{x}+D\tilde{u}\\ \end{array}$$ 19

The suggested converter's average model is structured according to (20)–(22), where in $\tilde{x}$, $\tilde{y}$, and $\tilde{u}$represent the control variable vector, system output vector, and state variable vector respectively.

$$A=\left[\begin{array}{cccc}0& 0& 0& \frac{-(1-D_1-D_2)}{L_1}\\ 0& 0& 0& \frac{-(1-D_1-D_2)}{L_2}\\ 1/C_1& 0& 0& 0\\ \frac{(1-D_1-D_2)}{C_0}& 0& 0& \frac{-(1-D_1-D_2)}{R{C}_0}\end{array}\right]$$ 20

$$B=\left[\begin{array}{c}\frac{2}{L_1}\\ \frac{2}{L_2}\\ 1\\ 0\end{array}\right],C=\left[\begin{array}{cccc}0& 0& 1& 1\end{array}\right],D=0$$ 21

$$\tilde{x}=\left[\begin{array}{c}{i}_{L_1}\\ i_{L_2}\\ v_{C_1}\\ v_0\end{array}\right],\tilde{u}=[\tilde{d}]$$ 22

The control transfer function for the recommended configuration is in (23)–(25)

$$\frac{{\widehat{V}}_0}{\widehat{d}}=C{\left[SI-A\right]}^{-1}f$$ 23

$$f=AX+B{V}_{\mathit{in}}$$ 24

$$X=A^{-1}b{V}_{\mathit{in}}$$ 25

$$\frac{{\widehat{v}}_0(s)}{\widehat{d}(s)}=\left[\frac{\begin{array}{c}{s}^3(C_{0}R(L_1+L_2))-s^2(-2(L_2+L_1)-8C_{0}R)-C_{0}R(D_1^2+D_2^2)\\ -2(L_1+L_2)C_0+4R{C}_0(D_1+D_2))+s(2R{C}_0{D}_1+4D_2-2R{C}_0{D}_1{D}_2)\\ \end{array}}{s^4(2R{C}_0(L_1+L_2))+s^3(2C_0(L_1+L_2)(1-D_1-D_2))-s^{2}R{C}_0((1-D_1^2-D_2^2)+2(D_1+D_2-D_1{D}_2))}\right]$$ 26

The frequency response of the suggested converter is tested using Eq. (26), and it is shown in Fig. 5. The bode plot shows that the gain margin is infinite dB, and the phase margin is 155°.

Figure 5.

Bode plot response.

Performance analysis of the suggested converter

Effect of parasitic

Figure 6 illustrates the converter configuration considering parasitic resistances. Where R_DS is the on-state resistance of the switch, r_D1, r_D2, and r_D3 are the forward resistance of the diodes D_1-3, respectively. r_L1-2 is the ESR of the inductor L₁-L₂. The output voltage with parasitic elements expression from the modes of operation is as follows²⁷.

Figure 6.

The proposed converter with parasitic.

Mode I:

During this mode, which lasts for D₁T_s, the devices S₂ and S1 are activated while S₃ remains deactivated. The equations describing the current of the capacitor (I_co), and voltage across (L₁), are provided in Eqs. (27–29).

$$V_{L_1}=V_{\mathit{in}}-i_{L_1}(r_{S_1}+r_{L_1})$$ 27

$$V_{L_2}=V_{\mathit{in}}-i_{L_2}(r_{S_2}+r_{L_2})$$ 28

$$i_{C_0}=\frac{-V_0}{R_0}$$ 29

Mode 2:

During this mode (D₂T_s), S₁ and S₂ are deactivated, while S₃ is activated. The equations of I_co and V_L1, are provided in Eqs. (30) and (31).

$$V_{L_1}=\frac{V_{\mathit{in}}+V_{C_1}-i_{L_1}(r_{S_3}+r_{L_1}+r_{L_2}+r_{D_2})-V_{D_2}}{2}$$ 30

$$i_{C_0}=\frac{-V_0}{R_0}$$ 31

Mode 3:

During the operation within the time interval of (1-D₁-D₂) Ts, all power switches are deactivated. Equations (32) and (33) provide the expressions for the I_co, and V_L1, in this mode.

$$V_{L_1}=\frac{V_{\mathit{in}}+V_{C_1}-i_{L_1}(r_{S_3}+r_{L_1}+r_{L_2}+r_{D_3})-V_{D_3}}{2}$$ 32

$$i_{C_0}=i_{L_1}-\frac{V_0}{R_0}$$ 33

where.

$$i_{L_1}=\frac{V_0}{R_0(1-D_1-D_2)}$$ 34

By employing the principle of volt-second balance to either inductor L₁ or L₂, Eq. (35) can be derived.

$$V_0=\frac{2V_{\mathit{in}}-V_{D_2}{D}_2-V_{D_3}(1-D_1-D_2)}{\begin{array}{c}\frac{2D_1}{R_0(1-D_1-D_2)}(r_{S_1}+r_{L_1})+\frac{D_2}{R_0(1-D_1-D_2)}(r_{S_3}+r_{L_1}+r_{L_2}+r_{C_1}+r_{D_2})\\ +(1-D_1-D_2)-\frac{(r_{L_1}+r_{L_2}+r_{C_1}+r_{D_3})}{R_0}\\ \end{array}}$$ 35

The gain of the proposed converter is tested using Eq. (35) at ideal and different values of load resistances. The corresponding plot is illustrated in Fig. 7.

Figure 7.

Change in the output voltage concerning the duty ratio, considering parasitic effects.

Power loss analysis

The input power is given in (36).

$$P_i=2V_{\mathit{in}}{i}_{L_1}{D}_1+2V_{\mathit{in}}{i}_{L_1}{D}_2+2V_{\mathit{in}}{i}_{L_1}(1-D_1-D_2)$$ 36

$$P_i=\frac{2V_{\mathit{in}}{V}_0}{R_0(1-D_1-D_2)}$$ 37

From Eqs. (36) and (37), the expression of efficiency for the proposed converter is given (38)

$$\eta =\frac{P_0}{P_i}=\frac{2V_{\mathit{in}}-V_{D_2}-V_{D_3}(1-D_1-D_2)}{V_{\mathit{in}}\left[2D_1(r_{S_1}+r_{L_1})+D_2(r_{S_3}+r_{L_1}+r_{L_2}+r_{D_2})-{(1-D_1-D_2)}^2-\frac{(r_{L_1}+r_{L_2}+r_{D_3})}{R_0}\right]}$$ 38

Based on the switching losses (Psw), the output power of the proposed configuration is as given in (40). Using (36), (37), and (40), the efficiency is as given (43).

$$P_{\mathit{SW}}=\frac{1}{6}{R}_{L}f\left(t_{\mathit{on}}+t_{\mathit{off}}\right)$$ 39

$$P_0=\frac{V_0^2}{R_0}-P_{\mathit{SW}}$$ 40

The inductor loss

$$P_{\mathit{rL}}=r_L^{}{I}_{\mathit{rms}}^2=r_L^{}{I}_0^2=\frac{r_L}{R_L}{P}_0$$ 41

The capacitor loss

$$P_{\mathit{rC}}=r_C\frac{\mathrm{\Delta }{i}_L^2}{12}$$ 42

$$\eta =\frac{P_{_0^{}}^{}}{P_{_0^{}}^{}+P_{\mathit{loss}}}$$ 43

Calculation of voltage stress

The voltage stress on the power devices in the proposed configuration is in the (44) and is based on²⁷.

$$\begin{array}{c}{V}_{S_1}=V_{s_2}=V_{S_3}=\frac{V_0}{2}\\ V_{D_1}=V_{D_2}=V_{D_3}=V_0\\ \end{array}$$ 44

Converter parameters design

The design and selection of the converter are followed in²⁷. The components and specifications of the components are listed in Table 1.

Table 1.

Test system specifications.

Parameter	Simulation
Input voltage (V)	30 V
Output voltage (V0)	400 V
Output currents (I0)	1.25 A
Switching frequency (f)	50 kHz
Inductors (L)	0.5 mH
Capacitor (C)	300 uF

The Inductance calculation is

$$L_{1min}=L_{2min}=\frac{2}{27}\frac{R_{Lmax}}{f_s}$$ 45

The inductor ripple current is calculated as (44)

$$\mathrm{\Delta }{i}_{L_{1}max}=\mathrm{\Delta }{i}_{L_{2}max}=\frac{D_{min}(1-D_{min})V_0}{f_{s}L}$$ 46

The determination of the capacitance value using below Eq. (47).

$$C_{\mathit{min}}=\frac{D_{\mathit{max}}{V}_0}{V_{\mathit{cpp}}{R}_{\mathit{Lmax}}{f}_s}$$ 47

$$V_{\mathit{cpp}}=\frac{V_r}{2}$$ 48

The ripple voltage (V_r) is 1% V₀.

Comparative analysis

A comparative evaluation of the proposed converter in relation to other advanced converters is presented in Table 2 and visually depicted in Fig. 8.

Table 2.

Comparison with existing high gain converters.

Ref. no.	Switches	Diodes	L	C	Voltage stress Vstress_max	Switching scheme	Operating range of duty ratio for high gain	Voltage gain
4	2	4	3	5	$V_S=\frac{(2-D)V_g}{D_{}^{\prime 2}}$	PWM	Extreme (D > 0.5)	$V_0=\frac{(2-D)(1+D)V_g}{D^{\prime 2}}$
5	1	3	2	3	$V_S=\frac{V_0+V_{\mathit{in}}}{2}$	PWM	Extreme (D > 0.7)	$V_0=\frac{1+d}{1-d}{V}_{\mathit{in}}$
6	1	3	2	4	$V_S=\frac{V_0}{1+\delta }$	PWM	Extreme (D > 0.7)	$V_0=\frac{2}{1-\delta }{V}_{\mathit{in}}$
11	1	3	2	3	$V_S=\frac{U_0}{2}$	PWM	Extreme (D > 0.7)	$U_0=\frac{2}{1-d}{U}_{\mathit{in}}$
19	1	5	2	5	$V_S=\frac{U_0}{2}$	PWM	Limited (D < 0.5)	$U_0=\frac{2}{1-d}{U}_{\mathit{in}}$
20	1	3	3	5	$V_S=\frac{U_0}{(1+d)}$	PWM	Limited (D < 0.5)	$U_0=\frac{1+d}{1-2d}{U}_{\mathit{in}}$
21	2	3	2	4	$V_S=\frac{U_0}{2}$	PWM	Limited (D < 0.5)	$U_0=\frac{2}{3-4d}{U}_{\mathit{in}}$
23	2	3	2	3	$V_S=V_0$	PWM	Extreme (D > 0.7)	$V_0=\frac{3-D}{1-D}{V}_{\mathit{in}}$
24	3	3	2	2	$V_S=V_0$	Time-sharing	Without extreme (D1 + D2 > 0.7)	$V_0=\frac{2-d_2}{1-d_1-d_2}{V}_{\mathit{in}}$
Pro	3	3	2	2	$V_S=V_0$	Time-sharing	Without extreme (D1 + D2 > 0.7)	$V_0=\frac{2}{1-D_1-D_2}{V}_{\mathit{in}}$

Figure 8.

Voltage gain comparison.

Results and discussions

The proposed configuration is simulated with an input voltage of 30 V, a switching frequency of 50 kHz, and duty ratios assigned as D (D₁ = 50%, D₂ = 35%). Detailed parameter information can be found in Table 1. Figure 9a illustrates the switching control gate pulses (G₁–G₃) utilized in the proposed converter for controlling the switches (S₁–S₃) respectively. Figure 9b shows the output voltage (V₀) is near 398 V, inductor current (i_L1 and i_L2) is 8.25A, and capacitor voltage (V_C1) is charged to 30 V. The simulated output voltage is cross-validated with the derived expression in Eq. (6). In Mode-1, both inductors are energized in parallel up to d = 50%, and in Mode-2 also, L₁ and L₂ are energized with d = 35%, facilitated through the active switches S₁, S₂, and S₃ respectively. The corresponding inductor currents are depicted in Fig. 9b.

Figure 9.

Simulation results: (a) Gate pulses of switches (G₁, G₃, and G₂) and (b) V₀, i_L1, i_L2, and V_C1.

Additionally, the voltage across capacitor C₁ is shown. Notably, V_C1 equals the input voltage. Figure 10 presents the insulation against voltage stress on the power semiconductor switches. A zero voltage across the switch indicates the ON state, while voltage is evident across the switch when it is OFF. Specifically, Fig. 10a illustrates the voltage stress for switches S₁, S₂, and D₁. The magnitude of the voltage across the device (S₁, S₂, D₁) is 200 V and validated with Eq. (44). Figure 10b depicts the voltage stress for switch S₃, diode D₂, and D₃. The maximum voltage stress on the device (S₃, D₂, D₃) aligns with the output voltage i.e. 398 V from the stress results. Furthermore, power loss distribution for switches and diodes is displayed in Fig. 11a, and efficiency with respect to output power is illustrated in Fig. 11b. The practical feasibility of the converter is validated on the laboratory prototype. The test is conducted at V_DC = 30 V, D₁ = 50%, D₂ = 35%, and the switching frequency is 50 kHz. The switching gate pules of the semiconductor devices (S₁-S₃) are shown in Fig. 12. Figure 13 illustrates the output voltage (V₀), current flows through the inductor (i_L1 and i_L2), and the voltage across the capacitor (V_C1) respectively.

Figure 10.

Voltage stress: (a) (D₃, S₃, and D₂) and (b) (D₁, S₁, and S₂).

Figure 11.

(a) Power loss across each component, (b) efficiency vs output power of converter.

Figure 12.

Experimental gate pules of the switches.

Figure 13.

Experimental results of output voltage, inductor currents, and the voltage across the capacitor.

Conclusion

In this manuscript, introduce a non-isolated high-gain step-up DC–DC converter designed for fuel cell-based electric vehicles. This converter enhances voltage gain without resorting to voltage multiplier units, transformers, or coupled inductors. A key advantage is its streamlined component count. The approach employs a time-sharing mechanism within the configuration, broadening the range of duty cycle operations, thereby boosting converter efficiency and optimizing input source utilization. The proposed converter achieves a remarkable voltage gain of 13.33 times the input voltage while attaining an efficiency of 97.4%. These results demonstrate competitive performance for fuel cell EV applications. In future work, the proposed converter will be tested in a DC microgrid through an inverter, along with a suitable energy management scheme to regulate the load voltage.

Author contributions

Data curation, B.A..; formal analysis, T.K. and T.S.B.; funding acquisition, T.S.B. and S.S.; methodology, B.A and T.K..; project administration, T.S.B. and S.S., resources, B.A., and T.S.B.; supervision, S.S.; writing—original draft, B.A. and T.K. All authors have read and agreed to the published version of the manuscript.

Data availability

The data used to support the findings of this study are included in the article.

Competing interests

The authors declare no competing interests.