A Wireless Artificial Mechanoreceptor in 180-nm CMOS

Abstract

This article presents an implantable low-power wireless integrated system for tactile sensing applications. The reported ASIC utilizes a low-loss magnetic human body communication channel for both wireless power and data transfer. The chip is hybrid-integrated with an in-house fabricated MEMS capacitive force sensor to form an implantable artificial mechanoreceptor. An on-chip correlated double sampling capacitance to time converter consumes 750nW from a 1.2V on-chip regulated supply, achieving a 2.0fF resolution for an input capacitance of 14pF and a FoM of 49 fJ/c-s while occupying an area of only 0.04 mm². The capacitance to time converter has a time-multiplexed mode to interface with 4 input capacitors. Wireless power management feedback is utilized to ensure robust operation in the presence of hand gesture changes and process-voltage-temperature variations. The on-chip data transmitter can operate in on-off keying or frequency-shift keying modulation formats, where it consumes only 7.8 $\mu \text{W}$ in the on-off keying mode. The 1.62mm² chip is fabricated in a standard 180nm CMOS process and consumes 110.3$\mu \text{W}$.

I. Introduction

SEVERAL medical conditions (e.g. spinal cord injury, stroke) lead to irreversible damage of the neural pathways between the brain and body, resulting in a loss of muscle function and the sensation derived from skin mechanoreceptors. While emerging brain-machine interfaces (BMI) have shown promise at restoring efferent communication in the form of brain-controlled functional electrical stimulation (FES) of paralyzed muscles [1], [2], they have lacked the technology to restore a sense of touch. To restore somatosensation, a sensor-brain interface system could acquire tactile signals with appropriate sensors and encode the information directly into the brain using a neural stimulator [3], [4]. To acquire the tactile signals, a variety of sensors, ranging from strain gauges and accelerometers [5] to more complex systems such as the BioTac [6], have been integrated into prosthetic hands for amputees (Fig. 1(a), bottom left). If reanimating a paralyzed hand with FES, a sensorized glove could be used [7] (Fig. 1(a), bottom middle). However, this strategy has major practical and aesthetic limitations. Gloves confound hand movements by introducing slip between the fingers and the manipulated object. Synthetic gloves are susceptible to damage from moisture and abrasion unlike native skin. Gloves also must be donned and doffed by an able-bodied assistant. Finally, wearing a bulky glove would likely decrease the psychological benefits conferred by restoring grasp in the native hand. An implantable force sensor (Fig. 1(a), bottom right) would not have these limitations.

Fig. 1.

(a) Different tactile sensing mechanism used to restore somatosensation, and (b) proposed implantable tactile sensing system.

In this work, we propose an implantable artificial mechanoreceptor (IAM) for acquiring and transmitting a tactile signal that could be mapped to neural stimulation in a somatosensory feedback system. As shown in Fig. 1 (b), the proposed IAM is composed of an in-house fabricated MEMS capacitive force sensor and an interface CMOS chip. The IAM, intended for subcutaneous placement in the palm or fingertip, is wirelessly powered by a base unit worn on the wrist. A data link carrying the measured force information is realized at the same time from the IAM to the base unit. In turn, the base unit could send stimulation commands accordingly to a neural stimulator.

By utilizing the low path loss, we reported the first magnetic human body communication (mHBC) based implantable sensor interface with both wireless power and data links in [8]. This paper elaborates on the device reported in [8] in significantly more detail and presents more relevant measurement results. In addition, this paper presents a second chip based on a similar architecture but utilizing a different frequency band to improve the power and data link efficiency.

Several design constraints and challenges were considered in the implementation of the proposed IAM. First, selection of the wireless communication band is critical since it affects the power efficiency of the wireless system. This is discussed in section II. Second, an efficient and reliable power management unit is needed to generate stable supplies for the functional on-chip circuitries. To achieve this, an on-chip power management unit with an input power level feedback scheme was designed that senses the input wireless power level and transmits it back to the base unit. As a result, the base unit can adjust the level of the generated power accordingly to form a robust power link in the presence of gesture changes as well as process-voltage-temperature (PVT) variations. Third, a low-noise and robust capacitance read-out circuit is required to quantize the capacitive force sensor output, which will then be transmitted to the base unit. To achieve this, a time-domain correlated double sampling (CDS) capacitance to time converter is implemented to read the sensor value with high resolution. The CDS technique helps to cancel the capacitance uncertainty caused by PVT variations, as verified by measurement. Fourth, besides the power link, a wireless data link should concurrently be established from the IAM to the base unit. The chip includes a data transmitter unit that can be configured to either on-off-keying (OOK) or frequency-shift-keying (FSK) format, where OOK format offers a high power efficiency and FSK is more robust against path loss variations. Finally, a force sensor is required to perform the tactile sensing. A custom MEMS capacitive force sensor with a diameter of 5mm was designed, fabricated, fully characterized, and hybrid-integrated with the implemented chip. This is discussed in section IV.D.

The rest of this paper is organized as follows: section II presents the design constraints on the wireless communication channel and its characterization, section III presents the chip implementation including detailed circuit design and measurement results for individual blocks; section IV presents the system measurement results, as well as the sensor fabrication process and characterization; section V concludes this work.

II. Wireless Channel

Since the base unit worn on the wrist is a battery powered device, reducing its power consumption, which is dominated by maintaining the power link for the IAM, becomes essential. Therefore, an important design consideration is the selection of the wireless communication channel between the base unit and the IAM since the path loss directly affects the required minimum radiated power from the wrist device. A commonly used wireless powering method is inductive coupling [9]-[11], which despite certain advantages, typically suffers from limited communication range and is sensitive to the alignment between the primary and secondary coils. As an alternative, broadcasting RF telemetries (e.g. 433 MHz or Bluetooth Low Energy) could be used for a much longer distance but at the cost of excessive loss. In this work, we utilized the body channel communication (BCC) technology, which are recently gaining increasing attentions in implantable medical devices [12]–[17]. Specifically, mHBC [12], [13] was chosen in this work to utilize its: 1) much lower path loss compared to galvanic or capacitive BCC approaches, and 2) robustness against environmental effects and gesture changes.

To characterize the mHBC channel from the wrist to the implant location under different gestures, similar to [12], the maximum available gain (MAG) was measured to find the path loss assuming ideal matching. For the wrist device, an in-house fabricated 3-turn coil using 24 AWG magnetic wire was employed. For the receiving coil at the palm / fingertip, a 7-turn PCB coil with 8mil-wide traces implemented on a 1cm-by-1cm FR4 board was used, as shown in Fig. 2(a). Two hand gestures were measured, where in the “straight” case, the receiving coil was attached to an open palm and in the “bent” case, the thumb and middle fingertips were in touch. The measurement results are shown in Fig. 2(b), which indicates a best-case path loss of 11 dB to 18 dB for the three different receiving coil locations and two hand gestures. The gesture induced path loss variation is smaller than 1.8dB. Both forward and backward MAG were measured and showed a good agreement. Coupling through air was measured for the same coil distance and relative positions, which shows more than 12dB higher path loss compared to mHBC. Note that compared to the results reported in [12] and [13], despite shorter distance, the path loss in this case increases slightly, which can be mainly attributed to the much smaller receiving coil size as it affects the amount of magnetic flux captured.

Fig. 2.

(a) Receiving coil. (b) The mHBC channel loss characterization, where the maximum available gain from the wrist to the implant location were measured for different hand gestures and receiver locations.

As suggested by Fig. 2(b), compared to the 7MHz/10MHz band that was utilized in [8], a higher wireless frequency (i.e. 20 – 45MHz) offers further reduced path loss (about 8dB better). Therefore, besides the chip presented in [8], this paper also presents the demonstration of a second chip that has a similar architecture but a modified design to exploit a higher communication frequency (i.e. 33MHz/35MHz) to further reduce the minimum required transmitted power from the wrist device as well as the on-chip transmitter power consumption. The chip presented in [8] will be referred to as IAM1 throughout this paper. The second chip with modified design will be referred to as IAM2.

III. Chip Implementation

Fig. 3 shows the block diagram of the proposed mHBC wireless interface chips (both IAM1 and IAM2 as they have a similar architecture), where the fabricated sensor functions as a tactile sensing mechanoreceptor and an interface IC reads and quantizes the sensor output and wirelessly transmits the results. The proposed mHBC wireless interface IC includes an on-chip power management unit (PMU), which regulates the power received from the mHBC channel and generates stable supplies for the analog (${\text{AV}}_{\text{DD}}$) and digital (${\text{DV}}_{\text{DD}}$) circuitries. A capacitance to time converter (CTC) is implemented to read the force sensor output. A data hub quantizes the CTC output (${\text{V}}_{\text{PWM}}$) and generates the output bitstream from the CTC output, the CTC channel information (“#CH”), and the power monitor system output (${\text{V}}_{\text{alarm}}$). The output bitstream is wirelessly transmitted out using a configurable OOK/FSK transmitter. An on-chip clock generator creates clock signals at different frequencies for the CTC, the data hub, and the transmitter. Three off-chip capacitors are used, where ${\text{C}}_1$ and ${\text{C}}_2$ are used for DC blocking between the PMU and the transmitter, and ${\text{C}}_3$ is used for impedance matching. To reduce the system size, the power and data links are frequency multiplexed enabling utilization of a single mHBC coil for both power transfer and data transmission.

Fig. 3.

Block diagram of the proposed implantable artificial mechanoreceptor.

A. Power Management Unit

Fig. 4 shows the circuit schematic of the PMU, which consists of a voltage doubler rectifier that converts the AC input power from the mHBC channel to a boosted DC supply, a bandgap reference that generates a temperature independent reference voltage, two voltage regulators for ${\text{AV}}_{\text{DD}}$ and ${\text{DV}}_{\text{DD}}$ generation, and a pair of power monitors that sense the input power levels. The same PMU design is used for both IAM1 and IAM2 chips.

Fig. 4.

Circuit schematic of the on-chip power management unit and device sizes (start-up circuit for the bandgap reference is not shown).

To improve the power conversion efficiency (PCE) of the voltage doubler rectifier, diodes ${\text{D}}_1$ to ${\text{D}}_4$ are implemented as diode-connected native NMOS devices with a near-zero threshold. The body terminals of those devices are tied to chip ground (GND). To prevent latch-up, as shown in Fig. 5, (1) PMOS and NMOS devices were placed with a relatively large separation in the layout, (2) the substrate resistance was increased by inserting natively doped isolation areas between transistors, and (3) rather wide $n^{+}$ guard rings around PMOS devices and $p^{+}$ guard rings around NMOS devices were implemented.

Fig. 5.

Layout of devices M₁, M₂, D₁ and D₂ in the rectifier.

Devices in the rectifier (shown in Fig. 4) are sized to achieve the highest PCE given a simulated fixed load resistance of 10 kΩ. In IAM1, the charge pump capacitors, ${\text{C}}_{\text{CP1}}$ and ${\text{C}}_{\text{CP2}}$, are chosen based on the input voltage swing, the input frequency, and the expected output power. For IAM2, since the power link frequency is higher (compared to that of IAM1), ${\text{C}}_{\text{CP1}}$ and ${\text{C}}_{\text{CP2}}$ can be decreased without sacrificing the PCE. However, to utilize a similar chip floorplan, ${\text{C}}_{\text{CP1}}$ and ${\text{C}}_{\text{CP2}}$ in IAM2 remain the same as in IAM1 at no PCE penalty. A 1.2 nF on-chip bypass capacitor, ${\text{C}}_{\text{BP1}}$, is placed at the rectifier output to suppress the output ripple and reduce sudden voltage changes. This capacitor is realized using stacked MOS and MIM structures to save chip area, achieving a capacitance density of approximately 10 $\text{fF}/\mu {\text{m}}^2$. Overvoltage protection circuits are implemented at both input and output of the rectifier. Fig. 6(a) shows the simulated PCE for various input power levels and load resistances. For a source resistance of 550 Ω (estimated based on the coil quality factor), an input frequency of 7 MHz (i.e. corresponding to the power link frequency of IAM1), an input power of 500 $\mu \text{W}$, and a load resistance of 10 kΩ, a rectifier PCE of 70% and an output ripple voltage of 5.5 ${\text{mV}}_{\text{pp}}$ are simulated. Fig. 6(b) shows the simulated PCE vs. input power for different process corners. For fast NMOS corners (“fs” and “ff”), PCE drops considerably since the native NMOS devices exhibit a negative threshold voltage leading to increased reverse leakage current. Note that the DC output voltage $\left({\text{V}}_{\text{out}}\right)$ of the rectifier can be calculated given the input power $\left({\text{P}}_{\text{in}}\right)$, the PCE, and the load resistance $\left({\text{R}}_{\text{load}}\right)$ in Fig. 6(a) and Fig. 6(b):

$$V_{out}=\sqrt{P_{in}\cdot PCE\cdot R_{load}}$$ (1)

An on-chip bandgap reference (BGR) consuming 4.1 $\mu \text{W}$ is used to generate the reference voltage for the regulators. For the ${\text{AV}}_{\text{DD}}$ regulator, a medium threshold PMOS pass transistor is used and it is designed such that the dominant pole in the feedback loop is placed at the regulator output. For the ${\text{DV}}_{\text{DD}}$ regulator, a native NMOS pass transistor is used and the regulator is designed such that the dominant pole is placed at the op-amp output. As a result, the ${\text{AV}}_{\text{DD}}$ regulator shows higher loop gain and thus better line regulation, while the ${\text{DV}}_{\text{DD}}$ regulator has a better power efficiency, load regulation, and remains stable as the load resistance varies. The simulated and measured regulator outputs for different input voltages are shown in Fig. 7, where for an input range of 1.4 V–2 V, a line regulation of 4.3 mV/V and 21.1 mV/V were achieved for ${\text{AV}}_{\text{DD}}$ and ${\text{DV}}_{\text{DD}}$ regulators, respectively. Measured load regulations under a 1.8V supply, is 55.0 mV/mA (for an output current of 15 – 115 $\mu \text{A}$) and 4.8 mV/mA (for an output current of 20 – 420 $\mu \text{A}$), compared to a simulated 60.8 mV/mA and 5.8 mV/mA for the ${\text{AV}}_{\text{DD}}$ and ${\text{DV}}_{\text{DD}}$ regulators, respectively. Simulated PSRR for both regulators (including the BGR) is higher than 60 dB at the ripple frequency (14 MHz for IAM1). Large on-chip bypass capacitors, ${\text{C}}_{\text{BP}2}$ to ${\text{C}}_{\text{BP}4}$, implemented using stacked MOS and MIM structures, are placed at the BGR and regulator outputs.

Fig. 6.

Simulated power conversion efficiency of the voltage doubler rectifier for (a) different input power and load resistances, and (b) different input power and process corners.

Fig. 7.

Simulated and measured regulator outputs for different input voltages.

As suggested by the measurement results in Fig.2, the path loss variation between a straight and bent hand can be as large as 1.8 dB. In addition, considering surrounding environment and PVT variation induced uncertainties, an adaptive wireless power transfer scheme was implemented to ensure full operation of IAM under all circumstances. This is achieved by a closed-loop power management system [9], [10], where a pair of on-chip power monitors (Fig. 4, top middle) are used to compare the divided rectifier output voltage to a fixed reference voltage (generated by the BGR). A low voltage threshold of 1.48V, which is slightly higher than the minimum input of the regulators, and a high voltage threshold of 1.90V, which is slightly lower than the device breakdown voltage, were chosen. Two generated bits, ${\text{V}}_{\text{H}}$ and ${\text{V}}_{\text{L}}$ (indicating an input power that is too high or too low, respectively), are wirelessly transmitted back to the base unit, where the radiated power is adjusted accordingly.

B. Clock Generator

An on-chip clock generator is implemented to create various frequencies required by different circuit blocks: the clock used for quantizing the CTC output $\left(f_{\text{quantizer}}\right)$, the carrier frequency of the transmitter $\left(f_{\text{carrier}}\right)$, the output bit rate $\left(f_{\text{data}}\right)$, and the clock signal used to switch between different CTC channels $\left(f_{\text{switch}}\right)$. This is achieved by implementing a relaxation oscillator followed by a digital frequency divider chain, as shown in Fig. 8. A relaxation oscillator is chosen in this work since compared to an LC oscillator, its area is significantly smaller when generating a sub-100 MHz clock while exhibiting robust frequency stability in presence of temperature variations. For instance, by using resistors with complementary temperature coefficients (TC), the temperature response of the timing resistors can be compensated to the first order [18]. A similar temperature compensation strategy is utilized for the clock generator, where the temperature response of the inverter-based comparators is also considered. As a result, under the typical process corner, the frequency response of the relaxation oscillator would be temperature compensated (to the first order) since the temperature-induced variations of ${\text{R}}_1$ to ${\text{R}}_4$ will counter-balance the temperature-induced threshold voltage variations in comparators. The measured effect of temperature variations on the performance of the implemented relaxation oscillator is shown in Fig. 9, where a worst case of 170 ppm/°C among 5 measured chips was observed. Note that since the chip is designed to operate as an implantable device, the measurement was done for the temperature range of 10 – 50 °C, which is sufficient for the intended application.

Fig. 8.

Schematic of the clock generator and its output frequencies.

Fig. 9.

Measured temperature response from 5 samples of the proposed relaxation oscillator and post-layout simulated response with (black) and without (blue) temperature compensation.

Due to its free-running operation, the relaxation oscillator in the clock generator suffers from process variation induced frequency uncertainty. Although measurement results in Fig. 9 suggests a chip-to-chip variation as large as 4.5%, simulations under different process corners show a maximum variation in the range of −29% (“ss” corner) to +41% (“ff” corner). This frequency uncertainty affects different system blocks and potentially leading to (1) variations of the on-chip CTC quantizer, which can be effectively suppressed by the CDS technique (see section C), (2) variations in the frequency of clock signals of digital circuitry, which is systematic (since all clock signals are generated by dividing down $f_{\text{quantizer}}$) and thus has a negligible effect on the digital logic, (3) variations of the data rate (i.e. $f_{\text{data}}$), which is addressed through receiver calibration performed in the base unit resulting in data synchronization, and (4) variations of the frequency of the data carrier signal (i.e. $f_{\text{carrier}}$), which suggests that the frequency of the power link signal (generated in the base unit) should be tuned to maintain a proper frequency separation between the power link and data link. A one-point calibration [18] can be used to further suppress this frequency uncertainty.

C. Capacitance to Time Converter

A CDS CTC is implemented to convert the output of the custom capacitive force sensor to a pulse width modulated waveform, V_PWM. As shown in Fig. 10(a), the CTC is essentially a relaxation oscillator that functions as a time-domain correlated double sampler, which alternatively charges an on-chip reference capacitor $\left({\text{C}}_{\text{REF}}\right)$ and an off-chip unknown capacitor $\left({\text{C}}_{\text{X}}\right)$ to the same threshold (set by the inverter-based comparator) through the same timing resistor $\left({\text{R}}_{\text{T}}\right)$. Timing diagram of the CTC is shown in Fig. 10(b). The time needed to charge ${\text{C}}_{\text{REF}}$ is written as

$$T_{REF}=R_T{C}_{REF}\ln \left(\frac{V_{DD}}{V_{DD}-V_{TH}}\right),$$ (2)

where $V_{DD}$ is the analog supply $\left(A{V}_{DD}\right)$ and $V_{TH}$ is the threshold voltage of the comparator, and the time needed to charge ${\text{C}}_{\text{X}}$ is written as

$$T_X=R_T{C}_X\ln \left(\frac{V_{DD}}{V_{DD}-V_{TH}}\right).$$ (3)

Using (1) and (2), the value of ${\text{C}}_{\text{X}}$ can be calculated as

$$C_X=T_X/T_{REF}\times C_{REF}.$$ (4)

An inverter-based comparator is chosen for its low power and simplicity. The transistor sizes, as shown in Fig. 10(a), are chosen considering the trade-off between their flicker noise contribution and parasitic capacitance. A start-up circuit is implemented to ensure oscillation start-up when the circuit is upon powered-on.

Fig. 10.

(a) Schematic of the correlated double sampling capacitance to time converter. (b) Timing diagram of the CTC. (c) Time-multiplexed mode enabling the CTC to interface with a capacitive shear force sensor.

A counter-based on-chip quantizer is implemented in the data hub to quantize the CTC output. Specifically, ${\text{T}}_{\text{REF}}$ and ${\text{T}}_{\text{X}}$ are quantized separately and transmitted to the base unit. The MCU in the base unit calculates ${\text{C}}_{\text{X}}$ using (4). Knowing the on-chip quantizer frequency, $f_{\text{quantizer}}$, the LSB capacitance can be calculated as

$$C_{LSB}=1/\left(f_{quantizer}{R}_T\ln \left(\frac{V_{DD}}{V_{DD}-V_{TH}}\right)\right),$$ (5)

suggesting that to achieve a smaller quantization error, $f_{\text{quantizer}}$ and ${\text{R}}_{\text{T}}$ should be increased. Considering this fact, the frequency of the clock generator in IAM2 (Fig. 8) is increased while a larger timing resistor ${\text{R}}_{\text{T}}$ is used (Fig. 10(a)). Furthermore, given the smaller capacitance of the fabricated second generation capacitive force sensors, the on-chip reference capacitor ${\text{C}}_{\text{REF}}$ is reduced in IAM2 for a better matching between ${\text{C}}_{\text{REF}}$ and ${\text{C}}_{\text{X}}$.

By adding a switch matrix and the related control logic, the proposed CTC can be configured to operate in a time-multiplexed mode to read 4 different input capacitors, as shown in Fig. 10(c). In this mode, 2 out of 4 unknown capacitors (sharing the same floating bottom plate, and hence configured as two series capacitors) are sensed. Note that the floating bottom plate is not accessible to the chip due to the sensor design and fabrication process, as explained in Section IV.D. In this case, by measuring 4 sets of series capacitor pairs the value of individual capacitors can be calculated. A clock ($f_{\text{switch}}=1.22\text{kHz}$ in IAM1 and $f_{\text{switch }}=1.01\text{kHz}$ in IAM2) is used for channel selection, resulting in an effective sampling rate higher than 250 Hz. This time-multiplexed mode allows the CTC to interface with a capacitive shear force sensor (Fig. 10(c) left), which uses 4 varying capacitors to measure both the magnitude and direction of the applied force.

By utilizing the CDS technique, the proposed CTC suppresses any capacitance uncertainty caused by PVT variations as well as the low frequency noise (e.g. flick noise of the comparator). Fig. 11 (left y axis, black squares) shows the measured CTC output (in IAM1) in the single channel mode for a set of fixed input capacitors $\left({\text{C}}_{\text{IN}}\right)$, where the error bars show the standard deviation (SD) ×1000. Note that the SD of the CTC output (which sets the CTC resolution) is calculated from averaged output capacitance in multiple (>5000) 1 ms windows, corresponding to the length of the CTC switching period. The CTC oscillation frequency as a function of ${\text{C}}_{\text{IN}}$ is also shown in Fig. 11 (right y axis, red circles). Note that for CTC output measurements, an off-chip quantizer with a sample-rate of 1 GS/s is used to digitize the CTC output pulse width. As shown, the SD of the CTC output increases as ${\text{C}}_{\text{IN}}$ increases, since (1) the CTC oscillation frequency drops with increased ${\text{C}}_{\text{IN}}$, as a result, the effect of CDS becomes weaker, leading to reduced noise suppression effect and increased noise foldover, (2) as the CTC oscillation frequency drops, the oversampling ratio (OSR) inside the 1ms windows also drops, and (3) as ${\text{C}}_{\text{IN}}$ increases, the output timing error of the oscillator increases [18]. For ${\text{C}}_{\text{IN}}=68\text{pF}$, the CTC resolution of 2.6 fF is measured. When ${\text{C}}_{\text{IN}}$ is increased to 330 pF the measured CTC resolution changes to 23.9 fF. A similar measurement was performed using the on-chip quantizer, in which case the output capacitance value and sampling rate remain the same, but the SD of the CTC output is increased (or equivalently the CTC resolution is decreased) due to the additional quantization error. In this case, when ${\text{C}}_{\text{IN}}$ changes from 68 pF to 330 pF, the measured CTC resolution changes from 5.3 fF to 53.1 fF. To find the CTC linearity, a four-point test was performed, where by using ${\text{C}}_{\text{IN}}=13\text{pF}$, 16 pF, 13 + 300 pF, and 16 + 300 pF, the linearity was measured to be 11.2 bits. All the measurements were performed using the on-chip generated supplies (${\text{AV}}_{\text{DD}}$ and ${\text{DV}}_{\text{DD}}$). Measured CTC performance in IAM2 will be summarized in section IV.

Fig. 11.

Measured CTC output, standard deviation (×1000), and oscillation frequency for different input capacitors. Note that standard deviation is calculated from averaged output capacitance in 1 ms sampling windows.

To investigate the capacitance read-out performance over process variation, the on-chip quantized CTC (in IAM1) output for 15 chips were measured (Fig. 12(a)). Considering all ${\text{C}}_{\text{IN}}$ cases, the raw data shows a 3.27% maximum difference between any two chips, which can be mainly attributed to the variations in the on-chip reference capacitor (${\text{C}}_{\text{REF}}$ in Fig. 10(a)). If a one-point calibration is performed, i.e. scaling the data points of each chip such that the output of all chips at ${\text{C}}_{\text{IN}}=200\text{pF}$ are equal, the maximum difference between any two chips under all ${\text{C}}_{\text{IN}}$ cases is reduced to 0.54%. Fig. 12(b) shows the measured CTC oscillation frequency for the same 15 chips, where an 8.59% maximum difference between any two chips was found. As expected, the oscillation frequency exhibits larger variation than the CDS based capacitance readout process. However, while this level of variation affects the effective sampling frequency accuracy, it has a negligible effect on the system performance given the relaxed timeline in sensor read-out and also the large time margin available for data transmission (as explained in section D). Fig. 13 shows the measured temperature response of the on-chip quantized CTC output in IAM1. For an input capacitance of 47 pF, a +65.2 ppm/°C TC was measured while without CDS, the TC of −1406.6 ppm/°C was measured. The TC of the CDS CTC is mainly affected by the TC of ${\text{C}}_{\text{REF}}$, which is implemented as a MIM structure.

Fig. 12.

Measurement results from 15 chips: (a) on-chip quantized CTC output and (b) CTC oscillation frequency.

Fig. 13.

Temperature response of the CTC output quantized using the on-chip quantizer.

D. System Timing

Fig. 14 shows the system timing diagram of IAM1 in the time-multiplexed CTC mode. The 40 MHz signal $\left(f_{\text{quantizer}}\right)$ generated within the clock generator circuit (Fig. 8) serves as the clock for the on-chip quantizers that digitize the CTC output (${\text{T}}_{\text{REF}}$ and ${\text{T}}_{\text{X}}$). The frequency of this clock signal, $f_{\text{quantizer}}$, is also divided down to 1.22 kHz, which is used to switch between the 4 input channels of the CTC. To ensure that the input capacitor is correctly sensed and fully discharged, a minimum discharge time is set (Fig. 14, $t1=3.2\mu s$) and the input channel switching takes place while the on-chip reference capacitor is being sensed. Output data transmission occurs during the time that the reference capacitor is being sensed (i.e. ${\text{T}}_{\text{REF}}$). Note that ${\text{T}}_{\text{REF}}$ remains nearly constant (Fig. 14, $t2\approx 55\mu s$). Triggered by every falling edge of the CTC output (Fig. 14, $t3=1\mu s$), a 33-bit output bitstream is transmitted. The first bit is a flag that is always “1”, indicating the onset of data transmission. The 2^nd and 3^rd bits are the power monitor output bits from the PMU, indicating the received wireless power level. The 4^th and 5^th bits are the CTC input channel number. The remaining two 14-bits segments are the quantized ${\text{T}}_{\text{REF}}$ and ${\text{T}}_{\text{X}}$, respectively. Since the data is transmitted at a bit rate of 1.25 Mbps, each output bitstream requires about $27\mu \text{s}$ (Fig. 14, $t4\approx 27\mu s$) to be transmitted, which is about half of the duration of ${\text{T}}_{\text{REF}}$. This enables reliable data transmission even in presence of the CTC oscillation frequency variations discussed in part C. The chip output remains “0” between two data transmission events. IAM2 uses a similar timing diagram with different clock frequencies (as shown in Fig. 8).

Fig. 14.

System timing diagram of IAM1.

E. Data Hub and Transmitter

Fig. 15 shows the schematic of the data hub and the transmitter. The data hub is implemented to synchronize the system operation and generate the output bitstreams. Two 14-bit counters, configured in a ping-pong buffer fashion, are used to quantize the CTC output.

Fig. 15.

Simplified schematic of the data hub and transmitter.

Since the signal phase within the mHBC channel strongly depends on the gesture, it is not desirable to employ phase-based modulation schemes [13]. Therefore, the transmitter of the proposed system (for both IAM1 and IAM2) was designed such that it can be configured for either OOK or FSK formats. Since in the OOK mode, the transmitter remains idle for about 87.5% of the time (Fig. 14, assuming ${\text{C}}_{\text{IN}}={\text{C}}_{\text{REF}}$ and, on average, half of the transmitted bits are “0”), the average power consumption drops significantly resulting in a high power efficiency. In the FSK mode, since the information is encoded in the frequency of the carrier, the data link is more robust against path loss variations. Unlike operation in OOK mode, the transmitter is always on for FSK mode resulting in power consumption that is 8 times larger than that of the OOK mode.

For the case that IAM1 (IAM2) operates in the OOK mode, ${\text{f}}_{\text{quantizer}}=40\text{MHz}$(66 MHz) is divided by four (two) to generate the 10 MHz (33 MHz) carrier, which is amplitude modulated by the output data using a switch placed before the coil driver. For the case that IAM1 is configured in the FSK mode, ${\text{f}}_{\text{quantizer}}$ is divided by 4 (representing logic “0”) or by 5 (representing logic “1”), resulting in FSK carrier frequencies of 10 MHz and 8 MHz, respectively. In the case that IAM2 operates in the FSK mode, carrier frequencies of 33 MHz and 22 MHz (corresponding to division ratios of 2 and 3) represent logic “0” and logic “1”, respectively.

Note that the base unit power consumption is dominated by the power consumption of its transmitter, which relaxes the power consumption requirement for the base unit receiver, allowing for a design with a higher receiver sensitivity at a negligible base unit total power consumption penalty. Given the mHBC channel loss (Fig. 2(b)), a higher sensitivity of the base unit receiver enables implementation of highly efficient IAM transmitters.

In OOK mode, the transmitter power consumption in IAM1 (transmitting at 10 MHz) and IAM2 (transmitting at 33MHz) is 15.6 $\mu \text{W}$ and 7.8 $\mu \text{W}$, respectively. Note that lower transmitter power consumption in IAM2 is the direct result of lower mHBC path loss at 33MHz, as suggested by Fig. 2(b).

Besides the mHBC path loss and matching network loss, other factors contribute to the total link loss. Simulations show that, within the IAM, about 25% of the transmitter output power is dissipated in the rectifier. Also, a part of the received power in the base unit is dissipated in the base unit transmitter. Considering the total link loss, simulation shows that a 7.8 $\mu \text{W}$ average transmitter power in IAM2 ensures a higher than −50 dBm received power at the base unit receiver, which can be amplified using a typical commercially available LNA to form a reliable link.

Note that, when operating in the OOK mode, data transmission will result in a temporary voltage drop on the ${\text{DV}}_{\text{DD}}$ power line since the transmitter draws extra current. Simulation for IAM2 shows that the maximum voltage drop during one transmission event is about 100mV. However, this has a negligible effect on the system performance as supply sensitive blocks are not powered by ${\text{DV}}_{\text{DD}}$.

IV. System Measurement Results

A. Chip Summary

The proposed mHBC wireless interface chip was fabricated in a standard 180nm CMOS process. The microphotograph of IAM1 and IAM2 chips are shown in Fig. 16(a) and 16(b), respectively. Both chips have an area of 1.62 mm² including pads. The two chips share a similar floorplan, where close to half of the chip area is occupied by the 4 bypass capacitors in the power management unit. Fig. 17(a) and Fig. 17(b) presents the chip power breakdown for IAM1 and IAM2, respectively.

Fig. 16.

Chip microphotographs for (a) IAM1, and (b) IAM2.

Fig. 17.

Chip power breakdown for (a) IAM1, and (b) IAM2.

B. CTC Performance Summary and Comparison

Table I summarizes the measured performance of the proposed CDS CTC in both IAM1 and IAM2 and provides a comparison with prior works. The CTCs were measured in two different set-ups. In the first set-up the raw CTC outputs in the pulse width format (i.e. ${\text{V}}_{\text{PWM}}$) were digitized using an off-chip 1 GS/s logic analyzer and in the second set-up the on-chip quantizer in the data hub was used to generate the digital output. The CTC resolution in both cases is calculated as the standard deviation of the measured raw data points (i.e. OSR = 1). For IAM1, measured raw CTC outputs have a fractional error (i.e. ${\text{C}}_{\text{resolution}}/{\text{C}}_{\text{IN}}$) of around 1/10000 when CIN ≥ 68 pF. With the on-chip quantizer power consumption included, the proposed capacitance read-out circuit consumes 3.9 $\mu \text{W}$ in IAM1 and 4.79 $\mu \text{W}$ in IAM2 (with a higher quantizer clock frequency). A linear input capacitance range of 360 pF and 39 pF for IAM1 and IAM2 were achieved, respectively. For IAM1, the best CTC FoM of 70 fJ/c-s is measured which increases to 500 fJ/c-s when the on-chip quantizer is used (where both the power consumption and output noise increase). For IAM2, the best CTC FoM of 49 fJ/c-s is measured which increases to 482 fJ/c-s when the on-chip quantizer is used. All the measurements used the on-chip generated supplies (${\text{AV}}_{\text{DD}}$ and ${\text{DV}}_{\text{DD}}$). Both CTCs occupy a chip area of only 0.04 mm². Considering the time-multiplexed mode, the area per channel is 0.01 mm². Compared to previously published capacitance read-out circuits, both CTCs achieve one of the lowest power consumptions (1.5 $\mu \text{W}$ and 750 nW), while CTC in IAM1 achieves one of the largest input ranges (360 pF). Among designs that have pulse width output format, both proposed CTCs achieve the lowest FoM (70 fJ/c-s and 49 fJ/c-s). The designs also achieve the smallest area per channel (0.01 mm²).

TABLE I.

CTC Performance Comparison with Prior Works

Publication	[19] TCAS 2018	[20] CICC 2017	[21] ISSCC 2019	[22] JSSC 2019	[23] ESSCIRC 2011	[24] JSSC 2012	[25] ISSCC 2020	This work, IAM1		This work, IAM2
Output format	Digital	Digital	Digital	Digital	Pulse width	Pulse width	Pulse width	Pulse widtha	Digitalb	Pulse widtha	Digitalb
Number of channels	2	1	1	1	1	1	16 (+ 16R)	4
Power per channel (μW)	15	50.4	3.32	2.92	0.27	211	2.2	1.5 c	3.9c	0.75 c	4.79c
Input range (pF)	1~10000	10	5	18.12	5.7	50	100	360		39
Meas. time @ input cap	128μs @2pF	125μs	12.5μs	850μs	1ms @5.7pF	7.6ms @6.8pF	1ms	132μsc @68pF	169μsc @100pF	132μsc @14pF	154μsc @18pF
Resolutiond @ input cap	0.2fF @2pF	0.4fF (a)10pF	0.29fF @5pF	1.24fF ®17.1pF	6.1bit @5.7pF	15bit @6.8pF	13.75fF @16pF	7.2fF @68pF	21.4fF @100pF	2.0fF @14pF	3.4 fF @18pF
FoM (fJ/c-s)	230	840	16	660	2100	49000	870	70	500	49	482
Area per channel (mm2)	0.11	0.42	0.06	0.76	0.07	0.51	0.04	0.01		0.01
Process (nm)	180	180	40	180	130	350	130	180

^aMeasured using CTC + off-chip quantizer

^bMeasured using CTC + on-chip quantizer

^cMeasured in the single-channel mode

^dThe CTC resolution is calculated as the standard deviation of the measured raw data points.

C. System Wireless Demonstration

Fig. 18 shows the setup for the system wireless demonstration. A base unit PCB is designed, which includes an oscillator to generate the carrier for wireless power link, a class C power amplifier (with a simulated efficiency higher than 80%), an LC notch filter to reject the power link carrier interfering with the data link carrier, an LNA, and baseband circuitry. The chip is mounted and wire-bonded to a 1cm-by-1cm FR4 board with trace coil implemented on the bottom layer. Four ceramic capacitors were used to emulate a shear force sensor (Fig. 10(c) left) when testing the CTC in the time-multiplexed mode. Single ceramic testing capacitor of different values is used when testing the CTC in the single channel mode.

Fig. 18.

Wireless test set-up.

As discussed in Section III. B, effect of process variations on the on-chip clock generator may lead to uncertainties in the data rate and data carrier frequency. To compensate for the data rate uncertainty, for both IAM1 and IAM2, the data rate is calibrated in the receiver of the base unit. To compensate for the data carrier frequency variations, the power link frequency is tuned in the base unit to maintain a sufficient frequency separation between the data link and the power link. In the case of IAM1, this frequency tuning is not necessary due to a large enough frequency separation between the data and power links. Note that the coil in IAMs has a relatively wideband response due to its limited quality factor (∼8 for IAM1 and ∼20 for IAM2).

Fig. 19(a) shows the wirelessly received chip output for the case that the IAM1 (operating in OOK format) and base unit are separated by 2 cm and the coils are coupled through air. As shown in the top right waveform, the CTC switches between the 4 input channels (“CH1” to “CH4”), resulting in different CTC oscillation frequencies. Two consecutively received bitstreams, one for the last sample of channel 2 and the subsequent one for the first sample of channel 3, are shown on the left of Fig. 19(a). The quantized capacitance output is calculated (on the bottom right) and compared with the input test capacitors, which matches well given the tolerance of the capacitors. Similar measurements were performed for another chip (with a different set of test capacitors) configured in the FSK mode and the results are shown in Fig. 19(b).

Fig. 19.

Wirelessly received chip outputs for IAM1 in (a) OOK mode, and (2) FSK mode.

The proposed mHBC wireless interface chips were also demonstrated on human body. In this case, the 1cm-by-1cm PCB (with IAM1 operating in the OOK mode) is attached to the surface of the palm (Fig. 20(a), right). Test capacitors with different values were used. Two custom coils made using 24 AWG magnetic wires are used as the power radiator (worn on the wrist) and data receiver (worn on the little finger), respectively. Note that a single coil can also be used for both powering and data receiving (Fig. 18). The received waveforms for IAM1 are shown in Fig. 20(a), where a good agreement between the quantized capacitance value and the actual input capacitor value is observed. Similar measurements were performed for IAM2 (Fig. 20(b)). For IAM1, the estimated radiated power from the wrist is 200 mW and for IAM2, due to a lower path loss, the estimated radiated power from the wrist is 30 mW.

Fig. 20.

Human body demonstration for the proposed (a) IAM1, and (b) IAM2, both configured in the single input channel mode.

D. Sensor Fabrication

A MEMS capacitive normal force sensor is fabricated for the proposed tactile sensing system. The sensor (Fig. 21) consists of two fused silica layers: a top diaphragm with a cavity with a circular electrode at the bottom of the cavity; and a bottom substrate with two semi-circular electrodes on the top of the bottom substrate. Therefore, the resulting two capacitors are connected in series (by the top electrode plate). To measure the capacitance of this series-connected capacitor, the electrodes on the bottom substrate are electrically connected to underlying pads. When there is a normal force applied in the middle of the top diaphragm, the deflection of this top diaphragm causes a decrease of distance between the top electrode and the bottom electrodes. As a result, the capacitance of the two serial capacitors increases as the applied normal load increases.

Fig. 21.

Schematic of the proposed capacitive force sensor.

The sensor fabrication process is comprised of three parts, as illustrated in Fig. 22. The first part is fabrication of the bottom substrate with two semi-circular electrodes, feedthroughs and pads. Two electrode pads on the bottom surface of the substrate are fabricated by copper electroplating through a photolithographically-fabricated mold. Excimer laser micromachining is utilized to form feedthrough vias, which are subsequently filled by electroplated copper. A titanium film is then deposited and patterned into two semicircular bottom electrodes, electrically connected by the feedthroughs to the pads. The second part is fabrication of the diaphragm. A circular cavity is formed in the top diaphragm utilizing reactive ion etching (RIE). To fabricate the circular top electrode, a titanium layer is deposited and patterned using lift-off. To complete the sensor, a simultaneous localized fusion bonding and dicing of the diaphragm and substrate layers are achieved using carbon dioxide (CO₂) laser-assisted technology [26], [27].

Fig. 22.

Sensor fabrication process. (a) wafer cleaning and Ti/Cu seed layer deposition; (b) lithography patterned mold for pads; (c) electroplate pads; (d) ablate feedthroughs using excimer laser; (e) electroplate feedthrough vias; (f) Ti deposition; (g) lithography patterned photoresist; (h) RIE etching cavity; (i) spray coating; (j) lithography patterned photoresist; (k) Ti deposition; (l) localized fusion bonding.

Fig. 23 shows the fabricated silica-based capacitive sensor prototype. Fig. 23(a) presents a top view of the sensor with an overall diameter of 5 mm. The dark circular region visible in the center is the titanium electrode on the top diaphragm as viewed through the upper silica layer. Fig. 23(b) shows a bottom view of the sensor. Two pads are electrically connected by feedthroughs to the electrodes on the bottom substrate.

Fig. 23.

Fabricated silica-based capacitive sensor prototype.

The fabricated sensor was characterized using the proposed interface chip. A Bose ElectroForce 3200 mechanical loading system is used to characterize the IAM for different applied static and dynamic normal forces. As shown in Fig. 24(a), the capacitance, as determined by the chip output, varies according to the applied static force of different values. The sensor capacitance monotonically increases over the applied force range of 0–2 N due to diaphragm deflection and saturates thereafter due to operation of the sensor in the touch mode, as expected. Measurement result of a dynamic force load, where a 1 Hz sinusoidal force in the range of 0–2 N is applied to the sensor, is shown in Fig. 24(b).

Fig. 24.

Sensor characterization using the proposed interface IC for (a) fixed force load, and (b) dynamic force load.

Table II presents a comparison of the proposed system to some previously published integrated wireless biomedical systems. By utilizing the low loss mHBC channel, the proposed system achieves both wireless power transfer and data uplink with an average transmitter power of only 15.6 $\mu \text{W}$ / 7.8 $\mu \text{W}$ in the OOK mode. The proposed chips have a low power consumption of 104.3 $\mu \text{W}$ / 110.3 $\mu \text{W}$ and small area of 1.62 mm². The IAM chip is hybrid-integrated with the in-house fabricated force sensor.

TABLE II.

System Performance Comparison with Prior Works

Publication	Application	Integrated sensor	Power link / freq. band	Data link / freq. band	PCE (%)	Supply (V)	Chip power (μW)	Mod. scheme	TX power (μW)	Area (mm2)	Process (nm)
[9] JSSC’ 09	Blood pressure sensing	Y	Inductive coupling / 4MHz	RF telemetry /433MHz	\	2	300	FSK	240	4.84	1500
[10] ISSCC’10	Neural recording	N	Inductive coupling / 13.56MHz	RF Telemetry /915MHz	80.2	3	5800	FSK	3300	16.17	5000
[28] JSSC’18	Pressure sensing	Y	Ultrasonic / 790kHz	Ultrasonic /790kHz	55	1.9	900	OOK	100	1.767	180
[29] ISSCC’19	ExG acquisition	N	\	UWB / 14MHz	\	1.2	340.6	FM	112.6	1	65
[30] ISSCC’20	Oxygen sensor	Y	Ultrasonic / 2MHz	Back scattering	\	1.2	140	AM	\	3.84	65
[31] ISSCC’20	PPG recording	N	Capacitive / l~10MHz	\	83.8	1.5/2.5	280	\	\	12	180
[11] ISSCC’20	Neural interface	N	Inductive coupling / 13.56MHz	RF telemetry / 433MHz	82	1.8/3.3/4	20700	OOK	9100	15	350
This work, IAMI	Tactile sensing	Y	mHBC / 7MHz	mHBC / 10MHz	70	1.2	104.3	OOK / FSK	15.6 (OOK)	1.62	180
This work, IAM2			mHBC / 35MHz	mHBC / 33MHz			110.3		7.8 (OOK)

V. Conclusion

This article presents a hybrid-integrated implantable artificial mechanoreceptor system for tactile sensing to recover a sense of touch to a paralyzed hand. The proposed chip is the first wireless sensor interface with both power and data links through mHBC. A 750 nW capacitance to time converter with an area of 0.04 mm² achieving 49 fJ / c-s is proposed. The wireless chip is demonstrated on human body with a 7.8 $\mu \text{W}$ average transmitter power consumption. The system power consumption is only 110.3 $\mu \text{W}$. A MEMS capacitive force sensor is fabricated and characterized using the proposed interface chip.

While the implemented artificial mechanoreceptor is designed to interface with one normal/shear force sensor, the proposed system can be scaled to be used in a multi-site sensing network. For instance, based on the proposed wireless powering and communication architecture, a frequency-domain multiple access protocol [32], [33] can be utilized, enabling multiple implanted chips to communicate with the base unit.

Biographies

Han Hao received the B.Sc. degree in Electrical Engineering from Huazhong University of Science and Technology, Wuhan, China, in 2015, and the M.Sc. degree in Electrical Engineering from University of Pennsylvania, Philadelphia, PA, USA, in 2017. He is currently pursuing the Ph.D. degree in the Department of Electrical and System Engineering at University of Pennsylvania.

His current research interests include CMOS integrated circuit design for biomedical applications as well as CMOS and silicon photonic design for communication. He is the recipient of the 2016–2017 UPenn ESE Graduate Award for Best Master’s Thesis. He is the recipient of 2020 IEEE Radio Frequency Integrated Circuits Symposium student paper award (^1st place).

Lin Du received the B.S. degree in Mechatronics Engineering and the M.S. degree in Mechanical Engineering, both from Beijing Institute of Technology, Beijing, China, in 2012 and 2015, respectively. She is currently a Ph.D. candidate in the Department of Electrical and Systems Engineering at University of Pennsylvania, Philadelphia, PA, USA.

Her research interests include implantable microelectro-mechanical (MEMS) sensors, hermetic packages, micromachining, and its applications for human health monitoring systems.

Andrew G. Richardson (Senior Member, IEEE) received the B.S.E degree in biomedical engineering from Case Western Reserve University, Cleveland, OH, USA in 2000 and the S.M. degree in mechanical engineering and Ph.D. degree in biomedical engineering from the Massachusetts Institute of Technology, Cambridge, MA, USA in 2003 and 2007, respectively.

He was a Senior Fellow at the University of Washington, Seattle, WA, USA from 2008 to 2012 and a Senior Research Investigator at the University of Pennsylvania, Philadelphia, PA, USA from 2012 to 2015. He is currently a Research Assistant Professor of Neurosurgery at the University of Pennsylvania. He has coauthored over 100 journal and conference papers and abstracts. His primary research interest is in brain-machine interfaces.

Dr. Richardson coauthored papers selected for Best Paper Awards at the IEEE International Symposium on Circuits and Systems in 2014 and 2017 and at the IEEE Biomedical Circuits and Systems Conference in 2015. His work was a finalist for the Brain-Computer Interface Award in 2018. He currently serves on the editorial board of Artificial Organs.

Tim Lucas, MD, PhD, MHCI is a board certified neurosurgeon and tenured neuroscientist at the University of Pennsylvania. He completed his clinical training, PhD and postdoc at the University of Washington. He completed his Master’s in Healthcare Innovation at Penn and subspeciality fellowships at the University of California San Francisco.

Dr. Lucas has been recognized with awards from National Medical Honor Society Alpha Omega Alpha (Leadership Fellow), the Wharton School (Mac Technology Fellow), Philadelphia Magazine (Top Doctors), American Brain Tumor Association, Congress of Neurological Surgeons, and Abramson Cancer Center.

Mark G. Allen (F ’11) received the B.A. degree in chemistry, the B.S.E. degree in chemical engineering, and the B.S.E. degree in electrical engineering from the University of Pennsylvania, Philadelphia, and the S.M. and Ph.D. degrees from Massachusetts Institute of Technology, Cambridge. In 1989 he joined the faculty of the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, ultimately holding the rank of Regents’ Professor and the J.M. Pettit Professorship in Microelectronics, as well as a joint appointment in the School of Chemical and Biomolecular Engineering. In 2013 he left Georgia Tech to become the Alfred Fitler Moore Professor of Electrical and Systems Engineering and Scientific Director of the Singh Nanotechnology Center at the University of Pennsylvania. His research interests are in the development and the application of new micro- and nanofabrication technologies, as well as MEMS. He has held the posts of Editor-in-Chief of the Journal of Micromechanics and Microengineering, co-chair of the IEEE MEMS Conference, and is co-founder of multiple MEMS companies, including Cardiomems, Axion Biosystems, and Enachip. He received the IEEE 2016 Daniel P. Noble Award for contributions to research and development, clinical translation, and commercialization of biomedical microsystems, and the 2020 IEEE Benjamin Franklin Key Award.

Jan Van der Spiegel is a Professor of Electrical and Systems Engineering at the University of Pennsylvania. He is former Department Chair of Electrical Engineering, and Associate Dean of Education and Professional Programs of the School of Engineering. He was a Senior Visiting Professor at the Institute of Microelectronics and the Department of Electronics Engineering at Tsinghua University (Sept. 2017 till Feb.2018).

Dr. Van der Spiegel received his Master’s degree in Electro-Mechanical Engineering and his Ph.D. degree in Electrical Engineering from the University of Leuven, Belgium. His primary research interests are in mixed-mode microelectronics circuits, smart CMOS vision sensors for polarization imaging, bio-inspired image sensors and brain-machine interfaces. He is the author of over 250 journal and conference papers and holds 8 patents. He is also the Founding Director of the Rachleff Scholars Program at the Engineering School of the University of Pennsylvania, and Director of the SUNFEST program that offers summer research opportunities to talented students. The SUNFEST program is sponsored by the National Science Foundation.

He is a Life Fellow of the IEEE, a Distinguished Lecturer of the Solid-State Circuit Society, and is the recipient of the IEEE Major Educational Innovation Award in recognition of his groundbreaking work with the SUNFEST program. He received the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the IBM Young Faculty Development Award and the Presidential Young Investigator Award.

He has served on several IEEE program committees (IEDM, ICCD, ISCAS, ISSCC, ASICON) and was the technical program chair of the 2007 International Solid-State Circuit Conference (IEEE ISSCC). He is an Associate Editor of the Transaction of BioCAS, a member of the Editorial Board of the IEEE Proceedings and Section Editor of the Journal of Engineering of Institute of Engineering and Technology (IET). He was the president of the IEEE Solid-State-Circuits Society (2016–2017). He is currently the Conference Chair of the IEEE International Solid-State Circuits Conference (ISSCC).

Firooz Aflatouni (SM’17) received the Ph.D. degree in Electrical Engineering from the University of Southern California, Los Angeles, in 2011. He was a post-doctoral scholar in the Department of Electrical Engineering at the California Institute of Technology before joining the University of Pennsylvania in 2014 where he is an Associate Professor in the Department of Electrical and Systems Engineering. His research interests include electronic-photonic codesign and low power RF and mm-wave integrated circuits. In 1999, he co-founded Pardis Bargh Company where he served as the CTO for five years working on design and manufacturing of inclined-orbit satellite tracking systems. From 2004 to 2006, he was a Design Engineer with MediaWorks Integrated Circuits Inc., Irvine, CA.

Dr. Aflatouni received the 2020 Bell Labs Prize, the Young Investigator Program (YIP) Award from the Office of Naval Research in 2019, the NASA Early Stage Innovation Award in 2019, the 2015 IEEE Benjamin Franklin Key Award, 2011 USC Department of Electrical Engineering best Ph.D. thesis award, and 2010 NASA Tech Award for his work on development of a Ka-Band SiGe receiver MMIC for space transponder applications.