Phase disposition PWM control topology based: A novel multilevel inverter with reduced switch for power electronics applications

Abstract

In the field of industrial drive applications, a neutral point clamped multilevel inverter (NPC MLI) is an extensively used option. The NPC MLI architecture involves more number of components for higher level and higher switching frequency operation. In this work paper, a novel three-phase 3-Level MLI is proposed evading the usage of clamping diodes and quadratic switches. Additionally, phase disposition pulse width modulation (PD-PWM) control technique is also employed for the proposed MLI. In comparison to NPC MLI, proposed MLI reduces the voltage switching stress as only one switch is operated per inverter leg. Another feature is that there is a considerable reduction in power losses as the current flows only through fewer elements. The proposed 3L inverter topology is explored thoroughly using the MATLAB simulation model. The evaluation of results is also demonstrated concerning the proposed PD-PWM technique by comparing its performance with the conventional sinusoidal PWM method. The Real-Time hardware-in-loop (HIL) simulator is also used to validate the simulation outcomes of the proposed model.

1. Introduction

Nowadays, automotive manufacturers are concentrating on pure electric vehicles (EVs), hybrid EVs, fuel-cell EVs, and plug-in hybrid EVs in response to the growing demand for sustainable and fuel-efficient automobiles [1,2]. These automobiles may also meet the power demands due to the rise in the usage of electronic technologies in these vehicles for improving vehicle performance, fuel efficiency, and carbon emissions, along with safety and passenger comfort. The challenges that are faced by the power converters, electric machines, and related electronics in EVs are to attain high efficiency, durability, portability, smaller component size, and cost-effectiveness. Especially in fuel-cell EVs, a power conditioning unit like a DC-DC converter is used to synchronize the fuel cell voltage with the voltage of the battery system to function in challenging environmental circumstances. Also, a fast responding motor, advanced converter topology, and intelligent control technologies are necessary for steer-by-wire and brake-by-wire applications. Additionally, integrating actuators with devices (like power electronics components) increases the system efficiency and reliability, while lowering costs, space, etc. The modern design of the electric motor, in addition to power electronics, has a significant impact on the dynamics of the EVs, and the different types of power converters are needed to regulate the operational parameters of the vehicle [3].

The most important technology for EVs and hybrid electric vehicles (HEVs) is electric motor drives [4]. The fundamental properties of an electric motor for EVs are: 1) Highly effective over extensive and speed torque ranges; 2) Great power and torque density; 3) An extensive speed range which includes high-speed cruising and low-speed crawling; 4) High constant-power operational ranges; 5) Wide torque ranges for hill climbing and electric take off; 6) High robustness and durability for automobile applications; 7) significant intermittent overload capacity for overtaking; 8) affordable price 9) low sound disturbance [5].

HEVs utilize two or more power sources, resulting in various configurations. The most common types combine an internal combustion (IC) engine with a battery, along with an electric motor and generator. The two fundamental configurations for HEVs are series hybrid and parallel hybrid. In a series hybrid design, the vehicle is powered by one or more electric motors that receive energy directly from the battery, the IC-engine-driven generator unit, or both. In a parallel hybrid design, the vehicle can be powered either by the engine through a transmission system, by one or more electric motors—either via the transmission or directly coupled to the wheels—or by both the electric motor and the IC engine simultaneously [6]. In addition to the characteristics listed above, the drive for HEVs also requires the following requirements: 1) Wide speed range with high-efficiency generation; 2) High-speed range and efficient voltage control. Permanent magnet (PM) motors are rising in popularity as high powered PM materials become easily accessible. PM brushless drives have been recognized as the best promising ones to offer the features mentioned above for the new age HEVs and EVs. These EVs are being continuously fuelled by innovative machine designs and control methodologies [7].

To fulfill the high power demand (250 kW), designs of heavy-duty electric and HEVs with massive electric drives and powerful inverter topologies are needed. Massive electric drivetrain development for these automobiles will result in better acceleration and braking, more fuel economy, and reduced emissions [8]. Due to large volt-ampere ratings, transformerless multilevel inverters (MLIs) are ideally suited for this application. A unique design of a multilevel voltage source inverter (VSI) may make it possible to achieve high-voltages with minimal harmonics, evading the need of transformers or any set of synchronized switching components connected in series [9]. The main purpose of MLIs is to generate various DC voltage levels to generate the required output voltages. Thus, MLIs may easily supply the high power required by a large electric powertrain. The synthesized output waveform includes more steps as the level count increases, creating a staircase wave that matches the required shape i.e. the sinusoidal waveform. Diode-clamped MLIs, flying-capacitor MLIs, T-type MLIs and cascaded H-bridge MLIs are the three basic types of transformerless MLI addressed in several literatures.

A unique feature of multilevel inverters (MLIs) is that as the number of output voltage levels increases, it reduces voltage stresses on devices, minimizes electromagnetic interference, and lowers total harmonic distortion (THD). This enhances output quality while reducing system costs. However, the structure and control methods of MLIs become more complex. For example, in neutral-point clamped (NPC) topologies, an increase in voltage levels significantly raises the number of capacitors and clamping diodes. Additionally, achieving voltage balance across the dc-link capacitors in NPC MLI topologies presents challenges [10]. Similarly, flying capacitor (FC) MLI topologies require more intricate control techniques to maintain voltage balance among the capacitors [11]. The cascaded H-bridge (CHB) topology, on the other hand, involves multiple phase-shifting isolation transformers or isolated DC sources, which adds bulk and expense to the overall system [12,13]. To overcome the above-mentioned drawbacks of innovative 3L inverter a three-phase 3-level (3L) inverter configuration is proposed which is a modified version of conventional neutral-clamp diode MLI (NPC MLI) evading the clamping diodes is presented in this paper and Table .1 presents the comparison component count of conventional 3L MLI.

Table 1.

Component count in 3L MLI topologies.

Topology	Active Switches	Clamping Diodes	Flying Capacitors	Freewheeling Diodes	DC sources
3L-NPC [10]	12	6	0	12	1
3L-FC [11]	12	0	3	12	1
3L-CHB [12]	12	0	0	12	2
Proposed 3L MLI	12	0	0	12	1

Generally, more than a 2-level output voltage to generate a sinusoidal waveform output causes the mitigation of the current harmonics at the load side. On the other hand, the real enhancement of the load current profiles can be depends on the employed control strategy. The furthermost widely employed control strategy for conventional inverters is the natural pulse width modulation (PWM), which is also known as the sinusoidal or subharmonic PWM. It is the more popular technique due to its ease of use and guarantees good outcomes under all operating conditions including “over modulation”. The overall classification of the switching techniques employed for MLIs is depicted in Fig. 1 [9]. In general, the same triangular carrier signal is used in PWM strategy considering three different modulating sinusoidal signals with the frequency $W_m$ and amplitude $A_m$. For example if an ‘m’ level output MLI is deployed, m-1 carriers' signals are needed; all these carriers have the similar peak-to-peak amplitude $A_c$ and frequency $W_c$. Every carrier signal is compared with the sinusoidal reference signal at each instant of time. In every comparison, if the reference sinusoidal is higher than the triangular carries in the first half of the cycle period, it generates 1, similarly it generates −1, if the reference sinusoidal is higher than the carries signal in the next half of the cycle period rather than it generate zero. The outcomes are summed to determine the level, which is needed at the inverter's output terminal ends. A basic logic circuit can be used to obtain the actual driving signals for the power devices from the results of the modulating-carriers comparison, which are obviously dependent on the specific structure selected to realize the inverter. For the three-phase system, the switching waveforms can be created in two ways based on the utilization of the carrier signal. Generally, a three-phase system employs three modulating sinusoidal signals with the phase difference of 120°. The carrier signals can be utilized in two ways to generate the PWM signal. First, a single carrier set can be compared with three different modulating sinusoidal signals each phase shifted by 120°. Second, three separate carrier (multicarrier) sets are compared with the appropriate three sinusoidal which have a phase displacement of 120° between them [14].

Fig: 1.

Classification of switching techniques for MLIs [15].

In this proposed work, the multicarrier technique is focused in which the carrier disposition approach is considered to be the source of the PWM scheme. Carrier-based PWM technique may be divided into two types: Level shifted PWM (LS-PWM) and Phase- Shifted PWM (PS-PWM). PS-PWM is an advancement of conventional PWM methods which is developed to lower the harmonic spectrum of the output voltage [16]. In this strategy, each pair of switches has a carrier signal with a phase shift to each other. For instance, a MLI with ‘m’ level output needs (m-1) triangular carrier signals. The carrier signals have the same peak to peak amplitude and frequency, however there is a phase delay ($\varnothing )$ concerning each carrier which can be expressed as $\varnothing =360/\left(m-1\right)$. LS-PWM can be obtained from the carrier disposition approach [15]. In general, LS-PWM technique classified as: phase disposition (PD) in which all carrier are in phase, alternative phase opposition disposition (APOD), every carrier signal is phase delayed by 180°, phase opposition disposition (POD), all carrier signals above sinusoidal zero reference are 180° out of phase which those below the zero point [17].

Section II of this article discusses the operation of conventional inverters. Section III gives briefs about the proposed MLI operation. PWM control techniques that are available for MLI are discussed in Section IV. Section V briefs about the proposed control technique and the simulation results of the proposed MLI. Section VI presents the real-time HIL simulator experimental setup and HIL outcomes. Comparative summaries are discussed in Section VII. The conclusion of Section VIII summarizes the inference made from this paper.

2. Conventaional inverters

Typically, multilevel inverters (MLIs) are classified into three categories: cascaded H-bridge inverters (CHB), flying capacitor inverters (FC), and neutral-point clamped inverters (NPC). Among these, the NPC type stands out due to its higher efficiency, greater reliability, and lower electromagnetic field interference. Section A discusses the conventional three-level NPC MLI, along with its operating modes, focusing on neutral point fluctuation (NPF) and common mode voltage (CM voltage) concepts. The other conventional three-level MLIs, including FC and CHB, are covered in Sections B and C, respectively.

2.1. Neutral point clamped (NPC) MLI

A three-phase NPC MLI 3L with load is shown in Fig. 2, two DC-link capacitors (C₁ and C₂) with a shared DC source ($V_s$) are connected to the inverter's three legs. This configuration consists of twelve semiconductor switching devices and six clamping diodes, each leg consist of four semiconductor switching devices ($S_1-S_4$) with four anti-parallel diodes $(D_1-D_4$) and two clamping diodes $(D_5-D_6$), where the switches $S_1$ and $S_3$ and the switches $S_2$ and $S_4$ are complimentary to each other. Furthermore, there are two complimentary pairs of switches in each phase. Through the neutral point and DC-link capacitor, the voltage stress on switches has been limited to $V_s/2$. This type of switching configuration can produce three output voltage levels: + $V_s/2$, 0, - $V_s/2$ [16]. The switching state table for a phase ‘a’ of the three-phase NPC MLI is tabulated in Table 2. A similar switching table can be derived for remaining phases. The output will be + $V_s/2$ and -$V_s/2$ when the upper switches ($S_{w1a}$ and $S_{w2a}$) and the lower switches ($S_{w3a}$ and $S_{w4a}$) are ON, respectively. In the ON condition, switches $S_{2a}$ and $S_{3a}$ will result in zero output. Fig. 3 depicts the three different operating modes of leg ‘a’ output voltages for the 3L NPC inverter. The mathematical computations for NPC inverters and their operational restrictions are discussed in Ref. [18].

Fig: 2.

Three -phase 3-level NPC inverter.

Table: 2.

Switching sequence table for three output level of three-phase 3L NPC inverter.

Output Levels	${\mathit{S}}_{\mathit{w}\mathbf{1}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{2}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{3}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{4}\mathit{x}}$
$V_S/2$	1	1	0	0
0	0	1	1	0
${-V}_S/2$	0	0	1	1

Where ‘x’ represent phase ‘a’,‘b’ and ‘c’.

Fig: 3.

Operation modes of leg ‘a’ output voltages for three-phase 3L NPC MLI (a) + $V_s/2$ (b) 0 (c) -$V_s/2$.

2.1.1. Neutral point fluctuation

In the NPC MLI, two DC-link capacitors (C₁ and C₂) are used in parallel with a DC voltage source. This two capacitors should have the same voltage across them i.e. $V_s/2$. Nevertheless, due to the switches' uneven commutation and the addition of third harmonic current in the neutral point, the DC-link voltages are not balanced. The change in voltages at a neutral point (N) is described with the term neutral point fluctuation (NPF), which can be expressed as

$$NPF=\frac{\raisebox{1ex}{$V_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.-V_{c2}}{\raisebox{1ex}{$V_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}\ast 100$$ (2)

where $V_s$ is the input voltage and $V_{c2}$ is the voltage in the capacitor, $C_2$.

2.1.2. Common mode voltage

The average sum of instantaneous voltage, which is further defined as the voltage between the inverter's ground and the load's neutral point, is known as common mode voltage (CM) voltage [18]. The CM voltage of the three-phase inverter is represented by

$$CMVoltage=\frac{V_{an}+V_{bn}+V_{cn}}{3}$$ (3)

where $V_{an}$, $V_{bn}$, and $V_{cn}$ are the voltage between neutral and phase of the load.

2.1.3. Losses calculation

The junction temperature of an inverter rises when a switch is turned on and off. Conduction and Switching power losses of the switching devices are responsible for this rise in temperature. Conduction and switching losses, therefore taken into account while evaluating the performance of the inverter [19].

• a.Conduction Power Losses

Conduction losses are produced when the switch is conducting (i.e. in turned ON state) and the voltage difference between the collector and emitter terminals ($V_{CE}$) is multiplied by the current. These losses may ignore when the switch is off since the leakage current is so negligible. The conduction power loss in the switch and diode of phase ‘a’ is provided in (1) and (2).

$$P_s=V_{ce.s}{I}_{avg.s}+R_s{I}_{RMS.s}^2$$ (4)

$$P_D=V_D{I}_{avg.D}+R_D{I}_{RMS.D}^2$$ (5)

• b.Switching Power Losses

During the turn-on phase, the current will begin to increase even before the switch voltage decreases to the forward voltage drop. Similarly, during the turn-off time, the voltage will begin to increase earlier than the current drops to forward leakage current. Switching loss refers to the losses that happen during turn-on and turn-off periods and is expressed as in (6)

$$P_{sw\_loss}=\frac{P_{sw\_on}+P_{sw\_off}}{2}$$ (6)

Selecting the appropriate PWM approaches that have lower switching losses will help to reduce the switching losses.

2.2. Flying-capacitor (FC) MLI

A proposed topology, the Flying-Capacitor (FC) MLI [11], uses flying capacitors instead of clamping diodes. As illustrated in Fig. 4, this topology includes two input bus capacitors, one flying capacitor, and four controllable switches in a phase leg to generate a three-level output. In this topology, four switching stages are possible to generate three-level output voltages of ${+V}_S/2$ , 0 and $-V_S/2$. Switches $S_{w1a}$ and $S_{w2a}$ are used to generate the ${+V}_S/2$ output voltage level, while switches $S_{w3a}$ and $S_{w4a}$ generate the $-V_S/2$ output voltage level. For the zero level output voltage, two switching states are possible due to the presence of a flying capacitor: one for charging mode and another for discharging mode, as depicted in Fig. 5. The switching states of FCMLI are presented in Table 3.

Fig: 4.

Three -phase 3-level FC inverter [11].

Fig: 5.

Operation modes of leg ‘a’ output voltages for three-phase 3L FC MLI (a) + $V_s/2$ (b) -$V_s/2$ and (c) Zero.

Table: 3.

Switching sequence table for three output level of three-phase 3L FC inverter [11].

Where ‘x’ represent phase ‘a’,‘b’ and ‘c’.

2.3. Cascaded H-bridge MLI

The CHB MLI consists of several H-bridge cell networks connected in series, with a three phase 3L CHB configuration shown in Fig. 6(a) [12]. Fig. 6(b) depicts a single H-bridge cell network of CHB, where each bridge cell is powered by an SDCS. Each H-bridge cell can produce a 3-level output voltage of ${+V}_S,0$ and ${-V}_S$ when switches $S_{w1}$-$S_{w4}$, $S_{w1}$-$S_{w2}$, or $S_{w3}$-$S_{w4}$, and $S_{w2}$-$S_{w3}$ are turned ON, respectively, as shown in Fig. 7. The switching states are presented in Table 4. The series connection of H-bridge cells increases the inverter's output voltage level. With multiple DC supplies applied to the CHB MLI's input, it generates high output voltage levels [13]

Fig: 6.

Three -phase 3-level CHB inverter [12].

Fig: 7.

Operation modes of leg ‘a’ output voltages for three-phase 3L CHB MLI (a) + $V_s/2$ (b) Zero and (c) -$V_s/2$.

Table: 4.

Switching sequence table for three output level of three-phase 3L CHB inverter [12].

Output Levels	${\mathit{S}}_{\mathit{w}\mathbf{1}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{2}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{3}\mathit{x}}$	${\mathit{S}}_{\mathit{w}\mathbf{4}\mathit{x}}$
${+V}_S$	1	1	0	0
0	1	1	0	0
	0	0	1	1
${-V}_S$	0	0	1	1

Where ‘x’ represent phase ‘a’,‘b’ and ‘c’.

3. Proposed MLI

In this a three-phase 3L MLI and its operating modes are presented in subsection A, in subsection B CMV and NPF with losses calculation is discussed.

3.1. Description and analysis of proposed MLI circuit

A proposed three-phase 3-level (3L) MLI is depicted in Fig. 8 which consist of twelve semiconductor power switches and twelve antiparallel diodes without employing any additional clamping diodes or bidirectional switches. The proposed MLI have capable to reduce the output voltage and current harmonics because of 5L stepped line–to–line voltages without the need of the output transformers. The applied voltage of each power switching device is equals to half of the DC-link voltage if the neutral point potential is maintained at the DC-link voltage's centre potential. As a result, the proposed MLI is well suitable for high voltage and power applications like EVs. In this proposed topology each phase leg consist of four power switches ($S_1-S_4$) with anti-parallel diodes ($D_1-D_4$). The 3L output voltages are achieved at phase voltages i.e. $V_{an},V_{bn},V_{cn}$ subsequently 5-levels are generated on the line-to-line voltages $V_{ab},V_{bc},V_{ca}$ .This type of switching configuration produce 3L in the phase voltages like + $V_s/2$, 0, -$V_s/2$.

Fig. 8.

Proposed three-phase 3-level MLI.

The switching state table for a phase ‘a’ of the proposed 3L three-phase MLI is shown in Table 5. A similar switching table can be derived for the remaining phases. It is clear that $S_{w1}$ equals to 1 when the switch is ON and 0 when it is OFF. The output will be + $V_s/2$ when the upper switch, $S_{w1a}$ is ON. The output is -$V_s/2$ when the lower two switches, $S_{w2a}$ and $S_{w4a}$, are turned ON. During ON condition, switches $S_{w2a}$ and $S_{w3a}$ produce zero output. The equivalent switching circuits are depicted in Fig. 9.

Table 5.

Switching states for phase ‘a’ of three-phase 3L proposed MLI.

Output Levels	${\mathit{S}}_{\mathit{w}\mathbf{1}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{2}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{3}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{4}\mathit{a}}$
$V_S/2$	1	1	0	0
0	0	1	1	0
${-V}_S/2$	0	0	1	1

Fig. 9.

Operation modes of phase ‘a’ output voltages for three-phase 3L MLI. (a) + $V_s/2$ (b) 0 (c) -$V_s/2$ output voltages.

For load current $i\ge 0$ the output will be + $V_s/2$ when the switch $S_{w1a}$ is ON. The output is $-V_s/2$ when the diodes, $D_2$ and $D_4$ conduct and for zero level output, switch $S_{w3a}$ and diode $D_2$ conduct. For load current $i<0$ the output will be + $V_s/2$ when the diode, $D_1$ conducts. The output is -$V_s/2$ when the switches, $S_{w2a}$ and $S_{w4a}$ conduct. Also, the switch $S_{w2a}$ and diode $D_3$ conduct to generate zero level output as depicted in Fig. 10 and the related switching state sequence are given in Table 6. Table 7 shows the 5-level switching sequence of the proposed MLI i.e. $V_s,V_s/2,0,-V_{s,}\text{and}-V_s/2$ level output as presented in Fig. 11.

Fig. 10.

Operating modes of phase ‘a’ output voltages for the proposed three-phase 3L MLI under different load current: (i) $i\ge 0$: (a)+ $V_s/2$ (b) 0 (c) -$V_s/2$; (ii) $i<0$ for: (d) + $V_s/2$ (e) 0 (f) -$V_s/2$.

Table 6.

Switching table of the proposed MLI for phase ‘a’.

States		${\mathit{S}}_{\mathit{w}\mathbf{1}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{2}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{3}\mathit{a}}$	${\mathit{S}}_{\mathit{w}\mathbf{4}\mathit{a}}$	${\mathit{D}}_{\mathbf{1}}$	${\mathit{D}}_{\mathbf{2}}$	${\mathit{D}}_{\mathbf{3}}$	${\mathit{D}}_{\mathbf{4}}$
$V_{DC}/2$	$i\le 0$	0	0	0	0	1	0	0	0
	$i\ge 0$	1	0	0	0	0	0	0	0
0	$i\le 0$	0	1	0	0	0	0	1	0
	$i\ge 0$	0	0	1	0	0	1	0	0
$-V_{DC}/2$	$i\le 0$	0	0	1	1	0	0	0	0
	$i\ge 0$	0	0	0	0	0	0	1	1

Table 7.

Switching table of the proposed MLI for line-to-line voltage.

Output Voltage	$S_{w1a}$	$S_{w2a}$	$S_{w3a}$	$S_{w4a}$	$S_{w1b}$	$S_{w2b}$	$S_{w3b}$	$S_{w4b}$	$S_{w1c}$	$S_{w2c}$	$S_{w3c}$	$S_{w4c}$
$V_s$	1	0	0	0	0	1	0	1	0	1	1	0
$V_s/2$	0	1	1	0	0	1	0	1	1	0	0	0
0	1	0	0	0	1	0	0	0	0	1	1	0
${-V}_s/2$	0	1	1	0	1	0	0	0	0	1	0	1
${-V}_s$	0	1	0	1	1	0	0	0	0	1	1	0

Fig. 11.

Operating modes of the proposed three-phase MLI with output voltage levels. (a) $V_s$ (b)+ $V_s/2$ (c) 0 (d) -$V_s/2$ and (e)- $V_s$ levels.

3.2. CM-voltage and NPF of three-phase proposed MLI

The proposed MLI has 27 types of switching modes, considering each phase can provide three different voltage levels ($3^3=27)$. These switching modes are illustrated in Fig. 12 with CM-Voltage calculation using (3) as discussed in Section II (B.2). Table 8 presents each switching state's CM-Voltage for the proposed three-phase MLI [17,18]. In the switching sequence, ‘‘N’’ indicates the turn on condition of the lower switches with the equivalent output voltage of − $V_s$, ‘‘P’’ indicates the turn on condition of the upper switch with the corresponding voltage of + $V_s$ and “Z” indicates the turn on condition of the middle switches with the corresponding voltage of zero volts. Similarly, NPF is calculated using (2) as discussed in Section II (A.1) (see Fig. 13).

Fig. 12.

Effects of switching states for the proposed MLI.

Table 8.

Sequence of switching state and CMV for proposed MLI.

Switching sequence	CMV Evaluation	CMV
ZZZ	0	0
PPP	($1/3$ + $1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2	$V_s/2$
NNN	(-$1/3$-$1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2	${-V}_s/2$
PZZ	($1/3$ +0 + 0) ${\mathrm{V}}_{\mathrm{s}}$/2	$V_s/6$
ZZP	(0 + 0+ $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2
ZPZ	(0+ $1/3$ +0) ${\mathrm{V}}_{\mathrm{s}}$/2
PPZ	($1/3$ + $1/3$ +0) ${\mathrm{V}}_{\mathrm{s}}$/2	$V_s/3$
PZP	($1/3$ +0+ $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2
ZPP	(0+ $1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2
ZNN	(0-$1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/3	${-V}_s/3$
NNZ	($1/3$ +0+ $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${\mathrm{V}}_{\mathrm{s}}$/3
NZN	(-$1/3$ +0-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/3
ZZN	(0+0-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6	${-V}_s/6$
ZNZ	(0-$1/3$ +0) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6
NZZ	(-$1/3$ +0 + 0) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6
PZN	($1/3$ +0-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0	0
ZPN	(0+ $1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0
NPZ	(-$1/3$ + $1/3$ +0) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0
NZP	(-$1/3$ +0+ $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0
ZNP	(0-$1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0
PNZ	($1/3$-1 $1/3$ +0) ${\mathrm{V}}_{\mathrm{s}}$/2 = 0
PPN	($1/3$ + $1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${\mathrm{V}}_{\mathrm{s}}$/6	$V_s/6$
NPP	(-$1/3$ + $1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${\mathrm{V}}_{\mathrm{s}}$/6
PNP	($1/3$-$1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${\mathrm{V}}_{\mathrm{s}}$/6
PNN	($1/3$-$1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6	${-V}_s/6$
NPN	(-$1/3$ + $1/3$-$1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6
NNP	(-$1/3$-$1/3$ + $1/3$) ${\mathrm{V}}_{\mathrm{s}}$/2 = ${-\mathrm{V}}_{\mathrm{s}}$/6

Fig. 13.

PD-PWM technique: (a) Two carrier signals for 3L MLI (b) Four carrier signals for 5L MLI.

3.3. Loss calculation

• aConduction power Losses

The losses that take place when the antiparallel diode, or IGBT, is operating and conducting current are known as conduction losses. The on-state current and voltage are multiplied to determine the overall power dissipation during conduction. In PWM applications, the average power dissipation is calculated by multiplying the conduction loss with the duty factor. The IGBT's average conduction loss dissipated is given in (1).

$$P_{COND}=\frac{1}{T}{\int }_0^T[V_{ce}\left(t\right)\ast I_{ce}\left(t\right)dt$$ (1)

In order to connect the datasheet values with (1), it is necessary to linearize to a more common on-state loss of the semiconductor devices as described in (2) and (3)

$$P_{COND\left(IGBT\right)}=V_{CEO}\ast i\ast R_0\ast i^2$$ (2)

$$P_{COND\left(Diode\right)}=V_{DO}\ast i\ast R_{DO}\ast i^2$$ (3)

Two distinct variables are introduced in the new linearized equation: $V_{CEO}$ is temperature dependent, on-state voltage threshold voltage, and $R_0$ on state resistance, temperature dependent.

• bSwitching power Losses

Based on the application's switching frequency, switching losses may be the main cause of device losses. In contrast, modular multilevel converters with lower frequency applications are more resistant to switching losses. VSIs, active front end rectifiers, and Buck/Boost converters are highly reliant on the applied switching frequency. Below is the basic approach for calculating an IGBT's switching power loss.

$$P_{sw\left(IGBT\right)}=\left(E_{on}+E_{off}\right)\ast f_{sw}$$ (4)

$$P_{sw\left(Diode\right)}=\left(Q_{rr}\ast V_{in}\right)\ast f_{sw}$$ (5)

where $f_{sw}$, $E_{off},E_{on},\text{and}{Q}_{rr}\text{represent}$ the switching Frequency, turn off energy loss, turn on energy loss, and reverse recovery charge, respectively.

The switch IGBT total losses is the sum of the conduction, switching losses of both IGBT and antiparallel diose as defined below

$$P_{Total}=P_{Cond\left(IGBT\right)}+P_{sw\left(IGBT\right)}+P_{Cond\left(Diode\right)}+P_{Sw\left(Diode\right)}$$ (6)

• c.Total power Losses

For calculating the device losses for the proposed MLI, the datasheet (SRE80N065F5UD8) is considered. Table 9 presents the device specifications which are taken form the considered datasheet. The total losses for single IGBT in the proposed MLI is calculate as below with considerable datasheet values

$$P_{Total}=13.82+4.032+0.6+0.654=19.10\mathrm{W}$$

Table 9.

Semiconductor device specification.

IGBT	DIODE
$V_{CEO}$ = 1.1v	$V_{DO}$ = 0.25 V
$R_0$ = 8.88 × 10-3Ω	$R_{DO}$ = 8.75 × 10-3Ω
$E_{on}$ = 3.1 mJ	$Q_{rr}$ = 541 nC
$E_{off}$ = 1.0 mJ

3.4. Mathematical expression for proposed model output currents

The continuous-time mathematical expressions of the proposed inverter output currents can be obtained by applying Kirchhoff's voltage law to the model shown in Fig. 8. The obtained voltages of the model in terms of output load currents are as follows

$$V_{aO}={Ri}_a+L_{dt}^{{di}_a}+V_{nO}$$

$$V_{bO}={Ri}_b+L_{dt}^{{di}_b}+V_{nO}$$

$$V_{cO}={Ri}_c+L_{dt}^{{di}_c}+V_{nO}$$ (1)

here the voltage differential between the neutral point ‘n’ of the load and negative dc-link voltage ‘O’ is represented as $V_{nO}$ and can be calculated as

$$V_{nO}=\frac{1}{3}\left(V_{aO}+V_{bO}+V_{cO}\right)$$

$$V_{xn}=V_{xO}-V_{nO}$$ (2)

where $V_{xO}$ is the phase voltage with respect to the dc-link voltage (negative) of the inverter and x = a, b and c. R and L are the resistance and inductance with appropriate assumption of the same value for all the three phase. $i_a$ , $i_b$, and $i_c$ are the load currents of phase a, b and c respectively and Equation (1) can be rewritten as

$$V_O={Ri}_O+L_{dt}^{{di}_O}$$

$${V_0=\left[V_{an}{V}_{bn}{V}_{cn}\right]}^{\mathrm{T}}$$

$${i_0=\left[i_a{i}_b{i}_c\right]}^{\mathrm{T}}$$ (3)

From equation (3), the load current continuous-time model can be obtained as follows

$$\frac{{di}_o}{dt}=\frac{1}{L}\left[V_o-{Ri}_0\right]$$ (4)

4. PWM strategies for MLI

PWM techniques such as multi-carrier PWM (MC-PWM) and space vector control strategy are widely used for MLI applications [20,21]. LS, PS, and variable frequency control strategies are the typical categories of MC-PWM scheme. PD, POD, and APOD are the further classification of LS-PWM approach. For generating the pulses to the MLI, (m-1) carrier signals are needed while implementing MC-PWM technique [22,23].

• i.Phase Disposition PWM

In the PD-PWM approach, each carrier signal's amplitude and frequency are the same; however amplitude of one carrier varies from 0 to 1, while the other varies from −1 to 0 for the 3L inverter. Fig.13 (a) depicts the PWM pulse generation arrangements for a 3L inverter with the corresponding reference and high-frequency carrier signals [24]. Nevertheless, four carrier waves are employed for the 5L inverter with different amplitude variations: 0 to 0.5 and 0.5 to 1 for the carrier waves above the zero reference; −1 to −0.5 and −0.5 to 0 for the carrier waves below the zero reference [25]. Fig. 13 (b) shows the arrangement of the reference and high-frequency carrier signals for the 5L inverter. The amplitude and frequency modulation index can be defined as

$$M_a=\frac{A_m}{\left(m-1\right)A_c}$$ (1)

$$M_f=\frac{f_c}{f_m}$$ (2)

where $f_m$ and $f_c$ are the frequencies of the modulating and carrier signal, respectively. While $A_c$ and $A_m$ correspondingly represent the amplitude of the carrier and modulating signal.

• ii.Phase Opposite Disposition PWM

The frequency and amplitude of each carrier signal are kept constant in POD PWM, similar to the PD approach [26]. Nonetheless, below and above the zero reference, the carrier signals' phase angles shift by 180°. For instance, the magnitude of the carrier signal above zero reference varies from 0 to 1, whereas the magnitude of the carrier signal below zero reference varies from 0 to −1. The pulse generation arrangement for a 3L inverter is presented in Fig. 14 (a). This method combines phase disposition and phase opposition strategies. Positive levels are produced by carriers over the zero reference, and negative levels are produced by carriers lower the zero reference. Without the aid of carrier signals', the zero level can be produce. The carrier and reference signal arrangement for 5L inverter is depicted in Fig. 14(b) [27].

• iii.Alternate Phase Opposite Disposition PWM

Fig. 14.

POD PWM technique: (a) Two carrier signals for 3L MLI (b) Four carrier signals for 5L MLI.

In the APOD PWM strategy, every carrier signals has the same frequency and amplitude. However, carrier signals' phase angles are alternatively changed by 180° as shown in Fig. 15 [28]. It is clear from Fig. 14, Fig. 15 that POD and APOD approaches produce the same results for the 3L inverter. Nevertheless, it is evident from Fig. 14, Fig: 15 (b) that POD and APOD schemes produce different pulses for the 5L inverter [29]. Hence, when the level is more than 3L, the outputs from POD and APOD differ as the carrier signals are in phase for both the over and lower (180° degree phase angle shifted) the zero reference in POD, while the carrier signal are alternatively phase shifted in APOD. The positive and negative levels of the inverter are generated using the carriers above and below the zero reference [30]. It is also proven that the voltage stress and total harmonic distortion (THD) are considerably reduced while implementing the APOD technique compared to POD [31,32].

Fig. 15.

APOD PWM technique: (a) Two carrier signals for 3L MLI (b) Four carrier signals for 5L MLI.

5. Control strategy and simulation outcomes

In order to evaluate the performance of the PD-PWM control strategy for the proposed MLI, it is evaluated using MATLAB/SIMULINK software. The complete system modelling with the proposed 3L MLI and its corresponding PD-PWM control strategy is depicted in Fig. 16. The system specification used to validate the suggested PD-PWM control strategy is given in Table 10.

Fig. 16.

MATLAB Simulink model for proposed MLI with PD-PWM control technique.

Table 10.

System specification.

DC voltage ($V_{dc}$)	200 V
Modulation Index(m)	1
Switching Frequency ($f_{sw}$)	5 kHz
Output Load ($R_l,L_l$)	1Ω, 20 mH

Considering the PD-PWM control strategy, two carrier signals with a switching frequency $f_{sw}$ of 5 kHz are compared with a reference sinusoidal signal with a modulation index of 1 to produce the aggregated three-level voltage waveforms as shown in Fig. 17. The PD-PWM gate triggering signals for the switches S_a1-S_a4 shown in Fig. 9(a) of proposed MLI topology are given in Fig. 18. Phase voltages, line-to-line voltages and load currents of the proposed MLI are represented in Fig. 19(a), (b), and (c), respectively.

Fig. 17.

(a) Signal layout for the carrier and reference in the proposed PD-PWM switching method and (b) aggregated signal $S\left(t\right)$.

Fig. 18.

PD-PWM switching pulses (S₁ to S₄) for a three-phase proposed MLI.

Fig. 19.

Simulated outcomes: (a) Phase voltage, (b) Line -to -Line voltage, (c) Three-phase load current and (d) Phase load current of the proposed MLI at switching frequency $f_{sw}$ = 5 kHz.

The enlarged view of the current and line-to-line voltage at the load of the suggested MLI topology is depicted in Fig. 20. The Fast Fourier Transform (FFT) evaluation of current at the load is depicted in Fig. 21 with a THD value are equal to 1.93 % at switching frequency $f_{sw}$ = 5 kHz under R-L load of 1Ω, 20 mH. The FFT analysis of line-to-line voltage is depicted in Fig. 22 with a THD value of 36.18 %.In the enlarged view of the voltage switching stress of phase leg ‘a’, which is decipted in Fig. 23, expect switch ‘Sw1a’ remain; all switches need to block only 100 V, which is half of the DC-link voltage (V_S). The swtchn ‘Sw1a’ needs to completely block the voltage of the DC link (V_S).

Fig. 20.

Current and line-to-line voltage levels $V_s,V_s/2,0,-V_{s,}\text{and}-V_s/2$ at the load of the suggested PD-PWM approach for the proposed MLI at switching frequency $f_{sw}$ = 5 kHz under R-L load of 1Ω, 20 mH.

Fig. 21.

FFT of load current profile of the proposed PD-PWM approach for the proposed MLI at switching frequency $f_{sw}$ = 5 kHz under R-L load of 1Ω, 20 mH (a) Selected signal and (b) FFT analysis.

Fig. 22.

FFT profile of line-line voltage of the suggested PD-PWM approach for proposed MLI at switching frequency $f_{sw}$ = 5 kHz under R-L load of 1Ω, 20 mH (a) Selected signal and (b) FFT analysis.

Fig. 23.

Voltage switching stress of phase leg ‘a’.

The enlarged view of the line-to-line voltage and load current profile of the convectional NPC MLI design is depicted in Fig. 24. The FFT evaluation of load current is depicted in Fig. 25, with % of THD value equal to 4.75 %. The line voltage FFT analysis is depicted in Fig. 26 with THD value of 36.35 %.

Fig. 24.

Phase voltage associated with load current profile of the PD-PWM based conventional NPC.

Fig. 25.

FFT profile for current of the conventional NPC MLI with PD-PWM control strategy (a) Selected signal and (b) FFT analysis.

Fig. 26.

FFT profile for output voltage of conventional NPC MLI with PD-PWM (a) Selected signal and (b) FFT analysis.

6. Hardware-in-loop (HIL) experimental setup

• a.Experimental setup

HIL systems are frequently used in engineering systems to conduct pre-prototyping tests using real-time simulation. Prototypes may be created and synchronized quickly with stacks. In OPAL-RT, the machine and controller are installed so that the system operates at the real clock time. The real-time dynamic behaviour of this system is attributed to its high-speed nano-to microsecond OPAL-RT sampling speed. The digital simulator (Real Time Data Service) commands for the RT-LAB are managed by the user's personal computer (PC). RT-LAB is used for editing, building, loading, and running the prototype. The HIL stack specifications and the potential to run real-time systems is presented in Table 11. The results are tested by employing the OP5700 HIL Simulator with RT-LAB, MSOX3014T, probes, connecting cables, and a programmable control board (PCB-E06-0560). The PCB's analog outputs and digital inputs can be utilized to communicate data between the simulator and the real controller. Fig. 27 shows the experimental setup for real-time results.

• b.RT Outcomes

Table 11.

HIL specifications [33,34].

Name of the device	OP5700
Field Programmable Gate Arrays	Xilinx® Virtex®7 FPGA on VC707 board Processing speed: 200 ns–2 μs
Input and output lines	256 lines, routed to eight analog or digital, 16 or 32 channels
High speed communication ports	Up to 5 GBps
Input and Output connectors	Four panels of BD37 connectors
Monitoring connectors	Four panels of RJ45 connectors
PC interfaces	Standard PC connectors
Power rating	Input: 100–240 VAC, 50–60 Hz, 10/5 A Power: 600 W

Fig. 27.

OP5700-HIL-RT experimental setup.

The HIL experimental outcomes of phase voltages, line-to-line voltages for the proposed MLI are represented in Fig. 28(a) (b), respectively. The three phase load current profile is presented in Fig. 29(a) and (b). The enlarged view of the current and line-to-line voltage at the load of the suggested MLI topology is depicted in Fig. 30(a). The Fast Fourier Transform (FFT) evaluation of current at the load is depicted in Fig. 30(b) with a THD value equal to 1.97 %

Fig. 28.

HIL-RT experimental outcomes: (a) Phase voltage, (b) Line -to -Line voltage of the proposed MLI.

Fig. 29.

HIL-RT experimental outcomes: (a) Three-phase and (b) Phase load current of the proposed MLI.

Fig. 30.

HIL-RT experimental outcomes: (a) Current and line-to-line voltage at the load (b) FFT of load current profile with 1.97 % THD of the proposed PD-PWM approach for the proposed MLI.

7. Comparative summary

The proposed 3L inverter is compared with other conventional topologies like NPC, ANPC, T-type, FC, and CHB and is present in Table 12. While the number of controlled power semiconductor switches (IGBT with anti-parallel diode) is similar for all of the configurations mentioned, it can be observed that clamping devices (capacitors, power diodes and quadratic switches) can be removed in comparison to conventional topologies which are mention above. Table 13 gives the comparative analysis of %THD values of both voltage and current of proposed MLI, NPC and conventional 180° VSI with SPWM, and PD-PWM control strategies. It can be evident that the suggested PD-PWM based MLI gives a low % of THD values of both voltage and current when compared with conventional SPWM. The impact of variation in modulation index for the Proposed PD-PWM approach for the proposed MLI is presented in Table 14, from the table, it can be noticed that, for the value of M_a = 1, the proposed MLI generates the low % of THD values and Fig. 31 presents the comparison of conventional topologies with the proposed 3L inverter.

Table 12.

Comparison of three-level inverters for phase.

Topology	NPC [24]	ANPC [25]	FC [26]	CHB [27]	T-type [28,29]	Proposed MLI
Switches	4	6	4	4	4	4
Clamping Diodes	2	0	0	0	0	0
Quadratic Switches	0	0	0	0	2	0
Flying capacitor	0	0	2	0	0	0
H-bridge	No	No	No	Yes	No	No
Synthesising positive output voltage	2	2	2	2	2	1

ANPC – Active NPC; FC –Flying Capacitor; CHB –Cascade H-Bridge.

Table 13.

% of THD in current and voltage.

Control Techniques	Conventional SPWM		Proposed PD-PWM
	% of THD in Voltage	% of THD in Current	% of THD in Voltage	% of THD in Current
Proposed MLI	38.25	4.44 %	36.18 %	1.86 %
NPC	38.26	5.41 %	36.35 %	4.72 %
180° VSI	64.83	8.04 %	50.83 %	6.38 %

Table 14.

Impact of variation in modulation index for the PD-PWM approach on the proposed MLI.

Modulation Index	Current		Line-to-Line Voltage		Line-to-Phase Voltage
Ma	Magnitude(A)	THD (%)	Magnitude(V)	THD (%)	Magnitude(V)	THD (%)
0.6	9.706	2.40	108.3	45.54	61.77	103.46
0.8	12.8	2.02	142.7	42.54	81.5	75.22
1	15.11	1.93	166.5	36.18	96.19	58.79
1.2	17.26	2.40	189.7	30.57	109.9	42.47

Fig: 31.

Comparison analyses of the conventional topologies with proposed 3L topology.

8. Conclusion

The proposed three-phase 3L inverter is derived by modifying the traditional NPC evading clamping diodes and quadratic switches. Each inverter leg operates at a high switching frequency, producing three levels of phase voltages and five levels of line-line voltages for the considered load condition of R = 1Ω and L = 20 mH. Owing to the elimination of clamping diodes and quadratic switches, the proposed 3L MLI requires a lower count of power diodes and only one power switch is used to synthesize the positive output compared to the traditional NPC. This in turn paves the way for a more accountable reduction in the percentage of conduction losses while implementing the proposed MLI than the NPC MLI. The Fast Fourier Transform (FFT) evaluation of the load current shows a THD value of 1.93 % at a switching frequency of 5 kHz under an R-L load of 1Ω and 20 mH. The FFT analysis of the line-to-line voltage indicates a THD value of 36.18 % for the proposed three-phase 3L inverter. The comparative study carried out in Section VI validates the efficacy of the proposed MLI. Additional implementation of the proposed PD-PWM scheme further enhances the MLI performance in terms of reducing the THD in the phase and line-to-line voltages and load current. Simulation results show a good agreement with both the proposed MLI and PD-PWM technique along with this the real-time HIL simulator is used to verify the proposed control scheme. With regard to lesser component utilization and lower voltage stress, the proposed three-phase MLI topology is considered to be the more desirable one. For future applications, the proposed 3L MLI combined with the PD PWM control technique can be utilized in electric vehicles and other power electronic applications.

CRediT authorship contribution statement

Vijaya Sambhavi Y: Writing – original draft, Visualization, Software, Resources, Methodology, Data curation, Conceptualization. Vijayapriya R: Writing – review & editing, Validation, Supervision, Project administration, Investigation, Formal analysis.

Declaration of competing interest

The authors declare no conflict of interest.