Digitalized analog integrated circuits

Abstract

Digital integrated circuits have significantly benefited from technology scaling down, while conventional analog integrated circuits suffer from more design constraints. In recent years, there has been strong research interest in replacing conventional analog blocks with digitally-friendly and digitally-intensive alternatives, while significant progress has been made. This paper reviews the existing digitalized analog integrated circuits, including amplifiers, analog-to-digital converters, phase-locked loops, and power supplies. Based on the review, the future development trends of the digitalized analog integrated circuits are derived.

1. Introduction

With the development of integrated circuits, electronic information techniques, such as wireless communication, the internet of things, and artificial intelligence, have been greatly improved. Generally, the integrated circuit presents the development and demand trend of the system-on-chip (SoC), which integrates all components of an electronic system on a single chip. These components typically include digital integrated circuits and analog integrated circuits. Fig. 1 shows the simplified sensing electronic system as an example. Analog integrated circuits convert the analog information captured by the sensor to digital data. Then, the digital signal processor (DSP) handles the digital information. Due to the SoC implementation requirement, the digital and analog circuits should be integrated into the same technology node.

Fig. 1.

Simplified sensing electronic system. 

With technology scaling down, digital and analog integrated circuits present inconsistent development progress. Fig. 2a shows the variations of the transistor intrinsic gain, threshold voltage variation and supply voltage under technology scaling [1]. The decreasing supply voltage and transistor intrinsic gain, as well as the increasing device variation, reduce the performance of analog integrated circuits and make their design much more difficult. By contrast, benefiting from technology scaling, the digital integrated circuits have increased their speed, as shown in Fig. 2b. Meanwhile, the scaling-down transistor size also increases the integration and automation (EDA) tools, and digital integrated circuits can have a short turnaround time. Therefore, the process upgrade of analog integrated circuits always falls behind that of the digital integrated circuits, which hinders the SoC implementation. To address this issue, researchers are exploring to replace conventional analog blocks with digitally-friendly and digitally-intensive alternatives.

Fig. 2.

The trends of (a) intrinsic gain, threshold voltage variation and supply voltage, and (b) the transistor speed is characterized by the cut-off frequency fT and the fan-out-of-4 delay of an inverter.

In recent years, significant progress has been made in digitalized analog integrated circuits. This paper aims to provide a comprehensive review of the digitization process in primary analog integrated circuits, including amplifier, ADC, PLL, and power supply.

This paper is organized as follows. Sections 2–5 review the digitalized amplifiers, digitalized ADC, digitalized PLL, and digitalized power, respectively. Finally, conclusions and future development trends are drawn in Section 6.

2. Digitalized amplifiers

To accommodate the scaling down of the CMOS process, some OTAs’ design trends towards multi-stage architectures [2], [3], [4], [5], where operating at 0.7 V supply with sufficient gain [2], and driving ultra-heavy capacitive load as much as 1000 pF under 1.4 V power supply can be realized [3,4]. However, the restricting voltage headroom cannot support these topologies when V_DD is below 0.7 V. Despite strategies like input push and pull [6] and ping-pong technique [7] having been adopted, there is still more than 100 mW dissipated in the OTA core and the bias-generating circuits. The traditional analog circuits can hardly keep pace with the scaling of the CMOS process.

As shown in Fig. 3, it illustrates the compromise design of an amplifier. The requirements between speed and precision are inconsistent and strongly related to power dissipation. However, digitalized amplifiers can improve analog performance by taking advantage of digital circuits. Recently, various types of digital OTA based on logic gates have been presented, which have less manufacturing cost and faster transient response. The inverter-based amplifiers (IBAs) [8] use a dynamically biased inverter as the OTA core, which realizes a 4th-order feedforward Δ-Σ modulator with 71-dB SNDR under 0.5 V V_DD, breaking the voltage bottleneck of the traditional OTAs, at the expense of CMR and PSR attenuation. To address this, a novel biased method that eliminates the systematical offset is investigated [9], [10], [11]. After that, the robustness with switched-capacitor schemes to achieve better energy efficiency was further enhanced [12,13].

Fig. 3.

Amplifier design trade-off. 

However, the gain and linearity of IBAs are restricted due to stability issues if incorporated into cascading or typically closed-loop. Therefore, some work tries to render the digital circuits with analog features in more effective but concise ways, whereas ring amplifiers (RAs) can represent the prior arts that achieve superior dynamic performance (THD < −80 dB) in the nanoscale process [15,16]. Such performance mostly benefits from the dead zone voltage, which brings flexible bias-generating plans at each inverter stage [17,18] respectively; hence the stability and linearity issues can be well-addressed.

To improve the CMR and PSR of the pseudo-differential architecture, the modified input pairs or CMFB loops are introduced [16], but there exists a compromise between bandwidth and stability. To address it, the floating inverter amplifier (FIA) has been promoted recently with robust CMR and PSR [19,20]. Besides, the mechanism of capacitive charging consumes zero power during the operating phase, which shows better efficiency than the mentioned inverter-based amplifiers. Systematical designs have been proposed based on FIAs to satisfy the different requirements in multiple applications [21], [22], [23].

2.1. Inverter based amplifier

The IBAs provide another perspective to increase gain and signal swing through inverter cascading rather than cascode-stacking in the analog pattern. With the same power consumption, IBA achieves higher gain bandwidth product (GBW) and better FoMs due to doubled input transconductance (GBW × C_L/Pow). However, the PVT sensitivity and bias generating need to be further addressed.

2.1.1. IBA with dynamic biasing (IBADB)

The IBA was first invested in previous research [9], serving as a switched capacitor integrator. Fig. 4a, b present the operation during reset and amplifying phases ɸ₁ and ɸ₂. The signal is fed through an AC-coupled scheme. At phase ɸ₁, M_p1 copies I_o from M_p2 while M_n1 is saturated and connected in diode type; the input/output common-mode voltages are V_gsn1. This configuration reduces the low-frequency PSR since the gain from V_DD to V_out changes from g_mp1(r_op1//r_on1) to 1/(g_mn1r_op1). Besides, the diode connected M_n1 provides an auto-zero feature that stores the offset (V_os,out) at the top plate of C_c2. At phase ɸ₂, the amplifier settles through the feedforward path consisting of C_c1, C_c2 and the inverter, so that the offset voltage observed at the output node is reduced to V_os,out/A compared to the OTA implemented by a pure inverter, where A is the intrinsic gain of an inverter. However, the current mirror brings noise issues, and the output V_om is somewhat ambiguous and PVT-sensitive.

Fig. 4.

(a) IBA with dynamic biasing at clk ɸ1 and (b) IBA with dynamic biasing at clk ɸ2.

The difficulty of optimizing noise characters in IBADB is the compromise between gain and bandwidth products. For example, a decoupling capacitor C_d added at V_gp1 can effectively reduce the noise bandwidth, but it also reduces the FoMs of the OTA. The equivalent input transconductance is

$$g_{me}=g_{mn1}+\frac{C_{C1}}{C_{C1}+C_d}{g}_{mp1}$$ (1)

As can be seen, g_me decreases with C_d, which finally reduces the FoMs of the OTA.

2.1.2. IBA with switched-capacitor floating voltage sources

To suppress the noise and improve the PVT robustness, Wang et al.[10] proposed an inverter amplifier with switched-capacitor floating voltage sources (SC-FVS). As shown in Fig. 5, the difference between ref. [9] and ref. [10] is that M_n1 is not configured in the diode at the reset phase but copies Io either. Therefore, the same bias current flows through M_p1 and M_n1, which is neutralized at the output node, thus reducing the systematical offset. V_om keeps constant due to the conservation of charge.

Fig. 5.

IBA with switched-capacitor floating-voltage-sources. 

Another advantage of the IBA with SC-FVS is the enhancement of PVT insensitivity. It is achieved by the balanced C_p, which refers to the parasitic capacitance at the gates of M_p1 and M_n1. During phase ɸ₂, charge sharing occurs among C_c1, C_c2 and C_p. This procedure repeats until V_gn1, V_gp1 and V_out reach a steady state. Considering V_gn1 as an example, after nT times charge sharing:

$$C_{C2}{V}_{bn}+(C_{C1}+C_{pn})V_{gn1}\left[(n-1)T\right]=(C_{C2}+C_{C1}+C_{pn})V_{gn1}\left[nT\right]$$ (2)

where C_pn refers to the parasitic capacitance at V_gn1, and V_bn represents the bias voltage generated from I_o. The steady voltage of V_gn1 can be acquired with summation equations from V_gn1[T] to V_gn1[nT], which is formulated as

$$V_{gn1}\left[nT\right]=V_{bn}[1-{\left(\frac{C_{C1}+C_{np}}{C_{C1}+C_{C2}+C_{np}}\right)}^{n-1}]$$ (3)

The difference between C_np and C_pp introduces a systematical input offset voltage at V_gn1[nT] and V_gp1[nT], which results in V_om drift. This issue can be well addressed through properly setting the transistor size. A sufficient C_c1 also contributes to suppressing the offset.

2.1.3. IBA with advanced dynamic biasing

The intrinsic gain of an inverter is only 5–10 at the nanoscale CMOS process, which is hard to support precision applications. Configurations based on cascading inverters can obtain a gain of (g_mr_o)ⁿ but at the expense of power efficiency. Stacking cascodes can efficiently increase the gain in a single-stage OTA but induce PVT issues since the mismatch dc current between pMOS and nMOS flows through higher output impedance, thus requiring CMFB circuits. Chae et. al [11] proposes an inverter-based OTA with advanced dynamic biasing. As shown in Fig. 6, it consists of a cascaded inverter, which is dynamically biased to improve its immunity to PVT variations. During phase ɸ₁, M_p1 and M_n1 are connected with cascode transistors M_p21, M_n21 and a floating current source composed of M₁ and M₂. At the same time, M_p22, M_n22 are in off state. This ensures that both M_p1 and M_n1 are biased with exactly the same bias currents. Note that the bias voltages V_op and V_on associated with this operating condition are stored on the offset-storage capacitors C_C. This auto-zeroing process is similar to previous work [9], which contributes to canceling the offset and 1/f noise. During phase ɸ₂, the bias voltages of cascode transistors M_p21, M_n21 are swapped with those of M_p22, M_n22. This disconnects the inverter from the floating current source and reconfigures it as a high-gain push-pull common-source amplifier with a well-matched bias current. As a result, the inverters of the 1st and 2nd stages draw less current while obtaining DC gains greater than 80 dB over PVT variations.

Fig. 6.

IBA with advanced dynamic biasing (a) at phase ɸ1 (b) at phase ɸ2.

However, the noise feature in ref. [6] is still disturbing since the thermal noise near DC increases due to the noise folding [12]. Consequently, the OTA contributes the most of the systematical noise, which inversely requires more power consumption to maintain the target signal-to-noise ratio (SNR). This penalty can be overwhelmed by decoupling the amplifier's noise density from its bandwidth [13,14]. During the auto-zero phase, the effective noise bandwidth can be decreased by increasing the value of compensation capacitor C_C and thus reducing the amount of noise-folding. This does not deteriorate the amplifier's settling time during the integration phase since C_C is connected in series with the amplifier's input, which avoids the load effect.

2.2. Ring amplifier

Despite the referred ideas of optimizing an inverter-based amplifier core, other dimensions can also efficiently improve the analog performance. RAs are popular and are preferred due to their superior linearity and relatively fast transient response [15], [16], [17], [18]. The essential concept and difference between ring and inverter-based amplifiers is the introduction of dead zone voltage (V_DZ), which ensures the robustness and linearity of the closed stability meanwhile providing a flexible plan for generating and configuring the biased states of each inverter stage.

2.2.1. The original RA

In Fig. 7, it shows the original RA and basic switched-capacitor feedback network [15]. Fundamentally, the RA is a ring oscillator that has been split into two separate signal paths. C₁ is used to cancel the difference between the MDAC virtual-node sampling reference (V_CMX) and the trip-point of the first-stage inverter. This ensures that the ideal settled value will always be V_CMX. An offset voltage is embedded in the second-stage inverters by storing a voltage offset across capacitors C₂ and C₃. On the condition that the RA is configured as Fig. 7, the offset voltage will be used to bias the last stage at the subthreshold as V_IN approaches V_CMX. Fig. 8 illustrates the frequency response, where it can be observed that the output resistance of the third stage dramatically increases, producing a dominant pole that stabilizes the overall amplifier.

Fig. 7.

The RA and the switched-capacitor feedback network. 

Fig. 8.

The frequency response of an RA. 

The introduction of V_DZ can be intuitively treated as a dynamical class B bias to avoid the gate voltages of MCP (MCN) reaching GND (V_DD), which is beneficial to reducing distortion. Since MCP and MCN can never enter the triode region, the RAs have relatively constant and robust output resistance, which is essential to high linearity.

2.2.2. Fully differential ring amplifier

The original ring amplifier is configured in a pseudo-differential structure, sensitive to common-mode and power supply variation. To address this issue, ref. [16] introduces a novel fully differential ring amplifier. Fig. 9 illustrates the fully differential ring amplifier with the bias and CMFB circuits.

Fig. 9.

Fully differential ring amplifier, bias, and CMFB. 

Using both pMOS and nMOS input devices can reduce the thermal noise of the first stage by maximizing transconductance for a given current bias. The pMOS triode device-based CMFB, consisting of M₅, M₆ and M₇, coarsely sets the common mode at the output of the first stage. Using V_CM as the cascode bias voltage will set the ring amplifier input close to V_CM. The second and third stages adopt pseudo-differential inverter-like structures for high speed. In the second stage, R_B dynamically applies offset voltages to the last stages. High V_TH devices in the second stage are used to prevent the transistors from entering the triode region. Besides, high V_TH devices in the third stage of the ring amplifier provide higher output resistance and increase the robustness of the ring amplifier to PVT variation.

However, the mentioned robustness only refers to the closed-loop stability in the differential signal path. Note that M₅ and M₆ are both biased in the triode region. Latch-up may occur if the input common-mode voltage is sufficiently small, so this topology usually requires dedicated start-up circuits to prevent the degenerate state, which complicates the design.

2.3. Floating inverter amplifier

Prior works on the RAs demonstrate that improving CMR accompanies auxiliary circuits, parasitic as well as a considerable power, which deteriorates the systematical-efficiency. To address this with minimum cost, the floating inverter amplifier (FIA) [19] is proposed, featured by capacitive charging. Since there is no static current dissipation during residue amplifying, this topology is more power-efficient than the inverter-based amplifier. However, the conceptual structure of FIA has difficulty in providing sufficient gain and linearity for closed-loop residue operation, which promoted many works of art based on multistage stage topologies.

2.3.1. Two-stage FIA

Traditional two-stage FIA is first investigated before [20], which is improved based on a single-stage FIA as depicted in Fig 10a. During sampling phase ɸ₁, the reservoir capacitance C_res is charged to V_DD and GND while the sources of M1–4 are floating; hence no current is dissipated in OTA core. Meanwhile, the input and output of FIA are connected to V_CM. During amplifying phase ɸ₂, the V_CM switch is cut-off and C_res connects with M_1–4. C_res provides charging and discharging paths so that the FIA is able to amplify the input residue voltage. The transient current through C_res can be derived by the equivalent circuits shown in Fig. 10b:

$$I_{amp}\left(t\right)\approx I_{amp}(0+)\exp [-(g_{mp}+g_{mn})t/C_{res}]\le I_{amp}(0+)$$ (4)

Fig. 10.

(a) Operation of a single stage FIA. (b) Common-mode small signal equivalent circuit. (c) Equivalent single-ended ac model with negative feedback. (d) Loop frequency response.

Although I_amp(t) decreases with time, the charging and discharging currents are of the same value. Therefore, V_om remains V_CM, addressing the CMR issue without any auxiliary circuitry cost. The two-stage FIA inherits the PVT immunity features with inverter cascading.

In Fig. 10c, it illustrates the equivalent single-ended ac model with negative feedback. In a closed-loop system, stability needs to be ensured during the amplifying operation. There are typically two poles located at both FIA outputs. Due to the large load capacitor C_L at the closed-loop amplifier output, the second pole p₂ is the intrinsically dominant one. In the conventional OTA design, to achieve a fast-settling speed, a constant wide unity-gain bandwidth (UGB) is required. To ensure a good phase margin in a two-pole system, the non-dominant pole frequency needs to be at least two times higher than UGB, resulting in considerable power consumption. Thanks to the capacitive charging technique, the locations of the poles at the output node move towards low frequency gradually. The closed-loop stability can be accessed by designing different charging/discharging RC time constants, which is actually equivalent to applying different C_res at each stage. Fig. 10d is the loop response [20], which indicates that poles can decline at different speeds with a dedicated design.

Unlike the conventional OTA that requires a constant sufficient BW to meet the settling requirement, the FIA usually requires a large initial current to provide a wide BW and dynamically reduces the current to ensure stability. The overall settling accuracy is determined by the equivalent BW during the amplification phase. This dynamically scaled operation relaxes the BW and power trade-off, thus improving the energy efficiency.

2.3.2. Improved two stage FIA

It should be mentioned that the topology in ref. [20] was used for a noise-shaping SAR, so a dc gain of about 33 dB was sufficient and an extra parasitic capacitance C_L1 was omitted because of the large C_L2 (∼2 pF). A two-stage structure with cascode in the first stage was firstly adopted in ref. [21]. Unfortunately, to facilitate the amplifier in a pipelined SAR ADC, the dc gain of the amplifier still needs to be significantly increased. [22] utilizing three-stage architecture achieves 80 dB. However, the cascode configuration of the last stage limits the output swing; the stability issue is also imposed due to more intrinsic poles.

In Fig. 11, it shows an improved two-stage dynamic amplifier presented in Ref. [23] that can achieve high dc gain and wide output swing, operating in a closed-loop configuration. The input transistors M_P1 and M_N1 of the first inverter are implemented with a long-channel high VT transistor (HVT), which increases the output impedance and dc gain. It consumes much less current as the sum of the threshold voltages (V_TP1 + V_TN1) increases. Adding cascode transistors M_CP and M_CN with low VT transistors (LVTs) in the first amplifier, allows a dc gain of 50 dB. The second inverter is implemented with HVTs without cascode transistors and achieves a wide output swing and a moderate dc gain of 30 dB. Therefore, the improved FIA can achieve an overall dc gain of 80 dB and a wide output swing of ±0.8 V from a 1.2-V supply.

Fig. 11.

Schematic of the improve two stage FIA. 

The fundamental poles are compared in Fig. 12. Benefits from robust stability due to wider poles splitting can be observed [23], which is suitable for residue management in pipelined ADC.

Fig. 12.

Frequency response.

In a conclusion, to tolerate the suppressed headroom and sustain the linearity and CMRR, the digitalized amplifiers as the IBAs based on cascading inverter stages, ring amplifiers embedding the dead-zone bias and FIAs are designed to help accelerate the digitalized signal processing and further reduce cost on analog circuits.

3. Digitalized ADC

ADC is the interface between analog and digital signals. The classic analog-intensive ADCs encounter severe difficulties in advanced nanometer-scale CMOS process due to a drop in transistor intrinsic gain, an increase in device variation, and a decrease in SNR caused by the shrinking supply voltage. Researchers have developed many digitalized ADC architectures. In the voltage-domain (VD) ADCs architecture, the successive approximation register (SAR) [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], domino-logic [37] and stochastic flash ADCs [38] have been proposed to overcome these limitations. Among them, SAR ADC is the popular choice owing to its digital-centric nature, low-voltage tolerance, and scaling-friendly circuits.

On the other hand, the CMOS scaling in transistor dimension and supply voltage reduces the gate delay in digital circuits. Thus, the time resolution and the transistor speed increase with CMOS scaling [39]. It is promising to process analog information in the time domain (TD). The interest in the TD ADCs is rapidly increasing, especially for a time-to-digital converter (TDC) [40], [41], [42], [43], [44], [45], [46], [47], [48], [49] and a voltage-controlled oscillator (VCO) [50], [51], [52], [53], [54].

However, the single architecture has its limitation in achieving higher performance. The hybrid ADCs employing combinations of SAR, TDC, and VCO architectures effectively achieve low power [55], [56], [57], [58], [59], [60], [61], [62], [63], [64], [65], [66], [67], [68], [69], [70], high speed [71], [72], [73], [74], [75], [76], and high resolution [77], [78], [79], [80], [81], [82], [83], which have become the hot topic in recent years as well.

The applications of SAR, VCO, TDC and their hybrid counterparts are shown in Fig.13. This section introduces the basic concepts and the typical topologies of them, discussing their performances and fundamental limitations.

Fig. 13.

The applications of SAR, VCO, TDC and their hybrid counterparts. 

3.1. SAR ADC

SAR ADC benefits more than other ADC architectures from technology scaling because of the primary digital architecture and the superior higher energy efficiency. A comparator, a capacitive digital-to-analog converter (DAC), and a SAR logic are the three main circuit blocks that make up a conventional SAR ADC, as shown in Fig. 14a. During Φ_S, the input signal V_in is sampled onto CDAC. After the sampling, N comparisons are serially made for an N-bit SAR ADC during Φ_C. It obtains the digital representation by converging the DAC voltage to the analog input in a binary search fashion.

Fig. 14.

The classical architectures and operation principles of (a) SAR ADC, (b) TDC, and (c) VCO.

Through the optimization of comparators [24], [25], [26], DAC switching [27], [28], [29], [30], [31], [32] and SAR logic [33], [34], [35], SAR ADCs become the most power-efficient ADCs [36]. However, there is a trade-off between speed, resolution, and power consumption in the traditional SAR ADC. The performance is constrained by sampling kT/C noise, comparator noise, and capacitor mismatch while pushing it toward better accuracy. Suppressing these requires increased comparator loading and DAC size, leading to speed degradation. Meanwhile, the power efficiency in SAR ADC significantly deteriorates with the increase of resolution from the stringent noise requirement of the comparator and the sharply increased DAC switching energy. Consequently, achieving high performance is challenging.

3.2. TDC

Instead of the signal amplitude, the signal information in TD ADCs is encoded in the waveform transitions. Fig. 14b shows a basic delay-line TDC that works by counting the number of sequential delay units that have transitioned between the rising signal edges of the start signal and stop signal. The operating principle is illustrated below. The start signal goes along a buffer chain that produces the delayed signals. Each of these inverters has an output that is connected to a D flip-flop (DFF), which is clocked with the rising edge of the stop signal. A thermometer code is then generated at the DFF output, summed as the TDC output.

The TDC is actually a flash ADC in the time domain [40]. ADCs consisting of the basic “VTC+TDC” have proved that TD ADCs can achieve a comparable or even better efficiency than traditional VD ADCs [41]. Besides, the conversion speed of the TDC itself could also be improved by various architectural innovations, such as an interpolation TDC [42] and pipelined TDC [43].

However, as the resolution is increased, the operation speed of “VTC+TDC” rapidly decreases exponentially. Additionally, the input range suffers from the nonlinearity of the VTC and is very narrow. Furthermore, while intrinsic delay continues to decrease with process scaling, the delay-line TDCs [46], such as flash TDC [47] and vernier TDCs [48], have limited resolution and nonlinearity due to the mismatch between delay stages. Additionally, the number of delay units exponentially increases with the number of digital bits, leading to an increase in the silicon area and power consumption. The cyclic TDCs [49] can improve the quantization range without scaling up at all, but the delay-line structure's asymmetry due to the multiplexer increases the mismatch. In conclusion, the traditional TDC designs become more difficult when high dynamic range, linearity, and resolution are taken into account.

3.3. VCO

In Fig. 14c, it depicts the VCO as a quantizer. Exploiting this mechanism that the VCO output frequency is directly proportional to the voltage applied to its input, a phase quantizer will usually be used after the VCO to extract the VCO's phase as digital codes. The edge-countering quantizer [50] and phase-encoding quantizer [51] are the two primary types of the phase quantizer. Since phase and frequency have an integral relationship, these phase codes are passed to a differentiator to get the final digital output.

The edge-countering quantizer can be implemented by the digital counter and the phase-encoding quantizer can be realized using an XOR gate. Therefore, the VCO enjoys superb scaling compatibility due to its highly digital implementation.

As shown in Fig. 15, the VCO is actually an open-loop ΔΣ ADC. Due to DAC-less compared with traditional ΔΣ ADC and mostly digital structure, the open-loop VCO-based ADC exhibits great potential in terms of compactness, high speed and simplicity [51]. Unfortunately, the VCO's frequency tuning gain suffers from inherent non-linearity and process-voltage-temperature (PVT) variations, which significantly limit the VCO's accuracy, dynamic range, and robustness.

Fig. 15.

(a) Conceptual block diagram of a first-order open-loop ΔΣ ADC. (b) VCO-based open-loop ΔΣ ADC.

Multiple approaches have been proposed to address this issue. A direct method is to design highly linear VCOs [52]. Open-loop VCO-based ADCs with digital calibration have solved this problem [53] but suffer from complicated design. The closed-loop structure calls for a power-hungry operational amplifier (op-amp), which is not scaling-friendly [54]. As can be seen, addressing the VCO non-linearity is a major goal in the open-loop VCO-based ADC research, so that they can be more practical for a wider range of applications that require converting large swing signals.

3.4. SAR+TDC

The hybrid two-step method employs a SAR ADC for coarse quantization in the voltage domain and a TDC for fine quantization in the time domain, as shown in Fig. 16. It consists of an N-bit asynchronous SAR ADC, a voltage-to-time converter (VTC), and an M-bit TDC back-end. The SAR ADC first converts the input-voltage signal. Then the residue is converted into a TD signal by the VTC and finally handed over to the TDC.

Fig. 16.

“SAR+TDC” two-step hybrid ADCs [[65], [66], [67], [68], [69], [70]].

In this configuration, the total size of the CDAC and the comparator requirement benefit from the reduced conversion cycles. The VTC linearity is greatly improved by the smaller input range of the coarse conversion residue [65,66]. Furthermore, "VTC+TDC" can be replaced with VCO while maintaining energy efficiency [67]. The phase quantizer is reset each cycle to perform a Nyquist conversion. The VCO's linearity requirement is also reduced.

Due to the serial conversion, the design in Fig. 16 shows low-power performance but relatively low conversion rates. As illustrated in Fig. 17, employing a pipelining technique between VD and TD circuits could increase the sampling frequency [71,72].

Fig. 17.

“SAR+TDC” pipelined hybrid ADCs[71]. 

At the end of the SAR conversion, its quantization error is left on the top plate of CDAC and amplified by the VD amplifier (VD-Amp). The residue is then further transformed into the time domain by the VTC, which is resolved by TDC to obtain the 2nd-stage digital outputs. Compared with the architecture in Fig. 16, the VD-Amp decouples SAR ADC from VTC and TDC to implement a truly pipelined operation. A 2D-Vernier TDC is used to obtain a low-power and high-speed conversion [71]. The number of stages is expanded to three in Ref. [72], which exploits both the current-domain and the time-domain residue processing for speed enhancement. Even though the pipeline technique improves the sampling frequency significantly, the single-channel conversion rate is constrained by serial quantization in the SAR ADC.

Flash ADCs benefit from parallel quantization and feature high speeds in the voltage domain. Two-stage hybrid approaches combining a Flash ADC and a TDC have been proposed [[73], [74]]. However, Flash ADCs poor power efficiency and often require extensive comparator offset calibration.

Thankfully, the TDC operates in the time domain as a flash ADC. To break through serial quantization limitation, a fully time-based two-stage architecture was proposed [[75], [76]], as shown in Fig. 18. In this ADC, two Flash TDCs are used in the 1st and 2nd stages. The codes from coarse TDC are applied to the CDAC, which generates the voltage residue on its top plate. Then the voltage residue is amplified by the VD-Amp, and resolved by fine TDC in the 2nd stage. In contrast to the SAR ADC that produces bits one by one, the Flash TDC generates the first N bits in one clock period; therefore, it is faster than the earlier work [71]. Moreover, thanks to the sub-ranging architecture, the nonlinearity of the coarse VTC and the quantization error in the coarse TDC are corrected by the redundancy. Therefore, the full accuracy of the ADC is determined by the CDAC. The precision requirement of the coarse ADC is only N-bit. The precision requirement of the fine ADC is also relaxed by the VD-AMP, which meets only M bits. The strict mismatch requirements are eliminated. A VD comparator operates parallel with the VTC in both the 1st and 2nd stages [76]. It produces a sign bit to represent the VD polarity, which reduces the complexity of the TDC by 1 bit, and speeds up the overall conversion.

Fig. 18.

Fully time-based two-stage architecture[75].

3.5. SAR+VCO

Noise-shaping (NS) ADC is a promising candidate for high-resolution ADC designs. One type of NS ADC is VCO, and another is NS SAR, which extends a standard SAR ADC operation by adding several extra steps, including the residue sampling, integration and feedback, to achieve the noise transfer function (NTF). The existing NS SAR ADC architectures mostly fall into two basic structures, the cascaded integrator feed-forward (CIFF) and the error-feedback (EF) structure. Fig. 8 depicts the block diagram, schematic, and timing diagram of an NS SAR with a CIFF or an EF path.

Most NS SAR designs are based on CIFF structure [77], [78], [79]. Once the SAR conversion finishes, the residue voltage V_res is left on the top plates of C_DAC. Then, it is passed through the loop filter and fed the integrated results V_int back to the other extra comparator input for dynamic summation. In this way, both the quantization and comparator noise is shaped, thereby enabling a higher-resolution architecture. To get a sharp NTF, the lossy integration caused by charge sharing is complemented through the comparator input pair [77], capacitive charge pump [78] or dynamic Amp [79].

The essential difference between the EF and CIFF structure, as illustrated in Fig. 19a, is that the EF structure directly feeds the V_int back into the ADC input rather than the comparator. The adder of the input signal and feedback residue can be implemented by charge sharing [80], capacitor stack [81] or multi-input pairs [82].

Fig. 19.

(a) The flow diagram of the CIFF and EF structure and (b) their corresponding schematic and the timing diagram.

According to the discussion in Section 3.3, VCO-based ADCs obtain the 1st-order NS and can achieve high resolution in the time domain when the phase quantizer is not reset. However, the performance of the ADC is severely constrained by the voltage-to-frequency conversion's nonlinearity. To alleviate this problem, Fig. 20 illustrates the block diagram and signal flow of the SAR-VCO hybrid ADC [83], which combines a low-resolution NS SAR ADC with a VCO. The passive integrator retains the digital nature. The attenuation residue V_int due to charge sharing is fed to VCO and quantized to digital codes. Since the VCO is effective at quantizing small inputs in the time domain, it quantizes the small V_int without op-amp. Also, the nonlinearity is shaped by the 1st-stage NS, which is significantly suppressed and does not need any correction. The VCO, in turn, reduces the SAR comparator's requirement and saves power. Furthermore, the intrinsic 1st-order NS property leads to high resolution.

Fig. 20.

1–1 MASH “NS SAR+VCO” hybrid ADCs[83]. 

Therefore, the 1–1 MASH architecture simultaneously achieves high-order NS and nonlinearity suppression. Meanwhile, this architecture is highly digital and scaling-friendly and will benefit from technology scaling.

In summary, to co-achieve low power, high speed, and high resolution in technology scaling, ADCs continue to evolve digital-intensive ADCs and their hybrid converters that combine the strengths of various ADC types, including SAR, TDC and VCO.

4. Digitalized PLL

The digital phase-locked loop (DPLL) was first launched by Texas Instruments. Since then, the research interest in DPLL has remained high. Compared with analog phase-locked loops (AMS-PLLs), DPLL reduces chip area and provides higher scalability, programmability, and testability [84]. However, its design specifications are too strict to ensure robustness within the PVT variations, which leads to a large power. As research continues, DPLL has also shown good performance in recent years. Based on the 65 nm CMOS process, A 98-fs integrated jitter at the 30-GHz output with sub-sampling bang-bang phase detection and digital error correction is achived [85]. A 79.5-fs random jitter and 107.6-fs jitter [86], including spurs with quantization noise shaping and digital background adaptive-shaping-control technique were achieved. The current DPLLs are divided into divider-based DPLL [87] and counters-based DPLL [88]. This section will describe the architecture of DPLL in detail, and analyze the key design issues.

4.1. Structure of DPLL

4.1.1. Divider-based DPLL

DPLL can be realized by replacing analog modules in CPPLL with digital alternatives. As shown in Fig. 21, for divider-based DPLL, phase detector and charge pump are replaced by TDC, the traditional analog filter is replaced by a digital filter, and VCO is replaced by digital-controlled oscillator (DCO).

Fig. 21.

Frequency divider-based ADPLL and CPPLL. 

Noting that the structure of divider-based DPLL is similar to traditional CPPLL, the feedback path is composed of a frequency divider. It is easy to prove that the in-band noise is dominated by the quantization noise of TDC and the out-band noise is dominated by DCO. It is well known that the quantization noise of TDC is related to its resolution. To obtain better in-band noise, the unit delay of TDC needs to be kept small.

In addition, the mismatch between the unit delay and the limited unit size in TDC also leads to spurs, which further deteriorates the performance of DPLL. Since TDC is sensitive to PVT variations and its unit delay is limited by process, it tends to have poor linearity and quantized noise performance. The binary phase detector DPLL (BB-DPLL) is widely used in current designs. In this structure, a complicated TDC is replaced by a binary phase detector (BBPD), which can be regarded as a one-bit TDC. Therefore, it has lower noise, and the matching problem between delay cells would not be considered in the design.

As shown in Fig. 22, BBPD has only one quantization output code, representing phase leading or lagging. Typically, BBPD is designed as a simple D flip-flop (DFF). When the phase of the reference signal is leading, its output is 1; otherwise, its output is 0. Then the output is fed into the digital filter and controls the DCO output.

Fig. 22.

Structure of BB-DPLL. 

Since BBPD is a one-bit quantizer, it also faces many problems. The first is the realization of fractional-N DPLL. BBPD can only identify the phase leading or lagging, so simple BB-DPLL cannot achieve the fractional-N mode. In recent years, the implementation of fractional BBPLL mainly relies on calibration. In order to realize the fractional-N mode, Tasca et al. [89] uses DTC to calibrate the phase difference introduced by DSM, so as to effectively reduce the nonlinearity of TDC. The problem is that DTC has a large nonlinearity, so the adaptive calibration algorithms are introduced [90,91] to compensate the nonlinearity. The second problem is the gain of BBPD, which depends on the probability density value of the phase difference. Because the phase difference is almost close when the PLL is locked, the gain is high, which is beneficial to noise suppression. However, when the loop is unlocked, the gain is small, so the bandwidth of the loop is greatly reduced. Therefore, a calibration circuit is also needed to achieve fast locking in BB-DPLL. For example, Jang et al. [92] uses the autocorrelation of BBPD to adjust the loop gain. Both locking time and jitter can be reduced by setting the loop gain reasonably. By using a multi-level BBPD and a dynamic gain adjustment control, the loop bandwidth can be adjusted automatically during looking procedure, and fast locking can be achieved [93].

4.1.2. Counter-based DPLL

Another method to implement DPLL is to place TDC in the feedback path. As shown in Fig. 23, the feedback path consists of counter and TDC in counter-based DPLL. PLL is achieved by measuring the phase of the oscillator at the reference clock edge and comparing it with the ideal reference phase in the digital domain. For the fractional-N mode, the counter is used to calculate the periods of VCO, and TDC is used to identify more sophisticated phase information. The sum of these two values, which represents the integer and fractional parts, is the total variable phase. Note that the counter and TDC operate at DCO frequency, so it has more power consumption. At the same time, TDC divides the VCO period into several phases. Therefore, when PLL is locked, its instantaneous phase error is not greater than the resolution of TDC. Compared with divider-based DPLL, the quantization noise of the counter-based DPLL is greatly reduced. However, TDC needs to cover one VCO cycle and high resolution with sub-ps is required to suppress in-band noise. Since its implementation is similar to that of divider-based DPLL, it is not described here. Another problem is that the counter and TDC circuits work separately and then are collected by the reference signal at the same time. It should pay attention to the influence of matching errors in the design, and the consistency of the two data can be maintained to prevent the occurrence of VCO periodic errors, which will affect the spur performance of DPLL. To solve it, Lee et al. [94] uses glitch correction logic for calibration.

Fig. 23.

Structure of counter-based DPLL. 

4.2. Digital module design

4.2.1. Time-to-digital converter

From the above analysis, we can know that TDC plays a very important role in DPLL. As an alternative to phase detectors, TDC converts the phase difference into the digital signal, and thus DPLL can offer a feedback to correct itself. Except for BB-DPLL, which transfers the design complexity to the calibration circuit, other DPLLs put forward high requirements to TDC. Assuming that the resolution is Δτ_TDC, the in-band noise caused by the quantization noise of TDC can be given that:

$$P{N}_{in\_band\_TDC}=10{\log }_{10}\left(\frac{N{\pi }^2\Delta {\tau }_{TDC}^2}{3T_{ref}}\right)$$ (5)

where N is the divider radio. Assuming that N = 100 and f_ref = 100 MHz, Δτ_TDC should be less than 1.75 ps to make sure that the in-band noise can be lower than −110 dBc/Hz. Unfortunately, Δτ_TDC cannot be less than one gate delay and is limited by the process.

The basic delay-line TDC cannot achieve such high resolution. Thus, many complex TDC structures are used to improve its resolution, such as Vernier TDC, GRO-based TDC, etc. However, it comes with high power consumption and design complexity. For better performance, dual-path TDC can be used to get a smaller resolution, as shown in Fig. 24. Of course, it can also be extended to obtain multi-path TDC. Note that delay matching between the multi-path is difficult, which will affect the improvement of the in-band noise.

Fig. 24.

Structure of the dual-path TDC. 

In addition, the dynamic range of TDC is also complicated to implement. When the PLL is unlocked, the phase difference may reach a reference period. After locking, due to random changes in delta-sigma modulator (DSM), the phase difference is about several oscillator periods, which depends on the bits of DSM. Thus, DTC and time amplifier (TA) TDC are used to solve the dynamic range and resolution, respectively [95]. Meanwhile, a large dynamic range also increases the design complexity of linearity. The nonlinearity of TDC can cause large fractional spurs [96]. Therefore, Kuo et al. [97] uses a 1/8 length TDC to solve it. In short, to get better performance, the design of TDC becomes more challenging.

4.2.2. Digital-controlled oscillator

Digital-controlled oscillator (DCO) is the core of DPLL, the direct generation module of DPLL output, and restricts the jitter and locking accuracy. Unlike VCO, the output frequency of DCO is discrete, as shown in Fig. 25. In order to realize digital control of DCO frequency, DCO needs to contain multiple capacitor arrays to obtain more frequencies. However, discrete frequencies cannot cover all target frequencies, DCO usually varies at different frequencies during locking, and it is similar to the delta-sigma modulator (DSM). Thus, DPLL suffers from large jitter in the time-domain. In order to analyze the influence of discrete frequency, the quantization noise introduced by frequency resolution is first analyzed. If the frequency resolution is ∆f_LSB, the quantization noise introduced by frequency resolution is

$$S\left(\Delta f\right)=\frac{\Delta f_{LSB}^2}{12f_{ref}\Delta f^2}$$ (6)

Fig. 25.

Characteristic of DCO. 

It can be seen that the influence of quantization noise is inversely proportional to frequency resolution and reference frequency. To meet the needs of future communication development, frequency resolution should be guaranteed to suppress the influence of quantization noise. Beyond that, DCO suffers from other noise mechanisms as VCO.

The structure and principle of DCO and VCO are similar, but the difference lies in the realization of frequency control. In order to realize the digital control of frequency, three approaches are commonly used in DCO. As shown in Fig 26a, the first one is to add a digital-to-analog converter (DAC) before the input of DCO [98]. For this method, DAC and DCO can be designed, separately. Additional filters can be added to filter non-ideal components. The second one is to think of DCO as a DAC, the digital output of the filter is used to directly control the capacitor array of the DCO. The last one is only used in Ring-DCO, which can be controlled by changing the current. Because the frequency of the Ring-DCOs is determined by the delay of unit circuits, the output frequency can be changed by the binary control current source, as shown in Fig. 26b. It is worth noting that in the first two ways the frequency is strictly negatively correlated with the digital code. In the third method, however, the control code and output frequency may be nonmonotonic due to the mismatch between current sources, especially in the high-digit cases. Therefore, as the number of digits increases, the matching between current sources becomes critical.

Fig. 26.

Control modes of the DCO. 

In DPLL, the output of VCO needs to consider both frequency resolution and tuning range. Such as for a DPLL with 4–6-GHz output and 100-MHz reference, if the frequency resolution is 1 MHz, the capacitor array or current source should cover 2000 steps. Such a large array of capacitors will greatly reduce the Q value of the DCO tank, thus seriously affecting its robustness. In addition, according to (4), the phase noise of DCO caused by quantization noise is −90.8 dBc/Hz@1 MHz, which seriously affects the spectral purity of DCO.

In order to solve the above problems, DCO usually contains two or more arrangement modes of capacitor array [99]. Often, DCO consists of two capacitor arrays, a digital control binary capacitor array (DCCA) and a MOS capacitor array in the form of a thermometer code. Among them, DCCA is a coarse tuning array, and has the same structure as VCO. Thermometer code capacitor arrays are used to prevent mismatches. In practical design, the switching order of the MOS capacitor array is predetermined. It ensures the monotonicity between the capacitor and the control code and is helpful in achieving the optimization of linearity. Note that the switching order should be consistent with the physical layout of the layout. To better control the capacitor array, the MOS capacitor array can be in matrix form [100]. As shown in Fig. 27, the most significant bits of the control codes control the switching of an entire line or column, and other codes determine the number of remaining access capacitors.

Fig. 27.

Implementation of the MOS capacitor array. 

In short, compared with VCO, DCO also suffers from the influence of quantization noise, which can be solved by improving the frequency resolution. It also indicates that the performance of DCO is worse than VCO. To achieve both wide tuning range and frequency resolution, it is very important to design the capacitor array of DCO reasonably.

4.2.3. Digital filter

Compared with analog filters, the digital filter shows huge advantages in the area. The digital filter can be obtained by mapping the traditional analog filter. The s-domain model of the first-order analog filter can be given that:

$$H\left(s\right)=R_1+\frac{1}{s{C}_1}$$ (7)

The first term can be seen as a proportional relation, while the second term is an integral relation. Therefore, a digital filter usually contains two paths: integral path and proportional path. Converting (7) to the digital domain can be expressed as

$$D_{out}\left(k\right)=\alpha +\beta \sum _{k=0}^{\infty }{D}_{in}\left(k\right)$$ (8)

The z-domain model can be given that:

$$H\left(z\right)=\alpha +\frac{\beta }{1-z^{-1}}$$ (9)

The structure of the digital filter is shown in Fig. 28a. Note that the coefficients α and β cannot be obtained by simple conversion of analog filters. Since the conversion from CPPLL to DPLL is not just a digital filter, it should be compared with the functions of other modules.

Fig. 28.

Implementation of the digital filter. 

Unlike analog designs, in which order is mainly limited by stability reasons, higher-order DPLL structures can be built to achieve noise reduction requirements and accurate frequency responses [101]. It can be implemented by IIR and FIR filters. For example, As shown in Fig. 28b, a cascade of 4 single-stage filters is used [102], which attenuates the TDC quantization noise and reference at an 80 dB/dec slope. Overall, the digital design of the loop filter makes DPLL have better testability, flexibility, and portability to processes.

In conclusion, to solve the serious nonlinearity, device leaks, and higher costs on AMS-PLLs in advanced process, divider-based DPLLs and counter-based DPLLs are realized by digital realization of phase discriminator, filter and oscillator.

5. Digitalized power supply

This section summarizes and expounds on the development history and research status of power IC involving linear regulators, switching power supply and digital power supply. Then, the conclusion is derived that the digital power supply will become the inevitable trend of the future development of electronic equipment power supply.

Nowadays, with the improvement of the integrated circuits, power management chips are also developing in the direction of digitization [103]. Proposing efficient and reliable power management solutions has become the mainstream of the current power chip industry [104], [105].

5.1. Digital low dropout regulator

Conventional analog low dropout regulators (LDOs) can achieve fast transient response and low output noise [106], [107]. However, for an energy-efficient circuit that operates at sub-1 V supply voltage, analog LDOs face several design challenges due to their low voltage headroom and high susceptibility to PVT variations. In contrast, digital LDOs have recently gained significant attention from researchers for their advantages in low supply voltage, excellent process scalability and better portability [108], [109], [110].

In Fig. 29, it shows the typical architecture of digital LDO. It uses a voltage comparator to replace the analog amplifier and can operate down to 0.5 V. The voltage comparator senses the difference between the output voltage and the reference and generates quantized digital codes to regulate the power-transistor array through the later logic controller. However, such switch-array-based digital LDO relies on the internal logic controller to linearly search, and the transient speed is mainly determined by their sampling frequencies [108], [109]. Using a higher clock frequency effectively improves the transient response, but this brings a large dynamic power consumption. Moreover, an increasing frequency easily moves the open-loop pole closer to the unit circle in the discrete domain, leading to stability issues [110].

Fig. 29.

Typical architecture of digital LDO. 

Some optimized linear search schemes have been presented in recent studies to achieve faster response time. These search schemes improve the transient response, as it requires fewer clock cycles to resolve the error. However, the complicated control logic causes a larger power consumption of up to hundreds of μA [111], [112]. The multi-bit comparator or voltage quantizer [113], [114] is proposed to directly quantize the output voltage error for faster response. The area overhead associated with the comparators is the primary limiting factor.

To achieve the tradeoff among response time, power consumption and stability, various adaptive design methods have been proposed. Nasir et al.[115] adopted multiple VCOs to generate a sampling clock. The clock frequency adaptively varied with the output overshot and undershoot voltages. Higher sampling clocks during overshoot or undershoot are beneficial for the faster transient response, and a lower value in the steady period reduces the power consumption with excellent stability. Kundu et al. [116] further utilizes a time-based approach to replace the conventional voltage quantizer for low complexity. As shown in Fig. 30, a pair of VCOs converts the reference voltage and the output voltage to equivalent clock CLK1 and CLK2. According to the input frequencies, the time quantizer generates the digital code NOUT. NOUT is compared with the desired value by the digital controller to regulate the PMOS switches in the power-transistor array. The time quantizer dynamically generates an adaptive sampling clock in the digital LDOs, achieving fast response, low power consumption and excellent stability at the same time.

Fig. 30.

Digital LDO architecture[116]. 

Off-chip capacitor for stabilizing the output voltage is one of the critical overheads in existing digital LDOs, which significantly increases printed circuit board space and chip pin count. To achieve a fully-integrated digital LDO design, D. Kim et al. [117] present event-driven control architecture to scale down the size of output capacitor and improve transient performance. The proposed even-driven control and the binary digital PI controller achieve the latency reduction of the control loop, leading to a 2.7× improvement in Figure-of-Merit with an internal capacitor of 400 pF over the previous designs. To support large load current with a lower output capacitance, S. Kim et al. [118] further present PI structure with parallel structure, which significantly reduces the latency of the proportional part and improves the load regulations FoM by 3.9× and current density by 8.7× over the state of the arts. Adaptive linear/binary two-step search techniques [119] have been introduced in even-driven control for better transient performance in advanced memory applications.

5.2. Switching power supply

At present, the analog switching power supply still occupies a large share in the power management chip market due to its years of development, simple and efficient structure. However, as the switching frequency gradually increases, the traditional switching power supply has gradually become stretched and cannot meet the development needs of the current era. Therefore, the digitalization, intelligence and integration of the switching power supply are the response to the rapid development of the current chips [[120], [121], [122]].

Compared with the analog switching power supply, the digitalized switching power supply has the following characteristics [20]: (1) high efficiency; (2) flexibility, reliability; (3) robustness; (4) portability. However, the realization of digital switching power supply still faces many difficulties and challenges: (1) the workload is large; (2) the design is difficult; (3) it involves a wide range of fields.

As a frontier research direction in the field of switching power supply, switching power supply digitization has also undergone a period of development and research, but its definition has always been vague. However, with the deepening of the research on digitalized power supply, the mainstream view is: on the premise of the topology of the analog switching power supply, the digital switching power supply is a digital-analog hybrid circuit structure composed of a digital feedback system with DPWM as the core is constructed.

The same part of the two switching power supplies is the main power stage, and the difference is in the control loop part. As shown in Fig. 31a, the control loop adopts analog circuits composed of analog compensation networks, pulse width modulators and ramp signal generators. The control loop in Fig. 31b adopts digital circuit control, which consists of three parts: analog-to-digital converter (ADC), digital-proportion-integral-derivative (DPID) and digital pulse width modulator (DPWM). ADC converts the analog output voltage into a digital signal, which has a dedicated unit; thus, it won't go into detail here. The DPID compensator plays a vital role in the digital power supply, which serves as an error amplifier with compensation in the control loop, determining the dynamic response speed of the system. The DPWM module is the last module in the control loop, which converts the discrete digital signal after DPID compensation into a square wave signal with certain duty cycle information. Then it controls the ON and OFF of the power MOSFET. The DPWM module is equivalent to a digital-to-analog converter module, which converts discrete digital signals into continuous analog square wave signals.

Fig. 31.

Structural comparison of analog control switching power supply and digital control switching power supply structure. (a) Analog control switching power supply; (b) digital control switching power supply.

To obtain the tradeoff between accuracy, transient response and stability, many kinds of research have been reported. Z. Sun et al. [123] proposed a counter-based DPWM with the best linearity, as shown in Fig. 32. But the high clock frequency of the counter has been the bane of this architecture when operating with high resolution and high switching frequency.

Fig. 32.

The counter-based architecture of DPWM. 

The delay line-based architecture in Refs [124], [125], [126] is achieved by exploiting delay cells in Fig. 33, and its time resolution is the delay of a delay cell. This method does not require a high-frequency clock; however, the structure is very unstable. With the improvement of precision, the number of required modules increases exponentially. In practical applications, there is often a big difference between the ideal PWM waveform represented by the PID code and the actual PWM waveform.

Fig. 33.

The delay line-based architecture of DPWM. 

In Refs. [127], [128], the hybrid architecture of DPWM combining counter and digital clock manager (DCM) or phase-locked loop (PLL) is presented in Fig. 34, which employs DCM or PLL to generate four phase-shifted clocks, and the time resolution is equal to the delay between two adjacent phase-shifted clocks.

Fig. 34.

The DCM-based hybrid architecture of DPWM. 

The trend toward higher power density and high resolution has been present in the digitalized switching power supply. As shown in Fig. 35, the Σ-Δ in Refs. [129], [130], [131] is mainly used to add an indefinite "0/1″ sequence to the truncated output to achieve PWM averaging, which is the result of analog averaging. Compared to other DPWM, it neither adopts a delay line composed of delay units nor a high-frequency counter. On the contrary, it operates through the idea of compensation. As shown in Fig. 36, Cheng et al. [30] present a hybrid DPWM architecture to combine counter, synchronous phase-shifted circuit and delay line, which achieves high resolution while remaining optimal performance of linearity and time resolution. The dyadic digital pulse width modulation (DDPWM) technique [[132], [133], [134]] is revealed to obtain accurate LCO-free operation at negligible cost and design effort [135].

Fig. 35.

The Σ-Δ-based architecture of DPWM. 

Fig. 36.

The hybrid architecture of DPWM. 

In brief, to optimize the power consumption, process scalability and enhance the setting time of the feedback loop, feedback voltage quantizing and digital control based on DAC are embedded into the loop to constitute the digitalized power supply.

6. Future trends

The practicality of fully and partially digital implementations of analog circuits has been demonstrated during the past ten years, showing notable improvements over more traditional methods in terms of area and power. However, it should be noted that, in most circumstances, the performance of digitalized analog circuit implementations is not yet competitive with the best traditional analog counterparts in state-of-the-art. The performance gap is expected to be filled as the digitalized analog integrated circuits advance further on the following trends. It is expected that the general-purpose, reconfigurable, completely synthesizable, intelligently designed, and highly integrated digital architectures will be created in the near future to address an expanding range of applications.

6.1. Reconfigurable and programmable design

The programmable design has been widely used in the digital integrated circuits. The most typical representative is the field-programmable gate array (FPGA). The digitalization of analog integrated circuits makes it possible for the programmable analog integrated circuits. The field-programmable analogue array (FPAA) and software-defined chip (SDC) are crucial to improving turnaround time for analogue circuit designs [136], [137], [138]. Meanwhile, they are also appropriate for the multi-standard system applications to reduce the total manufacturing cost, improve the system performance, and minimize the chip size. Additionally, large-scale FPAA has the potential to handle machine inference and learning applications with significantly low energy requirements, potentially alleviating the high cost of these processes today, even in cloud-based systems.

6.2. Full synthesis

Conventional analog integrated circuits design still heavily relies on manual efforts. Traditionally, designers have to choose system architecture, circuit topology, and size devices while layout engineers have to draw device placement and wire routing. This high customization and manual involvement in analog design has severely constrained the turn-around-time and design scale, making it challenging to keep up with the pace of expanding market demands. The highly automated digital design counterparts have scaled to billions of transistor count. Thus, new analog design methodologies and development in analog automation tools are desired to speed up the current manual design flows [139], [140], [141]. The digitalized analog integrated circuits make it possible to extend digital automated design techniques to analog and RF systems.

6.3. Artificial intelligence (AI)-driven chip design

The AI and machine learning are changing the way we think about chip design, and in turn accelerating the innovation of hardware products such as AI. The emergence of machine learning is bringing about new, disruptive, AI-driven design solutions [142], [143], [144]. Like self-driving cars that continuously observe real-world driving conditions, this new breed of design tools learns from iterations and uses the knowledge in chip design environments to offer a leap forward in productivity. It revolutionizes chip design by massively scaling the exploration of options in design workflows while automating less consequential decisions and searches for optimization targets in very large solution spaces of chip design to exceed the previously achieved power-performance-area results.

7. Conclusion

Recent advances and trends in digitalized analog integrated circuits over the last decade have been reviewed in this tutorial, with a special emphasis on the implementation of analog functions by fully or partially digital circuits. Under this perspective, digitalized amplifiers, ADCs, PLL and power supply proposed in the last years, have been reviewed, highlighting their suitability in technology scaling. The current challenges of digitalized analog integrated circuits and their potential application scenarios have been finally considered and future perspectives have been discussed.

Declaration of competing interest

The authors declare that they have no conflicts of interest in this work.

Biographies

Zhangming Zhu(BRID: 09278.00.28598) received the B.S. M.S. and Ph.D. degree in microelectronics from Xidian University, Xi'an, China, in 2000, 2003, and 2004, respectively. Since 2009, he has been a professor with the School of Microelectronics, Xidian University, Xi'an, China. He has published over 100+ papers in IEEE journal. His current research interests include digital analog integrated circuits, high performance ADC and AFE, power ICs, RF-ICs, Lidar sensors, integration of opto-sensing and computing, intelligent edge computing for sensors.

Shubin Liu received the B.S. and Ph.D. degree in microelectronics from Xidian University, Xi'an, China, in 2007 and 2014. He is currently an professor with the school of microelectronics, Xidian University, Xi'an, China. His research interests include CMOS data converters, analog-front end and RF integrated circuits. He serves as an associate editor and a guest editor for IEEE Transactions on Circuits and Systems-I:Regular Papers.