A high-efficiency transformer-in-package isolated DC-DC converter using glass-based fan-out wafer-level packaging

Abstract

A transformer-in-package (TiP) isolated direct current–direct current (DC-DC) converter using glass-based fan-out wafer-level packaging (FOWLP) is proposed. By using 3-layer redistribution layers (RDLs), both the transformer and interconnections are built without an additional transformer chip, and the converter only has 2 dies: a transmitter (TX) chip and a receiver (RX) chip. The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density. Moreover, the transformer built by the RDLs achieves a high quality factor (Q) and high coupling factor (k), and the efficiency of the converter is thus improved. The TX and RX chips were implemented in a 0.18 µm Biopolar CMOS DMOS (BCD) process and embedded in a compact package with a size of 5 mm × 5 mm. With an output capacitance of 10 µF, the converter achieves a peak efficiency of 46.5% at 0.3 W output power and a maximum delivery power of 1.25 W, achieving a maximum power density of 50 mW/mm².

Graphical abstract

1. Introduction

Isolated direct current–direct current (DC-DC) converters play a key role in guaranteeing system safety and reliability in harsh industrial environments, including preventing electrical shock to human operators, protecting expensive devices from the risk of damage on a high voltage side, and breaking potential loops. For applications that need isolated power supplies (i.e., 0.1–1 W), such as electrical vehicles, medical equipment, communication buses, and insulated gate bipolar transistor (IGBT) drives, the requirements for a high level of integration and low cost are driving the development of isolated DC-DC converters toward miniaturization, high power density and high efficiency [1], [2], [3], [4].

Transformers have become more attractive isolation barrier candidates for isolated DC-DC converters due to their advantages of high power transfer capability, high isolation rate, and high noise immunity, which mainly determine the size and efficiency of the converter. As shown in Fig. 1, isolated DC-DC converter modules with bulky discrete transformers achieve 80% peak efficiency and more than 2 W of output power [5]. However, transformers are expensive and occupy a large portion of a printed circuit board (PCB). Efforts have been made to implement these transformers on silicon [6], [7], [8], [9], [10], [11], [12], [13], [14], [15] or in package [16,17] to reduce the form factor of the converter and improve the transformer efficiency. However, a transformer postprocessed on a silicon substrate suffers from high energy losses and a low-quality factor (Q) due to the thin metal layers and limited width. In addition, substrate leakage may occur, especially at operating frequencies of 100 s of MHz [18]. As a result, the conversion efficiencies of these converters are typically less than 35% [6], [7], [8], [9], [10], [11], as shown in Fig. 1. For example, Qin et al. [6] used a coreless microtransformer with two cores with both 6 µm thick Au windings and 20 µm thick polyimide between the coils to support an isolation rating greater than 5 kV and a cross-coupled LC tank oscillator that the transformer resonates over the frequency range of 180 to 210 MHz and delivers a maximum output power of 0.8 W. However, since the Q of the coils is only 6.8 at 200 MHz, the converter has a peak efficiency of less than 34%. A coreless transformer was formed by using a 100-µm ultrathick winding with an embedded silicon-based coil, and a Q of 15.7 for the primary coil was achieved, allowing converter switching at 10 s of MHz [7]. However, the secondary coil limits the transformer efficiency, and a converter with a flyback topology generates a large resonant current flowing into the coil, causing the efficiency to drop to 34% with only 165 mW output power. A magnetic core transformer achieving a Q of 16 and >100 nH inductance was presented [12,13]. This transformer is an integrated solenoid transformer structure, and a laminated magnetic material with high permeability and high resistivity is adopted for the magnetic core, providing a high coupling factor (k) of 0.92 and low loss. As a result, the converter achieves a 52% peak efficiency and a 1.1 W output power. However, a magnetic core transformer is fabricated by combining a microplating and magnetic core deposition process, which increases the fabrication cost and limits the overall package size in terms of compactness.

Fig. 1.

Trends and challenges for isolated DC-DC converters. 

Transformers implemented in packages can alleviate the thickness and width constraints of silicon-based coils and reduce coil losses, but the power density of a converter is limited by the size of the transformer. A coreless transformer was implemented with two internal layers of a 4-layer package substrate and packaged with the chips in a land grid array (LGA) [17]. A converter without an extra transformer chip reached 51% peak efficiency with 0.4 W output power and 1.2 W power capacity. However, there are limitations in terms of the substrate processing accuracy, e.g., the substrate transformer still occupies a large package size, with an area of 4 mm × 2 mm, and the thickness of the insulating material in this substrate process is limited to 0.1 mm, limiting the coupling coefficient (k) of the substrate transformer.

Moreover, the abovementioned converters use a transmitter (TX) chip, a receiver (RX) chip, with at least one transformer chip or a larger package substrate transformer, and are packaged in a small outline integrated circuit (SOIC) with an 8-lead, a 28-lead or an LGA package. These package sizes are 6 mm × 10 mm [6], 10 mm × 18 mm [12], or 12 mm × 10 mm [17], with maximum power densities of 13.33 mW/mm², 6.11 mW/mm², and 10 mW/mm², respectively.

In summary, the performance of a transformer is mainly limited by the manufacturing processes, such as postprocessing technology, which restrict the size, cost, power density, and efficiency of isolated DC-DC converters. To overcome the bottlenecks of isolated DC-DC converters, advanced packaging technology has received extensive attention in the market due to its advantages, such as a small form factor, better electrical performance, and multichip integration capability [19]. Recently, advanced packaging such as fan-out wafer-level packaging (FOWLP) has been used in the processor and memory [20]. It would be desirable to implement a transformer using advanced packaging techniques rather than additional transformer chips. In addition, high-Q coils can be achieved with thick metal redistribution layers (RDLs) based on low-permittivity substrates (i.e., ε_r of 5.1 for glass [21]), and it will reduce substrate leakage as the distance between the RDLs and the package substrate is larger than that of the standard silicon-based process.

In this paper, we proposed a transformer-in-package (TiP) solution for a galvanic isolated DC-DC converter in FOWLP [16]. It achieves a maximum output power of 1.25 W in a 5 mm × 5 mm package (maximum power density of 50 mW/mm²) and a peak efficiency of 46.5%. The transformer and interconnections are formed by using RDLs with low loss in FOWLP, while the converter only uses one TX chip and one RX chip.

The rest of this paper is organized as follows. In Section 2, the proposed TiP isolated DC-DC converter solution and the FOWLP fabrication process are discussed. In Section 3, the system architecture of the converter and the implementation of the circuit blocks are presented. The measurement results are provided in Section 4, and the research efforts are concluded in Section 5.

2. Proposed TIP isolated DC-DC converter solution and fabrication process

2.1. TiP solution and block diagram

Different from traditional packaging schemes such as SOIC and wire bonding or flip-chip ball grid arrays (BGAs), wafer-level packaging features a smaller form factor, lower cost, and better electrical performance [19]. It becomes even more attractive when employed for isolated DC-DC converters. Fig. 2a shows a comparison of isolated DC-DC converters using traditional and advanced packaging [16]. An isolated DC-DC converter using traditional packaging schemes typically requires at least three dies: a TX chip, a transformer chip, and an RX chip. Among them, the transformer chip is fabricated by postprocessing technology, and an extra transformer chip greatly increases the form factor and cost of the system. Moreover, due to the limitations of the width and thickness of the coil by using postprocessing, the transformer suffers from a low Q, and the conversion efficiency of the converter is degraded. In addition, the interconnections use bonding wires, and the parasitic resistance and inductance of the bonding wires inevitably increase power losses and aggravate electromagnetic interference (EMI) problems. In contrast, if FOWLP is used, both the transformer and interconnections can be formed using RDLs without an extra transformer chip. Therefore, a converter based on FOWLP has better electrical performance and higher efficiency, and it only requires two dies: a TX chip and an RX chip. Hence, the proposed TiP solution provides a significant cost reduction and major improvement in the power density and form factor.

Fig. 2.

The proposed solution for isolated DC-DC converter. (a) Isolated DC-DC converters using traditional packaging and the proposed TiP FOWLP, (b) cross-section view of the proposed converter using FOWLP [16], and (c) simplified block diagram of the proposed converter.

The cross-sectional view of the proposed TiP isolated DC-DC converter is illustrated in Fig. 2b. The entire FOWLP consists of a glass material, TX/RX chips, passivation layer (PI), 3-layer RDLs, solder balls, and PCB. The properties of the proposed glass-based FOWLP are summarized in Table 1. The mold compound in the classic embedded wafer level ball grid array (eWLB) package [22] is replaced by a glass material, which has the advantages of low cost and less loss [21]. First, the TX and RX chips are implanted into a cavity 300 µm deep in a glass substrate with a total thickness of 600 µm. Then, photosensitive dry film is filled into the micron-scale gap between the chips and the glass using a vacuum lamination process. Finally, the 3-layer RDLs are routed to build the TiP. The overall package is soldered onto the top metal layer of a PCB. Multiple PIs are used to protect the chips and increase the thickness of the isolation layers. The land pads for the BGAs are in the bottom PI. Meanwhile, thin-film technology is implemented to realize the 3-layer RDLs and under bump metallization (UBM). Multiple RDLs thus allow more freedom in designing a high-performance transformer in a fan-out area.

Table 1.

Properties of the proposed glass-based FOWLP. 

Parameter	Value (µm)
Total package height (without ball)	600
Glass wall thickness	306
Silicon IC thickness	300–320
Via1 thickness	15
RDL1 thickness	10
Via2 and Via3 thickness	15
RDL2 thickness	6
RDL3 thickness	10
Solder ball height	190
Ball diameter	250
Glass substrate thickness	300
Ball pitch	500

The block diagram of the proposed TiP isolated DC-DC converter is shown in Fig. 2c, which consists of a TX chip, a glass-based TiP as an isolation barrier, and an RX chip. To deliver power across the isolation barrier, an LC tank oscillator is used for direct current–alternative current (DC-AC) conversion in the TX chip, a rectifier is used for alternative current–direct current (AC-DC) conversion in the RX chip, and isolated feedback control is used to transmit the pulse width modulation (PWM) control signal from the RX to the TX to regulate the output voltage V_ISO, as will be discussed in Section 3.

2.2. Transformer design

The implementation of the transformer for the power stage requires the use of a stacked configuration for primary and secondary windings to ensure the isolation rate, taking advantage of the longitudinal isolation of the PI dielectric properties. The transformer design requires at least 3-layer RDLs, which allow the TiP more design flexibility than that of a single layer. However, the TX and RX chips are bonded in the pre-etched cavities, and the manufacturing operations will cause expansion and shrinkage because of the existence of a dry film in the trench and several PIs. The resulting warpage in turn will affect the exposure accuracy or exceed the handling capability of subsequent equipment sets.

To solve this problem, it should be noted that the structural and material properties of the dry film and other dielectric films have a substantial impact on the warpage for glass-based FOWLP wafers. The warpage can be controlled by choosing an appropriate dry film and other dielectric films with less thickness, smaller elastic modulus, or smaller thermal expansion (CTE) coefficient. Meanwhile, the mixed-use of thick-glass and thin-mold processes is utilized to keep multiple RDLs on the side of the silicon chip, which will decrease the warpage value. In addition, the average copper coverage of multiple RDLs can be controlled at a lower value, which can reduce the warpage of the glass-based FOWLP process.

The 3D view of the proposed TiP converter in the 3-layer RDL FOWLP package is shown in Fig. 3a. In this work, the primary coil (L_P) and secondary coil (L_S) are implemented in RDL1 and RDL2, respectively. A thick 15 µm PI with a dielectric breakdown strength of >400 V/µm is stacked among the 3 RDLs to form an isolation barrier, providing an isolation rating better than 5 kV [16]. The detailed codesign process is described as follows.

Fig. 3.

Design of a glass-based transformer. (a) 3D view of a glass-based transformer in FOWLP [16]. (b) Flow diagram of the codesign of the transformer and the circuit. (c) EM-simulated Q/self-inductance of the primary and secondary coils [16]. (d) EM-simulated k of the transformer.

The flow diagram of the codesign of the transformer and the circuit is shown in Fig. 3b. The starting point is the definition of the system specifications (i.e., output power P_OUT > 1.3 W) and efficiency (> 40%) along with the transformer performance (i.e., Q factor and coupling factor k). Thus, the first step is to build an electromagnetic (EM) model of the transformer by using 3D EM tools. Then, under the condition of the package size constraints, the width w, spacing s, inner diameter D_IN and number of turns N of the coil are designed to obtain the optimized Q and k of the transformer at the resonant frequency. Finally, the transformer is designed, and an S-parameter model is extracted for the next step of the power stage simulation verification. In the codesign of the isolated DC-DC converter, the margin of the transformer design must be considered since the operating frequency deviation of the power stage can significantly affect the Q and inductance for the limited-bandwidth transformer. Indeed, this design flow requires several iterative steps to achieve the target performance.

Both the primary and secondary coils, which are wound with RDL1 and RDL3, are 100-µm wide and 10-µm thick, with 3.5-turn windings and an inner diameter of 880 µm. RDL2 is also adopted for the interconnections between the TX/RX chips and coils.

Finally, Fig. 3c presents the EM-simulated Q/self-inductance of the primary and secondary coils, which are 11.6/13.8 nH and 9.6/16.7 nH at 210 MHz, respectively. The simulated k is 0.79 at 210 MHz, as shown in Fig. 3d, enabling over 1 W of power delivery. Since the Q of an inductor is equivalent to (1-ω²/ω_SR²)R/Lω, where ω_SR is the self-resonant frequency of the inductor, at lower frequencies, Q increases linearly with frequency and decreases to 0 as the frequency approaches the self-resonant frequency of the inductor. Fig. 3 shows that the self-resonant frequency of the transformer is significantly higher than its operating frequency.

2.3. FOWLP process flow

Die-first and face-up wafer-level packing is the foundation of the FOWLP manufacturing process. Fig. 4 depicts the fundamental manufacturing process flow for FOWLP with 3-layer RDLs. A glass-based FOWLP manufacturing method is described [21]. The following provides a detailed description of the design process for the TiP.

Fig. 4.

The process flow of glass-based FOWLP manufacturing. 

After thoroughly cleaning the glass wafer carrier, a laser-induced chemical etching procedure is used to create a number of through-glass cavities with the desired size [21]. When immersed in a hydrofluoric acid solution, a glass wafer zone irradiated by a femtosecond laser had a greater etching rate than that for a laser-unaffected zone [23]. The proposed cavity is broader and longer than the chip that is intended to be incorporated. The thin known good dies are then precisely aligned, positioned, and bonded with an adhesive using the "die-down" strategy in the glass cavities. Die shift is a significant issue in this process because of its special structure and will have an impact on how precisely the following lithography is performed. To protect the chips, vacuum film lamination is used to fill the trench between the chips and cavity without cracks and voids, and lithography is used to remove the film from the pads by exposing, developing, and curing at 200 °C for 2.5 h. After manufacture, the opening shift is less than 7 µm. Because the trench has been filled and the built wafer has been covered and flattened by the polymer, there is a slight height difference between the chip and silicon carrier. However, this height difference has no influence on the continuity of the fine-pitch RDL lines.

A Cu RDL is created using a conventional technique similar to that used in FOWLP and includes seed layer deposition, photoresist patterning, copper plating, photoresist stripping, and seed layer etching. A titanium barrier layer and copper seed layer are created on the whole wafer surface using physical vapor deposition (PVD), as shown in the sixth stage of Fig. 4. The Ti and Cu layers have target thicknesses of 300 and 500 nm, respectively. Next, a generally negative photoresist (i.e., JSR111) is spin-coated onto the entire wafer surface and patterned using exposing and developing procedures. Cu RDL 1 is created by wafer-level electroplating on an RDL lithography opening. The nonexposed area's barrier and seed layer are etched away. RDL 1 is formed in contact with the silicon chip pads, and the next level interconnects. RDL 2 and RDL 3 are then produced by repeating the fifth to ninth steps.

Three-layer Cu RDLs are used in this work for the power, analog, digital, and ground lines, and thus, numerous PIs are utilized to protect the active side, chip, and metal lines. The last PL, which has the same passivation as that of the first PL, is employed in the twelfth step of the fabrication process and has an excellent loss tangent. The UBM for the solder ball is created on the last PL opening. Then, using the solder ball drop method, a BGA is joined to the backside of the UBM. The wafer is subsequently placed in a reflow furnace to melt the solder balls. Finally, solder ball interconnection is accomplished. After BGA formation, the wafer is diced, the embedded glass FOWLP is completed, and the fan-out package can be flip-chipped onto the PCB.

3. Implementation of the TIP isolation DC-DC converter

The block diagram of the proposed TiP isolated DC-DC converter is presents in Fig. 5. The power stage consists of an LC tank oscillator in TX and a full-bridge metal oxide semiconductor (MOS) rectifier in the RX. In the control stage, PWM control with Type-II compensation is used in the RX. The PWM signal switching at 625 kHz is transmitted from the RX chip to the TX chip by a digital isolator to regulate the output voltage V_ISO. Since the transmit power can be adjusted by turning the LC tank oscillator on and off according to the system output power, the overall efficiency of the converter can be optimized.

Fig. 5.

Block diagram of the proposed TiP isolated DC-DC converter and its working principle. 

3.1. Power stage design

The simplified schematic of the power stage is shown in Fig. 6. In the TX, an LC tank oscillator consists of a pair of power transistors (M_1,2) in a cross-coupled configuration that alternately charges the transformer for DC-AC conversion. A transformer with the center tap connected to V_DD produces an oscillation amplitude of approximately πV_DD for efficient energy transmission. To cope with the wide supply voltage range of 3 V to 6 V for various operating conditions, expensive processes, and large chip areas are required if a high voltage (HV) thick gate oxide process is used; thus, low-cost n-channel lateral double-diffused MOS (nLDMOS) power transistors can withstand a 20-V drain to source voltage (V_DS) and implement power transistor M_1,2 in this design. However, the oscillation amplitude is also too high for the thin gate oxide nLDMOS with a 5-V withstand voltage. Hence, the gate-source voltage (V_GS1,2) of M_1,2 is controlled within 5 V by an AC-coupled structure with a capacitive voltage divider formed by the AC-coupled capacitors C_P1,2 and the gate-source parasitic capacitance C_GS1,2, avoiding gate oxide breakdown.

Fig. 6.

Design of the power stage. (a) Schematic of the power stage [16]. (b) Simulated power loss breakdown of the proposed converter under different conditions.

Compared to the cross-coupled active TX and RX topology [24], the LC tank oscillator operates in a self-resonant state, and its power loss is only conduction loss without switching loss. The size of M_1,2 needs to be large enough to reduce on-resistance and drive 1.3 W output power P_OUT. After adding the capacitors C_P1,2, the resonant frequency of the oscillator can be calculated as $f_{osc}=1/2\pi \sqrt{L_P(C_{GS}+C_{GD})\parallel C_{P1}}$, where L_P, C_GS, and C_GD are the primary inductance, gate-source parasitic capacitance, and gate-drain parasitic capacitance of the power transistors, respectively. As a result, the oscillation frequency f_osc of the LC tank oscillator in this design is determined to be 200 MHz in this work.

However, for traditional AC-coupled structures with fixed coupling capacitors C_P1,2, the gate-source voltage (V_GS1,2) of M_1,2 will easily exceed a 5-V maximum voltage at high V_DD, i.e., 6 V. In this design, this issue is efficiently addressed by adding MOS varactors C_C1,2 into varactor section C_P1,2. As shown in Fig. 6a, when V_GS1,2 are in a safe operation region (V_GS < 4 V), the capacitance of C_P1,2 maintains a certain value. Because the capacitances of C_C1,2 decrease rapidly when V_GS1,2 becomes larger than 4 V, V_GS1,2 is well controlled at 5 V and even at 6 V V_DD. Moreover, it uses large resistors R_B to set the DC-bias voltages V_B on the gates of M_1,2 to guarantee the start-up condition of the oscillator.

As shown in Fig. 6a, in the RX, an MOS full bridge rectifier is used instead of a full bridge Schottky diode to achieve high conversion efficiency without process constraints. The cross-coupled structure is also applied to drive the 9-V LDMOS power transistors M_3,4 to prevent V_GS3,4 from being higher than 5 V. However, the conventional cross-coupled complementary MOS (CMOS) rectifiers have severe reverse currents from the load to the input of the rectifier [25], which will greatly degrade the efficiency. A voltage clamper composed of M₇ and M₈ is used to bootstrap the gate voltage V_CG of the power transistors M_5,6 to V_ISO−VTH,M8, so that M_5,6 can be completely turned off when V_OP,ON are low, and the reverse currents thus are eliminated [26].

The pie charts of the simulated power breakdown of the converter under different conditions are shown in Fig. 6b. When V_DD/V_ISO = 3.3 V/5 V at P_OUT = 0.25 W, the converter efficiency is 52.1%, and the LC tank oscillator, TiP, and rectifier efficiencies are 75.6%, 84.1% and 82%, respectively. When V_DD/V_ISO = 5 V/5 V at P_OUT = 0.25 W, the converter efficiency is 46.2%, and the LC tank oscillator, TiP, and rectifier efficiencies are 73.5% 76.7% and 82%, respectively. Owing to the low-loss RDL through using the FOWLP, the proposed TiP solution with high Q significantly improves the efficiency of the converter compared to that of other coreless transformers [6,7].

3.2. Control stage design

The schematic of the control stage is shown in Fig. 5. The isolated control stage utilizes PWM control for regulation by turning the LC tank oscillator on and off to regulate the output voltage V_ISO. The PWM control senses the output voltage V_ISO and compares it with the reference voltage V_REF. The choice of PWM frequency requires a trade-off between the output voltage ripple ΔV_ISO and the power consumption of the digital isolator. In this design, the PWM frequency is chosen to be approximately 625 kHz. The resonant frequency of the LC tank oscillator is considerably greater than that of the PWM frequency. This significant discrepancy facilitates a clear separation between energy regulation and conversion, thereby optimizing power transfer and preserving regulation.

Based on the TiP described above, a conjugate pole formed by its equivalent inductance of the transformer (approximately 10 s of nH) and the output load capacitance (C_L of 10 µF) is outside the loop bandwidth of the system (1/10 f_PWM). Thus, the power stage has only a single output pole (1/R_LC_L). Therefore, Type-II compensation is used to provide a value of zero to compensate for the output pole to stabilize the system and achieve a faster transient response.

The circuit schematic of the digital isolator is depicted in Fig. 7. The isolator consists of an encoder and a decoder with a pulse polarity modulation scheme [27]. The isolation barrier is realized by the on-chip transformers on the RX chip. An on-chip transformer using SiO₂ as an isolation dielectric with high noise immunity is an attractive candidate for the isolated control stage, providing a high dielectric isolation strength of >500 V/µm [28,29]. As shown in Fig. 7a, the encoder first detects the rising and falling edges of the input PWM1 signal, and then the short pulse signals S₁ and S₂ are used to control the driver transistors M_P1,2 and M_N1,2 to drive the coils to generate pulse signals V_PULSE. In this design, the typical swing and width of the V_PULSE after passing through the on-chip transformer are approximately 2 V and 500 ps, respectively. Then, the pulse signal V_PULSE is filtered and shaped, and the PWM1 signal is recovered at PMW2 by the hysteresis comparator in the decoder.

Fig. 7.

Schematic of control stage. (a) the digital isolator and (b) the undervoltage-lockout (UVLO).

In the RX, the output voltage V_ISO is also the power supply for the control circuit. At startup, the control stage cannot function properly at a low power supply since V_ISO is raised from 0 V. An undervoltage-lockout (UVLO) circuit is needed in the power-on of the RX. During startup (as shown in Fig. 7b), when the V_DD reaches a certain value (2.7 V in this design), the UVLO output enables the signal EN_UV (becomes “0”) to turn on the encoder, and the control stage begins to take over the system. Moreover, UVLO with hysteresis and a soft-start mechanism in the TX and RX ensures robust system performance under noisy conditions and avoids overshooting the output voltage during power-up.

4. Measurement results

The RX and TX chips are fabricated in a 0.18 µm bipolar-CMOS-DMOS (BCD) process and are assembled with the transformer in a compact glass-based FOWLP. Fig. 8a shows a microphotograph of the TX and RX chips and a photo of the proposed TiP converter. The overall package occupies an area of 5 mm × 5 mm. The die areas of the RX and TX chips are 800 µm × 1450 µm and 1200 µm × 1450 µm, respectively.

Fig. 8.

Measurement results. (a) Photo of the RX and TX chips and the proposed converter in package, (b) measured start-up waveforms, (c) measured steady-state at heavy load, (d) measured steady-state at light load, (e) measured load transient, and (f) measured conversion efficiency of the converter under various conditions.

The measured waveform of the output voltage V_ISO is shows in Fig. 8b. The proposed converter achieves a smooth transition during start-up. Fig. 8c,d show the measured steady-state waveforms of V_ISO and the PWM1 signal in the RX chip when the supply voltage V_DD and the output power P_OUT is 5 V/1 W (load current of 200 mA) and 3.3 V/0.1 W (load current of 20 mA), respectively. With an output capacitance of 10 µF, the measured V_ISO ripples are 18 mV and 20 mV, respectively.

The measured load transient responses is shows in Fig. 8e. The proposed converter achieves a stable transition between heavy and light loads with tight regulation. When P_OUT is changed between 0.75 W and 0.25 W, the measured undershoot and overshoot are only approximately 350 mV and 370 mV, respectively, with recovery times of 100 µs and 90 µs, respectively. The measured maximum P_OUT is 1.25 W when V_DD/V_ISO = 5.5 V/5 V, achieving a maximum power density of 50 mW/mm².

The measured conversion efficiency of the proposed isolated DC-DC converter under different conditions is shows in Fig. 8f. The peak efficiency reaches 46.5% at 300 mW P_OUT when V_DD/V_ISO = 3.3 V/5 V, and the efficiency is higher than 36.9% at a P_OUT of 0.1 W to 1.05 W under V_DD/V_ISO = 5 V/5 V conditions. The measured efficiency of the converter is approximately 6% lower than that of the presimulation results, as shown in Fig. 6b. This is mainly due to the loss on the vias and metal routing for the power transistors and manufacturing process deviation.

The performance comparison between the proposed converter and state-of-the-art designs is summarized in Table 2. Owing to the TiP solution using glass-based FOWLP, the proposed converter achieves at least 3.75 times higher power density than that of the prior designs and the highest delivery power capacity among the designs using coreless transformers in Table 2.

Table 2.

Performance comparison with previously published works. 

Reference	ISSCC’19 [6]	ISSCC’19 [12]	ISSCC’20 [7]	ISSCC’22 [2]	ISSCC’22 [17]	This work
Technology	0.35 µm BCD	0.35 µm BCD	0.35 µm BCD	0.18 µm BCD	0.18 µm BCD	0.18µm BCD
Isolation Barrier Type	Coreless TF chip	Magnetic core TF chip	Coreless TF chip	Off-chip capacitor with PCB coils	Coreless substrate TF	Transformer-in-package
Input Voltage	4.5–5.5 V	4.5–5.5 V	3.3 V	3.3 V	4–5.5 V	3–6 V
Output Voltage	3.3 V-5 V	5 V	3.3 V	1.8 V	3.3 V/5 V	3.3V/5 V
Max. POUT	0.8 W	1.1 W	0.165 W	0.8 W	1.2 W	1.25 W
Peak Efficiency	34%	52%	34%	68.1%	51%	46.5%
No. of Die	3	4	3	2	2	2
Package (Size)	SOIC-8 (10 mm × 6 mm)	SOIC-28 (10 mm × 18 mm)	N/A	Chip on board	LGA package (10 mm × 12 mm)	Glass-based FOWLP (5mm × 5mm)
Power Density *	13.33 mW/mm2	6.11 mW/mm2	N/A	N/A	10 mW/mm2	50mW/mm2

^⁎Power density is calculated by dividing the maximum output power by the package size.

5. Conclusion

This paper presents a TiP solution for an isolated DC-DC converter by using glass-based FOWLP. The winding of a high-performance coreless transformer was realized by using 3-layer RDLs on a compact 5 mm × 5 mm package, which required at least one less transformer chip, effectively improving the converter efficiency and power density. In addition, a varactor section was placed in an LC tank oscillator to cope with a wide V_DD range of 3 to 6 V. TX and RX chips were fabricated in a 0.18-µm BCD process and assembled in FOWLP. The experimental results verified the effectiveness of the proposed TiP solution. The converter achieved 46.5% peak efficiency and 1.25 W P_OUT, achieving a 50 mW/mm² power density.

Declaration of competing interest

The authors declare that they have no conflicts of interest in this work.

Biographies

Lin Cheng received the B.Eng. degree from Hefei University of Technology, in 2008, the M.Sc. degree from Fudan University, in 2011, and the Ph.D. degree from Hong Kong University of Science and Technology (HKUST), in 2016. He was a post-doctoral with HKUST, from 2016 to 2018. In 2018, he joined the School of Microelectronics, University of Science and Technology of China, where he is currently a professor. His current research interests include power management, mixed-signal integrated circuits and systems, and wireless power transfer circuits and systems. Dr. Cheng is serving as a member of the IEEE ISSCC Technical Committee and the chair of IEEE ICTA 2024 Technical Committee.

Dongfang Pan(BRID: 07627.00.80611) received the Ph.D. degree in electronics science and technology from the Department of Electronics Science and Technology, University of Science and Technology of China (USTC), China, in 2019. From 2018 to 2019, he was a visiting scholar with the Department of Electrical Engineering, Southern Methodist University (SMU), Dallas, USA. From 2019 to 2021, he was a post-doctoral fellow with the School of Microelectronics, USTC. He is currently an associate researcher with the School of Microelectronics at USTC. His research interests include Isolated DC-DC converters, high-frequency power ICs, CMOS RF transceivers, and system designs including PA, LNA, and analog IC.