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. 2024 Dec 31;10(1):1006–1011. doi: 10.1021/acsomega.4c08274

ITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM

Jeong-Min Park †,‡, Sein Lee †,‡, Junseo Lee †,‡, Jang-Yeon Kwon †,‡,*
PMCID: PMC11739972  PMID: 39829566

Abstract

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We developed a two-transistor, zero-capacitor (2T0C) gain-cell memory featuring a self-aligned top-gate-structured thin-film transistor (TFT) for the first time. The proposed indium tin zinc oxide (ITZO) channel-incorporated architecture was specifically engineered to minimize parasitic capacitance for achieving long-retention 2T0C memory operations. A typical 2T0C structure features five types of parasitic capacitances; however, the proposed SATG design effectively used an essential gate insulator capacitance (COX) and reduced four nonessential capacitances (CWBL-WWL, CWWL-SN, CRWL-SN, and CRBL-SN) to virtually zero. The ITZO-based 2T0C gain-cell memory achieved a retention time >10,000 s owing to the extremely low off-current (2.33 × 10–18 A/μm), superior positive-bias stability (0.71 V), and high saturation mobility [17.52 cm2/(V s)] of the optimized TFT structure. Our proposed memory with long retention and high endurance is a promising solution for next-generation 3D-integrated stacked dynamic random-access memories and defines a new structural standard for future memory architectures.

Introduction

Moore’s law has encountered considerable limitations over the years, particularly in the domain of dynamic random-access memories (DRAMs).1−4 A critical barrier is the minimum feasible size of a capacitor, which must be maintained to prevent the generation of leakage currents and to manage refresh rates.5,6 In addition, the large aspect ratios of these capacitors hinder the three-dimensional (3D) integration of DRAMs by obstructing the stacking of multiple layers. A two-transistor zero-capacitor (2T0C) gain-cell memory containing oxide channels has emerged as a promising solution, representing a potential paradigm shift in DRAM scaling.7−13 However, the current transistor-structure designs used for fabricating 2T0C memories contain numerous charge-trapping sites that disrupt the flow between the write and read transistors, ultimately compromising data storage at the storage node. The transistor structure is important because of the unique working principle of 2T0C. Charges are trapped in the gate oxide of the read transistor and can be leaked toward several paths in the device. The fast leakage of these charges degrades retention time, thereby increasing the refresh rate and energy consumption. The attempts to improve refresh rate and energy consumption were based on minimizing the leakage current using the characteristics of the oxide channels. Various thin-film transistor (TFT) structures have been introduced and employed in 2T0C DRAMs;11,13−15 however, the best approach for fully utilizing a storage node remains unexplored from the perspective of a transistor structure.

This study integrates a self-aligned top gate (SATG) structure in a 2T0C gain cell for the first time. A SATG ensures minimal parasitic capacitance in the structure and has been reported in many previous studies.16,17 A SATG structure effectively curtails unnecessary capacitances that do not contribute to charge storage and consequently improves the operational efficiency of the memory. In addition, using indium tin zinc oxide (ITZO) as the channel material, the proposed SATG design achieves a low-leakage current and significantly improves the electrical characteristics of the resulting 2T0C DRAM cells. The ITZO-based 2T0C gain-cell memory exhibits a remarkably low off-current of ∼2.33 × 10–18 A/μm, yielding retention times exceeding 10,000 s. The proposed memory marks a substantial advancement toward highly efficient, high-performance 3D-integrated DRAM architectures. Furthermore, the 2T0C gain-cell memory can be adapted to monolithic 3D integration devices.

Experimental Section

Device Fabrication

Figure 1a illustrates the SATG structure, and Figure 1b presents the fabrication process of the ITZO SATG TFT. The device was constructed on Si wafers containing a 300 nm-thick thermally grown SiO2 film. A 30 nm-thick amorphous ITZO layer was deposited using radio frequency sputtering, followed by patterning via maskless lithography and wet etching with a 2.5% diluted HCl solution. The device was subsequently annealed at 500 °C in air. Next, a 70 nm-thick SiO2 gate insulator and a 50 nm-thick tungsten gate layer were sequentially deposited using plasma-enhanced chemical vapor deposition and direct current sputtering. After patterning the gate, tungsten was wet etched and the photoresist was removed via acetone sonication. Subsequently, the SiO2 layer was dry etched along the gate pattern using an inductively coupled plasma reactive ion etching system (ICP-RIE). The device was then annealed at 300 °C in a vacuum, and the ITZO channel was metalized using Ar plasma in ICP-RIE to form the n+-ITZO source/drain region. The source and drain regions were defined using maskless lithography, followed by the deposition of a 50 nm-thick tungsten layer. Finally, the tungsten layer was patterned using the lift-off method to form the source and drain. The channel length and width were 20 and 40 μm, respectively.

Figure 1.

Figure 1

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(a) Schematic of the indium tin zinc oxide self-aligned top gate thin-film transistor (a-ITZO SATG TFT). (b) Fabrication process of the a-ITZO SATG TFT. (c) Optical image of the write and read transistors connected via tungsten (2T0C DRAM). (d) Cross-sectional transmission-electron-microscope image of the gate/gate insulator/channel layer.

Device Characterization

Figure 1c shows an optical image of two interconnected SATG TFTs, in which the drain of the write transistor connects to the gate of the read transistor for memory operations. Figure 1d presents a cross-sectional image of the 2T0C memory, highlighting the storage node for charge storage. The cross-sectional image was investigated using JEM-F200 (JEOL). The electrical characteristics were measured using a Keithley 4200 Semiconductor Characterization System under vacuum conditions with four probes, as the 2T0C DRAM structure operates as a four-point device.

Results and Discussion

Figure 2a presents the transfer curve and saturation mobility of the ITZO SATG TFT obtained under a gate voltage sweep from −15 to 15 V with a drain voltage of 5.1 V. At VDS = 0.1 V, ION is 3.31 × 10–8 A/μm and IOFF is 2.33 × 10–18 A/μm, achieving an on/off ratio of 1.4 × 1010, as displayed in Figure S1. The current values were normalized by dividing by channel width, 40 μm. The saturation mobility of 17.54 cm2/(V s) is critical for fast memory write and read speeds, and a VTH of −1.34 V minimizes leakage current. The subthreshold swing was 80 mV/decade, essential for fast switching between data “0” and “1” and a large read margin in the 2T0C memory. Figure 2b displays the output curves, and Figure 2c and d illustrate the positive-bias stabilities (PBS) and negative-bias stabilities (NBS) of the ITZO SATG TFTs, respectively. In PBS and NBS transfer curves, ΔV1nA shifted by 0.71 and 1.11 V when the gate was stressed at 15 and −15 V for 1 h, respectively.18 Bias stability is crucial for retention and endurance in DRAM operations. Several voltage pulses from 5 to −5 V are simultaneously applied at the gate and drain during the memory operation of the write transistor, as depicted in Figure 3b. Moreover, the read transistor must maintain a stable transfer curve despite the voltage bias generated by the accumulated charges in COX. Therefore, the device must yield a stable transfer curve even after numerous cycles to obtain high endurance and long retention of the 2T0C DRAM.

Figure 2.

Figure 2

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Electrical properties and reliability of the a-ITZO SATG device. (a) Transfer characteristics of the a-ITZO SATG TFT with a drain voltage of 5.1 V and gate voltage sweep from −15 to 15 V. The saturation mobility is depicted in red. (b) VGS output characteristics from −5 to 15 V in 5 V steps. (c) Positive-bias stability results obtained by applying a gate voltage of 15 V for 1 h. (d) Negative-bias stability obtained by applying a gate voltage of −15 V for 1 h.

Figure 3.

Figure 3

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2T0C circuit schematic, pulse diagram, and electrical characteristics of data “1” and “0”. (a) Schematic of the ITZO SATG 2T0C DRAM cell. The red signs describe the unnecessary capacitances. (b) Voltage pulse diagram of the write word, write bit, read word, and read bit lines. (c) Measured drain current of the read transistor. The blue and red points represent data “1” and “0”, respectively. (d) 29 endurance data cycles. The blue and red points represent data “1” and “0”, respectively.

A horizontal shift in VTH was observed in the transfer curve obtained under VDS = 0.1 and 5.1 V due to Ar plasma metallization, which induces defects and charge trapping in the n+ ITZO region. Despite this shift, the stable bias properties of the TFT ensured reliable 2T0C DRAM performance.

Figure 3a displays the schematic of the 2T0C gain-cell memory, in which the drain of the write transistor and the gate of the read transistor are interconnected to facilitate charge movement. The parasitic capacitances that can disturb the write and read operations are illustrated in red. Figure 3b depicts the pulse voltage diagram of the memory operation; the write word line (WWL) receives ±5 V to toggle the write transistor during write and hold operations. The write bit line (WBL) applies +5 V to write data “1”, enabling charge flow from the storage node (COX) of the read transistor. To write data “0”, WBL applies −5 V to enable charge flow to the COX of the read transistor. The read bit line (RBL) and read word line (RWL) are maintained at 0.1 V and ground, respectively, during reading. Figure 3c demonstrates the write 1 → read → write 0 → read operation sequence, yielding a read margin greater than 105 between data “1” and “0” due to the substantial on/off ratio obtained from the transfer curve of the device. Figure 3d confirms excellent endurance performance, maintaining the original read margin between data “1” (blue) and “0” (red) for over 29 cycles, with the endurance limited only by mechanical constraints. This robust endurance can be attributed to the exemplary bias stability of the SATG TFT device.

Figure 4a depicts the retention characteristics corresponding to data “1” and “0” with various VHOLD (−5, −2, and 0 V) applied on the WWL. To measure the retention time, following the write “1” pulse, a read operation was executed for 104 s, and subsequently, a similar read operation was conducted for the same duration after a write “0” pulse. As shown in Figure 4a, the current corresponding to data “1” remains stable, registering an initial current of 1.14 × 10–7 A at 0 s and 1.24 × 10–7 A at 104 s under a VHOLD = −2 V applied at the WWL during reading. The current corresponding to data “0” increased from 4.88 × 10–13 to 2.06 × 10–11 A owing to the slow depletion of charges in the storage node. This steep increase of IRWL corresponding to data “0” indicates that the retention time of the 2T0C device is contingent on the current level of data “0”. The fitted curves shown in Figure 4b and c are used to determine the retention time by converting IRWL to VSN. Figure 4d shows the VSN corresponding to data states “1” and “0” with VHOLD = −2 V, revealing a retention time of >104 s. Retention failure was identified when ΔVSN exceeded 0.5 V.19 The data states “1” and “0” maintained a substantial margin exceeding 4 V even after 104 s of holding. Figure 4e presents the retention characteristics under varying VHOLD settings applied at the WWL during the read phase; VHOLD = −2 V is sufficient for minimizing the leakage current to the write transistor. At VHOLD = 0 V, an increase in leakage current via the write transistor reduced the retention time to 824.4 s, which is still long in relation to DRAM operations. However, at VHOLD = −5 V, despite controlled drain leakage, the increased gate leakage slightly impaired the retention properties. Therefore, selecting the optimal VHOLD is pivotal for achieving optimal retention in 2T0C DRAM applications.

Figure 4.

Figure 4

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Retention property of the 2T0C device with several hold voltage (−5, −2, and 0 V) conditions. (a) Measured IRWL of the read transistor for 104 s. (b) Polynomial fitting of the VSN calculation in the high-drain-current domain. (c) Exponential fitting used for VSN calculation in the low-drain-current domain. (d) Extracted VSN from IRWL. (e) Retention time with different hold voltages applied.

To ensure long retention in the 2T0C DRAM, minimizing leakage current is crucial; this can be effectively achieved using an ITZO channel. However, charges continue to leak from the COX via pathways such as CRWL-SN and CRBL-SN.10,20 Applying the SATG structure is key, as it prevents overlap between the gate, source, and drain, ensuring full charge retention in the storage node without interference from extraneous capacitances. This design effectively suppresses capacitive coupling effects, thereby avoiding a sharp drop13,14,19 in VSN immediately after a write operation ends and a read operation begins. Future research on 2T0C DRAM should focus on selecting the appropriate device structure to maximize the COX and minimize other parasitic capacitances.

When the channel size is reduced to the nanometer scale, the capacitance (COX) should decrease, thereby reducing retention time, if the leakage current (Ileak) remains consistent. The retention time (tRET) can be estimated using the following equation

graphic file with name ao4c08274_m001.jpg 1

Scaling down the channel dimension is crucial for adapting this device to DRAM technology. When the channel dimension of the SATG is reduced to a few nanometers, a retention time of ∼1 s can still be achieved to accommodate the present DRAM refresh rate of 64 ms. Moreover, the voltage scale can be reduced via device scaling and by using high-dielectric-constant insulators21 to facilitate low-power memory operations.

Table 1 compares the retention times of the 2T0C device with those of other TFT structures. The SATG TFT-based 2T0C device exhibits minimal parasitic capacitance and is, therefore, an excellent candidate for use in DRAM cells in the future. This device structure efficiently uses charges solely for the read operation, effectively compensating for the structural features of the 2T0C configuration without the use of capacitors. In future studies on the 2T0C DRAM, the structure of the TFT should be carefully considered to facilitate efficient charge accumulation in the COX.

Table 1. Performance Comparison with Other TFT Structures.

  Reference (11) Reference (14) Reference (8) Reference (15) this work
structure vertical CAA bottom gate top gate bottom gate SATG
channel IGZO IGZO/CNT IGZO ITO ITZO
IOFF (A/um) 1.8 × 10–17 1 × 10–14 1 × 10–19 4 × 10–19 2.3 × 10–18
retention (s) 300 500 >1000 2250 >10,000
TWRITE NA NA 10 ns 100 ns 200 ms
endurance NA NA >1011 NA >29
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Conclusion

We demonstrated a 2T0C memory using an ITZO SATG TFT structure optimized for long-term operation with minimal parasitic capacitance. The high-performance ITZO TFT exhibited a saturation mobility of 17.54 cm2/(V s), an ION/IOFF ratio of 1.4 × 1010, a subthreshold swing of 80 mV/decade, and a threshold voltage shift ΔV1nA of 0.71 V and achieved an exceptionally low leakage of 2.33 × 10–18 A/μm. The proposed 2T0C memory device exhibited a read margin greater than 105 and an endurance exceeding 29 cycles. Additionally, we have successfully reduced four nonessential capacitances, namely, CWBL-WWL, CWWL-SN, CRWL-SN, and CRBL-SN, to virtually zero. Consequently, our device achieved a retention time >10,000 s, with a ΔVSN drop of 0.34 V only. The application of the SATG structure to the 2T0C DRAM enabled the efficient storage, reading, and writing of charges, underscoring the efficacy of the structure in enhancing memory performance and stability.

Acknowledgments

This work was supported by BK21 FOUR (Fostering Outstanding Universities for Research) funded by the Ministry of Education (MOE) of Korea. This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIP) (Grant. No RS-2024-00351713).

Supporting Information Available

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsomega.4c08274.

  • Transfer curve and mobility of SATG ITZO TFT, VGS swepted from −15 to 15 V with VDS = 0.1 V applied (PDF)

Author Contributions

J.-M.P.: conceptualization; formal analysis; investigation; methodology; validation; visualization; writing—original draft; writing—review editing. S.L.: conceptualization; formal analysis; validation; visualization. J.L.: visualization; investigation. J.-Y.K.: conceptualization; project administration; resources; supervision; validation; writing—review editing.

The authors declare no competing financial interest.

Supplementary Material

ao4c08274_si_001.pdf (111.2KB, pdf)

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Associated Data

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Supplementary Materials

ao4c08274_si_001.pdf (111.2KB, pdf)

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