A review of GaN RF devices and power amplifiers for 5G communication applications

Abstract

In the emerging 5G and beyond 5G (B5G) era, the spotlight is sharply focused on the power amplifier, a critical component with stringent specification requirements that dictates the performance of the transmitter. The gallium nitride (GaN) device, with its superior inherent properties, is surfacing as a front-runner for power amplifier applications. The increasing demand for high frequency, high linearity, and cost-effective GaN power amplifiers is driven by anticipated traffic surges and the need for extensive 5G deployment. This paper offers a thorough review and future perspective on research developments in RF GaN device technology. It encompasses critical issues in advanced device and circuit technology, with a focus on high frequency, high linearity, cost-effective GaN-on-Si high electron mobility transistors (HEMTs), and compact modeling. This work aims to serve as a guide for the utilization of GaN HEMTs in 5G communication applications.

1. Introduction

The emerging fifth generation (5G) communication system is expected to unlock countless new services and provide growth platforms for many industries. The key technical requirement of 5G mobile communication is to realize the ubiquitous connection of billions of devices and support a multi-Gbps data rate. The goal is to achieve a capacity thousands of times larger than the existing mobile system. 5G can improve the performance of commercial applications, and realize new user experiences and services in areas such as augmented reality, virtual reality, and hybrid reality applications (AR, VR, and MR), video conferencing, industrial automation, autonomous vehicle, and networked medical devices (as shown in Fig. 1a). In order to achieve 5G, there are countless challenges in hardware development, system architecture, and network deployment.

Fig. 1.

(a) 5G can improve the performance and enable new applications of consumer, enterprise, and government [1]; (b) Block diagram of a sub-array APAA massive MIMO [2]; (c) Advantages of GaN power amplifier in 5G mobile applications [3].

In 5G designs, an analog front end (AFE) is required to support multiple transmit and receive paths in a multiple input multiple output (MIMO) configuration. Fig. 1b shows the block diagram of the sub array active phased array antenna (APAA) massive MIMO. As shown in Fig. 1b, the RF front-end module consists of power amplifier (PA), low-noise amplifier (LNA), and switches. The increasing complexity of 5G limits the number of manufacturers with expertise in developing such complex RF subsystems. However, with the maturity of 5G design, more and more suppliers are meeting the designs challenges of AFE. As we all know, the performance of RF PA usually dominates the performance of the whole transmitter (TX), because its power-added efficiency (PAE) determines the power and heat dissipation of the whole TX. In order to enhance the user experience and massive MIMO antenna at the centimeter wave/millimeter-wave frequency, the 5G system will need more PAs integrated into the RF front-end module (FEM), which makes the design of 5G PA more critical than 4G PA. For any successful commercial 5G application, the output power (P_out), linearity, cost, circuit topology design, and shape factors of PA are very important. Many other companies are also investing a lot of resources to realize the 5G revolution, in which the frequency range 1 (FR1) of sub-6G frequency bands and FR2 of the millimeter wave frequency bands will be used.

Since the technology entered the market in the 1990s, RF power amplifiers have been dominated by lateral diffusion metal oxide semiconductor (LDMOS) devices, especially at frequencies below 2 GHz, because of their low cost. Their biggest competitor are gallium arsenide (GaAs) based amplifiers, which are more suitable for higher frequency but have lower power transmission levels and higher costs. Compared with silicon and gallium arsenide (GaAs) semiconductor materials, GaN is a broadband compound semiconductor with high breakdown electric field strength, high electron saturation velocity, high thermal conductivity, and low dielectric constant [4]. GaN will replace traditional semiconductor materials for 5G network applications, such as small batteries, which require higher frequency, tight integration, and the lowest implementation cost. The efficiency provided by low-voltage GaN will inevitably enter mobile phones. GaN is capable of working in high temperature environments, which is very suitable for passive cooling, all outdoor tower top base station electronic [5,6] equipment, and automotive applications [7].

Given the challenges outlined above, the need for high frequency in GaN power amplifiers is on the rise due to the upcoming demands for huge traffic in 5G. Furthermore, the complex modulation schemes and crowded RF spectrum in 5G technologies have resulted in a greater demand for the high linearity of GaN-based power amplifiers. Additionally, GaN-on-Si has emerged as a promising option due to its competitive performance, which is enabled by its integration into standard semiconductor process flows that provide economies of scale. Finally, this paper reviews several types of compact models for RF GaN modeling, as frequency, linearity, cost, and compact modeling all play key roles in determining the performance and competitiveness of GaN-based power amplifier devices for mobile communications. Ultimately, the aim of this paper is to present the research progress of GaN-based power amplifier devices and modeling from the four aspects outlined above.

2. High frequency GaN HEMTs and key issues

This section reviews two aspects aimed at improving the performance of GaN-based millimeter-wave HEMTs. The first aspect is gate structure design and fabrication, which aims to decrease gate parasitic capacitance and gate resistance to improve high-frequency device operation. The second aspect is short-channel effects. As gate length is scaled down to deep-micrometer size, the gate control ability is reduced, leading to poor pinch-off characteristics and reduced transconductance (g_m), resulting in reduced breakdown voltage and small signal gain.

2.1. High-frequency gate structure design and fabrication

High saturation velocity and breakdown electric field make GaN-based high electron mobility transistors (HEMTs) attractive for high-speed, high-power applications, promising a broad future for modern communication and scientific exploration [8]. Research on gate structure and operating modes has always been at the core of microwave device design and could be an individual research direction. To decrease the resistance of the gate electric and compensate for the critical increase of the I-shaped gate due to the decrease of its sectional area with the gate length scaled, researchers have mainly adopted the T-shaped gate, and more recently, the Y-shaped gate [9], gradually shifting towards self-aligned gate [10] and other novel gate structures. Each method provides a way to achieve high power, frequency, and efficiency, ensuring that power devices have more imaginative development.

2.1.1. T shaped gate

T-shaped gates are commonly used in high frequency (∼1–300 GHz), low noise transistors on III–V materials since they provide a combination of short gate length and low gate resistivity [11]. The T-gate with a spacer is a replacement of the traditional highly challenging exposure method by using an easily removable sacrificial layer, like SiN_x and Ge spacer. The gate fabrication is one of the most important steps in microwave devices fabrication process. For mm-wave device operation, T-gates with submicron gate “foot,” which have lower resistance and capacitance in comparison to conventionally used gates, are usually produced. To fabricate such T-gates, multilayer resists mask are used, and the pattern in the mask is generated by electron-beam lithography [12]. The type and the quantity of resist layers are selected based on the required form and geometric size of the gate. Exposure and development conditions should be chosen individually for each resist stack.

Typical T gates are fabricated using a single electron beam lithography step and a multilevel resist stage [13]. It is possible to use processes requiring two lithography steps: one for the foot and another for the head [14], but the extra lithography level is clearly a disadvantage in such schemes. As gate dimension shrink to 100 nm and below, the challenges involved in the single step process are considerable. However, due to the challenges involved in the typical T-shaped gate process, some researchers have suggested methods that use sacrificial layers, such as removing the SiN passivation layer of the HEMT with the gate supported by the SiN passivation. Other researchers scarify the interlayers like Ge-spacer and resist spacer structures, as shown in Fig. 2a-c [15], always employing a thin passivation that can guarantee low collapse effects for high power applications [16]. In summary, all of these processes can achieve the designers’ intended outcome with some extra well influence on their device, satisfying the different demands in microwave products.

Fig. 2.

(a) SEM micrograph and schematic of a 100 nm long gate with an air gap introduced by the use of a Ge spacer. (b) Small-signal high frequency performance of a passivated HEMT with the structure. The SiN_x layer introduces parasitic capacitances, which severely limit f_max. (c) Small-signal performance of a passivated AlGaN/GaN HEMT with a gate length of 90 nm fabricated using the Ge-spacer technology [15]. Technology cross sections of HRL's four GaN HEMT scaling generations: (d) Generation I, (e) Generation II, (f) Generation III, and (g) Generation IV.

2.1.2. Self-aligned gate

The reduction of device size can effectively improve its performance. However, when the gate length is less than 100 nm, short channel effects can significantly impact device performance. Short channel effects can be reduced, and the device frequency can be improved by proportionally reducing the gate length. To ensure the ratio between gate length and gate-to-channel length, people often employ a few nanometer barrier materials with a much stronger polarization effect, such as AlN. However, the problem is that traditional T-gate exposures are too challenging to scale down to match the barrier thickness.

Under this background, researchers at HRL Laboratories scaled down the device size to the limit of self-aligned gate technology, achieving a remarkable frequency characteristic [17] with a current gain cutoff frequency (f_T) of more than 450 GHz (with f_max of 440 GHz) and a maximum oscillation frequency (f_max) close to 600 GHz (with f_T of 310 GHz). This development reveals a large potential for microwave power devices in power amplifiers, as shown in Fig. 2d-g. The development of this device can be summarized into four generations. The first generation involves fabricating a low ohmic contact resistance by doping enough concentration of Si in GaN during the regrowth of drain and source in molecular beam epitaxy (MBE). The second generation aims to reduce the horizontal distance of the drain-to-source electrode and make the gate electrode with self-alignment technology. In the third generation of experiments, n+-GaN was directly contacted with 2DEG, reducing the resistance installed in series of the on-state. Finally, the fourth generation uses asymmetric self-aligned gate technology to make high-frequency devices with good performance based on the first three generations. The structures of the four-generation devices are shown in Fig. 2g [10,17,18].

2.2. Short channel effect

To operate at higher frequencies (e.g., Ka to W bands), short gate length and fast carriers in the channel are necessary, and transistors must be highly scaled. However, downscaling the gate length into the deep submicrometer regime leads to undesirable short-channel effects (SCEs) [19], [20], [21]. For transistors in the off-state, SCEs are responsible for the shift in the threshold voltage, the degradation of pinch-off, the increase of subthreshold swing (SS), and the increase of drain-induced barrier lowing (DIBL). In the on-state, SCEs are represented by the increase of output conductance and the degradation of RF performance.

2.2.1. Recess gate structure

In the early years, gate-recess technology was an effective way to enhance gate control by decreasing the distance from gate to channel, thus improving the aspect ratio and mitigating short-channel effects. In 2005, J. S. Moon et al. [22] fabricated deep-submicrometer field-plated AlGaN–GaN HEMTs by utilizing a recess gate structure. The AlGaN–GaN HEMTs exhibit a CW power density (measured at 30 GHz) of 5.7 W/mm with a power-added efficiency (PAE) of 45% and drain-efficiency of 58% at V_DS = 20 V. In 2010, J. W. Chung et al. [23] reported a gate-recessed AlGaN/GaN HEMTs on a SiC substrate with a f_max of 300 GHz, an on-resistance of 1.1–1.2 Ω·mm, and a breakdown voltage of ∼20 V. To achieve this high f_max, a low-damage gate-recess technology, scaled device geometry, and recessed source/drain ohmic contacts were combined to simultaneously enable minimum short-channel effects (i.e., high output resistance R_ds) and very low parasitic resistances. In 2016, Y-K. Lin et al. [24] presented the electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method, achieving a maximum drain current density of 1.54 A/mm, a f_T of 153 GHz, a f_max of 167 GHz. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet photons in the conventional inductively coupled plasma reactive ion etching method. Fig. 3a-b shows the high-resolution transmission electron microscope (HRTEM) images of the NBE recessed gate region and the inductively coupled plasma-reactive ion etching (ICP-RIE) recessed gate region. The atomically sharp interface observed after the GaN was recessed via NBE was due to the low damage of the NBE technique, as seen in the HRTEM images. The better interface is a result of the low damage nature of the NBE process. In 2018, Y. Zhang et al. [25] implemented a high-temperature gate recess technique to fabricate high-performance millimeter-wave AlGaN/GaN HEMTs with a f_T of 81 GHz and a f_max of 194 GHz, a high power-added efficiency of 42.8% and a high output power density of 5.1 W/mm at 35 GHz in a continuous-wave mode by employing a 0.2-µm T-shaped gate technology. Fig. 3c-d shows the improvement of small signal gain and large-signal power characteristics by the high-temperature gate recess technique.

Fig. 3.

(a) HRTEM image of the NBE recessed gate region. (b) HRTEM image of the ICP-RIE recessed gate region [24]. Small-signal and large-signal characteristics of the fabricated HEMTs at V_DS = 10 V, V_GS = −0.8 V with gate recessed at 20 °C (c) and 160 °C (d) [25].

2.2.2. Strong-polarization barrier design

Regarding epitaxial layer design, a basic design principle to mitigate short-channel effects is to reduce the thickness of the barrier layer and thus the gate to-channel distance. However, excessively decreasing the thickness of the barrier layer for conventional AlGaN/GaN heterojunction has serious limitations such as the reduction of the density in the channel [23,26]. Therefore, InAlN/GaN heterojunction and AlN/GaN heterojunction can be superior in respect to AlGaN/GaN heterojunction primarily because of expected higher two-dimensional electron gas (2DEG) density with the precondition of maintaining thin barrier. Kuzmik [27] was the first to propose the use of InAlN for high performance GaN devices. In 2009, H. Sun et al. [28] reported 0.1-μm gate AlInN/GaN HEMTs grown on a (111) high-resistivity silicon substrate with a 9 nm thick lattice-match In_0.17Al_0.83N barrier that achieved a maximum current density of 1.3 A/mm, an extrinsic transconductance of 330 mS/mm, and a peak current gain cutoff frequency as high as f_T = 102 GHz. Continuous-wave power measurements in class-A operation at 10 GHz with V_DS = 15 V revealed a 19 dB linear gain, a maximum output power density of 2.5 W/mm with an ∼23% power-added efficiency (PAE), and a 9 dB large-signal gain. At V_DS = 8 V, the output power was 1 W/mm, and the peak PAE reaches 50%. In 2010, H. Sun et al. [29] report 55-nm gate AlInN/GaN HEMTs with 10 nm thick lattice-match In_0.17Al_0.83N barrier featuring a current/power gain cutoff frequency of f_T/f_max = 205/192 GHz at room temperature, a maximum current density of 2.3 A/mm at V_GS = 0 V, and a peak extrinsic transconductance of 575 mS/mm. In 2013, P. Saunier et al. [30] reported excellent low-voltage (5 to ∼10 V drain bias) microwave and millimeter-wave performance of deeply scaled InAn/ GaN devices with field-plate gate of ∼50-nm length, MBE regrown ohmic contacts, and sub-500-nm S-D spacing, achieving high f_T/f_max of ∼270/230 GHz and excellent performances at 10 GHz with up to 67%–69% power-added efficiency (PAE) at 6 V bias and 30 GHz with up to 14.4 dB associated gain and 2.6 W/mm and 39.6% PAE at 8 V bias. Also in 2013, S. Tirelli et al. reported the large-signal performance of InAlN/GaN HEMTs with a maximum power density of 5.8 W/mm in large-signal operation at 40 GHz [31]. In 2015, Y. Tang et al. [17] reported the RF performance of deeply scaled depletion-mode GaN HEMTs based on double heterojunction AlN/GaN/AlGaN epitaxial structure, achieving high f_T/f_max of 454/444 GHz on a 20-nm gate HEMT with 50-nm-wide gate–source and gate–drain separation. With an off-state breakdown voltage of 10 V, the Johnson figure of merit of this device reached 4.5 THz-V.

2.2.3. Strong confinement back barrier design

Another source for poor pinch-off is the hot electron injection into the GaN buffer layer. These electrons travel within the substrate and are far from the gate. Thus the gate cannot effectively modulate them. To solve this problem, back barrier or double heterojunction can be employed to increase carrier confinement, suppressing the short-channel effect [32]. Back barrier technology was developed later than the InAlN and AlN barrier technology for the millimeter-wave application. In 2011, D. S. Lee et al. [33] studied the effect of AlGaN back barriers in the dc and RF performance of In_0.17Al_0.83N/GaN high-electron mobility transistors grown on SiC substrates. The f_T of a transistor with an AlGaN back barrier is 210 GHz, which is higher than that of the standard device with the same gate length (f_T = 195 GHz). Also in 2011, D. S. Lee et al. [34] reported lattice-matched In_0.17Al_0.83N/ GaN high-electron-mobility transistors on a SiC substrate with an In_0.15Ga_0.85N back barrier to suppress the short-channel effects for the first time. In a 30-nm-gate-length device with an on-resistance of 1.2 Ω·mm and an extrinsic transconductance of 530 mS/mm, a peak f_T of 300 GHz is achieved. To further achieve strong confinement and suppressed buffer trapping effect, L. Yang et al. proposed a novel approach based on Fe/C co-doping and a thick graded AlGaN back barrier structure [35]. M. Wu et al. presented the excellent power and RF performances of GaN HEMTs grown on a freestanding GaN substrate using a unified Fe/C co-doped GaN buffer [36].

3. High-linearity enhancement technique and key issues

Emerging wireless links such as 5G and beyond-5G have strict effective isotropic radiated power (EIRP) requirements due to high path loss at mm-wave frequencies. Such stringent requirements of the mm-wave frequency spectrum have made GaN devices an attractive choice for power amplifier (PA) applications as they can outperform traditional III-V semiconductors and silicon devices with their ability to work at higher voltages, temperatures, and frequencies with higher efficiencies [37]. This advantage is attributed to GaN's inherent material properties, including its large bandgap (3.4 eV), exceptional peak saturation velocity (2.5 × 10⁷ cm/s), and high critical electric field (3.3 MV/cm), leading to improved operating voltage, power density, efficiency, ruggedness, and a high Johnson figure-of-merit (FoM). Having a high output power density is a major advantage in GaN HEMTs compared to other semiconductor technologies. For example, a high output power density allows for the use of smaller transistors for a desired output power, leading to lower parasitic capacitance and wider bandwidth. It also results in compact PA chips, reducing the size and cost of electronic systems in various applications. Moreover, GaN HEMTs can be designed with a gate width that achieves an optimal load resistance, close to the load resistance, resulting in a near unity impedance transformation ratio. This allows for low-loss, broadband impedance matching networks, which is not typically possible with semiconductor technologies that have lower supply voltages [38].

However, GaN devices have their own set of challenges that limits them from achieving their maximum theoretical performance in the context of PA design. Issues such as soft compression, DC-RF dispersion, and self-heating limit the device's output power, power-added-efficiency (PAE), and linearity, all of which are critical metrics in a PA [39,40]. In addition, modern wireless links have a different set of challenges when employing modulation techniques such as orthogonal frequency-division multiplexing (OFDM), higher-order quadrature amplitude modulations (QAMs), Quadrature phase shift keying (QPSK), Binary Phase-shift keying (BPSK), and carrier aggregation to increase channel capacity. These modulation methods have high dynamic ranges, which results in high peak-to-average power ratio (PAPR) demands. High-PAPR signals have strict linearity requirements, demonstrated in the form of adjacent channel power ratio (ACPR) and error vector magnitude (EVM), to maintain signal quality. These requirements force PAs to operate below their maximum output power, leading to lower average output power and efficiency compared to peak continuous wave (CW) performance as seen in Fig. 4a [41].

Fig. 4.

(a) Output power and efficiency vs. input power under the presence of a modulated signal with high PAPR. (b) Reported efficiency vs. output power for CW (peak DE/PAE vs. Psat) and modulation (average DE/PAE vs. Pout,avg) conditions for GaN PAs from [42].

Nonetheless, this is a persistent challenge across all semiconductor technologies that have not been fully resolved. To exacerbate the situation, GaN HEMTs have stricter requirements and require higher power back-off (PBO) to address amplitude-to-amplitude (AM-AM) and phase-to-amplitude (AM-PM) distortion caused by nonlinearities such as soft compression. Soft compression occurs when the gain compresses much earlier than expected before reaching the device's P_out limit due to electron-trapping effects [40].

The data for GaN-based PAs from the PA survey in [42] shows significant degradation in average output power (P_{out, avg}) and efficiency under modulation when compared to CW performance (i.e., saturated output power (P_sat) and peak efficiency). Fig. 4b displays the efficiency vs. output power for CW (i.e., peak drain efficiency or PAE vs. P_sat and modulation (i.e., average drain efficiency or PAE) conditions in GaN PAs from the PA survey in [42]. Based on this data, it becomes evident that there is a big gap between CW and modulation performance, and it can be addressed by improving the linearity at the device or circuit levels.

Improving the linearity performance of PAs is crucial as it affects the achievable data throughput and the average output power (P_out,avg) and average power added efficiency (PAE_avg) in the transmit block. To understand better the ways to achieve high linearity from a PA, we need to define what an ideal linear transistor is. An ideal linear transistor is one that amplifies input signals in a linear manner, i.e., no additional frequency content is generated, and the superposition principle is not violated. At the circuit level, a linear transistor has a linear output power response, as demonstrated by the gain vs. P_out and phase vs. P_out characteristics. A key difference between an ideal linear transistor and a non-linear one is the minimal difference between metrics such as output 1-dB and 3-dB compression points (OP_1dB/OP_3dB) and P_sat.

3.1. Metrics for PA linearity

There are various metrics used to measure GaN HEMT linearity. Among them, output-referred third order intercept point (OIP3) is the most commonly used metric for measuring device linearity performance, primarily because it is straight forward to measure and calculate through linear extrapolation.

This metric is obtained by a “two-tone'' test that involves applying two signals with different frequencies (f₁ and f₂) but equal amplitude, spaced out from the fundamental frequency of interest (f_o) by a quantity ∆f. It also assumes that the input signals are small enough that the output signal's energy is concentrated mainly in the lowest-order harmonics, i.e., "weakly nonlinear behavior'' or "low-distortion conditions'' [43]. Under these conditions, OIP3 is defined as the power level at which the fundamental curve and the third-order intermodulation distortion (IM3) curve intersect, referred from the output. OIP3 is calculated in [44] assuming a third-order Taylor series of the non-linear drain current I_D(V_GS) relationship as:

$$OIP3\left(dBm\right)=10{\log }_{10}\left(\frac{2}{3}\frac{g_{m1}^3}{g_{m3}}{R}_L\right)+30$$ (1)

where, g_m1 is the transconductance (i.e., first derivative of the drain current), g_m3 is the third derivative of drain current, and R_L is the load resistance. However, intercept point specifications such as OIP3, are only accurate under low-distortion conditions and suffer from various issues when a device exhibits strongly nonlinear behavior, such as PAs that switch between the saturation and cut-off regions. The accuracy of the harmonic intercept point in OIP3 is based on the assumption that the IM3 curve is a straight line with a slope of 3, which is mathematically extrapolated instead of directly measured. When a device behaves in a strongly nonlinear fashion, the slope of the IM3 curve deviates significantly at high power levels because higher-order intermodulation terms become dominant [45].

Fig. 5a provides a visual and qualitative illustration of a scenario in which the slope of the IM3 curve changes dramatically as the device approaches high power levels. The conclusion that can be drawn from Fig. 3 is that even if a high OIP3 can be achieved by implementing g_m3 cancelation or other small-signal techniques at the device or circuit level, it will only be effective under low-distortion conditions, where the assumptions of OIP3 are valid. However, in high power or strongly nonlinear device operation, any uncancelled higher-order intermodulation terms will worsen IM3, negating the entire purpose of a high OIP3 [46], [47], [48]. Hence, it is crucial to consider other linearity metrics to gain a more comprehensive understanding of practical PA operation.

Fig. 5.

(a) Qualitative example of fundamental and IM3 curves at high power levels leading to an inaccurate OIP3 extraction. (b) Visual representation of the definition for EVM. (c) Output spectrum as a function of frequency along with the reference channel and the first and second adjacent channels for a 64-QAM modulated signal with f_c = 10 GHz and channel BW = 10 MHz.

At the system level, the 3rd Generation Partnership Project (3GPP) established specifications for Error Vector Magnitude (EVM) and Adjacent Channel Power Ratio (ACPR) to assess the quality of the signal for different modulation schemes as seen in Table II. Understanding these metrics and their significance in PA operation is crucial, so they must be defined correctly. EVM is mathematically calculated by finding the root mean square of the error vectors across active subcarriers for all symbols in the modulation scheme. It represents the error in the modulation signal constellation and is usually expressed as a percentage of the ideal signal power. A qualitative visual representation of the definition for EVM through an IQ constellation can be seen in Fig. 5b. ACPR, on the other hand, is the ratio of unwanted power in adjacent channels to the RMS power of the transmitted signal in the main (reference) channel. PAs operate at high power levels to enhance efficiency, which can cause output power in the main channel to spill over into adjacent channels and cause interference. ACPR is used to assess spectral regrowth in these scenarios. Fig. 5c shows the output spectrum as a function of frequency for a 64-QAM modulated signal with f_c = 10 GHz and channel BW = 10 MHz. The reference and adjacent channels are shown accordingly.

3.2. Need for device innovations and circuit techniques

To compensate for PA nonlinearity at low GHz frequencies, digital pre-distortion (DPD) techniques are often used. However, these techniques are challenging and impractical at mm-Wave frequencies due to cost, speed/latency, complexity, and performance limitations. Hence, it is important to improve the hardware linearity through device innovation and circuit techniques to meet communication standards [41].

While the efforts of the device community have mainly focused on linearizing the transconductance of the device or voltage-dependent junction capacitances (e.g., gate-source capacitance), circuit designers exploit device nonlinearities to enhance linearity using techniques such as feedback, derivative superposition (DS), harmonic terminations, and complementary capacitance-compensation [49], [50], [51]. Circuit designers primarily focus on improving AM-AM and AM-PM distortion, as these directly affect communication standard-based metrics such as ACPR and EVM and are easy to simulate.

3.2.1. A. Derivative superposition

Derivative superposition is a technique to cancel out g_m3 over a specific window by using multiple transistors [49,50]. Fig. 6a illustrates the g_m3 curves of two transistors: M_A and M_B, with M_A being the main transistor and M_B the auxiliary transistor. The g_m3 curve of M_A exhibits a positive peak followed by a negative peak. The aim is to cancel out the negative peak by adding another transistor, M_B. By properly biasing and sizing M_B, its g_m3 curve can be shifted to the right, thereby cancelling out the negative peak of the main transistor. This results in an effective g_m3 curve with values close to zero over a cancelation window, which can then be used for device operation. The cancelation window can be expanded by using several auxiliary transistors, although using more than three or four auxiliary transistors yields diminishing returns in linearity improvement. The main advantage of this technique at the circuit-level is that it can be adjusted for process variations by modifying the gate bias of each transistor as necessary.

Fig. 6.

(a) A qualitative circuit-level derivative superposition using two devices (M_A and M_B) with differing gate biases. Third-order transconductance as a function of V_GS for the different devices (after [49]). (b) Qualitative representation of complementary capacitance cancelation. The active device is shown in red, and the complementary device is shown in blue. (c) The cross-section of a GaN device for enhancing linearity, which includes both the active and auxiliary components, and (d) their capacitance-voltage profile. (after [52]). (e) Nonlinear equivalent circuit showing second harmonic termination (after [59]).

3.2.2. Complementary capacitance cancellation

Besides the nonlinear transconductance g_m, the voltage-dependent capacitances (i.e., gate-source capacitance C_gs and the miller effect of the gate-drain capacitance C_gd) are another source of distortion in GaN HEMTs. Generally, an increase in the average g_m variation results in AM-AM distortion, which manifests as gain compression or expansion, while an increase in the average C_gs variation leads to phase variation. One method to improve AM-PM distortion is to use complementary capacitance cancelation [51]. As such, enhanced performance can be achieved using a compensating or complementary nonlinearity, which can be provided by the C_gs of a properly biased and sized p-type device as seen in Fig. 6b. Doing so will effectively linearity the C-V profile of the active device.

While such technique has been proven to be successful in Silicon platforms due to the feasibility of p-type doping in this material system, there have been few attempts in the GaN community, where a complementary component based on a p-type GaN device is used to achieve the desired compensating behavior [52]. A schematic of such a structure is seen in Fig. 6c, d.

The main disadvantage of this technique is that each transistor of interest needs its own complementary device, which increases the capacitive loading of the circuit and lowers the achievable bandwidth of the circuit or system.

3.2.3. Harmonic terminations

At the circuit-level, previously reported works have demonstrated increased amplifier efficiency and linearity by using harmonic termination [40,[53], [54], [55], [56], [57], [58]]. Commonly used harmonic terminations include second harmonic termination at the input or output by presenting a short circuit at 2*f_o (i.e., the second harmonic). This is because in a realistic device, the presence of g_m and higher order coefficients such as g_m2 (second derivative of the drain current with respect to V_GS) and g_ds2 (second derivative of the drain current with respect to V_DS) generate second harmonics, which couple back to the input through the gate-drain capacitance. Both the feedbacked second harmonics and the fundamental signal are responsible for generating the third harmonics [53]. Even if careful work has been done to linearize g_m and g_ds, the linearity bottleneck will be determined by the nonlinear harmonic distortion produced by the gate-source capacitance. In a class-AB amplifier, which is biased close to the g_m3 zero-point crossing, g_m2 is generally very large and significant third harmonics are generated through intermodulations of g_m2 between the second harmonics from the second-order coefficient of the gate-source capacitance (C_gs2) and the fundamental voltages. Therefore, circuit designers take special care to terminate the second harmonic properly. An example of a nonlinear equivalent circuit is shown in Fig. 6e with second harmonic termination.

3.3. Device-level linearity enhancement technique

As mentioned above, GaN-based HEMTs can realize superior output power (P_out) and power-added-efficiency (PAE). However, GaN-based HEMTs or power amplifiers still suffer from severe non-linearities, limiting their application of wireless communications. Non-linearities in the power amplifier (PA) transistors can lead to significant side-bands, saturation of output power at high input power and in-band signal distortion [40]. As for device-level linearity, based on two-tone stimulus, the key parameters which can evaluate the linearity of PA transistors include the third-order intermodulation products (IM3), the ratio of the carrier power to IM3 (C/IM3) or third order intermodulation distortion (IMD3), the OIP3 and OIP3 normalized over dissipated DC power (OIP3/P_DC) [58]. Among these parameters, IM3 and C/IM3 is proportional to the second derivative of transconductance (g_m3), and OIP3 is inversely proportional to the second derivative of transconductance. In order to improve the linearity of PA transistors, the IM3 and C/IM3 should be decreased, and OIP3 should be increased. It should be noted that the OIP3 is not the only criterion for evaluating linearity, due to the increased phase distortion (AM-PM distortion), which comes from nonlinear junction capacitances such as C_gs and C_gd, will also deteriorate the linearity. Hence, the combination of both flat transconductance profile and linearized junction capacitances will give the best linearity [60]. In the view of the device-level linearity, the second derivative of transconductance should be reduced for the improvement of the linearity of devices, which means that the flatten transconductance curve profile is necessary to realize the improvement of the device-level linearity. However, as for traditional GaN-based HEMTs, the extrinsic transconductance is increased initially and then decreased rapidly, resulting in the deterioration of the device-level linearity. To modulate the transconductance profile, approaches from the aspect of material epitaxial design including double channel structure, graded barrier structure, sub-channel structure, coupling channel structure and N-polar GaN-based heterostructure, and from the aspect of device structure design and process optimization including gate recess, field plate, MIS structure, in-plane gate, Fin structure and Fin-like structure, will be discussed.

3.3.1. Material epitaxial design for high linearity GaN-based device

The material epitaxial design for high linearity GaN-based device is proposed mainly based on the conventional GaN-based device structure, which owns the merit of a relatively simplified device fabrication process but brings challenges for the material epitaxial design. The core challenge for high linearity material epitaxial design is to modulate the dependence of the electron velocity on the electron density (i.e., the relationship between electron velocity and electric field) by the design of the material bandgap structure. The representative material epitaxial structures for high linearity GaN-based devices include graded barrier structure, double channel structure, sub-channel structure, coupling channel structure, and N-polar heterostructure, proposed by universities and institutions including the Ohio State University, HRL Laboratories, Xidian University, Hong Kong University of Science and Technology, and University of California-Santa Barbara.

Graded barrier structure, which is also called polarization-graded field effect transistors (PolFETs), as shown in Fig. 7a, is one of the methods to mitigate non-linearity that stems from the transconductance drop-off. The graded barrier structure is based on the conventional AlGaN/GaN heterostructure. In the graded barrier structure, the Al composition of the AlGaN barrier is linearly graded from GaN to a specific Al composition, replacing the two-dimensional electron gas (2DEG) channel with the quasi-three-dimensional electron gas channel (3DEG). With the utilization of the graded barrier structure, the profiles of transconductance, f_T, and f_max as a function of current density or gate bias are flattened, which means constant transconductance, f_T, and f_max over wide gate voltage and drain current density range is realized, indicating the improved linearity performance of the PolFETs [61]. Based on the 20nm-thick graded barrier with Al composition linearly graded from 0 to 40%, S. H. Sohel et al. [62] realized the PolFETs with output power density (P_out) of 2 W/mm, OIP3 of 33 dBm and linearity figure-of-merit OIP3/P_DC of 3.4 dB based on two-tone measurement at X-band, and further achieved the improvement of linearity and output power density based on the same epitaxial structure by replacing traditional plasma enhanced chemical vapor deposition SiN_x passivation with low pressure chemical vapor deposition (LPCVD) grown SiN_x passivation [63], reducing the current collapse and revealing a P_out of 3.4 W/mm, an OIP3 of 39 dBm and linearity figure-of-merit OIP3/P_DC of 13.3 dB at X-band. Moreover, based on the traditional graded barrier structure with Al composition linearly graded in the AlGaN barrier layer, other Al composition graded approaches were also investigated by simulation [64] and fabrication for the balanced improvement of linearity, power density, and frequency. Bin Hou et al. [65] proposed a sandwich-like graded barrier structure with Al_0.05GaN back barrier to modulate polarization-graded field for a more flattened transconductance profile under high drain bias, realizing a P_out of 7.3 W/mm, OIP3 of 38 dBm, and linearity figure-of-merit OIP3/P_DC of 4.5 dB under the high drain voltage of 60 V at X-band. Jeong-sun Moon et al. [66,67] reported the graded-channel (actually graded barrier) GaN HEMTs and realized the scaling of the aspect ratio for the effective operation under millimeter-wave frequency range, achieving P_out of 3 W/mm, OIP3 of about 32 dBm and C/IM3 of 30 dBc with PAE of about 50% at 30 GHz (Ka-band).

Fig. 7.

The typical material epitaxial design for high linearity GaN-based device. (a) Graded barrier structure [62], (b) double channel structure [71], (c) coupling channel structure [79] and (d) N-polar GaN-based heterojunction [58].

Double channel structure, as shown in Fig. 7b, is also an effective method to suppress the transconductance drop-off. A double-channel structure was initially proposed for the increment of the output current density and the suppression of the current collapse-induced gain compression [68]. As the gate voltage increases, the channel turns on subsequently, which is helpful for the suppression of the drop of the transconductance curve [69,70]. With the design of the graded bottom barrier and the recessed gate, it was found that the linearity was enhanced by tailoring the differential access resistance, leading to the increase of the gate swing of the extrinsic transconductance and achieving the improvement of more than 2 dB in the two-tone linearity measurement at X band [71]. Moreover, some double channel structures may suffer from the degradation of breakdown characteristics which can be attributed to the weakened gate control for the bottom channel, but from another point of view, the enhanced current driver capability of the double channel structure provides the potential high linearity application under low voltage operation. Q. Yu et al. fabricated the AlGaN/GaN/graded-AlGaN:Si-doped/GaN double channel HEMTs, realizing a maximum current density of 1909 mA/mm, PAE of 58%, and a theoretical OIP3 of 39.8 dBm at the drain voltage of 7 V by the Si-doped graded bottom barrier [72]. C. Shi et al. demonstrated the power performance of the double-channel HEMT for sub-6 GHz applications using a heterostructure of Al_0.3Ga_0.7 N/GaN/Al_xGa_1−xN/GaN [73]. It is noteworthy that the excellent metal-2DEG ohmic contact for the multi-channel system is difficult to form. To address this issue, L. Yang et al. investigated the ohmic contact formation mechanism and gate electrostatic control of the deep-recessed ohmic contact structure for double-channel [74] and five-channel GaN-based systems [75].

With the development of the research of double channel structure, it was implied that the modulation of the bandgap structure was important for the improvement of the linearity. In a general way, in order to realize the flattened transconductance profile and the increased gate swing of transconductance, the distance between the two channels (i.e. the distance between the two heterojunction interfaces) should be decreased and the Al composition of the barrier of the two heterojunctions should be carefully designed. As the two heterojunction interfaces are adjacent, the coupling effect between the adjacent channels will be obvious [76]. The coupling channel structure, as shown in Fig. 7c, which utilizes the coupling effect, can modulate the transconductance profile and improve the nonlinear increment of the differential source resistance. W. Song et al. [77] found that the closely coupled double-channel GaN HEMT delivered the more improved OIP3 by 5.2 dB over the traditional single-channel GaN HEMT, achieving an OIP3 of 33.9 dBm at 4 GHz with a 1 MHz spacing in the two-tone measurement. Furthermore, Shahadat H. Sohel et al. [78] reported a AlGaN/GaN HEMT with graded InGaN sub-channel for high linearity applications, forming flat transconductance and power gain profile by the composite two-dimensional and three-dimensional electron channel and realizing an OIP3 of 38 dBm and a corresponding linearity figure of merit OIP3/P_DC of 9.7 dB at 10 GHz (X band). H. Lu et al. [79]fabricated AlN/GaN/InGaN coupling-channel HEMTs, achieving a flat transconductance, f_T and f_max profile with gate swing larger than 4 V and a significant theoretical improvement of OIP3 value boost by 7.1 dB compared with AlN/GaN HEMT. Furthermore, they observed a steep subthreshold swing (SS) of less than 60 mV/decade by implementing a scaled-down coupling-channel architecture [80]. However, in these studies, achieving low-resistance ohmic contacts in the AlN barrier posed a limitation on device performance. To address this issue, H. Lu et al. successfully achieved an ultralow R_C with values below 0.1 Ω·mm using a Ta/Al/Ni/Au metal stack, thus eliminating the need for the high-cost source–drain n+ regrowth technique [81].

Moreover, in recent years, N-polar GaN-based heterojunction and related HEMTs, as shown in Fig. 7d presented high linearity characteristics, especially when the device worked at high frequency (even expended to W-band). So far, only UCSB has reported the electrical characteristics of N-polar GaN-based HEMTs, including the two-tone measurement results from X [82] to Ka-band [58,83], achieving linearity figure-of-merit OIP3/P_DC of 12 dB at 10 GHz and 15 dB at 30 GHz, respectively. The reason for the improvement of linearity by N-polar GaN-based HEMTs may be attributed to the inverted bandgap structure and the feature of the natural back barrier structure for N-polar GaN-based heterojunctions.

In conclusion, the key factor of the material epitaxial design for the improvement of linearity characteristics is the modulation of the bandgap structure. With the design of the epitaxial layer structure and related bandgap structure, the polarization field or the electric field and the related transport characteristics are modulated, leading to the improvement of device linearity.

3.3.2. Device structure design for high linearity

The device structure design and process optimization for high linearity GaN-based devices are mainly based on the conventional GaN-based heterostructure, which has the advantage of relatively mature material characteristics but brings challenges for the device structure design and the fabrication process. High linearity device structure design and process also need to face the challenge of modulating the dependence of the electron velocity on the electric field. Thus, in the early research, studies more attention was paid to the electric field modulation technology, such as gate recess structure [84] and field plate structure [85,86], as shown in Fig. 8a. However, it was found that gate recess structure had no improvement on the linearity of GaN-based HEMTs for the conventional GaN-based heterostructure, even presenting deterioration in the high linearity design [84], whereas the gate recess structure may have a positive effect on the linearity when combining with double channel structure [71] or N-polar structure [58]. Field plate structure has a positive influence on the device linearity, and it was found that the C/IM3 of GaN-based HEMTs with field plate was improved by approximately 2 dB compared with the device without field plate [85]. However, the parasitic capacitance introduced by the field plate limits the device's high frequency operation.

Fig. 8.

The typical device structure design for high linearity GaN-based device. (a) field plate structure [86], (b) MIS structure [87], (c) laterally gated structure [88], (d) Fin structure [89], (e) Fin-like structure [90] and (f) TRG structure [91].

The MIS (metal-insulator-semiconductor) structure, as shown in Fig. 8b, is also an effective way to modulate the linearity of GaN-based HEMTs, which is mainly attributed to the influence of gate dielectric on the electric field. By introducing an Al₂O₃ gate dielectric by atomic layer deposition, the gate swing of transconductance for GaN-based MIS-HEMTs was increased, and the C/IM3 of GaN-based MIS-HEMTs was about 5 dB higher than that of conventional GaN-based HEMTs [87]. Moreover, the researchers also changed the type of the dielectric (i.e., changed the permittivity of the dielectric) [92] and introduced nonlinear polarization dielectrics (such as ferroelectric dielectric) [93] to improve the gate voltage swing of transconductance. However, the current collapse phenomenon induced by the interface state problem is the critical limitation for the high linearity application of MIS structure, which needs complicated process optimization.

Apart from gate-recess structure, field plate structure, and MIS structure, the attention to the device structure design under the gate region was paid by many groups and the laterally gated (or buried gate) structure as shown in Fig. 8c [88,94] and Fin structure [89,95,96] were proposed to improve the linearity of GaN-based HEMTs. As shown in Fig. 8d, the laterally gated structure enhances electron confinement by raising electrostatic potential below the 2DEG [88] and improves the source resistance [94], attributing to the improvement of the flatness of the transconductance and gain profile. E. Özbay et al. [94] fabricated laterally gated GaN-based HEMTs and realized a 6.9-dB improvement of linearity figure-of-merit OIP3/P_DC. Compared with laterally gated structure, the Fin structure further enhances the electron confinement from the gate on the top of the channel. Compared with the conventional planar GaN-based HEMTs, the Fin structure enhances the electrostatic control by the sidewall gates. The improvement of the transconductance profile flatness and related device linearity by utilizing the Fin structure mainly contributed to the capacitance control from the sidewall gates [97] and the modulation of differential source resistance [95,98]. Kai Zhang et al. [96] fabricated AlGaN/GaN Fin-HEMT with a T-shaped gate and the Fin structure only under the gate region, achieving an output power density of 11.3 W/mm and an improvement of ∼5.5 dBc in IM3 characteristics at high input power level. M. Zhang et al. investigated the AlGaN/GaN nanochannel high-electron-mobility transistors (HEMTs) with tri-gate and dual-gate structures [99]. Moreover, some groups also fabricated planar nanostrip-channel by ion implantation instead of the dry etch of the trench region in the Fin structure, realizing the improvement of the gate swing of transconductance and C/IM3 [100], [101], [102]. However, the introduction of ion implantation process in the fabrication flow of GaN-based HEMTs can lead to process complexity and the diffusion of implanted ions limits the minimum geometry of the Fin structure [103].

In recent years, the theory of the device-level threshold voltage engineering and transconductance compensation was proposed and developed for the improvement of linearity. In the theory, multiple field effect transistors (FETs) with different threshold voltages are connected in parallel (common source and drain) with different channel widths (the channel corresponding to the FETs with related threshold voltage). By designing the channel width duty ratio, the transconductance profile is designed and tailored, realizing the increase of the gate voltage swing of transconductance and the suppression of the peak value of transconductance derivatives [104]. Based on the theory, GaN-based HEMTs fabricated by the connection of Fin structures with different channel widths in parallel were first developed [104,105]. Furthermore, in order to improve the performance of GaN-based high linearity HEMTs, a Fin-like structure, as shown in Fig. 8e, was developed with the feature of controlling the device performance loss from the trench region which was etched in Fin structure. Many groups simplified, optimized, and developed the Fin-like structure, and the traditional trench region in the Fin structure was replaced by shallow chlorine-based gate recess or selectively fluorine-based ion implantation to form the double threshold voltage coupling Fin-like structure [90,[106], [107], [108]]. Moreover, Xidian University proposed the transitional-recessed-gate (TRG) structure [91], as shown in Fig. 8f, realizing the combination of channels with continuously varied threshold voltage and achieving the improvement of gain and linearity. With the Fin-like structure or TRG structure, OIP3, C/IM3, and linearity figure-of-merit OIP3/P_DC were improved from the X-band to the Ka-band. What's more, because of the potential high linearity application of Fin structure and Fin-like structure, the small-signal performances of AlGaN/GaN HEMTs with Fin and Fin-like structure were investigated, and their small-signal models were also developed [109,110].

4. Cost-effective and high-performance RF GaN-on-Si HEMTs

4.1. Applications of GaN-on-Si HEMTs

Since 2000, Si substrates have been widely used in the field of high-voltage GaN-based power electronics and large-scale integrated circuits owing to their lower cost, larger wafer size, good thermal conductivity, and excellent compatibility with CMOS technology [111,112]. In recent years, with the development of materials and device technology, GaN-on-Si RF power devices have shown outstanding performance in fields such as aerospace, radar detection, and 5G communication base stations. Currently, the GaN-on-Si HEMTs are capable of meeting the operating requirements of the Sub-6G frequency band [113,114] and the Ka-band [115,116]. And the GaN-on-Si HEMTs are effectively applied in Sub-6G communication base stations and wireless WiFi, simultaneously in high frequency [117,118].

This session mainly investigates the research progress of RF GaN-on-Si devices in terms of material structure, device structure, and process technology in recent years both domestically and internationally, and analyzes the existing problems and corresponding technical difficulties in detail. It is found that with the development of material epitaxy technology, GaN-on-Si RF power devices have made significant progress in microwave power characteristics. However, several problems still exist: (1) the huge lattice mismatch which makes it difficult to grow high-quality GaN materials [119,120]; (2) the high leakage current across the material below the GaN channel, which introduces parasitic effects such as high RF Loss, resulting in degradation of the RF characteristics [121], [122], [123], [124]; (3) the poor breakdown characteristics due to the significant vertical leakage [125,126], and the severe current collapse [127]. In summary, the challenges such as huge lattice mismatch, high RF loss, and poor breakdown characteristics greatly limit the frequency and power characteristics of GaN HEMT on Si.

To improve the RF power performance of GaN-on-Si device, the following techniques are mainly used: stress modulation layer technology for high-quality GaN epitaxy [127,128], RF loss reduction technology [122,[129], [130], [131], [132]], high breakdown characteristics technology [133], [134], [135], etc. Based on the above techniques, GaN-on-Si devices have achieved excellent power performance in various RF frequency bands [114,136,137], revealing the unique advantages and application prospects in 5G applications and low-cost radar, et al.

4.2. Key issues of RF GaN-on-Si HEMTs

4.2.1. High-quality epitaxial growth

Large lattice mismatch and thermal mismatch are key bottlenecks in high-quality GaN-on-Si material epitaxial growth technology [119,124], as shown in Fig. 9a. Dislocations and stress generated by mismatch seriously affect the crystalline quality and cause RF collapse. Unlike power electronics materials on Si, reducing the thickness of the Si substrate and (Al)GaN buffer layer is required to reduce thermal dissipation and parasitic dissipation to meet the requirements of millimeter-wave RF applications, thereby effectively improving efficiency. However, the reduced thickness of the buffer is unable completely release the large stress, resulting in the degradation of the quality of the GaN channel layer, the degradation of the saturation current density, mobility, and breakdown voltage. Consequently, how to achieve high-quality GaN epitaxy while reducing the thickness of the buffer layer is a key point. In 2015, M. Zhao et al. studied the dispersion and leakage of three different types of buffers, namely a step graded buffer, a buffer with low temperature (LT) AlN interlayers and a superlattice buffer, as shown in Fig. 9b. They compared and analyzed the effects of different thicknesses and doping concentrations and found that the superlattice buffer layer can simultaneously achieve low dispersion and low leakage [127], as shown in Fig. 9c. In the same year, Wei-Cheng Tzeng et al. compared the differences in material quality and RF characteristics between step graded buffer and superlattice buffer, as shown in Fig. 9d and e, and found that the superlattice buffer layer structure can achieve better material quality, DC and RF characteristics of devices [128], as shown in Fig. 9f-k.

Fig. 9.

The research of high-quality buffer layer structure on Si substrate. (a) three different types of buffers and (b-c) the corresponding dispersion and leakage [127], (d-k) the material quality, DC and RF characteristics between step graded buffer and superlattice buffer [128].

4.2.2. RF loss suppression of GaN-on-Si HEMTs

In 2005, Nitronex developed a GaN-on-Si high-power chip with a gate width of 36 mm using the source field plate technology on a high-resistivity silicon HR-Si substrate, as shown in Fig. 10a. The chip achieved an output power of 368 W (power density of 10.2 W/mm) and drain efficiency of 70% in pulse mode operation at a working voltage of 60 V, demonstrating the power potential of GaN-on-Si materials in RF applications [113], as shown in Fig. 10b. GaN-on-Si materials and devices have since received widespread attention both domestically and abroad. In 2007, Nitronex further studied the device characteristics of GaN-on-Si HEMTs in continuous wave mode and found that, unlike in pulse mode, the power density and efficiency of the device significantly declined with increasing drain voltage, especially above 30 V [124], as shown in Fig. 10c. The research showed that RF loss and thermal resistance of the Si substrate were the two main factors limiting the device's high voltage and high power applications. Therefore, this session investigates and summarizes the development history of RF loss in recent years.

Fig. 10.

(a) The high power potential of GaN materials on Si for radio frequency applications [113], (b) two main factors in high voltage and high power applications: the RF loss to the silicon substrate and the thermal resistance of the device to the heat sink [124], (c) the power collapse in continuous wave mode and several technologies to suppress RF LOSS (d) Pre-Al pre-treatment technology [138], (e) substrate nitridation pre-treatment technology [130], (f) 3C-SiC barrier layer technology [132], (g) low-temperature AlN growth technology, (h) Traditional AlN Nucleation technology [123].

In 2008, Xiao et al. pointed out that the Si substrate would introduce parasitic load effects, resulting in degradation of power gain and PAE, indicating that loss would affect the device's power characteristics [139]. HR-Si substrates have a high substrate resistivity, thereby introducing small substrate leakage and substrate loss. In 2012, Xiao et al. used an HR-Si substrate (> 5 kΩ∙cm) and the measured RF loss was less than 0.5 dB/mm at 10 GHz. The GaN-on-Si RF device developed had an output power of 3.7 W/mm, a power added efficiency of 49.2%, and a gain of 14.3 dB at 2 GHz and 50 V drain voltage. Although this technology effectively reduced substrate loss, it did not consider another important type of loss, which is RF Loss of parasitic conductive path caused by the diffusion of Al and Ga into the P-Si substrate [129].

As early as 2007, Hanson et al. proposed forming a thin layer of amorphous SiN_x on the Si substrate surface as a barrier for Al and Ga diffusion, thereby reducing interface leakage current [140]. However, the amorphous layer can cause degradation of crystalline quality of the AlN nucleation layer and GaN buffer [123]. To overcome the problem, in 2014, Lumbantoruan et al. used the Pre-Al pre-treatment technology to suppress the formation of the amorphous SiN_x layer at the AlN/Si interface, improving the crystalline quality of AlN nucleation layer and reducing leakage current [138], as shown in Fig. 10d. The Pre-Al technology is now widely used in material epitaxy of GaN on Si. To further reduce RF Loss and improve material quality by suppressing Al and Ga diffusion, in 2020, Bo Shen et al. used substrate nitridation pre-treatment technology to promote the formation of an amorphous silicon nitride layer, which plays an important role in suppressing Al diffusion and reducing interface loss [130], as shown in Fig. 10e. The following year, Yachao Zhang et al. also used substrate nitridation technology to achieve high-quality AlN and GaN [131]. In 2020, CNRS used 3C-SiC barrier layer technology [132] to effectively suppress Al and Ga diffusion, as shown in Fig. 10f, and the measured RF loss was less than 0.78 dB/mm at 40 GHz. It should be noted that the above research technologies effectively suppress Al and Ga diffusion by introducing additional barrier layers. In 2016, Yamaguchi et al. used low-temperature AlN growth technology to effectively suppress the diffusion of Al and Ga atoms, what's more, the formation of interface hole layers [122], as shown in Fig. 10g.

In fact, in addition to the substrate loss and interface loss mentioned above, international research has shown the existence of another interface loss, which is caused by the electron inversion layer channel between the Si substrate and the AlN nucleation layer induced, thus introducing leakage paths. Internationally, this interface loss is reduced by changing the way the AlN nucleation layer grows. In 2017, Luong et al. [123] achieve the RF loss less than 0.8 dB/mm at 40 GHz by using the high-temperature/low-temperature/high-temperature layer-by-layer AlN nucleation growth technology (HLH-AlN Nucleation). Compared with traditional technology, RF LOSS has been obviously reduced, as shown in Fig. 10h. In 2020, Bo Shen et al. effectively reduced the interface leakage and RF loss [130] by reducing the thickness of the AlN nucleation layer.

In summary, the research on GaN on Si has been studied throughout nearly 20 years. It has been found that multiple parts of the material structure introduce non-negligible RF loss, including substrate loss caused by the Si substrate, the interface loss caused by Al and Ga diffusion in the Si substrate, and the interface loss caused by the electron inversion layer formed between the Si substrate and AlN nucleation. Although various technologies to suppress RF LOSS have emerged based on the different loss mechanisms, they are mutually constrained due to the interdependence between the related loss mechanisms. Fundamentally, RF loss based on GaN-on-Si materials is a multi-objective optimization problem, and the RF LOSS of any single loss mechanism is not the final optimal value. It is necessary to establish a comprehensive physical and mathematical model to minimize the overall RF loss.

4.2.3. High-breakdown technology

Although GaN-on-Si devices exhibit superior performance compared to devices based on pure silicon technology, their breakdown characteristics deteriorate sharply in high-voltage applications due to the large vertical leakage current [125]. For RF applications, the reduction in overall thickness of material means that the thinner (Al)GaN buffer layer cannot fully release the large stress between GaN and Si, resulting in high dislocation density and defect density, which presents significant challenges for high-voltage applications. In 2020, T. Erlbacher et al. found epitaxial overgrown V-pits and the incorporation of oxygen and carbon across layers in the vertical direction by characterization methods such as AFM, SEM, and SIMS [126]. The results indicate that these areas are composed of high-concentration n-type carriers and contribute the vertical leakage path of the buffer layer, which will worsen the device breakdown characteristics [141]. To reduce vertical leakage, two methods are usually used: the use of a local p+ doping of the silicon substrate just below the drain-gate region [133], and the local removal of the substrate between the gate and drain [134,135].

4.3. RF performance of GaN-on-Si HEMTs

This paper makes a summary of the research progress of GaN HEMT on Si substrate for RF power applications in the past 20 years, mainly covering the achievements of major companies and universities worldwide. The session compares and analyzes different material structures, device structures and process technologies, to further understand the operating mechanisms and explore methods for achieving high power density and efficiency. It is shown that as the operating frequency increases, RF loss increases as well, mainly due to increased RF leakage introduced by the substrate and the AlN/Si interface [123], which leading to significant degradation in power density and efficiency. The following analysis presents the basic trends of RF power characteristics as the frequency gradually increases, at different operating voltages.

In 2020, Daniel Gryglewski et al. achieved a GaN HEMT on Si substrate for the L-band (1.2–1.4 GHz) with output power of 100 W and 116 W, power-added efficiency of 60% and 55%, and gain of 16 dB and 17.5 dB at 48 V and 50 V drain voltage, respectively. However, it was found that significant RF leakage exists at low frequencies and low temperatures, and the device has a relatively small temperature range [136]. In 2022, H. Lu et al. adopted the passivation implanted termination (PIT) process [114] achieving a GaN HEMT on Si substrate for the S-band (3.6 GHz) with output power density of 10.2 W/mm, power-added efficiency of 69% and drain efficiency of 72% at 30 V and 40 V drain voltage. The measured RF LOSS is less than 0.4 dB/mm at 3.6 GHz. The breakdown voltage is higher than 130 V, with Fe-doped buffer layer technology. In 2014, Min-Seong Lee et al. achieved a GaN HEMT on Si substrate for the X-band (8 GHz) with output power density of 8.1 W/mm, power-added efficiency of 39.3% and gain of 8 dB at 38 V drain voltage by HR-Si substrate, ICP-CVD passivation layer and ISV back via technology [137]. However, the thermal management problem of the material still exists. In 2015, Philippe Altuntas et al. used material layer stress modulation and double-passivation technology to improve the current collapse and frequency degradatio, achieving a GaN HEMT on Si substrate for Ka band (40 GHz) with output power density of 2.7 W/mm, power-added efficiency of 12.5% and gain of 6.5 dB at 25 V drain voltage. Based on the above summary, as the operating frequency increases, the RF power characteristics of GaN HEMT on Si degrade significantly. Therefore, how to reduce RF loss at high frequencies is the focus of future research and a core requirement for GaN-on-Si RF devices in millimeter-wave applications.

In addition to the aspects mentioned above, it is also necessary to consider the trade-off between the performance and cost of GaN-on-Si devices. In recent years, the growth technology for large-size 12-inch GaN-on-Si materials has seen significant advancements. The wafer yield and production efficiency have improved with the development of the large-size GaN-on-Si growth technique. Nevertheless, there remain cost challenges in the 12-inch GaN-on-Si epitaxy wafer and device fabrication due to the related tools required for large-size wafer processing. It is noteworthy that existing mature Si-based CMOS fabrication processing lines can accommodate 12-inch large-size GaN-on-Si fabrication without incurring additional setup costs, as exemplified by the Au-free GaN-on-Si fabrication process [112,142]. Furthermore, the utilization of CMOS-compatible GaN devices on large-size Si substrates holds promise for future heterogeneous integration and plays a crucial role in realizing high-performance RF power devices [117]. Therefore, it is essential to develop 12-inch GaN on Si wafer considering both performance and cost aspects.

5. GaN compact modeling

A precise nonlinear large-signal model that incorporates thermal and trapping effects is necessary to simulate DC, S-parameters, and nonlinear Figures of Merit (FoMs) such as AM-AM/AM-PM distortion, intermodulation distortion, EVM, and ACPR. There are several types of compact models available for RF GaN modeling: measurement-based models and physics-based models. There are different types of measurement-based models, including empirical models, table-driven models, and neural network-based models. These models will be described in more detail in the subsections below and the role they play in GaN compact modeling.

5.1. Empirical models

Empirical models represent measured terminal device characteristics by using an equation (i.e., a polynomial or cubic spline) to fit the data. The parameters in the model are just for fitting purposes and do not have any physical significance. These models are commonly used as a way to transfer information from device-level measurements to the circuit level for performance prediction. Their main advantage is their extraction ease as they only requirement measurements over a desired operating range. Their disadvantages include the need for large amounts of data and a lack of physical understanding of the device. There are two commonly used models for GaN: the Angelov model and the EEHEMT model. The Angelov model is a widely used empirical non-linear equivalent circuit model for various semiconductor technologies, which include GaN, GaAs, and CMOS [143]. The main focus of the Angelov Model is to capture the non-linearity in g_m observed in different semiconductor technologies, which usually follows a bell-shaped characteristic. The transconductance is expressed by a hyperbolic tangent function formulation to ensure the current expressions have infinite derivatives so that they can be utilized with ease for HB simulations. The model requires approximately 90 fitting parameters and has well-defined derivatives, but it is not physics-based. As such, the model must be re-extracted if any changes are made to the dimensions or process technology. An extension of the Angelov model (i.e., Angelov-GaN model) was introduced for GaN devices to improve harmonic management and present a more physically oriented approach to dispersion [144]. The equivalent circuit for the Angelov model can be seen in Fig. 11a.

Fig. 11.

(a) Equivalent circuit for Angelov model. (b) Modeling for various regions of the transconductance in EEHEMT model and its equivalent circuit. (c) Equivalent circuit for NeuroFET model showing the intrinsic device along with its parasitics. (d) The intrinsic equivalent circuit of the dynamic model shows the electrical circuit (left-top), thermal circuit (left-middle), and both trapping and averaging circuits (left-bottom). Training of I_D from measured NVNA waveforms (right). (e) The schematic of the core drain current model for the ASM-HEMT model illustrating all the real device effects that incorporated into it (after [151]). (f) The schematic of a GaN HEMT showing the various transistor regions in the MVSG model (left-top). The series-transistor modeling approach (right-top), and the sub-circuit approach used in the MVSG model (bottom), which illustrates the current sources and distributed charge modeling, which correspond to each region of the device (after [158]).

The Eesof HEMT (EEHEMT) model was initially created to target GaAs HEMTs [145]. This model is a derivative of the Curtice model. It was developed by Agilent Technologies (now Keysight Technologies) with the purpose of fitting the measured electrical behavior of HEMTs. The EEHEMT model features self-heating correction for I_DS, dispersion model (to fit high frequency conductances and DC characteristics), flexible g_m formulation, isothermal I_DS fitting, and a breakdown model. The complete model for fitting an RF HEMT device structure involves various equations along with 75 parameters. Fig. 11b shows the region-wise modeling of the transconductance and the equivalent circuit of the EEHEMT model.

5.2. Table-driven and neural network-based models

Table-driven and neural network-based based large-signal FET models are attractive options because they can predict the nonidealities (e.g., thermal and trapping effects) in the device without the need for complex physics-based equations. They are especially useful when good measurement data is available, and it is not feasible to obtain a physics-based model of the device in use. In particular, there are three models (Root, NeuroFET, and DynaFET models) that have been implemented natively in PathWave ADS [146]. These three models were developed by Agilent/Keysight Technologies. The Root model is a measurement-based table-driven model that computes state functions from measured raw data, stores the values in tables, and interpolates them during simulation using cubic spline functions [147]. It offers efficient and fast simulation of FET behavior in a circuit environment and its model generation procedure is simple, requiring only DC, S-parameters, and parasitic elements. However, a main drawback is the interpolation from spline functions, which may result in poor accuracy at low signal levels during nonlinear simulations if the data used to generate the model is noisy.

To overcome the limitations of the Root Model, the NeuroFET model was introduced as a solution. It uses neural networks to generate smooth, infinitely differentiable, and uniform approximations of the device characteristics, instead of relying on cubic spline functions [148]. NeuroFET uses the same framework, data, and model generation procedures as the Root Model, with the main difference being the use of neural networks to express the constitutive relations analytically, resulting in improved simulation accuracy at low power levels. This is crucial for simulating linearity metrics like the OIP3. Fig. 11c shows the equivalent circuit for the NeuroFET model.

DynaFET is a neural network-based model takes into account the nonlinear dynamic effects (e.g., thermal and trapping) using large-signal nonlinear vector network analyzer (NVNA) data [149,150]. NVNA data, when combined with DC and S-parameter data, provides valuable information such as large-signal waveforms, which enhances nonlinear circuit modeling compared to models that rely solely on DC and S-parameters. To extract this model effectively, measurement data at two or more temperatures is necessary. The DynaFET model includes an intrinsic equivalent circuit, which includes an electrical, thermal, trapping, and averaging circuits as shown in Fig. 11d. As a result, this model is an accurate and global solution that predicts device performance without requiring any application-specific model tuning. However, this model is not appropriate for FET switch designs as its formulation does not apply to switch applications and mainly focuses on PA applications [149,150].

5.3. Physics-based models

Unlike measurement-based models, physics-based models take time to develop as they are based on analytical expressions derived from physics laws governing the physical phenomena of electronic devices such as transistors. In GaN HEMTs, these expressions are obtained by simplifying the rigorous 3D electrostatics and charge equations (e.g., Poisson and Schrodinger equations) and transport equations (e.g., ballistic transport or drift-diffusion) into 1D equations by making the clever assumptions and approximations. One of the main advantages of these types of models is that they provide robust simulation within complex circuits, and they have a minimal compromise in the physics of the device as they use limited number of empirical parameters. This also implies that can be used to understand the physics of the device and can be scaled with respect to the device geometry once extracted. Another advantage of physics-based models is that they support statistical analysis for performance prediction in circuits as well as yield estimation in a given semiconductor process. The two main physics-based models for GaN HEMTs are the Advanced SPICE Model for High-Electron Mobility Transistors (ASM HEMT) and the MIT Virtual Source GaNFET (MVSG) model [151,152]. These two models have been approved by the Compact Modeling Coalition (CMC) and have been designated as industry standards.

The ASM HEMT model is based on a surface-potential formulation that solves the Poisson and Schrodinger equations in a triangular potential well by considering the first two energy sub-bands [151]. The drain current of the device is then calculated using the surface-potential formulation within the drift-diffusion framework and captures various real device effects such as self-heating, temperature dependence, mobility degradation, drain-induced-barrier-lowering (DIBL), velocity saturation, and trapping effects. Fig. 11e shows a schematic of the core drain current model and the incorporated real device effects. Past works in the literature have reported the model's capability of operating in the X, Ka, and W-bands [153], [154], [155].

The MVSG model calculates the terminal currents and charges in the device using a charge-based approach in a self-consistent manner. Fig. 11f illustrates a typical device cross-section, consisting of the gate, access, and field-plated regions. Although the charge and current formulations in each region are the same, they rely on different input parameters due to variations in electrostatics and transport. It also employs a series-connected transistor subcircuit topology, which is represented as a virtual source current source [152]. These virtual source current sources rely on the intrinsic source/drain potentials as seen in Fig. 11f. Similar to the ASM HEMT model, the MVSG model can capture both the static and dynamic behaviors of the transistor (e.g., thermal and trapping effects). Additionally, the model includes parameters for the subthreshold operation of the transistor, which is crucial for the accurate modeling of class-C biased devices such as auxiliary amplifiers in Doherty power amplifiers [156]. This model has been used extensively to design and analyze high-performance GaN RF and high-voltage (HV) circuits, allowing for the examination of crucial device-circuit interactions [59,[157], [158], [159]].

6. Conclusion

In this article, we provide a comprehensive review and offer future perspectives on research developments in RF GaN device technology. We delve into the realm of high-frequency, high-linearity, and cost-effective GaN devices for communication applications, accompanied by a thorough exploration of compact modeling in the literature. The insights gained from this extensive examination underscore the immense potential of GaN technology to revolutionize the field of telecommunications. In addition to the performance aspects discussed above, it is imperative to assess the reliability, lifespan, and repeatability of GaN RF devices, particularly when deployed in practical wireless communication applications. Future work will include evaluating the long-term reliability of critical components of RF GaN HEMTs, such as metal-semiconductor contacts, epitaxial stack layers, and passivation dielectrics. This review article aims to serve as a guide for the utilization of GaN HEMTs in 5G communication applications. It is believable that through reasonable device design and rigorous reliability verification, GaN devices can usher in a new era of dependable telecommunications infrastructure.

Declaration of competing interest

The authors declare that they have no conflicts of interest in this work.

Biographies

Hao Lu received the B.S. degree from the Nanjing University of Science and Technology, Nanjing, Jiangsu, China, in 2016, and Ph. D. degree from the Xidian University, Xi'an, Shaanxi, China, in 2022. He is currently a postdoc researcher with the School of Microelectronics, Xidian University, Xi'an, Shaanxi, China.

Meng Zhang received the B.S. degree in electronic science and technology from Xidian University, Xi'an, Shaanxi, China, in 2013, and the Ph.D. degree in material physics and chemistry from the Xidian University, Xi'an, Shaanxi, China, in 2019. He is currently an associate professor with the School of Microelectronics, Xidian University. His current research interests include the fabrication and characterization of GaN-based high frequency field effect transistors and GaN-based device with fin-shaped structure.

Ling Yang received the B.S. degree in electronic science and technology and the M.S. and Ph. D. degrees in microelectronics and solid-state electronics from Xidian University, Xi'an, Shaanxi, China, in 2005, 2008, and 2011, respectively. He is currently a professor with the School of Microelectronics, Xidian University.

Bin Hou received the B.S. degree in electronic science and technology from Xidian University, Xi'an, China, in 2011, and the Ph.D. degree in Material Physics and Chemistry from Xidian University, Xi'an, China, in 2018. He is currently an associate professor with the School of Microelectronics, Xidian University. His current research interests include fabrication and characterization of GaN-based normally off field-effect transistors and monolithically integrated E/D-mode HEMTs for GaN digital ICs.