Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor

Abstract

This paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance. The PTLA is designed with pass transistor logic that helps in optimization of transistor count. By effectively integrating PTLA with a low-power trimode technique, the proposed design optimizes key metrics such as power consumption, delay, and area. The innovative use of graphene based GNRFET ensures high carrier mobility and temperature resilience, while the trimode technique dynamically manages operational states for improved energy efficiency. The performance of two distinct configurations, 24T PTLA and 21T PTLA, has been evaluated under varying temperature and voltage conditions. Process voltage temperature (PVT) and Monte Carlo analysis validate the proposed circuits’ adaptability and reliability, showcasing substantial improvement in power-delay product (PDP) and leakage current. These advancements establish the designs as ideal candidates for AI-enabled devices and edge computing applications, where low power and high speed are critical parameters. Extensive Synopsys HSPICE simulations have been employed for performance optimization, demonstrating the robustness of the designs for next generation digital computing technologies. The 24T PTLA structure reduces the power by 99.9% and PDP by 99.5% compared to conventional CMOS, hybrid and transmission gate logic, which proves the highly energy-efficient nature of the circuit. The 21T PTLA design enhances delay stability by 99.6% and reduces leakage current by 99.8%, which ensures dependable performance under diversified conditions.

Introduction

Efficient computational components in VLSI systems become an important requirement in rapidly changing digital technology. The design and optimization of adder circuits are required at the very root, starting from basic calculation algorithms to sophisticated digital processing units, and act as the backbone of many applications¹. Consequently, conventional adder designs that have traditionally been based on CMOS technology have inborn limitations in power, processing delay, and area use. These constraints mean there are significant challenges in meeting up to modern technology demands that require more increase in speed, lesser consumptions of power, and miniaturization. Adder circuits are one of the digital building blocks fundamentals to many digital systems used to add binary numbers². All features of adder circuits, such as speed, amount of power, delay, and IC area used, become important in determining digital systems’ performance. The performance of traditional CMOS based adder has limitations due to transistor parasitic capacitances, interconnect delays, threshold voltage variations, charging and discharging of output node^3,4. So, there is need to more work on emerging technologies with addition of new material replacing convention Si based devices to obtain higher performance and miniaturization. Several researches have been targeted to develop power-efficient adder circuits, whereby such dual goals of low power consumption and high computational speed could be achieved. Among those efforts, some involve entirely new designs for gates; for instance, a new concept and design for an XOR and XNOR gate has been found to raise appreciable performance improvement after rigorous simulation and analysis. Again, a hybrid-logic full adder architecture to function based on a 10-T cell has also brought about appreciable improvements in terms of speed and power efficiency². Hybrid approaches have also been explored, like merging complementary pass-transistor logic and static CMOS logic to implement scalable low-power 1-bit hybrid full adders³. Another trend in research in this area is toward non-volatile hybrid full adders using technologies like the spin hall effect and spin-transfer torque magnetic tunnel junction for zero leakage in data storage due to nonvolatility nature of spin orientation resulting in low power consumption⁵. One of the researchers have proposed a radiation-hardened full adder design with layout selective duplication in CMOS to improve radiation tolerance against single-event transient effects caused by radiation⁶.

Various optimization techniques integrate transistor sizing with logic styles in the implementation of efficient hybrid full adders, like the hybrid logical effort technique proposed in^7,8. The hybrid approximation adders were investigated for low energy image and video processing accelerators in which it has been revealed that specific approximate adder structures can be co-designed with energy reductions ranging from 7.7% up to 73.2%⁹. Few circuits for ultra-low-power ternary half adders have been implemented using complementary nanowire field-effect transistors and gate-overlap tunneling field-effect transistors with the support of modern technology. Research into performance.

characteristics of CNTFET (Carbon Nano Tubes Field Effect Transistor) and GNRFET (Graphene Nano Ribbon Field Effect Transistor) transistor technologies in optimizing low-power applications has also been highlighted¹⁰. GNRFET have demonstrated excellent electrical properties with high carrier mobility and transconductance due to the long mean free path and zero band gap. The thin graphene channel of GNRFET results in to increased scalability limit up to 10 nm technology¹¹. The power consumption in integrated circuit should not go beyond certain limit when the circuit is operating at higher frequencies. GNRFET has been proved to be suitable for such circuit at reduced power consumption maintaining delays under limit. Recent research work includes multivalued ternary logic gates in the sub-32 nm technology domain to improve the power, delay, and area parameters^12–14. The design of complex digital logic circuits namely decoders, carry-skip adders and three operand binary adder has been a focus using GNRFET in 22-nm technology. This creates the driving force towards developing new efficient adder architectures as well as VLSI hybrid adder designs^15–17. Yadav et al. introduced a low-power, high-speed full adder design using CPL cross coupled full adder circuit and achieved power consumption of 2.65nW at 130 nm technology with 1.2 V supply voltage and frequency of 1 GHz¹⁸. Seok et al. reported an approximate adder using single input pair-based computation at 65-nm CMOS technology, achieving 21% and 12% improvements in area and power respectively¹⁹. Shah et al. proposed six different architectures of 32-bit hybrid adder and analysed their performances to obtain optimum speed and power consumption²⁰. Comparative studies proves that FinFET, CNTFET, and GNRFET technologies has enormous potential for low-power digital logic circuits in state-of-the-art electronics applications²¹. Sneha et al. claims the reduction in power dissipation and delay up to 10^–11 W and 10⁻⁸ sec respectively for GNRFET based 14T and 15T decoders at 22-nm technology showed improvement in logic density and performance²². On the other side, full adders designed with CNTFET technology has been proven noise tolerant and resistant to process variations, which help in realisation of low power design²³. A holistic approach towards the analysis of an GNRFET-based 20T hybrid full adder proved its applicability for computationally intensive application with 7.76nW power consumption and 481ps latency²⁴. The development of a high-speed multiplier for signal processing applications described in^25,26 highlights the optimisation of transistor configurations to enhance the computational speed and reduce delay. Similarly, the energy-efficient design of quantum-based multipliers tailored for nano-scale devices in IoT systems²⁷ underscores the importance of quantum-inspired techniques for achieving energy and space efficiency. For instance, the inclusion of 5 input majority gates in QCA-based SRAM designs²⁸ shows how future technologies can render circuits less power-hungry while still maintaining high performance in memory systems. Also, QCA provides fault-tolerant majority voter gates²⁹ that reliable and fault-tolerant systems with high clock frequencies, reduced circuit complexity, and lower power consumption³⁰. These advances underline the continued efforts in overcome conventional limitations that exist in the designs of full adders, with a view to meeting the ever-growing demand of modern digital systems, which places newer technologies and newer techniques in VLSI design at the forefront for better performance, efficiency, and reliability.

This paper present two different architectures 22 nm GNRFET based on hybrid pass transistor logic adder (PTLA), a pass transistor logic-based adder which is technique used to lower the number of transistors in a circuit combined with using trimode technique to enhance the power efficiency, lower operational delay, and optimize the area usage of adder circuits. 20T and 21T 22 nm GNRFET PTLAs is designed and simulated using Synopsys HSPICE validate the efficiency of these designs against real-world scenarios, including temperature and voltage variations.

Synopsys HSPICE was chosen for its advanced simulation capabilities, particularly its accuracy in handling complex transistor-level designs such as those involving GNRFETs. HSPICE offers precise transient, DC, and AC analysis, enabling a detailed evaluation of power, delay, and leakage current across varying conditions, such as temperature and voltage. Its ability to model nanoscale devices like GNRFETs ensures realistic performance characterization, critical for verifying the effectiveness of the proposed 21T and 24T configurations. Additionally, HSPICE’s Monte Carlo analysis feature facilitates robust statistical evaluations, ensuring the designs’ stability and reliability under process variations. These capabilities make HSPICE an ideal tool for optimizing the proposed adders and validating their suitability for modern low-power, high-speed digital applications.

A dynamic gate control effect in the trimode technique, reduces the leakage current extensively in the ground path leading to low power at higher operating speed. According to the input signals, the trimode technique dynamically turns operational states of adder circuits, namely active, and sleep modes, and thereby optimizes the power consumed with reduced delay. In this paper, a high electron mobility of GNRFETs and the efficiency of PTL (Pass Transistor Logic) is used to achieve a significant improvement in some key metrics like power delay product (PDP) and leakage current compared with the conventional full adder circuits. The primary objectives of the paper are to maximize the power efficiency, minimize the operational delay, and optimize PDP in adder circuits, where PDP, defined as the product of power consumption and delay, serves as a comprehensive metric to evaluate circuit efficiency, balancing speed and energy usage.

The proposed 21T and 24T GNRFET-based PTLA designs leverage advanced material properties of graphene nanoribbons, including high carrier mobility and excellent scalability, to achieve superior performance in low-power VLSI applications. The trimode technique dynamically transitions between active, park, and sleep states, minimizing leakage current and power consumption during idle periods without compromising performance during active operation. Theoretical insights into the physical principles, such as the role of dynamic virtual ground and efficient signal restoration through XOR/XNOR logic, further validate the robustness of these designs. Additionally, by mitigating voltage swing degradation and optimizing the critical path, the proposed approach ensures consistent performance under diverse conditions, making it highly suitable for AI acceleration and edge computing scenarios.

Methodology

The proposed 22 nm GNRFET PTLA circuits are designed using trimode technique for dynamic ground path management to achieve better power performance and circuit performance. The proposed 24T and 21T PTLA configurations exhibit distinct design trade-offs tailored for different performance metrics. The 24T configuration is optimized for power efficiency by incorporating additional transistors, which enhance leakage current reduction and ensure operational robustness under varying environmental conditions. This configuration prioritizes stability and energy efficiency, particularly at lower temperatures. Conversely, the 21T configuration employs a reduced transistor count to achieve minimal capacitive loading and enhanced switching speed, making it highly suitable for delay-critical applications. The 21T design’s simplified architecture, coupled with the trimode technique for dynamic ground path management, contributes to significantly lower leakage currents and improved delay stability.

A pair of transistors can be used to engineer the ground path, generating a virtual ground, which can then be dynamically regulated by carry-in and its complement. Here, the PTLA are designed with PTL that is hybrid of NMOS/PMOS and CMOS transmission gate (TG). This regulation is very important in shaping the logic at the output nodes through XOR and XNOR configurations for accurate logic operation. The trimode technique proposes three independent modes of operation: active, park, and sleep; all under the direct control of carry input signals. The proposed method also reduces the overall transistor count by avoiding additional switches or any control logic that are normally needed for power gating. The innovation behind the trimode technique lies in intelligently dealing with the three power states without using any additional transistors. Thus, with dependencies only on the carry inputs defining transitions among the active, park, and sleep modes, the circuit design provide optimum power consumption and usage of silicon area. One of the major problems associated with PTL is reduced voltage swing; hence, the integrity of the signals may be degraded while slowing down in circuit performance. These undesirable effects are taken care of by our design using the trimode methodology to achieve dynamic selection of operational states at the circuit level. For example, during active-mode operation, the virtual ground path gets fully turned on, and thus, the voltage levels are strong enough to overcome the effect of reduced voltage swing which is an inherent drawback of PTL. Also, the applications of both XOR and XNOR configurations in a trimode technique ensure proper restoration of logic levels for improving signal integrity and performance. This dynamic control, therefore, overcome the demerits of PTL while exploiting its advantages of reduced transistor count and reduced power consumption. The trimode technique, therefore, offers a strong solution to voltage variability issues by providing stability and reliability in logic transitions. In general, these hybrid full adders exhibit better efficiency and stability against voltage fluctuations, making them exceptionally well-suited for high-speed computing applications.

The proposed 22 nm GNRFET-based PTL adder incorporates low-power trimode technique to dynamically regulate the operating states in logic transitions among active, park, and sleep modes. This technique reduces the power consumption and leakage current quite effectively by managing the path of ground with carry input signals without any extra control logic and transistors. The active mode enables full circuit functionality, ensuring strong voltage levels and high-speed operation for critical tasks. In contrast, the sleep mode minimizes power consumption by gating the virtual ground path, reducing leakage currents when the adder is idle. The park mode serves as an intermediate state, maintaining minimal power consumption while preserving circuit readiness for rapid activation. The trimode technique impacts the operational states as in the active mode, it ensures perfect logic levels and high-speed operation by fully enabling the virtual ground path, reducing delay. In the sleep mode, it significantly reduces leakage currents by gating the ground path, minimizing power consumption during idle periods. During hold (park) mode, it maintains the logic state with minimal power, allowing quick transitions to active mode while balancing energy efficiency and performance.

The trimode technique utilizes a dynamic virtual ground, which is generated by carry-in (C_in) and its complement (C_in−bar) signals applied on the footer and holder transistors. The approach eliminates negative pass-transistor logic effects while maintaining robust logic operation by preventing signal degradation and reduced swing voltage. The trimode technique improves power efficiency, stability, and signal integrity so that the proposed adder is suitable for high-performance applications that are suitable in low power devices and portable electronics. Power delay tradeoff makes this design innovative and sets a new benchmark in low-power VLSI design.

Proposed 22nmGNRFET PTLA designs & simulation setup

This paper proposes a low-power hybrid technique exploiting intrinsic strengths of both PTL and TG logics in the design of adder circuits, targeting enhancement in power efficiency, reduced processing delay and area ensuring usage of classical optimization methodologies. PTL is strategically deployed to control the signal flow through critical path for multiplexing action and optimising the delay at reduced transistor count. Other than PTL, TG logic can be used for similar operations while maintaining the signal levels. Due to involvement of PMOS along with NMOS transistor, the transistor count is higher in TG comparative to PTL. As such, PTL and TG logic with a trimode configuration inherently self-adjusts to different operational modes: active, parking, and sleeping all taken from the logic states of the carry inputs. This adaptive feature leads to the design of a robust adder that will be stable against voltage fluctuations, allowing it to provide higher efficiency.

Figure 1 (a) is a functional block diagram of a full adder with XORs and XNORs in which an efficient compact method performing binary addition with Sum and Cout as output signals. The use of this kind of configuration that uses multiplexers for selecting the right output according to the inputs A, B, and carry-in (C) reduces the logic really to the minimum and possibly increases the speed for the adder circuit.

Fig. 1.

(a) Block diagram adder using XNOR and XOR²³ (b) Trimode Technique Block Diagram.

This is combined with tri-mode logic to improve the performance with the use of high carrier mobility GNRFET. Figure 1(b) demonstrates the schematic diagram of the proposed tri-mode technique, which dynamically controls the current path of the adder circuit by switching between active, park and sleep modes. In this design, a virtual ground has been used, controlled through two control signals: “SLEEP” and “PARK.” The current signals for these control signals are obtained by using the carry (C_in) and its complement (C_in−bar) signals such that state transitions are smoothly achieved. In the active mode, the virtual ground path is completely enabled for high-speed operations and robust logic levels. In the park mode, the circuit only consumes minimal power while still being ready in a fraction of a second for activation when necessary. During the sleep mode, the virtual ground further reduces the leakage currents since it is gated for optimal energy efficiency in idle states. The dynamic management of operational states allows the circuit to improve both performance and power efficiency while ensuring robust logic operation. The benefits of this approach are:

Critical path

The critical path experiences a reduced delay using PTL, which gives way to minimal series-connected transistors and hence a reduced capacitive load.

Non-Critical paths

Utilization of the TG in the non-critical path will still cut the power consumption with no sacrifice to the speed, as it very efficiently handles the transition between the logic levels with minimal loss of energy.

Area utilization

The compact structure of the hybrid adder is provided by the integration of a minimum number of transistors, as PTL and TG circuits need less silicon area in contrast to a bulk CMOS design.

Furthermore, the area savings and power efficiency of the proposed PTLA, compared to classical CMOS full-adder circuits which generally involve a larger number and size of transistors and consume more power for an equivalent functionality, is clear.

The mathematical equation for PTL power consumption in an adder circuit was first presented in the paper¹⁴. The equation can be expressed as:

1

Where is the power consumption of the PTL circuit, is the total load capacitance, V_dd is the supply voltage, f_clk is the clock frequency, Σ(W/L) is the total transistor area, α is the activity factor, and V_t is the threshold voltage of the transistor.

The mathematical equation for TGL power consumption in an adder circuit was presented in the paper¹⁵. The equation can be expressed as:

2

Where P_TGL is the power consumption of the TGL circuit, C_L is the total load capacitance, V_dd is the supply voltage, f_clk is the clock frequency, R_Trans is the resistance of the transmission gate, and C_Trans is the capacitance of the transmission gate.

The mathematical equation for trimode power gating technique in an adder circuit was presented in the paper by¹⁶. The equation can be expressed as:

3

Where P_Trimode is the power consumption of the trimode power gating technique, C_L is the total load capacitance, V_dd is the supply voltage, f_clk is the clock frequency, Σ (W/L) is the total transistor area, α is the activity factor, V_t is the threshold voltage of the transistor and C_gnd is the capacitance of the additional transistors added to the ground path. The use of different transistor sizes, threshold voltage, and clock frequency to achieve the desired performance requirements of the proposed adder circuit.

The GNRFET model parameters used in the simulation were sourced from ‘gnrfet.lib’, ensuring accurate representation of graphene nanoribbon transistor behavior with key parameters included as nRib = 2 (number of ribbons), n = 6 (number of conduction sub-bands), L = 32 nm (channel length), Tox = 0.95 nm (oxide thickness), sp = 2 nm (spacing between nanoribbons), and dop = 0.001 (doping concentration), optimizing device performance. Simulation accuracy and convergence were managed with settings such as ABSTOL = 10⁻⁵, RELTOL = 10⁻², and GSHUNT = 10⁻¹² respectively, ensuring stable numerical solutions for power, delay, and leakage current calculations. The operating temperature was set at 25 °C, with V_DD=1 V, and transient analysis was performed with a 1ns time step over 500ns, providing precise insight into dynamic behavior. Monte Carlo analysis was performed by varying nRib using a Gaussian function, ensuring stability and reliability assessment under process variations for real-world robustness. The Synopsys SPICE simulations were configured with key parameters to balance accuracy, convergence, and runtime, including ABSTOL = 10⁻⁵, RELTOL = 10⁻², and GSHUNT = 10⁻¹² respectively, ensuring numerical stability and efficient computation. The temperature was set at 25 °C, with V_DD=1 V, and the transient analysis was executed over 500ns with a 1ns time step, allowing precise measurement of power, delay, and PDP under realistic operating conditions. A trimode technique was applied to dynamically regulate the ground path, minimizing leakage currents during inactive states and improving power efficiency, validated through HSPICE transient and DC analysis. Voltage sweep analysis was performed across 0.8–1.2 V to assess power and delay trade-offs, showing quadratic power dependence on voltage while maintaining stability in delay for energy-constrained applications. Temperature-dependent behaviour was analysed, revealing that carrier mobility initially improves delay but later stage it is dominated by phonon scattering, ensuring the stability of 21T and 24T PTLA designs under varying thermal conditions.

Figures 2 and 3 presents new circuit design I & II of 24T and 21T PTLA respectively that are hybrid of PTL and Transmission gate logic (TGL) for better logic outputs, while decreasing the number of transistors. Such hybrid adders also make use of another low power technique called the trimode technique. The hybrid adder design balances the power, delay, and area parameters that allows the adder to be used for any low power digital circuit application. In trimode technique, an adder has a ground path with two extra transistors to enhance the ground bounce noise and reduce the power consumption. TGL-based NOR gate is used in the ground path to reduce the number of transistors in a critical path. The TGL-based NOR gate has been designed using four transmission gates and two inverters to reduce the propagation delay and improve the performance of the circuit.

Fig. 2.

Design I- 24T PTLA.

Fig. 3.

Design II- 21T PTLA.

The methodology blended in the design of this novel adder circuit is trimode technique, which includes a new management in ground path handling. In this methodology, the two transistors are used to create a virtual ground, a critically important feature that enhances the critical and non-critical paths in the circuit. These two transistors have inputs representing carry-in and its complement, C_in and C_in-bar respectively, which are essentially employed to develop logic at the output nodes. However, it is possible to find the logic of the output nodes through core structures of XOR and XNOR, which become an integral part of the adder design. The innovative aspect of the trimode technique lies in its ability to effectively handle voltage variations, offering better stability and higher efficiency. This is achieved without the need for additional transistors traditionally required for managing different operational states. Instead, the trimode technique uses the carry inputs to generate three distinct modes: active, park, and sleep. These modes are crucial for reducing power consumption, as they allow the circuit to dynamically adjust its power state based on the current computational requirements.

In Fig. 2, the design I-24T GNRFET based PTLA include XOR and XNOR logic for intermediate logic signals. Transistors P1, P2, N1, N2, P6, P7, N7, and N8 generate the initial XOR and XNOR logic to produce preliminary sum and carry signals. Transistors P4 and N5 function as inverters to redefine these intermediate signals. Only N9 and P10 implement the trimode low power technique, which improves leakage current and enhances full swing outputs. Transistors N4, P5, N6, and P8 are responsible for generating the sum signal, while N3, P3, P9, and N10 create the carry signal.

In Fig. 3, the design II, GNRFET based PTLA utilizes 21 transistors (21T) for efficient logic operations and low power consumption. Transistors P1, P2, N1, and N2 act as inverters for input A and the carry input (C_i). The combination of P3, P4, N11, N5, and N6 generates XOR and XNOR logic for intermediate signals, creating the initial sum and carry logic signals. Transistors P10 and N10 function as inverters to redefine these intermediate signals, ensuring proper logic levels. The trimode low power technique, implemented by P8 and N8, improves leakage current and enhances the full swing results for the outputs. For generating the sum signal, the circuit uses transistors N4, P6, N7, and P7. Meanwhile, transistors N3, P5, P9, and N9 are responsible for producing the carry signal. This configuration ensures effective logic operations, reduced power consumption, and improved signal integrity. Hence, the structure uses the benefits of PTL like optimized for speed, ability to switch faster, and trimode technique combats the negative effects of PTL such as full swing outputs for the critical path. Figure 4 shows the waveform of 22 nm GNRFET PTLA. The Avanwaves tool is used to analyse the correctness of the waveform output of the PTLAs designed in this study. The waveform output confirms that the PTLAs are operating correctly and achieving the desired performance metrics.

Fig. 4.

Waveform of PTLA Designs (24T & 21T).

For the non-critical path that calculates the carry-out (Cout), TGL is selected because it has the tradeoff with efficiency of signal transitions, meaning even the number of transitions increase, corresponding power increase can be kept low without degrading signal quality. The TGL path has a pair of complementary transistors acting as a transmission gate, providing a way with low resistance when the carry signal is asserted. On the other hand, employing synergy between the PTL and TGL paths in the trimode configuration allows the overall transistor count reduction to only 21, compared with many more required in traditional design styles. This makes it both power-efficient by reducing power consumption and contributes to a smaller silicon footprint for scaling down the chip size in dense VLSI applications. This 21T design is specifically aimed at addressing the urge of modern electronic devices, which demand high-speed computation as well as energy competence. The trimode, PTL, and TGL paths work in close cooperation to bring the full adder into action very reliably with practically all voltage conditions. It is suitable to be used in portable electronics, wearables, and IoT edge devices where power efficiency is also very critical in addition to performance. The leakage current and noise are reduced with the new signals ci and ci bar. These are generated using pass-transistor logic to bring down the voltage drop over the pull-up and pull-down networks of the circuit. This results in reduced leakage current and improved noise immunity.

These set of design techniques are used so that the final adder balances power consumption along with latency and noise immunity and supports any kind of digital circuit application. Use of optimized signal propagation paths reduces the capacitance for PTL/TGL logic styles, with great backlog performance and less power consumption. At last, this approach to final adder design purports to ensure the optimized propagation paths of the signals, to effectively and clearly reduce the assigned values of designed capacitance in the circuit at the same time, and to apply the low-power design technique as PTL and TGL are applied by ensuring high performance and low power usage in the process of digital circuits.

Results and comparative analysis

The PTLA designed using trimode technique for low-power applications with 22 nm GNRFET in the Synopsys HSPICE tool, have shown significant improvement in parameters of power, delay, PDP, and leakage current with respect to the full adder design. These improvements are realized by means of the low-power design technique PTL and TGL logic styles combined with the trimode technique, and the model used for GNRFET is Nano hub Spice model²⁵.

A) Circuit Performance Analysis.

Among the prime factors in low-power design, power consumption has played a vital role in the HFAs designed in this work. In comparison to traditional full adders, it has largely reduced power consumption. The reasons all lie in the low-power design techniques of PTL and TGL logic styles used, which require fewer transistors and provide faster switching speeds. Another prime factor in the performance of digital circuits is delay. The proposed PTLA have shown a reduction in the delay compared to the conventional adder circuit due to the optimized signal propagation path and reduced capacitance. Since PDP is the product of both power consumption and delay, it becomes a metric used in the assessment of general digital circuit efficiency. Compared to traditional full adders, the designed HFAs show improved PDP with low-power design techniques and optimized signal paths.

One of the major concerns in the design of modern digital circuits is leakage current. In this work, the designed hybrid full adders exhibit reduced leakage current owing to GNRFET technology. Figure 5 shows power consumption for hybrid 24T and 21 T PTLAs with considerable reduction due to low leakage currents. Figure 6 shows propagation delay of PTLAs. It shows decrease in delay compared to traditional full adders. Figure 7 shows PDP of proposed PTLA adders, this represents the power efficiency enhancement of hybrid adders. Due to the operation of transistors in the trimode, specially in the park mode, the leakage current got reduced as the leakage path got disconnected whose effect can be clearly observed in Fig. 8. EDP depicted in Fig. 9 of PTLAs is also under limit and lowest in design II of 21T PTLA due to the low leakage current and reduced delays.

Fig. 5.

Power consumption.

Fig. 6.

Delay Output.

Fig. 7.

PDP Output.

Fig. 8.

Leakage Current Output.

Fig. 9.

EDP.

Table 1 compares different designs that have been implemented, showing the supremacy of the proposed designs with respect to major parameters. In our proposed designs, the 24T PTLA shows a very low power consumption with PDP of 0.000123fJ·s. This can be explained by the fact that it is implemented using PTL Hybrid with GNRFET technology. The 21T PTLA design is power-efficient at low temperatures; hence, it is very appropriate for use where reliable operations under harsh environments are required. The 21TFA GNRFET design is rather steady on delay in different conditions, thus providing uniformity in performances. In contrast, conventional CMOS-based designs—the HFA-20T, HFA-17T, and HFA-26T—referenced from¹, tend to consume larger power with larger leakage currents, thereby underlining the efficiency of the proposed GNRFET-based approaches. Further, CPL and TGA designs based on MOSFET technology and FA Design-4 based on CNTFET technology also show comparable performance metrics but not as efficient and innovative as our proposed PTLA circuit with GNRFET designs. This clearly indicates that our work has immense contributions to the circuit design community by providing enhancements in power efficiency, delay stability, and technology advancements over earlier methodologies.

Table 1.

Comparison of various adders.

Design	Power (µW)	Delay (ns)	PDP (fJ)	Leakage Current (pA)	EDP (E-25 J*s)	Key Contribution/Parameter
HFA-20T [1]	0.039	0.0855	0.00333	15	0.0285	OR NOR based
HFA-17T [1]	0.0378	0.0943	0.00356	60	0.0336	OR NOR based
HFA-26T [1]	0.0452	0.0738	0.00333	35	0.0246	OR NOR based
Zavarei [2]	27	0.0723	1.95	43	1.41	Hybrid logic
Valsahni [2]	25	0.0713	1.78	41	1.27	CMOS logic
CPL [3]	48	0.452	21.7	67	9.81	Hybrid logic
TGA [3]	16.3	0.158	2.58	56.5	4.08	Transmission gate logic
X-Design5 [17]	0.0762	0.47	0.0358	35	0.168	Hybrid logic
FA Design-4 [23]	25.8	0.0415	1.07	71	0.444	Alternative Technology
24T PTLA GNRFET [This work]	0.00308	0.04	0.000123	0.9	0.000493	Best Power Efficiency at Low Temperature
21T PTLA GNRFET [This work]	0.00574	0.00314	0.000018	0.3	0.0000565	Best Delay Stability

Table 1 shows, FA Design-4²³, implemented using CNTFET technology, demonstrates high power consumption and delay compared to the proposed GNRFET adders. The 21T and 24T GNRFET PTLA achieve significant improvements in power efficiency, delay stability, and PDP due to the synergistic effects of the trimode technique and the inherent high carrier mobility of GNRFETs. For FinFET technology-based adder^32,33, similar power-efficient designs have been achieved with power in the range of low nano watts. However, the proposed GNRFET designs outperform in terms of power and delay stability, particularly at low voltages, underscoring their suitability for energy-constrained applications.

For area optimization, the number of transistors remains comparable across designs using FinFET, MOSFET, CNTFET, and GNRFET technologies, ensuring compatibility in terms of silicon footprint. This makes the proposed adders highly adaptable for integration into existing fabrication processes without introducing significant area overhead.

The optimization of metrics such as power, delay, PDP, leakage current, and EDP in the proposed designs is rooted in the strategic use of advanced techniques and innovative design methodologies. The reduction in power consumption is achieved through the trimode technique, which dynamically regulates the ground path, minimizing leakage currents during inactive states and ensuring efficient use of energy in active states. The improved delay performance stems from the reduced transistor count and optimized signal propagation paths, which shorten critical paths and reduce capacitive load, enabling faster switching. The enhanced power-delay product (PDP), which balances power and delay, results from the synergy between GNRFET technology and hybrid logic styles (PTL and TGL), leveraging high electron mobility and low threshold voltages for energy-efficient high-speed operations. The minimization of leakage current is attributed to the dynamic gate control inherent in the trimode technique, which prevents unnecessary current flow during idle periods. Lastly, the improved energy-delay product (EDP) reflects the circuit’s capability to deliver high-speed performance with minimal energy loss, owing to the efficient coordination of active and sleep modes without additional control overhead. Together, these advancements make the designs highly suitable for modern, energy-sensitive VLSI applications.

B) Temperature Analysis.

Temperature analysis becomes important in low-power VLSI design due to the fact that it impacts the performance, power, and reliability of the circuit. It has been observed that power gating, voltage scaling, and thermal-aware placement and routing reduce power consumption and enhance the performance of the circuit. Temperature analysis is applied on all circuits, and the effect is studied on delay and average power parameters. The average power seems to increase exponentially with temperature. This is consistent with many semiconductor behaviours. However, the general trend of rising power with temperature indicates increasing currents, which may be leakage or active currents. High temperatures raise the leakage current and power consumption that may cause thermal runaway, leading to circuit failures. The temperature also affects the speed of the transistors, thus contributing to delay and signal integrity issues. Further, high temperatures may cause electromigration and hot carrier effects, thus affecting circuit reliability. All circuits are found to have stable response at a high temperature. The delay performance curve indicates that there would be a massive drop in the delay with an increase in temperature initially, due to improved carrier mobility at higher thermal energies, followed by a plateau, indicating that GNRFETs reach a limit in their thermal stability where increased lattice vibrations no longer contribute to improved carrier mobility. The power curve follows an exponential rise in the average power with temperature, which is considered consistent with an increase in leakage currents at increasing temperatures and their impact on the average power consumed by the GNRFET-based PTLA. Figure 10 shows variation of delay with temperature for 24T PTLA design implemented using GNRFET technology. Figure 11 shows variation of average power consumption with temperature for 24T hybrid adder design.

Fig. 10.

Delay vs. Temperature 24T PTLA.

Fig. 11.

Average Power vs. Temperature of 24T PTLA.

The 24T delay curve decreases slightly with increasing temperature initially due to increased carrier mobility but deteriorates at higher temperatures due to phonon scattering that outweighs mobility benefits. The power consumption curve increases at higher temperatures, which corresponds to increased leakage currents and heightened phonon activity within the GNRFET structure and hence greater power dissipation.

Temperature analysis helps designers pinpoint those areas of the circuit most sensitive to temperature and deploy temperature-aware design techniques that mitigate the effects of temperature. These include thermal-aware placement and routing, power gating, dynamic voltage, and frequency scaling to reduce power consumption and hence temperature. The delay response shows a minor deflection at very low temperatures. Graphene is supposed to have a very high electron mobility, which could further lead to fastest devices. However, this high electron mobility can vary with temperature due to increased lattice vibrations also known as phonons and other scattering mechanisms.

The delay increases quadratically with temperature due to increased carrier scattering and lattice dilation in GNRFETs for a 21T design, while the steep rise of the power curve at higher temperatures is related to the increase in thermal generation of carriers, leading to higher leakage and dynamic power.

In low-power VLSI, where power consumption becomes a critical factor, the impact of temperature on power consumption and performance is even more paramount; the output proves high stability of output parameters in case of temperature variation analysis. Figure 12 shows the relation of delay with temperature for the 21T PTLA using GNRFET technology. The missing natural bandgap in graphene can be engineered using nanoribbons, which bring in quantum confinement effects, leading to the formation of a bandgap. As such, ribbon width and edge profiles could impact GNRFET delay. With changes in temperature, the band structure and transport properties might change, which could have implications for delay. These are local imperfections in graphene, such as defects, impurities, or grain boundaries, which might form localized states that will finally impact carrier transport. The impact of the localized state may be temperature dependent and result in small delay variations. Figure 13 shows the average power consumption of the proposed 21T hybrid adder design at various temperatures. Graphene has high electron mobility, making it potentially very fast. Still, low off-state leakage may be hard to achieve without natural bandgap. If GNRFETs have poor on/off ratios or the nano ribbons have been designed/fabricated with smaller bandgaps, then off-state leakage can be huge and strongly temperature dependent.

Fig. 12.

Delay vs. Temperature 21T PTLA.

Fig. 13.

Average Power vs. Temperature 21T PTLA.

The impact of temperature variation on power and delay in the proposed 21T PTLA design is primarily influenced by the intrinsic properties of the GNRFET material. As temperature increases, the enhanced carrier mobility due to thermal activation initially reduces delay by improving charge transport efficiency. However, at higher temperatures, phonon scattering dominates, increasing resistance and counteracting the benefits of enhanced mobility, leading to a saturation or slight rise in delay. This dual effect is critical in ensuring that the design operates reliably across a wide temperature range, balancing performance and thermal stability. The proposed design also leverages the trimode technique to dynamically manage power dissipation, reducing leakage currents in sleep mode and ensuring energy-efficient operation even under thermal stress.

In terms of power, the GNRFET-based PTLA demonstrates strong thermal resilience. At elevated temperatures, while leakage currents increase due to thermally activated carriers, the trimode dynamic ground path management significantly mitigates their impact. Additionally, the high electron mobility of graphene and the bandgap engineered through the nanoribbon structure ensure a robust balance between power efficiency and stability under varying thermal conditions. By coupling these material properties with advanced design techniques, the proposed 21T PTLA achieves substantial gains in energy efficiency and delay stability, making it a promising candidate for low-power, high-performance applications in thermally variable environments.

C) Voltage Analysis.

Voltage sweep analysis is the simulation approach used to test the performance of the circuit under varied voltage conditions. In this paper, we analyze hybrid full adders with 24T and 21T circuits as the voltage changes from VDD 0.8 V to 1.2 V. This involves voltage sweep analysis done using a circuit simulator HSPICE. First, we need to design the hybrid full adders with 24T and 21T circuits by applying the correct transistor models. After this, we make a simulation regarding the circuit under different voltage conditions. Figure 14 shows Average power consumption of the 24T hybrid full adder design at different supply voltages. Figure 15 shows Delay variation with supply voltage for the 24T hybrid full adder design. One very basic thing, concerning digital electronics as far as semiconductor devices are used in VLSI circuits, has been the impact of voltage variation on average power and delay.

Fig. 14.

Average Power vs. V_DD 24T PTLA.

Fig. 15.

Delay vs. V_DD 24T PTLA.

Dynamic Power: This is the power consumed when the transistor switches states (from ‘0’ to ‘1’ or vice versa). It’s given by the expression (4):

4

where: α is the activity factor (fraction of time the transistor is switching), C_L is the load capacitance, V_dd is the supply voltage, f_clk is the frequency of operation. As evident from the equation, dynamic power has a quadratic dependence on voltage.

Leakage power is evaluated when the transistor is off but still has a small amount of current flowing through it. The leakage current tends to increase with increasing voltage, but not as fast as the dynamic current.

Overall, the total average power increases with increasing voltage, with the dynamic component typically showing a stronger dependence due to its quadratic relationship.

As the voltage changes from 0.8 V to 1.2 V, we plot the delay and average power consumption of the circuits. The delay is the time it takes for the output to change in response to a change in the input. The average power is the amount of power consumed by the circuit over a period. For the 24T design, average power consumption increases nonlinearly with V_DD due to the quadratic relationship between supply voltage and dynamic power, compounded by voltage-aggravated leakage currents. Delay decreases with rising V_DD, reaching a threshold where intrinsic capacitance charging rates outpace the benefit of higher drive currents, plateauing the delay reduction.

To calculate the delay, we measure the time difference between the rising edge of the input and the rising edge of the output. The delay varies with voltage, and we plot the delay vs. voltage graph to visualize how the delay changes with voltage. The delay of a transistor, which signifies the swiftness with which it can alternate between its states, is profoundly influenced by its supply voltage. As the supply voltage escalates, the differential between the ‘on’ and ‘off’ states of the transistor grows, ushering in a more potent electric field. This enhanced field is adept at moving charges with greater rapidity, thereby accelerating the transistor’s switching and diminishing its delay. However, it’s pivotal to consider the transistor’s threshold voltage, which is the minimum voltage required for it to activate. When the supply voltage hovers near this threshold, even minute variations can lead to pronounced fluctuations in delay. Moreover, as we keep augmenting the voltage, the benefits in terms of reduced delay start showing signs of diminishing returns. This means that while the delay continues its descent with higher voltages, the magnitude of improvement tapers off.

To calculate the average power, we integrate the power consumption over time and divide by the simulation time. The power consumption also varies with voltage, and we plot the power consumption vs. voltage graph to visualize how the power consumption changes with voltage. Figure 16 illustrates the average power consumption of the 21T hybrid full adder design at different supply voltages. Figure 17 displays the delay output of the 21T hybrid full adder design at different supply voltages.

Fig. 16.

Average Power vs. VDD 21T PTLA.

Fig. 17.

Delay vs. VDD 21T PTLA.

For the 21T design, the average power exhibits a nonlinear rise with increasing VDD, reflecting the square-law dependency of dynamic power on supply voltage, compounded by elevated leakage currents at higher voltages. The delay curve’s initial dip and subsequent rise suggest an optimal voltage range for performance before delay penalties from increased resistive effects and signal integrity degradation at higher voltages become significant. The results of the voltage sweep analysis help us optimize the design of the hybrid full adders. For example, we find that the 21T circuit has the lowest power consumption and delay at a particular voltage, so we may choose to use that circuit in the final design.

In summary, voltage sweep analysis is a powerful simulation technique for evaluating the performance of circuits under different voltage conditions. Design and optimization of the circuit is performed by calculating the delay and average power consumption of hybrid full adders with 20T, 21T, circuit style with supply voltage variation from 0.8 V to 1.2 V. The increase in voltage can improve performance by reducing delay at the cost of increased power consumption. This trade-off is central to concepts such as dynamic voltage and frequency scaling (DVFS) used in modern processors to balance performance and power consumption. In specific advanced technologies, other effects, such as short-channel effects, velocity saturation, and increased leakage due to thinner gate oxides, can further complicate the relationship between voltage, power, and delay. But in GNRFET, there is significant improvement in short channel effects, the delay results are having minor changes over the voltage variations.

Each of the proposed 20T and 21T PTLA, leveraging GNRFET technology, exhibits distinct characteristics that cater to different application needs. The 21T design excels in minimizing delay, as evidenced by its performance at varying voltage levels, making it an excellent candidate for high-speed applications where timing is critical. Its higher power consumption might be a trade-off for environments where speed takes precedence over energy efficiency. This stability is crucial for applications requiring reliable performance regardless of external conditions. It demonstrates moderate power consumption and delay, positioning it as a well-balanced option for general purposes. The 20T design shows optimal power efficiency at lower temperatures, suggesting its suitability for cool environments, potentially making it ideal for energy-constrained applications where maintaining lower temperatures is feasible. While its delay sensitivity to temperature changes is more pronounced, it could still be the design of choice for systems that operate within controlled temperature ranges. Each design brings valuable benefits, and the choice among them would be guided by the specific priorities of the intended application, whether it is speed, stability, or power efficiency.

In summary, the research conducted highlights that the utilization of 22 nm GNRFET PTLA in low-power VLSI design, employing PTL and TG logic exploiting trimode techniques, offers significant advantages in terms of power consumption, performance, and reliability. The 21TFA GNRFET design has demonstrated the most favourable results with benefit in power consumption, delay, and leakage current when compared to conventional adder designs.

D) Monte Carlo Analysis:

An important analysis which checks stability of the circuit is Monte Carlo analysis, here the proposed 21T PTLA is analysed, showing an evaluation of the stability and performance of the circuit under diverse conditions. This statistical method is based on varying the number of ribbons, Nrib, by a Gaussian function to imitate real variations in power and delay. Results prove that the adder is highly reliable and robust enough to ensure its operation under different operational scenarios.

Figure 18 shows only slight variation in the average power during the Monte Carlo analysis of the proposed adder, thus highly stable. In this case, the number of ribbons, nrib, will be swept by a Gaussian function to check the stability of the power of the adder. In these two cases, the power remains stable, which proves the strength of the 21T PTLA. The slight deviations noted are within acceptable limits, thus proving the reliability of the adder’s power efficiency under various conditions.

Fig. 18.

Average Power Monte Carlo Analysis of 21T PTLA.

The delay response of Monte Carlo analysis for the proposed adder, as shown in Fig. 19, has slight fluctuations thus showing an excellent response and stability. The number of ribbons, nrib, is varied using a Gaussian function to evaluate its delay performance. Offsets analyzed, the adder has extremely stable delay times. The variations noticed are at a minimum, thereby further validating the 21T PTLA for its ability to perform reliably under varying conditions. This consistent performance underlines the robustness of the adder and its efficiency with respect to delay.

Fig. 19.

Delay on Nrib Variations for Monte Carlo 21T PTLA.

E) Ultra Low-Voltage Analysis.

Ultra-low voltage analysis under extreme conditions is important in evaluating the applicability and reliability of such circuits in energy-constrained environments, such as in the development of portable electronics and IoT devices. It therefore provides insight into the behavior of power, delay, and leakage current at subthreshold voltage levels for ensuring circuit robustness and efficiency in diversity of operation scenarios.

The proposed 22 nm GNRFET-based hybrid Pass Transistor Logic Adder (PTLA) employing tri-mode exhibits significant improvements in power efficiency, delay, and PDP over conventional CMOS adders. To verify the applicability and limitation of the design under extreme conditions, ultra-low voltage analysis has been performed, as shown in Fig. 20. This ultra-low voltage analysis evaluates power performance of both the 21T and the 24T PTLA designs to ensure that their designed configurations still exhibit operational reliability along with efficient power consumption in the broad voltage range from 0.2 V up to 0.6 V. The experiment results show that the 21T PTLA will consume less power as it has fewer transistors and reduces dynamic switching activity to a minimum, while the 24T PTLA provides better leakage control, especially at low subthreshold voltage. These conclusions demonstrate the proposed PTLA circuits’ suitability for low power applications such as portable electronics or IoT devices, with their proven capabilities within ultra-low voltage environments. However, the limitations observed in this is rise in leakage currents at lower voltage thresholds which might potentially be alleviated with further optimization of the GNRFET structure or use of advanced leakage suppression techniques.

Fig. 20.

Ultra Low Voltage Analysis on Power.

Conclusion

The two proposed 24T and 21T GNRFET PTLA’s have huge improvements over traditional CMOS-based adders. Specifically, the 24T GNRFET PTLA (Design I) reduces the power by 99.9% and PDP by 99.5% compared to conventional CMOS, hybrid and transmission gate logic respectively. The 21T GNRFET PTLA (Design II) enhances delay stability by 99.6% and reduces leakage current by 99.8% at lesser transistor count. Presented here is the in-depth analysis of all parameters, including power, delay, PDP, EDP, leakage, temperature effect, and voltage variations. Hybrid adders of PTL and TG logic with trimode technique make PTLAs unique in architecture with minimum IC area and power efficient. The Monte Carlo analysis has also proved the adder to be very robust and stable, with only small visible variations in different process conditions. The result reflects the transformative potential of 22 nm GNRFET technology improve the performance of PTL and TGL based adder circuit toward the advancement of energy-efficient digital circuitry and provide a solid backbone for the next generation of AI-enabled devices and processors with high computational powers. Expanded comparative experiments have demonstrated that the proposed designs outperform state-of-the-art adders, such as FinFET and CNTFET based adder implementations, in terms of power-delay product (PDP) and leakage current under varying temperature and voltage conditions. Furthermore, discussions on physical mechanisms such as carrier mobility, phonon scattering, and bandgap engineering in GNRFET provide deeper insights into the observed temperature resilience and stability of the proposed circuits. These mechanisms are pivotal in ensuring consistent performance for AI-enabled systems operating in variable environmental conditions, thereby reinforcing the practical relevance of this work in low-power and high-speed applications. The proposed 21T and 24T PTLA designs are well-suited for AI-enabled devices, particularly for tasks such as neural network computations and edge-based analytics. The reduced power consumption, achieved through the trimode technique, ensures efficient operation in energy-constrained environments, a critical requirement for mobile and wearable AI systems. Additionally, the low delay of the 21T configuration supports the rapid processing demands of neural network inference and real-time data analysis at the edge, minimizing latency. These characteristics, combined with the compact architecture of the designs, make them ideal for integration into space-constrained AI hardware, enabling energy-efficient, high-speed intelligent systems.

Author contributions

Scholar Sneha Arora carried out the design work. Suman Lata Tripathi wrote the introduction and analysis, Sobhit Saxena wrote the abstract and conclusion, and Inung Wijayanto wrote the overall review.

Funding

Funding is not received for this design and analysis work.

Data availability

The data will be made available upon reasonable request to first author Sneha Arora.

Declarations

Competing interests

The authors declare no competing interests.

Conflicts of interest/competing interests

The authors don’t have any conflict of interest.

Ethics approval

This work is related to simulation-based design and analysis that is not producing any environmental hazards.