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. 2025 Apr 4;17(15):23357–23367. doi: 10.1021/acsami.5c01274

Analysis of the Ambipolar Conduction of Tin Monoxide Thin-Film Transistors with Indium Tin Oxide Electrodes

Sahngik A Mun †, Seoryong Park †, Min-Hyun Lee ‡, Yonghee Lee †, Sukin Kang †, Jinheon Choi †, Jaewon Ham †, Juneseong Choi †, Cheol Seong Hwang †,*
PMCID: PMC12012736  PMID: 40183700

Abstract

graphic file with name am5c01274_0007.jpg

This study investigates the hole and electron conduction properties of thin-film transistors (TFTs) with a tin monoxide (SnO) channel and indium tin oxide (ITO) source/drain (S/D) electrodes, considering the adoption to three-dimensional (3D) NAND Flash. Compared to SnO TFTs with gold (Au) S/D electrodes, significant enhancement of electron conduction was observed when adopting ITO S/D electrodes. The ITO electrodes decreased the Schottky barrier height for electron injection, enhancing electron conduction and consequently inducing ambipolar conduction behavior. The ambipolar SnO TFT exhibited coexisting electron and hole channels, which induced a transition from normal to abnormal conduction properties. These transitioning conduction characteristics were analyzed, and a method to extract saturation mobility in ambipolar TFTs considering the electron–hole (e–h) recombination effect was proposed. Furthermore, bias-stress stability tests were conducted to examine the effect of the coexisting electron and hole channels on the carrier-trapping properties. This analysis provides valuable insights into the electrical characteristics of ambipolar TFTs, considering the coexisting electron and hole channels.

Keywords: ambipolar conduction, tin monoxide, thin-film transistor, mobility extraction method, electron−hole recombination

Introduction

The increasing demand for higher-density NAND Flash memory has driven dimensionality scaling and device structure transition from two-dimensional (2D) to three-dimensional (3D).1,2 The conventional polysilicon channel has shown deteriorated electrical characteristics as the channel thickness reached sub-10 nm in the 3D NAND Flash structure, prompting the exploration of alternative channel materials, with metal oxide semiconductors emerging as strong candidates. A metal oxide semiconductor channel must support the conduction of both holes and electrons because they must be injected from the channel to the charge trap layer to erase and program the cells. When adopted as a channel material in NAND flash memory, n-type oxide semiconductors such as InGaZnO have demonstrated effective electron conduction and programming capabilities.3,4 However, they lack holes, making the erase operation challenging.5

Tin monoxide (SnO) is an appealing contender for this purpose due to its relatively small indirect bandgap of 0.7 eV,6−8 which allows for the contact metal’s Fermi level (EF) to be close to both the conduction band minimum (CBM) and valence band maximum (VBM). In addition, the energy band structure, comprising Sn 5p orbitals at the CBM and hybridized Sn 5s and O 2p orbitals at the VBM, provides a metallic character in both band edges, facilitating the conduction of both holes and electrons.8 Consequently, SnO can be a feasible hole- and electron-conducting channel material in 3D NAND Flash cells. Furthermore, SnO is compatible with the atomic-layer deposition (ALD) technology, further evidencing its suitability to 3D NAND Flash technology as the channel must be deposited within a deep hole structure.7,9,10 ALD SnO shows both p-type and n-type conduction in the sub-10 nm thickness, which is a beneficial feature for scaling of 3D NAND Flash device.11 Despite its potential to address the limitations of current polysilicon and n-type metal oxide semiconductor channels, research on the possibility of applying ALD SnO as a channel material for 3D NAND Flash remains limited.

SnO inherently exhibits p-type conduction characteristics due to the formation of tin vacancies, which form shallow acceptor states and generate holes.12 However, the high density of defect states within the bandgap hinders the upward shift of EF, disturbing the formation of an electron-conducting layer and consequently limiting electron conduction. As SnO is an intrinsically p-type material, forming an electron-conducting layer in the channel is called “electron inversion”. Considering the adoption as a channel material for 3D NAND Flash, enhancing the electron conduction properties of SnO is essential for efficient program operation. Previous studies proposed various methods to improve the electron conduction properties of SnO thin-film transistors (TFTs). They focused mainly on decreasing the subgap defect states through annealing and adopting surface passivation layers to facilitate the formation of an electron inversion layer in the SnO channel.13−15 A few studies reported on oxygen vacancy-induced electron conduction enhancement by incorporating metallic Sn.16,17

However, the electron conduction properties of SnO are not only affected by the subgap defect state-dependent electron inversion capability of the channel but also by the source/drain (S/D) electrodes. Particularly, the electron injection barrier between the channel and S/D electrodes significantly impacts the electron conduction behavior in the SnO channel. This study reports on adopting indium tin oxide (ITO) as S/D electrodes to enhance the electron conduction of SnO TFTs, making it show ambipolar conduction properties. This work demonstrates the potential of ambipolar SnO as a channel material for 3D NAND Flash memory.

Moreover, this study analyzes the effect of coexisting hole accumulation and electron inversion channels on the electrical characteristics of ambipolar SnO TFTs. This coexistence induces electron–hole (e–h) recombination, deteriorating the device’s electrical performance and inducing a transition from normal to abnormal conduction characteristics. These phenomena have rarely been discussed despite the importance of the conduction disruption caused by e–h recombination and the transitional conduction properties. This work provides a detailed analysis of these effects and suggests a new mobility extraction method that accounts for the influence of e–h recombination. The bias-stress stability tests were also conducted to examine the effect of coexisting electron and hole channels on the charge-trapping properties.

Results and Discussion

Figure 1a shows a top-view scanning electron microscopy (SEM) image of the SnO TFT having a staggered bottom-gate structure, with 7 nm-thick SnO film as the channel, 80 nm-thick Au or ITO thin films adopted as S/D electrodes, heavily doped p-type substrate as the gate, and a 30-nm-thick SiO2/15 nm-thick Al2O3 stacked dielectric layer as the gate insulator. Figure 1b,c displays the cross-section transmission electron microscopy (TEM) images at the Au/SnO and ITO/SnO contact regions, respectively. Both electrodes exhibit sharp interface structures without notable intrusions or chemical reactions. The crystallographic properties of the SnO channel were also investigated. Figure 1c indicates lattice spacings of 4.76 Å with Fast Fourier transform (FFT) patterns in the lower left corner corresponding mainly to the (001) planes and subsidiary planes such as (002), (110), (111), and (112) planes. In addition, Figure 1d displays the glancing angle X-ray diffraction (GAXRD) pattern with a sharp diffraction peak at 2θ of 18.3°, also indicating the polycrystalline SnO film with its tetragonal (001) plane.

Figure 1.

Figure 1

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(a) Top-view SEM image of SnO TFT. Cross-sectional TEM images of (b) Au/SnO/Al2O3 and (c) ITO/SnO/Al2O3 configurations and FFT pattern (inset at the lower left corner) analysis of SnO deposited on Al2O3/SiO2/p++-Si. (d) GAXRD analysis results of SnO deposited on Al2O3/SiO2/p++-Si.

Analysis of ambipolar devices requires considering both holes and electrons and their interactions, which may complicate the accurate understanding. Therefore, the electrical characteristics of unipolar SnO TFTs with Au S/D electrodes, which allow only the holes to be injected, were first examined. Figure 2 shows the electrical properties of SnO TFTs with Au S/D electrodes. Figure 2a shows the drain current–gate voltage (ID–VG) curves of SnO TFTs with Au electrodes, measured at a drain voltage (VD) of −5 V. The gray lines denote ID–VG curves measured from 10 devices. The devices show unipolar characteristics with large hole-induced ID in the negative VG region and negligible electron-induced ID in the positive VG region. The unipolar conduction characteristics are due to the Ohmic contact between Au and SnO for hole injection, while a Schottky contact with a larger injection barrier height is formed for electron injection. Figure 2b schematically demonstrates the band diagram of Au/SnO/Au configuration at VG = VD = 0 V. SnO exhibited a work function of 4.12 eV, which was extracted from ultraviolet photoelectron spectroscopy (UPS). Supplementary Note 1 describes the details of the UPS measurements. As the Sn vacancies form acceptor states near VBM, EF is likely positioned near the VBM.13 Therefore, the electron affinity and ionization potential are expected to be slightly smaller than 3.7 and 4.4 eV, respectively, the values reported in previous literature.18 The work function of Au (5.1 eV) exceeds the ionization potential of SnO, enabling Ohmic contact formation for hole injection. On the contrary, Au’s work function is significantly larger than SnO’s electron affinity, inducing a high Schottky barrier height for electron injection.

Figure 2.

Figure 2

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Electrical characteristics of SnO TFT with Au S/D electrodes: (a) ID–VG curves measured at VD = −5 V. (b) Schematic band diagram of Au/SnO/Au configuration at VG = VD = 0 V. ID–VD curves measured at (c) VG = −15 to −3 V and (d) VG = 3–33 V. Schematic illustrations of carrier profiles in SnO channel at (e) VG = 3 V and VD = 10 V and (f) VG = 6 V and VD = 10 V. The red regions indicate free holes. (g) Inline graphic–VD curves extracted from ID–VD curves measured at VG = 3–15 V. The straight lines indicate curves fitted to eq 4.

Figure 2c,d illustrates the drain current–drain voltage (ID–VD) curves at VG, VD < 0 V, and VG, VD > 0 V, respectively. Normal output characteristics in Figure 2c with linear curves at −VD < – (VG – Vth,h) and saturated curves at −VD > – (VG – Vth,h) indicate the formation of a hole accumulation channel at VG, VD < 0 V, where Vth,h is the threshold voltage of the device in the hole-conducting region. Vth,h was −2.9 V, obtained from the linear fitting of gm–VG plot (Supplementary Figure S2a) obtained from the ID–VG curve in Figure 2a, where gm is the transconductance.19,20

On the contrary, Figure 2d shows a nonlinear increase in ID with increasing VD at VG, VD > 0 V, deviating from the normal ID–VD curves.13 It should be noted that the ID level in this graph is in the order of nA, whereas that in Figure 2c was in the order of μA. This anomaly is attributed to hole conduction, as VGS-induced electron conduction is negligible, as noted by the ID–VG curves in Figure 2a. As VD increases, VGD decreases, which facilitates hole accumulation and injection from the drain electrode, leading to the abnormal ID–VD curves observed in Figure 2d. Supplementary Figure S3a shows that the gate leakage current (IG) was negligible (<10–10 A) across the VG range of 3 to 27 V over the entire VD measurement range due to the thick gate insulator stack (30 nm-thick thermal SiO2/15 nm-thick ALD Al2O3). On the contrary, Supplementary Figure S3b displays a significant increase in IG in the VG range of 30–33 V, which led to noise in the ID–VD curves in Figure 2d in that VG range. Methods to overcome this catastrophic leakage current, considering its application to 3D NAND Flash, are elaborated in Supplementary Note 2.

Figure 2e presents a schematic diagram illustrating the VGD-induced hole conduction properties of SnO TFT with Au S/D electrodes at VG, VD > 0 V. The gate and drain electrodes are biased at 3 and 10 V, respectively, while the source electrode is grounded. While electron inversion layer formation from the source electrode is negligible at VGS of 3 V, a strong hole accumulation layer is formed due to VGD of −7 V, as indicated by the schematic diagram’s red regions. As VD increases to higher values, VGD decreases, increasing the concentration of accumulated holes from the drain. Therefore, VGD-induced holes from the drain electrode contribute to the nonlinearly increasing ID with increasing VD in Figure 2d.

Figure 2d also shows a decrease in ID with increasing VG. This negative correlation between ID and VG is attributed to the increase in VGD with increasing VG, which decreases the injection and accumulated concentration of holes. The schematic diagrams in Figure 2e,f clarify this trend. Figure 2f schematically illustrates SnO TFT with Au S/D electrodes where the gate is biased at 6 V, larger than the VG of 3 V in Figure 2e, with the same VD of 10 V (VGD of −4 V). Same as Figure 2e,f exhibits negligible VGS-induced inversion electrons as no sign of electron inversion is observed in the transfer characteristics (Figure 2a) at VGS of 6 V. On the other hand, holes are accumulated from the drain electrode due to negative VGD of −4 V. Fewer holes accumulate in Figure 2f compared to Figure 2e in which VGD of −7 V is applied. Therefore, ID decreases as VG increases due to the smaller concentration of VGD-induced holes in the SnO channel.

The abnormal ID–VD curves in Figure 2d at VG, VD > 0 V were modeled based on the conventional ID–VG equation for metal oxide semiconductor field-effect transistors (MOSFETs).21 In conventional p-type MOSFETs, VGS accumulates holes at VG, VD < 0 V. The ID–VG relationship and the mobility of holes in the saturation region (μhsat) can be expressed as eqs 1 and 2, respectively21:

graphic file with name am5c01274_m001.jpg 1
graphic file with name am5c01274_m002.jpg 2

where W, L, Cox, and m indicate the channel width, channel length, gate oxide capacitance, and the slope of the Inline graphic–VG curve, respectively.

On the contrary, at VG, VD > 0 V, VGD is responsible for hole accumulation. VGD acts as VGS in conventional p-type MOSFETs, and VSD acts as VDS in conventional devices. The device operates in the saturation mode because −VSD > – (VGD – Vth,h) in this region. Therefore, the ID–VD relationship at VG, VD > 0 V can be expressed as eq 3, derived from eq 1:

graphic file with name am5c01274_m004.jpg 3

Therefore, ID quadratically increases with the increase of VD. Equation 3 leads to a linear relationship between Inline graphic and VD, as shown in eq 4:

graphic file with name am5c01274_m006.jpg 4

Figure 2g shows that the experimental Inline graphic–VD curve is well-fitted to eq 4, with the fitted curves indicated as straight lines. The linear Inline graphic–VD curves corroborate the VGD-induced hole conduction at VG, VD > 0 V in these SnO TFTs with Au S/D. μhsat can be derived from the slope of the linear Inline graphic–VD curve, which is ∼1.78 × 10–1 cm2/V s at the VG range of 3 to 15 V. This value is comparable to μhsat of 1.67 × 10–1 cm2/V s (±1.39 × 10–2 cm2/V s) extracted using eq 2 from the ID–VG curve in Figure 2a at VG, VD < 0 V. Based on the abnormal ID–VD properties and the new μhsat extraction method (eq 4) in unipolar SnO TFTs, ambipolar SnO TFTs were analyzed.

Figure 3 shows the electrical characteristics of SnO TFTs with ITO S/D electrodes. Figure 3a displays the ID–VG curve of the device measured at VD = −5 V, indicating ambipolar characteristics with hole-induced ID at negative VG and electron-induced ID at positive VG regions, respectively. As in Figure 2a, the gray curves indicate ID–VG curves measured from 10 devices. The ambipolar characteristics are due to the Ohmic contact between ITO and SnO for hole injection and decreased Schottky barrier height for electron injection compared to the one between Au and SnO. Figure 3b schematically illustrates the ITO/SnO/ITO band diagram. ITO exhibited a work function of 4.33 eV, extracted using UPS (See Supplementary Note 1 for details). As the ionization potential of SnO is smaller than the work function of ITO, Ohmic contact is formed for hole injection. Regarding electron injection, the smaller work function of ITO (4.33 eV) compared to Au (5.1 eV)22 lowered the Schottky barrier height, consequently enhancing the electron conduction at positive VG. Furthermore, Supplementary Figure S4 indicates a negligible interface reaction between the ITO electrode and the channel, which is crucial for achieving ambipolar conduction. Details are provided in Supplementary Note 3.

Figure 3.

Figure 3

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Electrical characteristics of SnO TFT with ITO S/D electrodes: (a) ID–VG curves measured at VD = −5 V. (b) Schematic band diagram of ITO/SnO/ITO configuration at VG = VD = 0 V. ID–VD curves measured at (c) VG = −15 to −3 V, (d) 9–33 V, and (e) 9–18 V. Schematic illustrations of carrier profiles in SnO channel at VG = 9–18 V and (f) small VD and (g) large VD. The blue and red regions indicate free electrons and holes, respectively. (h) Inline graphic–VD curves extracted from ID–VD curves measured at VG = 9 V ∼ 18 V. The straight lines indicate curves fitted to eq 4. (i) VG-dependent μhsat values extracted from Inline graphic–VD curves in Figure 3h. (j) Schematic illustration of carrier profile in SnO channel at VG = 21 V ∼ 33 V and VD = 0–15 V.

Figure 3c,d denotes the ID–VD curves at VG, VD < 0 V and VG, VD > 0 V, respectively. Figure 3c shows normal p-type output characteristics in the VG, VD < 0 V region. Figure 3d shows the ID–VD curves at VG, VD > 0 V, exhibiting anomalous behavior, more evidently shown in Figure 3e. It illustrates the ID–VD curves at VG, VD > 0 V, where VG ranges from 9 to 18 V, indicating that the device shows normal output characteristics at small VD but abruptly increases ID at large VD, transitioning into the abnormal state. The transition from normal to abnormal ID–VD state in this device is attributed to the coexisting electron and hole channels.

Schematic diagrams of SnO TFTs with ITO S/D electrodes, where VG of 9 to 18 V is applied with small and large positive VD, are illustrated in Figure 3f,g, respectively, to explain this transition. As the device is ambipolar, positive VGS induces fluent electron injection from the source electrode and channel inversion, displayed as blue regions in Figure 3f,g. Figure 3f demonstrates that electrons dominate the entire channel at small VD as VGD-induced hole accumulation is negligible. Consequently, normal ID–VD curves that show the transition from a linear to a saturating curve are observed in the low VD region in Figure 3e. However, as VD increases, abnormal ID–VD curves emerge, which can be understood from the following considerations.

At the large VD region, VGD becomes negative, which induces a hole-accumulated channel with holes injected from the drain electrode, indicated as red regions in Figure 3g. As VD further increases, more holes accumulate and become predominant over the VGS-induced electron inversion channel. Consequently, the saturated ID curves in Figure 3e at small VD transition to a quadratically increasing trend at large VD. Therefore, the competition between VGS-induced electron inversion and VGD-induced hole accumulation channels accounts for the transition from normal to abnormal ID–VD curves.

Supplementary Figure S7 presents the schematic band diagrams of ITO/SnO/ITO structure at the VG range of 9–18 V for varying VD. These diagrams corroborate the observed transition from normal to abnormal ID–VD behavior. Supplementary Figure S7a,b is the band diagram at VD = 0 V and small VD, respectively, which shows that EF is positioned near the CBM over the entire channel region, resulting in normal ID–VD curves by the electron conduction. In contrast, Supplementary Figure S7c depicts EF aligning closer to the VBM in the overall channel region at large VD, causing hole conduction to dominate and inducing abnormal ID–VD curves. This VG- and VD-dependent dominant carrier-type transition has significant implications for the operation of 3D NAND Flash devices. Details are illustrated in Supplementary Note 4.

μhsat was extracted from the abnormal ID–VD curves in ambipolar SnO TFT with ITO S/D electrodes. The device operates in the saturation region in the large VD region, where VGD-induced hole conduction dominates over VGS-induced electron conduction, as −VSD > – (VGD – Vth,h) in this region (Vth,h = −2.2 V). Supplementary Figure S2b shows the gm–VG curve for Vth,h extraction, with the linearly fitted curve indicated as a straight line. Figure 3h indicates that Inline graphic–VD curves exhibit a linear relationship that follows eq 4 at large VD. The fitted lines are exhibited as straight lines in Figure 3h. μhsat was extracted from the slope of the fitted linear curves following eq 4. The μhsat values of SnO TFTs with ITO S/D electrodes extracted at VG, VD > 0 V ranged from 7.65 × 10–4 to 3.27 × 10–3 cm2/V s. These values are significantly lower than μhsat of 1.93 × 10–1 cm2/V s (±3.87 × 10–2 cm2/V s) extracted at VG, VD < 0 V from the ID–VG curves in Figure 3a.

This deterioration in μhsat at VG, VD > 0 V is attributed to e–h recombination between VGS-induced electrons and VGD-induced holes. The presence of an electron channel decreases hole concentration by inducing e–h recombination. As SnO TFTs operate under the multiple carrier trapping conduction mechanism at room temperature,23 μhsat decreases with decreasing carrier concentration. Thus, μhsat at VG, VD > 0 V decreased due to the e–h recombination phenomenon, decreasing hole concentration. In contrast, the larger μhsat extracted at VG, VD < 0 V resulted from the absence of VGS-induced inversion electrons and consequently e–h recombination.

Moreover, Figure 3i indicates that the extracted μhsat values from abnormal ID–VD curves decrease with increasing VG at VG, VD > 0 V. This negative correlation is due to the enhanced e–h recombination process as the concentration of VGS-induced electrons increases with increasing VG, further decreasing the VGD-induced hole concentration. Consequently, μhsat decreases from 3.27 × 10–3 cm2/V s at VG = 9 V to 7.65 × 10–4 cm2/V s at VG = 18 V.

Figure 3d also depicts normal ID–VD characteristics across all measured VD in the VG range of 21–33 V. This indicates that the VGS-induced electron inversion channel dominates over the VGD-induced hole accumulation channel in this VG region. Figure 3j schematically illustrates the carrier profile when VG is in the range of 21–33 V. Large VGS induces electron inversion in the channel and injection from the source electrode, indicated as blue regions, while relatively lower VGD does not accumulate holes in the measured VD range. However, if VD increases to values where the VGD-induced hole accumulation channel dominates over the VGS-induced electron channel, ID–VD curves will transition from normal to abnormal curves with the increase of VD.

The electron saturation mobility (μesat) was also extracted from the abnormal ID–VD curves where the VGD-induced electron inversion channel dominates over the VGS-induced hole accumulation channel. The black curve in Figure 4a illustrates the transitioning ID–VD curve at VG = 0 V. Normal ID–VD curve at small −VD, in which VD ranges from −9 to 0 V, transitions into abnormal ID–VD curve at large −VD, in which VD is smaller than −9 V. Schematic diagrams in Figure 4b,c which depict the carrier profiles in the SnO channel at small and large −VD, respectively, at VG = 0 V, clarify the origin of this transition. Comparable to the ID–VD curves in Figure 3c, the normal ID–VD curve corroborates hole conduction at small −VD at VG = 0 V. Thus, VGS (0 V)-induced hole accumulation channel dominates over VGD-induced electron inversion channel in the small −VD region. Therefore, the normal ID–VD curve is measured at small −VD. Unlike the normal ID–VD curves measured at VG of −15 to −3 V in Figure 3c, the one measured at VG = 0 V exhibits decaying ID with the increase of −VD in the saturation region. This behavior is attributed to the SnO channel depletion effect at the drain and channel overlap region as the channel is pinched off at the saturation region.24 As the device is in the subthreshold region at VG = 0 V, the depletion effect severely degrades the hole conduction characteristics, decreasing ID with increasing −VD.

Figure 4.

Figure 4

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Analysis of the electron conduction characteristics of SnO TFT with ITO S/D electrodes: (a) ID–VD curves measured at VG = 0–3 V at negative VD. Schematic illustrations of carrier profiles in SnO channel at VG = 0 V and (b) small −VD (−9 to 0 V) and (c) large −VD (< −9 V). The blue and red regions indicate free electrons and holes, respectively. (d) Inline graphic–VD curves extracted from ID–VD curves measured at VG = 0–3 V. The straight lines indicate curves fitted to eq 6. (e) VG-dependent μesat values extracted from Inline graphic–VD curves in Figure 4d. (f) ID–VG curves measured at VD = 10 V.

Figure 4c shows that at large −VD, VGD-induced electron inversion channel is predominant over VGS (0 V)-induced hole accumulation channel. This transition of the dominant carrier type, from holes at small −VD to electrons at large −VD, triggers the shift from (saturating) normal to (abruptly increasing) abnormal ID–VD curve. As −VD exceeds VGD–Vth,e at large −VD, the device operates in the saturation region and the ID–VD relationship follows eq 5:

graphic file with name am5c01274_m011.jpg 5

Consequently, ID quadratically increases with the increase of −VD in the large −VD region.

In contrast to the ID–VD characteristics measured at VG = 0 V, VGS-induced hole accumulation is negligible at VG of 1–3 V, as observed in the ID–VG curves (Figure 3a). Therefore, Figure 4a exhibits abnormal ID–VD curves in this VG region in all VD values.

μesat can be extracted from the abnormal ID–VD curves in Figure 4a, where VGD-induced electron inversion dominates VGS-induced hole accumulation. Derived from eq 5, Inline graphic exhibits a linear relationship with VD, as shown in eq 6:

graphic file with name am5c01274_m013.jpg 6

The linear curves in Figure 4d indicate that the Inline graphic–VD curves are well-fitted to eq 6. According to eq 6, μesat can be extracted from the slope of the linear Inline graphic–VD curve. Figure 4e shows that the extracted μesat is 4.82 × 10–4 cm2/V s at VG = 0 V, which is 4.00 times smaller than the value of 1.93 × 10–3 cm2/V s obtained from the ID–VG curves at VG, VD > 0 V (Figure 4f) using eqs 7 and 8(21):

graphic file with name am5c01274_m016.jpg 7
graphic file with name am5c01274_m017.jpg 8

This deterioration in μesat extracted from the slope of the Inline graphic–VD curve at VG = 0 V originates from the e–h recombination phenomena. The e–h recombination between VGS-induced holes and VGD-induced electrons decreases the electron concentration from the VGD-induced electron inversion channel. Consequently, significantly lower μesat is extracted from the Inline graphic–VD curve at VG = 0 V compared to μesat extracted from the ID–VG curves at VG, VD > 0 V (Figure 4f), where the e–h recombination process is not involved.

On the other hand, μesat values extracted from the Inline graphic–VD curves (Figure 4d) at VG of 1–3 V range from 1.72 × 10–3 to 1.94 × 10–3 cm2/V s, which are comparable to 1.93 × 10–3 cm2/V s obtained from the ID–VG curves at VG, VD > 0 V (Figure 4f). As VGS-induced hole accumulation is negligible at VG of 1–3 V and VD < 0 V region, e–h recombination minimally affects the conduction of inversion electrons. The negligible e–h recombination phenomenon corroborates the comparable μesat values extracted from the Inline graphic–VD curves at VG of 1 to 3 V and VD < 0 V, as illustrated in Figure 4e, and ID–VG curves at VG, VD > 0 V (Figure 4f).

μesat neglecting the e–h recombination effect can also be extracted from the normal ID–VD curves in Figure 3d,e using eq 7. However, the mobility values extracted from ID–VG and normal ID–VD curves can be different due to capacitance variation with VG.25,26 Normal ID–VD curves are not influenced by the device capacitance variation with VG, as VG is fixed during the ID–VD sweep. On the contrary, ID–VG curves incorporate the VG-dependent capacitance variance as VG is swept. Therefore, comparing μesat values extracted from the ID–VG and normal ID–VD curves could be inaccurate. On the other hand, μesat values extracted from abnormal ID–VD curves incorporate the capacitance variation with VG, validating their similarity with the values extracted from ID–VG curves. In abnormal ID–VD curves, VGD acts as VGS in conventional MOSFETs. As VGD changes with varying VD during the ID–VD sweep, capacitance varies with VGD, analogous to the capacitance variation with VGS in the ID–VG sweep.

μesat was measured to be approximately 100 times smaller than μhsat in SnO TFTs with ITO S/D electrodes. Table I summarizes the mobility values extracted from various extraction methods. This large imbalance is attributed to the higher subgap density of states (DOS) and the larger contact resistance (RC) between SnO and ITO S/D electrodes in the electron conduction region compared to the hole conduction region.13 The influence of RC and subgap DOS-induced channel resistance (Rch) was confirmed using the transmission line method (TLM). Figure 5a,b shows the total resistance (Rtot) dependence on L in the hole and electron conduction regions, respectively, obtained from the TLM patterns. RC and Rch were calculated using eq 9(27),(28):

graphic file with name am5c01274_m022.jpg 9

where the y-intercept corresponds to RC and the slope represents Rch. RC and Rch of 2 and 1.23 MΩ were extracted in the hole conduction region. On the other hand, in the electron conduction region, Rc and Rch were significantly larger, measured at 0.105 and 0.737 GΩ, respectively. This discrepancy in RC for hole and electron conduction is due to the Ohmic contact for hole injection and the Schottky contact for electron injection. The smaller ionization potential of SnO compared to the work function of ITO (4.33 eV) leads to an Ohmic contact with a small RC for hole injection. In contrast, the smaller electron affinity of SnO compared to the work function of ITO (4.33 eV) leads to a Schottky contact with a large RC for electron injection.

Table I. Mobility of SnO TFTs Extracted from Various Extraction Methodsa.

S/D electrodes Au
 ITO
carrier hole electron hole electron
μsat (ID–VG) 1.67 × 10–1 (±1.39 × 10–2)   1.93 × 10–1 (±3.87 × 10–2) 1.93 × 10–3 (±4.92 × 10–4)
μsat (Abnormal ID–VD) VG 3–15 V 1.78 × 10–1 VG 9 V 3.27 × 10–3 0 V 4.82 × 10–4
12 V 2.11 × 10–3 1 V 1.94 × 10–3
15 V 1.71 × 10–3 2 V 1.72 × 10–3
18 V 7.65 × 10–4 3 V 1.72 × 10–3
μ0 (YFM) 2.64 × 10–1 2.76 × 10–1 2.93 × 10–3
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a

Unit of mobility: cm2/V s.

Figure 5.

Figure 5

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Rtot–L plot measured using TLM patterns in the (a) hole and (b) electron-conduction region. ID/gm0.5–VG curves in the (c) hole and (d) electron conduction region. The straight lines indicate the curves fitted to eq 10.

The discrepancy in Rch in the hole and electron conduction region can be attributed to the higher subgap DOS near the CBM than in the VBM.13 The high subgap DOS near CBM severely deteriorates the electron conduction characteristics. The larger Rch for electron conduction compared to hole conduction was further verified through intrinsic mobility (μ0) extracted using the Y-function method (YFM).29,30 YFM extracts μ0 from the slope of the ID/gm0.5–VG curve, based on eq 10:

graphic file with name am5c01274_m023.jpg 10

Since YFM excludes the contribution of RC, it enables the evaluation of the intrinsic electrical characteristics of the channel. Figure 5c,d shows the ID/gm0.5–VG curves in the hole and electron conduction regions, with the straight lines indicating the fitted curves to eq 10. It should be noted that the y-axis in Figure 5c has a maximum of 10–2 A0.5 V0.5, while that in Figure 5d has a maximum of 10–3 A0.5 V0.5. μ0 in the electron conduction (μ0,e) region was 2.93 × 10–3 cm2/V s, which is significantly lower than μ0 of 2.76 × 10–1 cm2/V s in the hole conduction region (μ0,h). This substantial decrease in μ0 in the electron conduction region corroborates the larger Rch in this region. Together with the larger RC, larger Rch significantly decreases the mobility in the electron conduction region compared to the hole conduction region.

VG- and VD-Dependent Carrier-Trapping Analysis

The electron and hole coexisting channel significantly affects the carrier-trapping characteristics. Therefore, VG- and VD-dependent carrier-trapping properties were analyzed by bias-stress stability tests. Carriers are trapped inside the gate insulator during stress, affecting the measured ID–VG curves after stress.

Figure 6a–c exhibits the stress time-dependent ID–VG curves following positive bias stress (PBS) under different drain voltages during stress (VD, stress): 0, 15, and 30 V, respectively, with the gate voltage during stress (VG, stress) fixed at 15 V. Figure 6a shows a positive Vth,h and Vth,e shift (ΔVth,h and ΔVth,e) after PBS after VG, stress and VD, stress of 15 and 0 V, respectively, which is in the voltage regime where electron inversion channel is formed in SnO. Also, the ΔVth,h and ΔVth,e – stress time plot, indicated by black square data points in Figure 6d,e, fit well with the stretched exponential equation, with the fitted curves as black dashed lines. The stretched exponential equation follows eq 11:

graphic file with name am5c01274_m024.jpg 11

where Inline graphic, τ, and β are the ΔVth,h(e) after infinite time, characteristic trapping time constant, and the stretched-exponential exponent in the hole (electron) conduction region, respectively. The positive ΔVth,h and ΔVth,e after PBS, which follows eq 11, corroborates that solely electrons are trapped in the gate insulator under VG, stress of 15 V and VD, stress of 0 V.31,32

Figure 6.

Figure 6

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Analysis of bias-stress stability test results of SnO TFT with ITO S/D electrodes: ID–VG curves measured at VD = −5 V after PBS of VG, stress = 15 V and (a) VD, stress = 0 V, (b) VD, stress = 15 V, and (c) VD, stress = 30 V. (d) ΔVth,h and (e) ΔVth,e of ID–VG curves after PBS compared to pristine devices. Error bars indicate the standard deviation extracted from 10 devices. (f) ID–VG curves measured at VD = −5 V after negative bias stress (NBS) of VG, stress = −15 V and VD, stress = 0 V. (g) ΔVth,h and ΔVth,e of ID–VG curves after NBS compared to pristine devices. Error bars indicate the standard deviation extracted from 10 devices. The dashed lines indicate the curves fitted to eq 11.

Figure 6b indicates the ID–VG curves after PBS with VG, stress of 15 V and VD, stress of 15 V. The red circle data points in Figure 6d,e represent the ΔVth,h and ΔVth,e–stress time plot, where smaller ΔVth,h and ΔVth,e are observed compared to when VD, stress = 0 V. This decrease is due to the coexisting electron and hole channels during stress. VGS (15 V)-induced electrons undergo e–h recombination with VGD (0 V)-induced holes during stress, decreasing the concentration of electrons trapped in the gate insulator. In addition, ΔVth,h and ΔVth,e–stress time plots do not fit eq 11, indicating that the trapping process is more complex due to the coexistence of both electrons and holes at VG, stress of 15 V and VD, stress of 15 V.

Figure 6c demonstrates the ID–VG curves when VD, stress is increased to 30 V, while VG, stress remains at 15 V. The blue triangle data points in Figure 6d,e exhibit negligible ΔVth,h and ΔVth,e, which is due to the strong e–h recombination between VGS, stress (15 V)-induced electrons and VGD, stress (−15 V)-induced holes. Holes are the majority carrier in this stress condition. The VGS, stress (15 V)-induced electrons significantly decrease the concentration of VGD, stress (−15 V)-induced holes being trapped in the gate insulator. In addition, the device showed an increase in subthreshold swing with increasing stress time. Supplementary Note 5 explains the possible origins of this behavior.

To investigate the hole-trapping properties without the disturbance of electrons, VG, stress of −15 V was applied with the S/D electrodes grounded. The same bias of VGD, stress (−15 V) was applied as in Figure 6c. However, unlike the case in Figure 6c, inversion electrons are negligible as VGS, stress of −15 V is applied, minimizing the influence of e–h recombination. The ID–VG curves in Figure 6f and the black square and red circle data points in Figure 6g show that the device exhibits negative ΔVth,h and ΔVth,e under this stress condition. In addition, the black and red dashed lines in Figure 6g indicate that the ΔVth,h and ΔVth,e–stress time plots follow eq 11. This result suggests that holes are trapped inside the gate insulator. The larger |ΔVth,h| compared to |ΔVth,e| is due to the higher concentration of holes at VG, stress = −15 V and VD, stress = 0 V compared to the concentration of electrons at VG, stress = 15 V and VD, stress = 0 V.

Conclusions

This study analyzes the ambipolar conduction characteristics of SnO TFTs achieved by adopting ITO S/D electrodes. The lower work function of ITO compared to Au reduced the Schottky barrier height for electron injection, enhancing electron conduction. ID–VD curves of ambipolar ITO S/D SnO TFTs exhibited a normal-to-abnormal transition at VG, VD > 0 V, attributed to coexisting electron and hole channels. This coexistence induces the e–h recombination effect. A method to extract μhsat and μesat while incorporating the e–h recombination effect was proposed, revealing that e–h recombination deteriorates the conduction performance. μhsat when e–h recombination occurred ranged from 7.65 × 10–4 to 3.27 × 10–3 cm2/V s, which was ∼59 to ∼252 times smaller than that of 1.93 × 10–1 cm2/V s extracted in the voltage region in which e–h recombination did not occur. μesat when e–h recombination occurred was 4.82 × 10–4 cm2/V s, which was ∼4.00 times smaller than the value of 1.93 × 10–3 cm2/V s extracted in the voltage region in which e–h recombination did not occur.

μesat was measured to be ∼100 times smaller than μhsat, attributed to the larger Schottky barrier for electron injection and larger subgap DOS in the electron conduction region. The larger RC of 105.1 MΩ corroborated the higher electron injection barrier compared to 2 MΩ for hole injection. In addition, the larger subgap DOS in the electron conduction region was corroborated by the larger Rch and μ0 of 73.7 MΩ and 2.93 × 10–3 cm2/V s in the electron conduction region compared to Rch and μ0 of 1.23 MΩ and 2.76 × 10–1 cm2/V s in the hole conduction region.

In addition, bias-stress stability tests were conducted to analyze the carrier-trapping properties when electrons and holes participate in the trapping process. When carriers were solely trapped during stress, the ΔVth-stress time plot followed the stretched exponential equation. On the contrary, when both the electrons and holes participated in trapping, |ΔVth| significantly decreased, and ΔVth–stress time plot deviated from the stretched exponential equation. This finding indicates that the electron and hole coexisting channel not only affected μhsat but also the carrier trapping characteristics during voltage stress.

Experimental Section

To fabricate the SnO TFTs, a 30-nm-thick SiO2 gate insulator and a 15-nm-thick Al2O3 interfacial layer were deposited onto a heavily doped p++-Si wafer, which serves as the bottom gate of the TFT. The SiO2 and Al2O3 layers were grown by thermal oxidation and ALD, respectively. A 7-nm-thick SnO channel layer was then deposited on the Al2O3 interfacial layer via ALD with (bis(1-dimethylamino-2-methyl-2propoxy)tin(II) (Sn(dmamp)2) as an Sn precursor and H2O as an oxidizing agent at a deposition temperature of 200 °C. Subsequently, Au and ITO were deposited using the direct current (DC) sputtering system and patterned as S/D electrodes. Au electrodes were deposited with a deposition power of 400 W in an argon (Ar) atmosphere of 40 sccm. ITO electrodes were deposited with a deposition power of 380 W in an Ar atmosphere of 35 sccm. The electrodes were patterned using the lift-off method. Finally, a passivation layer of Al2O3 was deposited using ALD with trimethyl aluminum and H2O as aluminum and oxygen sources, respectively, at a deposition temperature of 150 °C followed by annealing at 250 °C in a nitrogen ambient.7 The channel width and length of the TFT were 20 and 5 μm, respectively.

The thickness of all the films was measured using spectroscopic ellipsometry (SE, M-2000, J.A. Woollam). The surface morphology of the films was examined using SEM (Hitachi, S-4800). The crystallographic properties of the films were characterized using GAXRD (X’Pert Pro, PANalytical) and aberration-corrected scanning transmission electron microscopy (Cs-STEM, JEM-ARM200F). Cs-STEM samples were prepared by a focused ion beam (FIB, Helios 650, FEI). The electrical structure of the films was measured using UPS (ULVAC-PHI, VersaProbe III). Electrical characteristics of the TFTs were analyzed using a probe station (HP 4155B).

Acknowledgments

This work was supported by the National Research Foundation of Korea (Grant No. 2020R1A3B2079882) and Samsung Electronics Co. Ltd. TEM analysis results were obtained using the instrument installed at the Research Institute of Advanced Materials (RIAM) at Seoul National University.

Supporting Information Available

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsami.5c01274.

  • Extraction of the work functions of SnO and ITO; methods to overcome gate leakage current; requirements of S/D electrodes for achieving ambipolar conduction in SnO TFTs; implications of VG- and VD-dependent carrier-type transition in SnO TFTs to the operation of 3D NAND Flash; S.S. increase after VG, stress = 15 V and VD, stress = 30 V; threshold voltage extraction method; VD-dependent schematic band diagrams of ITO S/D SnO TFTs at positive VG (PDF)

The authors declare no competing financial interest.

Supplementary Material

am5c01274_si_001.pdf (606KB, pdf)

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Supplementary Materials

am5c01274_si_001.pdf (606KB, pdf)

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