Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Abstract

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal–Oxide–Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74  ± 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Introduction

Fractional-Order Elements (FOE) also referred to as Fractors or Constant Phase Elements (CPE) are two-terminal passive electronic devices whose impedance (Z) is given by Z = 1/Y = 1/(s^αF). In this expression, the variable s = jω represents the complex frequency, ω is the angular frequency and the constant F is the fractance. The real number α is the order of the element and is typically in the range from − 1 to + 1. It is apparent that FOEs represent a generalization of the classical circuit elements (e.g. resistors, capacitors and inductors). Each of the traditional elements are special cases of the FOE when α = 0 (resistor), + 1 (capacitor) and − 1 (inductor). Since this article focuses on the capacitive FOE variant (0 < α < 1), the admittance Y = s^αF will be used for its description rather than impedance. In this case, both order α and admittance phase angle are positive numbers which is more convenient. The FOE is also referred to as CPE since its admittance phase is constant, independent of frequency, and is determined by απ/2 in radians or 90α in degrees.

Summary of FOE implementations

A recent survey on current approaches to design single- or multi-component FOEs proposed by different research groups can be found in¹. In this survey, the authors note that single-component FOEs are the class of devices most actively researched. These devices are mostly based on electrochemical principles utilizing various chemical substances, for example porous polymer materials², nanocomposites of conductive particles in a dielectric^3–5 or layered structures in a dielectric^6,7. Design of these devices is typically achieved through selection of suitable materials and then empirical study of their arrangement using a particular fabrication technology. At this time, there are no automated design tools or algorithms based on circuit theory to support their design. Limitations of these devices are their small range of fractional orders, narrow frequency band, and commercial unavailability¹.

In response to the limited availability of single-component FOEs, devices to emulate their desired characteristics are realized using multicomponent Integer-Order (IO) passive or active circuits. This method is based on the approximation of the term s^α in the impedance function by an IO rational function, see e.g.⁸ and⁹. This function is then implemented using topologies such as the Foster or Cauer passive ladder networks with resistors and standard capacitors (or inductors in case of inductive FOEs)¹⁰. However, the values of these elements must be precise to obtain the required accuracy of approximation¹⁰. Furthermore, when α values close to 0 or 1 are required, the ratio of the resistances and capacitances is very high¹¹. This makes the implementation by an integrated circuit technology very difficult or even impossible. Another limitation is that passive emulation structures cannot be tuned electronically. These last two drawbacks can be eliminated by active FOE emulators, which are usually based on state-variable multi-feedback structures with transfer function equal to an IO rational function approximating the required FOE impedance function¹². These circuits offer electronic adjustability resulting from the controlled active elements and are suitable for integrated implementation. These emulation techniques are still limited in their operational (and tunable) frequency band and have higher circuit complexity that increases with increasing approximation accuracy.

The motivation for further research to advance methods for implementing FOE lies in the fact that these elements constitute the main part of circuits and systems of fractional order. Fractional-order circuits and systems are an actively evolving multidisciplinary area giving rise to many new potential applications^13,14. The increased interest in these systems stems from the presence of the fractional order which represents another degree of freedom to design/tune behavior of a function block. This further generalizes characteristics compared to standard IO systems. This is beneficial in many applications e.g. for dynamic shaping of spectral character in biomedical signal processing^15,16, modeling of electrical parameters of biological and real-world materials^17–19, communications²⁰, control and regulation²¹, and modeling of supercapacitors²² and lithium-ion batteries²³ (to name a few).

FOE based on distributed RC layers

A lossy transmission line has been reported to exhibit fractional-order behaviour²⁴. The input admittance of an infinitely long line at any frequency has an order of α = 0.5 and shows a phase angle of 45 degrees. These findings were applied to the design of FOE based on layered structures with distributed resistive and capacitive properties. According to²⁵, a configuration of layers called R-C-NR (resistive-capacitive-resistive with N-times higher resistance) could provide an admittance phase between 5 and 85 degrees with a variance of ±1 degree over an average range of two frequency decades. Even wider frequency ranges can be obtained for higher phase values (above about 45 degrees) by employing a different layer configuration, namely C-R-NC (capacitive-resistive-capacitive with N-times higher capacitance), as demonstrated in²⁶. The FOEs in these works are composed of several individual distributed resistive-capacitive (RC) structures with different lengths and specific interconnections between them. The lengths and configurations are determined using a Genetic Algorithm (GA) optimization approach. Due to the specific design process, these structures are suitable for implementation by thick- or thin-film technology²⁷.

Unfortunately, these film technologies are not suitable for the production of integrated circuits and the FOEs produced using them are physically large (in comparison to other fabrication technologies). To reduce their size and also improve their manufacturability, FOE implementations using MOS (Metal Oxide Semiconductor) are being investigated. This production technology is widely adopted for integrated circuits and is able to realize very small device sizes. A distributed RC structure based on a resistive p-type MOS capacitor derived from PMOS transistor has been previously demonstrated²⁸. This device operates as a single long transmission line in the form R-C-0 (resistive-capacitive-perfectly conductive), which demonstrates characteristics of an FOE with α = 0.5 in the frequency range from approximately 70 kHz to 20 MHz, or 2.5 decades. The resistive layer is formed by an unsalicided polysilicon gate, which has a relatively low sheet resistance (approximately 240 Ω). Hence, the structure needs to be very long and narrow to provide sufficiently high resistance to be usable at low frequencies. Therefore, to achieve a sufficient length and due to the limitations of the dimensions, the MOS device must be divided into multiple fingers, i.e. shorter segments that are connected in series and placed side by side, between which parasitic capacitances and resistances may appear. An adverse effect of these parasitics are deviations of the FOE characteristics from their ideal values at high frequencies.

In²⁹, an alternative R-C-0 layer arrangement was demonstrated for creating a MOS-based FOE with α = 0.5. Instead of a gate, the resistive layer is represented by a conductive channel between source and drain. This realizes higher sheet resistance, usually several tens of kiloohms. The layer’s length thus can be significantly reduced without the need for fingers or with a much smaller number of them.

In this article we present a novel method to design FOEs with any admittance phase between 0 and 90 degrees (order α between 0 and 1) utilizing MOS transistors as layered structures with distributed resistive-capacitive properties. The novelty of this approach is that these FOEs are compatible with current technologies for the production of MOS integrated circuits. In contrast to²⁸ and²⁹, the MOS transistor is not considered as only an R-C-0 structure. Resistive-capacitive properties of all parts of the MOS transistor are considered and modeled during the FOE synthesis. One resistive layer is formed by the gate electrode contacted at its ends close to the source and drain electrodes. The second resistive layer is realized by the channel between the source and drain. A total of three distributed capacitive layers are considered, namely between gate and channel, channel and bulk, and between gate and bulk. In addition, other lumped parasitic resistances and capacitances present in the structure of the MOS transistor are included in the design. A native n-channel MOS transistor (having nearly zero threshold voltage) in TSMC 65 nm technology is chosen for this design due to the existence of the channel without significant gate bias voltage.

As the FOEs proposed in this work are implemented completely on a chip, these elements are suitable for utilization in so-called MOS-only circuits^30,31. In these circuits all elements are implemented using MOS structures. This approach is based on the ability of MOSFETs operating in the saturation region to be used as voltage-controlled current sources. MOS transistors are also employed as active elements in so-called MOSFET-C circuits, especially frequency filters^32,33. The MOS-based FOE described in this article can be used in fractional-order variants of MOS-only and MOSFET-C electronic circuits as a fractional capacitor, replacing the standard capacitor.

A summary of FOE implementations for comparison to this work is given in Table 1. The table compares the solutions most relevant to the design in this work with respect to the range of phase values, frequency range, accuracy and type of fabrication. The last row shows the solution presented in this work, specifically for the 74-degree admittance phase selected for detailed analysis in section “Selected FOE with 74-degree phase”. It is important to note though that for the general overview of achievable parameters, refer to section “Overall results of synthesis”. Comparing these works, the proposed FOE solution in this work outperforms existing designs in terms of range of realizable admittance phase (i.e. order), frequency bandwidth, and phase tolerance.

Table 1.

Comparison of selected FOE realizations.

Refs.	Admittance phase (degrees)	Frequency range (Hz)	Bandwidth (decades)	Phase tolerance (degrees)	Type of manufacture	Simulated	Measured
7	65 to 83	150 k to 10 M	2	± 3	P(VDF)-based polymers (chemical substance)	No	Yes
3	31	20 to 2 M	5	± 2	polymer-CNT composite (chemical substance)	No	Yes
34	58 to 80	100 to 10 M	5	± 4	MoS2 (chemical substance)	No	Yes
12	18, 45, 72	20 to 800	1.5	± 2	0.35μ CMOS (integrated circuit)	Yes	No
35	27, 45, 63	30 to 300	1	± 5	0.35μ CMOS (integrated circuit)	No	Yes
36	45 to 85	110 to 20 M	< 2	± 2	MWCNT (chemical substance)	No	Yes
37	30, 45, 60	5 k to 500 k	2	± 5	OTA-C MOSFET (integrated circuit)	Yes	No
38	74	100 to 1 M	4	± 5	CB-FOE (chemical substance)	Yes	Yes
28	45	70 k to 20 M	2.5	± 1	R-PMOScap (integrated circuit)	Yes	Yes
39	32	1 to 100 k	5	± 3	(chemical substance)	No	Yes
25	37.5, generally 5 to 85	8 k to 3 M	2.6	± 1.5	Thick-film distributed R-C-NR	Yes	Yes
26	45 to 85	1 k to 10 M	4	± 2	Thick-film distributed C-R-NC	Yes	No
This work	74, generally 5 to 85	1.5 k to 11 M	3.8	± 1	Distributed MOS (integrated circuit)	Yes	Planned

List of previously unexplained abbreviations: P(VDF)—Polyvinylidene Fluoride-Based Polymers, CNT—Carbon Nanotube, MoS2—Molybdenum Disulfide-Ferroelectric Polymer Composite, CMOS—Complementary Metal–Oxide–Semiconductor, MWCNT—Multi-Walled Carbon Nanotubes, OTA-C MOSFET—Operational Transconductance Amplifier—Capacitor Metal Oxide Semiconductor Field Effect Transistor, CB-FOE—Carbon Black Fractional-Order Element, R-PMOScap—Resistive P-Type MOS Capacitor.

The article is structured as follows. Section “Method of FOE design” discusses the FOE design method including the MOS transistor model with its admittance matrix, interconnections and parameters of partial MOS structures, computing the input admittance and fitness score of a solution, and also the synthesis algorithm and computer program to support the design process. Section “Results” presents and analyzes the results of the proposed design technique and describes in detail a selected solution with a phase of 74 ± 1 degrees. Section “Conclusions” summarizes the findings described in the article.

Method of FOE design

This section describes the synthesis method to design a FOE composed of individual MOS structures. This method uses a MOS transistor model with distributed parameters and its admittance matrix description to calculate the input admittance of the proposed FOE using a modified nodal analysis method. The generation of the FOE topology and physical parameters of the individual MOS structures is realized using a genetic algorithm. This metaheuristic approach was chosen due to the large search space (resulting from the total number of parameters and their wide range/type of values) for the FOE design. For example, some parameters express the connection scheme of particular MOS transistors forming the FOE and others are continuous values representing physical parameters such as dimensions of the transistors.

MOS transistor model with distributed parameters and its admittance matrix

To calculate the input admittance of the FOE during its synthesis, a model of the MOS transistor with distributed parameters and its admittance matrix are required. A model of the MOS transistor operating in triode region from the point of view of the layered RC structure with distributed parameters is shown in Fig. 1.

Fig. 1.

MOS transistor as a layered RC structure with distributed parameters.

The model contains a gate (G) resistance R_g distributed along the transistor length (L) and divided into m partial lumped resistors R_g1 to R_gm, where m → ∞. Similarly, the distributed channel resistance R_c and capacitances between gate and channel C_gc, channel and bulk (B) C_cb and gate and bulk C_gb are represented. The MOS transistor was identified to have parasitic resistances and capacitances which are modeled as lumped elements attached to the ends of the distributed structure as in Fig. 1. It is assumed that the source (S) and drain (D) are symmetric for these parasitics. These are the source and drain resistances R_sd, the gate to source/drain overlap capacitances C_gsd and the source/drain to bulk depletion capacitances C_sdb. The bulk is treated as a perfect conductor in the model. While a perfect conductor is not possible for a physical design, it is very closely approximated by contacting the bulk to metal shunting on all sides of the transistor.

The structure from Fig. 1 is redrawn to the form in Fig. 2 containing a uniform distributed RC network with parameters R_g, R_c, C_gc, C_cb, C_gb expressing the total resistances and capacitances of the layers, and the corresponding parasitic elements.

Fig. 2.

MOS transistor as a uniform distributed RC network with parasitics.

Based on the formulas for a distributed parameter network⁴⁰ and considering the node numbering in Fig. 2, the admittance matrix for this structure is given by

1

Note that these relations only apply to the distributed structure with the nodes 0 to 4 in Fig. 2 i. e. when parasitic lumped resistors and capacitors are omitted. The matrix elements previously reported by⁴⁰ are

2a

2b

2c

2d

2e

2f

2g

2h

2i

2j

2k

3a

3b

3c

3d

3e

3f

3g

In the above Eqs. (3a–3g), the resistances with a zero at the end of their subscript (e.g. R_c0, R_g0 etc.) are sheet resistances of the respective layer. For example, R_g0 is the sheet resistance of the gate with units of ohms. Similarly, capacitances with a zero at the end of the subscript (e.g. C_cb0, C_gc0) have values per square meter. For example, C_gc0 is the capacitance between the gate and channel in farads per square meter. The quantity L is the physical length of the structure in meters, and W is the physical width of the structure in meters.

The lumped parasitic elements attached to the ends of the distributed structure in Fig. 2 modify the admittance matrix (1). Denoting the new admittance matrix elements with a prime yields

4a

4b

The quantities C_gsd0 and C_sdb0 are the values per unity width of the gate to source/drain overlap capacitance and the source/drain to bulk depletion capacitance, respectively. It holds, for example, C_gsd = C_gsd0W. The new diagonal elements Y′₁₁, Y′₂₂, Y′₃₃, Y′₄₄, and Y′₀₀ are given by the negative sum of the off-diagonal elements in their respective rows as before.

The addition of parasitic resistances R_sd causes the number of model nodes to increase from five to seven. The new admittance matrix expands to 7 × 7 as follows and its last two rows and columns pertain to the added nodes 5 and 6, shown in Fig. 2.

5

It holds that R_sd = 1/G_sd = R_sd0/W, where R_sd0 is the unity width source and drain resistance. Since nodes 3 and 4 become internal and cannot be connected externally, it is advisable to omit them from the admittance description. This can be done by Kron reduction⁴¹. The elements of the reduced admittance matrix achieved eliminating the node e are computed using the formula

6

where s, t are integers from 1 to the size of the matrix being eliminated except e, since row e and column e are to be eliminated. Note that s, t, e are coordinates of the elements in the original matrix before the elimination. Since two nodes (3 and 4) need to be eliminated, the Kron reduction using (6) is performed twice. In the resulting admittance matrix, the rows and columns correspond to the nodes 1, 2, 0, 5, 6 as marked in Fig. 2.

Parameters of the MOS model from Fig. 2 for the selected native n-channel MOS transistor in TSMC 65 nm technology were extracted from Process Design Kit (PDK) device model using Cadence Spectre simulator. For this purpose, a single MOS device was simulated while in the deep triode region (V_ds = 10 mV) with zero gate bias voltage (V_gs = 0 V). The DC Operating Point (DCOP) parameters of the device as listed in Table 2 were recorded from the simulation results and used to derive the values of the distributed MOS model parameters.

Table 2.

Parameters of distributed MOS model.

Parameter of distributed MOS model	DCOP annotated lumped parameter
R g0	Not modeled
R c0	ron
C gc0	cgs + cgd
C cb0	csb + cdb
C gb0	cgb
C gsd0	covlgs = covlgd
C sdb0	cjs = cjd
R sd0	rseff = rdeff

It should be emphasized that the DCOP parameters defined by the BSIM standard⁴² consider the transistor as a lumped device. For this reason, it is not possible to use Cadence to simulate the behavior of the distributed MOS structure as a FOE. Simulations to verify the function of the synthesized FOE must therefore be performed with a model of the transistor, in which the distributed parameters are replaced by a network of lumped resistors and capacitors, as illustrated in Fig. 1.

Coding interconnections and parameters of MOS structures

The synthesis method assumes that the designed FOE will consist of n suitably interconnected MOS structures as shown in Fig. 3. Since the FOE synthesis utilizes a GA, the individual connections and parameters of MOS structures are represented by chromosomes. The connection between adjacent structures as well as the connection of the outer terminals of the first and last structure are encoded in the CCh chromosome (Connection Chromosome). It consists of the matrices of connection factors E_k, A_k, B, where k (in the range from 1 to n–1) indicates that the matrix refers to the interface of the k-th and (k + 1)-th structure. The matrix E_k codes the interconnection of two adjacent MOS structures, as shown in Fig. 4. It is a coincidence matrix containing ones in rows and columns corresponding to connected nodes.

Fig. 3.

MOS structures forming FOE.

Fig. 4.

Possible interconnections of adjacent MOS structures (a) and their coding by E_k matrices (b)²⁵.

Nodes without a connection are coded with zero, see Fig. 4b. A total of eight different connections are allowed and thus the design algorithm selects one of the eight variants of the matrix E_k for each boundary between two MOS structures.

Figure 4 does not show the nodes B (bulk), which are always interconnected and connected to the ground node gnd in the synthesis algorithm. This is done because implementation on one chip with one grounded substrate is assumed. However, the design algorithm also allows the bulk nodes to be left ungrounded (i.e. interconnected and floating) or to be disconnected from each other.

The matrix A_k with 4 rows and 1 column encodes the grounding of nodes of two adjacent structures. It contains ones in the rows corresponding to the numbers of the grounded nodes, and the other elements are zeros, as shown in Fig. 5. The choice of grounded nodes is related to their interconnection given by the matrix E_k. Therefore, when the connection of certain nodes is present, grounding is either implemented or not in the entire connection.

Fig. 5.

Example of grounding adjacent MOS structures and its coding by matrix A_k.

The matrix B encodes the connection of external nodes of the entire group of interconnected structures. At least one of these nodes must be connected to the FOE input labeled in. At least one other node is selected as a ground node gnd. The resulting input admittance of the FOE is then present between the nodes in and gnd. If the other two external nodes remain unconnected to either in or gnd, these nodes can also be interconnected in a separated node (con) or remain unconnected (floating—flo). The matrix B has the form

7

An example of coding the connection of external nodes of a series of MOS structures using matrix B is shown in Fig. 6.

Fig. 6.

Example of coding external connections by matrix B.

The physical parameters of individual MOS structures connected according to the connection factors in CCh chromosome are encoded in the PCh chromosome (Parameter Chromosome), which has the form of a single matrix

8

In this case, the parametric factors chromosome PCh contains only lengths L of individual structures. The width W of all structures is chosen as a constant and is the same for all. The width does not affect the FOE admittance phase, only its magnitude, whereas the admittance magnitude is directly proportional to W. Other physical parameters such as resistances and capacitances present in the model in Fig. 2 are unambiguously determined by the dimensions L and W and the fabrication technology (see Table 2).

In the MATLAB software, in which the synthesis algorithm was implemented, an individual FOE solution is represented by a cell array which is a data type with indexed data containers called cells, where each cell can contain any type of data. In this array, cell with index 1 contains the matrices E_k and A_k arranged in an (n – 1) × 2 cell sub-array, where in the first column are the matrices E_k and in the second the matrices A_k. The k-th row of this cell sub-array refers to the interface of the k-th and (k + 1)-th MOS structure. For example, in the first row are the matrices E₁ and A₁. Cell with index 2 contains the matrix B, cell with index 3 the chromosome PCh, i.e. the length matrix, and cell with index 4 contains the fitness score of this solution, see the end of section “Solving input admittance and computing fitness score”.

The admittance matrices of the n MOS structures are stored in MATLAB in a 4-dimensional array, where the indices in dimensions 1 and 2 correspond to the five terminals of the MOS structure in Fig. 2. The index in dimension 3 is the structure number (from 1 to n) and in dimension 4 are the individual frequencies (here 100 frequency points).

Solving input admittance and computing fitness score

In order to determine the admittance phase response of the entire FOE composed of n interconnected MOS structures, the input admittance must be calculated. The generalized method of modified nodal analysis (MNA) is used for this purpose⁴³. This method is described below for specific application to the distributed FOE structure. MNA is used to construct a matrix equation of the form

9

For MNA, each node in a circuit with p nodes is designated by a number corresponding to its row/column in the matrices. The ground node gnd corresponds to 0, and the remaining nodes correspond to 1 through p. For a circuit with p nodes and q voltage sources, the M matrix will be (p + q) × (p + q) and consist of four smaller submatrices Y_G, F, G, H

10

The global admittance matrix Y_G is p × p and is determined by the admittance between nodes.

• Each element in the diagonal of Y_G is the sum of all admittances connected to that node.

• Each off-diagonal element of Y_G is the negative of the admittance connecting the pair of corresponding nodes.

The admittances between nodes for the Y_G matrix can be found using the admittance matrices of the particular MOS structures.

The F matrix is p × q. An entry is a 1 if its corresponding node is connected to the positive terminal of a voltage source, − 1 if its corresponding node is connected to the negative terminal of a voltage source, and 0 otherwise. In the case of the considered FOE, the input is the only voltage source used for testing the input admittance by sensing current flowing through this source, so q = 1. The input node in is always numbered as 1 so the first element of F is a 1 and the rest 0. The G matrix is the transpose of the F matrix, and the H matrix is 0.

The x matrix in (9) is (p + q) × 1. Each of its first p elements contains the unknown voltage at the corresponding node in the circuit, and each of the last q elements contains the unknown current into the corresponding voltage source. As before, q = 1 for this FOE.

The z matrix is (p + q) × 1 and holds the independent current and voltage sources. Each of the first p elements contains the sum of independent current sources into the corresponding node, and each of the last q elements contains the value of the corresponding voltage source. For this FOE, there are no independent current sources so the first p elements are zero. As q = 1, the final entry in z matrix contains a 1 corresponding to an AC signal of the voltage source with 1 V amplitude.

The circuit is solved by the matrix manipulation

11

The last element of the x matrix contains the current flowing into the input voltage source. The current into the FOE structure is the negative of this value, and the input admittance (in siemens) is equal to the input current in amperes because the input voltage amplitude is 1 V

12

Solving for the FOE input admittance can be summarized by the following steps. (The external nodes 1, 2, 0, 5, 6 of the MOS structure in Fig. 2 will be referred to as the terminals in this summary to avoid confusion with the nodes of the FOE solution in terms of the described MNA.)

1. Identify the nodes in the solution. The terminals that are a part of node 0, corresponding to ground gnd, can be identified using the A_k matrices and the second row of the B matrix in CCh. The terminals that are a part of node 1, corresponding to the input in, can be identified using the first row of the B matrix in CCh. The remaining nodes can be identified using the remaining rows of the B matrix and the E_k matrices in CCh.

2. Compute the admittance matrices of the n MOS structures as described in section “MOS transistor model with distributed parameters and its admittance matrix” at frequency points of interest.

3. Construct the Y_G global admittance matrix using the identified nodes. For each terminal that is a part of a given node, use the admittance matrix of a MOS structure to determine the admittance to all terminals that are a part of different nodes.

4. Construct the F, G, H, and z matrices as described above.

5. Calculate the input admittance Y_in between the nodes in and gnd at each frequency point using (12).

A fitness score (also referred to fitness value or just fitness) is used to determine the success of the FOE design and also evaluate the quality of individuals in the population within the GA. This score is calculated based on the course of the admittance phase characteristic calculated according to (12). The requirements for the frequency response of the admittance phase of the synthesized FOE are determined in the form of a window as seen in Fig. 7.

Fig. 7.

Window of the admittance phase response for fitness score calculation.

This window is given by the required frequency range of f_min to f_max and the admittance phase range from φ_min to φ_max. The FOE admittance phase values are calculated in a defined number of frequency points between f_min and f_max. The fitness score is proportional to the number of the phase response points, which are located between φ_min and φ_max. In the example in Fig. 7, the value of the fitness score is Fit = 11 out of its maximum possible value 18.

Genetic algorithm

The possible combinations of connection and parametric factors given by the chromosomes CCh and PCh for forming a FOE composed of a series of MOS structures are nearly infinite. For this reason, we developed the Genetic Algorithm^44,45 to perform the synthesis and identify the best possible results from the vast space of factors essential for designing a MOS-based FOE. The mathematical representation of the GA for this synthesis is given by

13

where P is a population of M individuals. Each individual is defined by the chromosomes CCh and PCh, see section “Coding interconnections and parameters of MOS structures”. The fitness score Fit is a result of a fitness function which evaluates the quality of the given individual. It is computed as explained in the end of section “Solving input admittance and computing fitness score”. The selection operator Θ selects parent individuals from P. The operator Ω includes the crossover operator Ω_c and the mutation operator Ω_m that produce offspring from parent solutions. The reproduction operator Ψ removes two randomly selected individuals from the worst half of the population P and replaces them with the newly generated offspring. Termination check τ is used to determine whether the desired quality of the solution was met.

The initial approach for implementing the algorithm used two nested GAs, where the first would optimize the connection factors CCh and the second would optimize the parametric factors PCh²⁵. However, this approach has drawbacks: (1) it is slow because two complex algorithms are executed in each iteration and (2) since the optimization of parametric and connection factors is not performed in one iteration, the algorithm likely attempts to optimize parametric factors based on connection factors that are not optimal (having been optimized based on less favourable parametric factors).

The newly designed approach for implementing the GA for synthesis is depicted in Fig. 8.

Fig. 8.

Flowchart diagram of GA synthesis.

In the beginning, the initial population P is constructed by generating individuals described by the factors PCh and CCh. In this study, the population size M ranging from 250 to 500 was used to obtain satisfactory solutions within a reasonable time frame.

In the block τ the algorithm checks whether the population contains individuals of sufficient quality in terms of fitness score. If a solution is good enough the algorithm proceeds to the final optimization stage. Otherwise, it verifies whether the specified number of runs (“hops”) of GA y has been reached. If yes, the algorithm proceeds to the final optimization; if not, it continues with an additional run of a predefined set of x GA iterations. The values x = 1000 and y = 15 were used in this work.

Two parent individuals are selected based on the selection operator Θ (we support rank and roulette wheel selection). The crossover and mutation operations for both connection and parametric factors are executed in one run. This addresses the inefficiency in the previous design²⁵, where the connection and parametric factors were optimized separately, causing a lack of synchronization. The crossover operator Ω_c exchanges information between parent individuals to produce offspring that potentially have better combinations of connection and parametric factors. We support one-point, two-point, and uniform crossover. The mutation operator Ω_m introduces small random changes to both connection and parametric factors, helping to explore the search space more thoroughly and avoid local optima.

The reproduction operator Ψ is applied after the fitness evaluation. Newly generated offspring replace individuals in the population, typically those with the lower fitness values, ensuring that the population evolves over time. In this work the new offspring replace two randomly selected individuals from the lower half of the population.

The algorithm checks whether the fitness of the population has reached the desired quality threshold τ. If no, the process iterates, starting from parent selection. If the threshold is met, final optimization attempts in terms of parametric factors are performed to further refine the best individuals. The MATLAB function fmincon which optimizes constrained nonlinear multivariable function is used for this purpose. The computation time required for fmincon is too great to implement at every GA iteration, so instead it is only used on the final solution to ensure the parametric factors are locally optimal.

Finally, the algorithm concludes by identifying the optimal parametric (PCh) and connection (CCh) factors, which define the best FOE synthesized through this GA.

Synthesis program

The FOE synthesis using the described GA was implemented in MATLAB. This environment is suitable for this purpose, as the factors describing the solution are matrices and the calculation of admittance using MNA uses matrix operations. Input and output graphical user interfaces (GUIs) were created, shown in Fig. 9, enabling convenient entry of the input parameters and displaying solution properties.

Fig. 9.

Input (a) and output (b) GUI windows of the synthesis software (some values have been deleted as restrictions apply to the availability of these technology parameters).

The input interface contains other tabs not shown in Fig. 9a. One tab is for setting GA parameters (e.g. number of GA iterations, population size, selection and crossover type). Another tab is used to enter the phase characteristic window (i.e. the boundary phases and frequencies shown in Fig. 7), the number of frequency points between f_min and f_max, and the number of structures n.

The output interface (Fig. 9b) presents the fitness score out of the total number of frequency points, and recapitulates the Material Parameters entered in the input interface. At the top right are Additional Parameters describing other properties of the solution, such as chip area, required phase and frequency range, the frequency when the phase response of the designed FOE first enters the desired window (FreqIn), when it exits it for the last time (FreqOut), and the number of decades between these frequencies (Freq In Phase). This is followed by Physical Parameters, such as the ratio of gate and channel resistances N (which is given by the technology), the designed lengths L of individual MOS structures and a graphic representation of the FOE topology based on the connection factors in CCh. The upper resistors represent the gates of the transistors contacted at two ends (G1 and G2), the lower resistors represent the channels of the transistors between their source (S) and drain (D) electrodes. The bulk electrodes (B) are not shown as they are always connected to ground (gnd) due to the manufacturing technology (as previously mentioned). Nodes marked with the same color are interconnected. The FOE input is between the nodes marked I (in) and the black dot (gnd). Floating nodes are represented by a black square with a white fill. At the bottom of the GUI are the resulting magnitude and phase admittance responses (blue) and the required phase window (red).

It should be noted here that this version of the program considers additional parameters, namely the R_esd resistance, C_pck capacitance and R_gcon resistance. The resistance R_esd = 225 Ω represents an on-chip Electro-Static Discharge (ESD) protection and occurs in series with the designed FOE with one terminal connected to the input pad of the chip and the other to the FOE in node. The capacitance C_pck = 1 pF represents the parasitic capacitance of the input terminal to ground caused by the package lead and printed circuit board (PCB) pad. This capacitance is connected in parallel to the series combination of FOE and R_esd. The values of R_esd and C_pck must be considered if the on-chip fabricated and packaged FOE is to be measured on PCB by an impedance analyzer. If the FOE admittance could be measured directly on chip without bringing its contacts out of the package, the resistance R_esd and the capacitance C_pck can be set to zero in the synthesis.

The resistance R_gcon represents the resistance of the gate contacts considered in the FOE admittance calculation due to the gate being contacted only in the corners. A visualization of this detail of the lower left corner of the structure is demonstrated later in Fig. 15. The TSMC MOS technology does not allow the gate to be contacted over the entire dimension of the width W, but only in short areas of extension of polysilicon (blue in Fig. 15) located outside the active area and the source electrode (red). Analyzes in Cadence showed that these contacts exhibit R_gcon resistance of approximately 25 Ω. The procedure for including R_gcon in the admittance matrix of the MOS structure is similar to that in the case of resistances R_sd, see the description of Kron reduction in section “MOS transistor model with distributed parameters and its admittance matrix”.

Fig. 15.

Zoomed-in section of the FOE layout from Fig. 14—bottom left corner of transistor M1; visible layers: poly, active, p-select, co, m1, v1, m2, v2, m3.

Results

To evaluate the performance of the FOE synthesis process, a series of test cases for different fractional orders was performed. For all test cases a constant width of W = 50 μm for MOS structures was assumed. The width only affects the FOE impedance magnitude without influencing the phase. While running the synthesis program with the parameters of the selected TSMC 65 nm technology, a width of 50 μm was found to lead to impedance magnitudes in the order of 1 MΩ at the beginning of the frequency band to 1 kΩ at the end of the band. If, for example, a tenfold larger impedance magnitude is required, this can be achieved by reducing the width by a factor of ten.

The input parameters for the synthesis process were: admittance phase tolerance of ± 1 degree, frequency range of 5 decades, and evaluation using 100 frequency points in the frequency band. Using these inputs, the fitness score determines what percentage of the 100 frequency points across this five-decade frequency band are within the window between minimum (φ_min) and maximum (φ_max) phase. For example, a fitness score of 70 can be interpreted as the phase response meeting requirements over approximately 3.5 decades.

The allowed range of lengths L during synthesis was 100 μm to 900 μm. The minimum is given by the aspect ratio of the structure (L/W) being at least two for which the structure can be considered as distributed. The maximum length is determined by the TSMC 65 nm technology rules. The presented synthesis results assume n = 4 and 5 MOS structures. For n < 4, poor fitness values were observed and n > 5 did not yield significant fitness improvements.

Overall results of synthesis

The design software described in section “Synthesis program” provides the possibility to set many input parameters, including the number of runs of repeating the whole algorithm per individual phase value of the FOE. If the number of runs is high enough, the probability that synthesis will come close to the best possible fitness score for an individual phase is very high. However, increasing the number of runs also increases the computational time. In this work, thousands of runs were performed for individual phase values ranging from 5 to 85 degrees for both n = 4 and 5. To provide insight into the time demands of the synthesis, Table 3 is provided. It shows that the required time increases with n, while the average time per run decreases for higher number of runs thanks to the parallelization and other global effects.

Table 3.

Computational times for one phase value.

n	Time of 1 individual run (s)	Average 1-run time for total of 1000 runs (s)
4	65.9	14.2
5	80.2	17.7

Measured for the phase 74 ± 1 degrees, using 6 cores on Intel i5-14400F CPU with 64 GB RAM, running on Windows 11 and in MATLAB R2024b (using Parallel Computing Toolbox and Optimization Toolbox).

The best fitness values obtained using the synthesis software depending on the desired mean admittance phase for phases from 5 to 85 degrees (in 1 degree steps) for both n = 4 (blue line) and n = 5 (yellow line) are shown in Fig. 10. From these scores, a general trend of increasing best fitness score for increasing phase is observed. Above 45 degrees yields the most successful synthesis results, where the best fitness values are between 60 and 80. Higher fitness values are achieved for n = 5 compared to n = 4, with improvements up to 10 observed for a few (but not all) cases. The most successful solutions achieve best fitness around 80 for n = 5 and admittance phases of 68 and 74 degrees. This supports that the designed FOEs have a frequency range of approximately 4 decades within the established ± 1 degree phase tolerance.

Fig. 10.

The best fitness values of the synthesized FOEs depending on phase and number of structures n forming the FOE.

The approximate chip areas of the designed FOEs with the best fitness values from Fig. 10 are demonstrated in Fig. 11 for both n = 4 and 5. Overall, the chip areas range from approximately 0.02 mm² to 0.18 mm² for n = 4 designs and from approximately 0.07 mm² to 0.22 mm² for n = 5. Elements with n = 5 have larger area on average (0.145 mm²) than n = 4 (average of 0.106 mm²).

Fig. 11.

Approximate chip areas of synthesized FOEs having the best fitness values for each phase and both n values.

An analysis of the frequencies where the phase characteristic of the best designed FOEs first enters the desired phase tolerance window (FreqIn values in the GUI) is shown in Fig. 12. These frequencies most often range from several hundred Hz to several kHz. When the results in Figs. 11 and 12 are compared, it supports that solutions with larger chip area achieve lower frequencies meeting the target phase characteristics. When the parameters of the technology are fixed, increasing n from 4 to 5 can lead to downshifting the operating frequency band while slightly increasing the number of decades of operational frequency (as visible from the slight increase of the fitness score in Fig. 10).

Fig. 12.

Minimum working frequency (FreqIn) of the synthesized FOEs having the best fitness value for each phase and n.

The operational frequencies of the FOE are determined by technology parameters and permitted lengths of individual transistors (as mentioned previously). If, for example, operation at lower frequencies is required, longer MOS structures than the TSMC 65 nm technology limit of 900 μm should be allowed in the synthesis. On the contrary, if higher working frequencies are required it is necessary to allow lower minimum lengths (L) than the current 100 μm limit. Therefore, it is expected that phase coverage across higher frequencies is possible and that resulting structures will have smaller physical dimensions. The focus on designing FOEs operating at low frequencies by allowing largest possible lengths during the synthesis was a specific choice of this work. The intent of this choice supports the future measurement of fabricated devices by an impedance analyzer at the external pins of the integrated circuit without introducing significant parasitic effects associated with higher frequencies.

Selected FOE with 74-degree phase

Based on the results shown in previous section a FOE with phase of 74 ± 1 degrees and n = 4 (with fitness value of 75.87) was selected for further simulation and validation. This solution is shown in the output GUI presented in Fig. 9b with its admittance magnitude and phase shown in Fig. 13.

Fig. 13.

Magnitude (a) and phase (b) admittance frequency responses of FOE from Fig. 9b with 74 ± 1 degrees and of Valsa FOE emulator for comparison.

The theoretical synthesized results from MATLAB are shown as dotted green lines. For comparison, the simulations from Cadence using parasitic extraction (PEX) are shown as a solid blue lines. The Cadence simulated results model the distributed MOSFET (Fig. 1) with parameters extracted from TSMC 65 nm PDK. For reference, these parameters are listed in Table 2. The PDK is an official process design kit provided by the Europractice consortium which is the selected manufacturer for future fabrication of these elements. The kit includes accurate Spectre models, DRC/LVS rules, PEX models, and process variation data. Access to this material ensures that the fabricated designs will align with the design simulations. In this work, the PEX was applied to the entire design without any skip-cell methods and with sufficiently small tolerance control parameters. Therefore, the simulations are expected to accurately reflect the on-chip parasitic phenomena caused by the layout. These parasitic phenomena include the resistance and intrinsic/coupling capacitance of the interconnection and the capacitance of the transistors’ polysilicon extensions. The Cadence generated magnitude and phase in Fig. 13 show very good visual agreement with the synthesized theoretical characteristics. Overall, the magnitude relative error is less than 0.5% and the phase absolute error is below 0.1 degrees in the presented frequency range.

A comparison of the admittance characteristics of the FOE designed using the method proposed in this work against the characteristics of another FOE emulator is also demonstrated in Fig. 13. The characteristics of the alternative design, presented as purple dashed lines, are simulations of the RC-ladder structure realized using the procedure in⁴⁶. The emulator was designed to contain four pairs of resistors and capacitors, similar to the compared distributed FOE with four MOS structures (n = 4). The allowed phase tolerance of the emulator was set between 73 and 75 degrees and the initial frequency in accordance with FreqIn of FOE, i.e. 1.57 kHz. It is clear from Fig. 13b that the emulator achieves a lower operational frequency range. Overall, the operating band is 2.38 decades using the alternative FOE compared to 3.85 decades achieved by the MOS-based FOE. The MOS-based FOE presented here has a 1.62-fold larger frequency range.

Figure 14 shows the layout of the designed FOE with phase of 74 ± 1 degrees and n = 4. The layout consists of four native n-channel MOSFETs with W = 50 μm, namely M1 (L = 100 μm), M2 (L = 900 μm), M3 (L = 473.66 μm), and M4 (L = 406.86 μm), non-salicided n-poly ESD protection resistor R1 (W = 10 μm, L = 12.92 μm), routing (m1, m2, m3 layers), and substrate rings. The FOE dimensions are 1020 × 120 μm. The pins are placed on the right edge of the prBoundary.

Fig. 14.

Layout of designed MOS-based FOE from Fig. 9b with 74 ± 1 degrees admittance phase; visible layers: poly, m1, m2, m3, prBoundary.

A zoomed-in section of the FOE layout can be seen in Fig. 15. The metal wires are sufficiently wide to ensure low resistance. A wide p + ring is placed around each transistor to maintain a uniform substrate potential across the entire device. The top and bottom corners of the poly gate are connected through an m1 vertical path.

Conclusions

This work has presented the design and implementation of a FOE employing MOS transistors, considered as distributed resistive-capacitive structures. A MATLAB based computer program was used for the FOE synthesis, generating interconnections and parameters of partial MOS structures to achieve a target admittance phase response in a wide frequency range. The program is based on a genetic algorithm, admittance matrix description of MOS structures and modified nodal analysis method. The algorithm benefits from a synchronized approach where both connection and parametric factors of the solutions are optimized in one run, addressing inefficiencies in previous implementations and improving execution speed.

The proposed technique can be used for FOE design with order α in the range of 0–1, i.e. with an admittance phase of 0–90 degrees. For an allowed phase ripple of ± 1 degree, a frequency range of 3–4 decades was achieved for phases above 45 degrees. For lower phase values 1.5–2.5 decades of operational frequency were achieved; supporting that this method can be used across a wide range of orders and target frequency bands. Another important novelty of this work is the compatibility of the synthesized elements with contemporary integrated circuit fabrication technologies and the use of algorithmic design derived from electrical circuit theory. Many other solutions rely only on experimentation with differently composed and arranged chemical materials which results in a low range of the realizable phase and/or narrow frequency band.

The validity of the synthesis has been validated using PEX post-layout circuit simulations of the test samples in Cadence. The admittance phase characteristics correspond with sufficient accuracy to the requirements specified during the synthesis and prove the functionality of the proposed design tool.

Current efforts are preparing the layout of selected FOEs using native n-channel MOS devices in TSMC 65 nm technology with plans for their on-chip fabrication within the mini@sic service of the Europractice consortium. Future work to characterize the fabricated samples aims to further verify the theoretical assumptions in this work and demonstrate single-device FOEs.

Author contributions

D.K. prepared the concept of the article, wrote and collected the main manuscript text and worked on the synthesis program; A.S. and V.K. authored the MOS layout and conducted the Cadence simulations; P.S. prepared the genetic algorithm and its description; J.D. tested the synthesis program and prepared the results section; J.J. tested the synthesis algorithms, prepared statistical analyses, coordinated the author team and administration; C.C. worked on the circuit analysis and synthesis methods and computer program and wrote the respective article sections; T.F. reviewed the methodology for designing the elements and participated in writing and reviewing the text; P.U. is the original author of the described method of fractional element design and consulted on the correctness of the procedures and computation methods. All authors have read and agreed to the published version of the manuscript.

Data availability

The datasets and code described in this study are available from the corresponding author on reasonable request.

Competing interests

The authors declare no competing interests.