A Study on the Synaptic Behavior of Al/ZrO₂/TiO₂/Al Electronic Bipolar Resistance Switching Memristor

Abstract

This study presents the Al/ZrO₂/TiO₂/Al (AZTA) memristor, a device based on a nonfilamentary mechanism. It is designed to simulate artificial synapses for both artificial neural networks and spiking neural networks. The AZTA device exhibits highly linear and symmetrical potentiation and depression under identical pulse operation conditions, and demonstrate spike-timing-dependent plasticity through precise modulation of the shapes of the pre- and postsynaptic spikes. The mechanism for linear potentiation is thoroughly studied by analyzing the trap distribution through temperature-modulated space charge-limited current spectroscopy. The analyzed trap distribution and J-V align well with Mark-Helfrich’s model, demonstrating the high reliability of the analysis. An exponential trap distribution model was found in the bandgap of the switching layer, and deep trap levels were filled preferentially under identical voltage pulses. Subsequently, an expression based on this model was proposed to explain linear potentiation for the first time. Finally, a temporal SNN simulation demonstrates that the small nonlinearity factors enable AZTA synapses to excel in classifying the MNIST data set. The best accuracy achieved was 93.7%, which is comparable to that of a perovskite memristor, one of the most linear devices reported. Along with a Gaussian noise analysis, the high uniformity of AZTA results in trivial performance degradation. These findings highlight the potential of the AZTA memristor in practical applications of neuromorphic computing.

1. Introduction

Emerging nonvolatile memory devices, such as resistive random-access memory (RRAM) and phase-change memories (PCMs), have garnered significant attention for neuromorphic computing. Those devices have been utilized as neurons and artificial synapses in neuromorphic computing systems. − The characteristics of linear long-term potentiation (LTP) and long-term depression (LTD), achieved through voltage pulse engineering, are crucial for efficiently emulating brain synapses. Among several candidates, metal-oxide RRAM has been widely studied due to its electrical adjustability and compatibility with the conventional complementary metal-oxide-semiconductor (CMOS) integration processes. − The two-terminal configuration of the RRAM offers flexibility and simplicity in fabricating the synaptic array devices for the neuromorphic systems, compared to devices with three-terminal configurations, such as transistors. −

Two-terminal memristors based on resistance switching can be broadly categorized into two main working mechanisms, distinguished by their area-dependent switching properties. One type is the filamentary ion migration-type mechanism, in which the conductance (synaptic weight) changes are induced by the movement of metal ions (such as Cu or Ag) or oxygen vacancies. The other type is the nonfilamentary-type mechanism, where the synaptic weight changes can be attributed to the trapping and detrapping of electrons. Many RRAM devices governed by conducting filament (CF)-based switching mechanisms exhibit abrupt and stochastic switching properties due to the random localized formation and rupture of the CFs. , These properties are undesirable when used as synapses for neuromorphic computing as they induce accuracy reduction and energy inefficiency in artificial neural networks (ANNs). In contrast, nonfilamentary RRAM may offer a superior choice for its enhanced synaptic properties. Unlike CF-based RRAMs, such nonfilament-controlled memristors participate in electrical conduction throughout the entire electrode area. They generally encompass better uniformity and higher area scalability, whereby the smaller device area favors low power consumption. ,

Bipolar resistive switching (BRS) TiO _x -based memristors are nonfilamentary memristors and promising candidates for neuromorphic computing because it is highly CMOS compatible and scalable. The conduction mechanisms of these devices have been reported to be trap-mediated SCLC since 2010. − The electron trapping/detrapping from the TiO _x -layer is believed to be the resistive switching mechanism. These studies evidence such mechanism by area-type switching, J-V curve fitting of SCLC conduction, and decreased activation energies from HRS to LRS. − Then, recent studies have started to investigate the analogue switching of BRS TiO _x -based memristors through electrical pulses, and utilize the analogue-type TiO _x memristors as synapses in neuromorphic computing since 2020. − These studies have further shown that analogue resistive change can be modulated by width and amplitude of the pulse, which is another evidence of the electron trapping/detrapping mechanism. , In 2024, Park et al. used the Mark Helfrich’s model to calculate the total trap density changes of different analogue states of Al₂O₃/TiO₂/TiO _x memristor to evidence that the conductance switching is trap-mediated. Furthermore, these studies tried to demonstrate linear LTP/LTD under tuned electrical pulses, and showed that linear LTP/LTD can benefit the performance of ANN. However, it remains unclear why the device can demonstrate linear LTP/LTD due to the difficulties of revealing trap distributions in MIM memristors. Trap-sensitive spectroscopies, such as deep-level transient spectroscopies (DLTS) and thermal admittance spectroscopies (TAS), are commonly used to measure the trap depth and concentrations of thin-film transistors. Because these methods typically fill the traps by applying voltage pulses to the gate first and use the capacitance change caused by electron re-emission from the traps to obtain information on traps, it is hard to be used for mapping the trap distributions of electronic switching type memristor, especially the intermediate states and low resistance states once electrons are already trapped in the memristors. , There is only one recent study using DLTS to characterize the traps in the memristor. However, it can only extract the trap depth and fails to measure the trap distribution in the device. In contrast, the temperature-modulated space-charge-limited current (TMSCLC) spectroscopic method, which was first proposed by Scheuer et al., can be used to analyze the trap distribution of both crystalline and amorphous semiconductors as long as the SCLC conduction mechanism governs the device. This method has been used to analyze the trap distribution in organic semiconductors, primarily due to the critical role of traps in their applications, such as organic light-emitting diodes. − As several previous research studies on TiO _x -based ReRAM devices have confirmed that the dominant conduction mechanism of the device is SCLC, and conductance switching is governed by electron trapping/detrapping, ,,,,, this research utilizes the TMSCLC to reveal the trap distribution of different states of the TiO _x -based memristor for the first time.

In the previous work, the authors reported a nonfilamentary Al/ZrO₂/TiO₂/Al (AZTA) RRAM device that exhibited various promising properties, including excellent uniformity, forming-free characteristics, and area-scalable behavior. These performances were based on the electronic bipolar resistive switching (e-BRS) mechanism. This study further investigated the ability of the AZTA RRAM device to simulate artificial synapses. It was found that the AZTA device demonstrated linear synaptic plasticity for both LTP and LTD, as well as intrinsic spiking timing-dependent plasticity (STDP). The trap distribution analysis of different states facilitates the understanding of why the device exhibits linear LTP under electrical pulses, which has not been studied in previous research. The results indicate that an exponential trap distribution exists in the bandgap of the TiO _x layer, and electric pulses fill the deep traps preferentially, resulting in linear LTP and LTD. Finally, the supreme online learning capability of a temporal encoding spiking neural network (SNN), utilizing the high linearity and uniformity of AZTA as the synapse, is also demonstrated through simulations to illustrate the importance of high linearity characteristics on SNN relying on real-time learning. This work can help researchers interested in any memristors showing SCLC trap-mediated conduction mechanisms to understand why tuning the pulse width and amplitudes can make the device demonstrate linear LTP/LTD. Furthermore, a new SNN framework is built for researchers in synaptic memristors to demonstrate the influence of linearity on the performance of neural networks relying on real-time weight updates. This is also valuable because modern algorithms in ANNs that rely on backpropagation have mitigated the adverse effect on performance brought by the nonlinearity of memristors.

2. Materials and Methods

2.1. Fabrication of the Al/ZrO₂/TiO₂/Al Resistive Switching Memory

First, a 100 nm-thick Al bottom electrode was deposited via electron beam evaporation (Sorona, SRN-200i) onto a substrate comprising a 5 nm-thick TiO₂ adhesion layer, deposited by reactive sputtering (SNTEK, PSP5004) on a 200 nm-thick SiO₂/Si wafer. Subsequently, the as-deposited Al electrode is placed in ambient air for 1 h, during which it naturally oxidizes to form an approximately 5 nm-thick AlO_x layer. Thereafter, a 25 nm-thick TiO₂ film was deposited on the resultant AlO_x/Al/TiO₂/SiO₂/Si stack using a radio frequency (RF) magnetron sputtering (SNTEK, PSP5004) with a Ti₄O₇ target in an O₂/Ar reactive atmosphere at room temperature (RF power: 200 W; deposition pressure: 5 mTorr; oxygen concentration: 20% O₂). Then, a 2 nm-thick ZrO₂ oxygen vacancy blocking layer was subsequently deposited on the TiO₂ film via atomic layer deposition (CN1, Atomic Classic System) by 15 deposition cycles (Zr-precursor: Zr­[N­(CH₃)­(C₂H₅)]₄; oxygen source: O₃ with a concentration of 180 g/m³; deposition temperature: 250 °C). Finally, a 100 nm-thick Al top electrode was deposited using electron beam evaporation (Sorona, SRN-200i). Both the bottom and top Al electrodes were patterned using a maskless photolithographic system (Nano System Solution, DL-1000 HP) and a lift-off process to form a crossing line shape with effective cell areas of 10 μm × 10 μm, 8 μm × 8 μm, 6 μm × 6 μm, 4 μm × 4 μm, 2 μm × 2 μm, and 1 μm × 1 μm. The plan-view pattern and the top view of a single device are presented in Figure S1 of the online Supporting Information (SI).

2.2. The Electrical Test of the Al/ZrO₂/TiO₂/Al Artificial Synapse

The Al top electrode is connected to the bias voltage, while the Al bottom electrode is grounded. Direct current (DC) current–voltage (I–V) characteristics were measured using a semiconductor parameter analyzer (Hewlett-Packard, 4145B). For pulse-switching tests, a semiconductor parameter analyzer (Hewlett-Packard, 4155B), a pulse generator (Tektronix, AFG3010C), and an oscilloscope (LeCroy, WaveSurfer 62MXs-B) were employed. Due to the extremely high initial resistance (∼9 × 10⁹ Ω at V_read = 0.5 V) of the AZTA device with an electrode area of 100 μm² and the high input impedance of the oscilloscope (2 MΩ), an accurate current reading in pulse mode was unlikely. Therefore, the device’s conductance was measured using the DC sweep mode after the pulse was switched. A switching box was used to switch between DC and pulse modes. The in-house built test program controls the test interval between switching modes. All data in this work were obtained from an electrode area of 100 μm².

2.3. Nonlinearity Value Calculation

Ideal linearity is defined as a state in which changes in conductance due to potentiation or depression are independent of the current conductance state. The conductance as a function of the normalized pulse number is modeled to obtain the linearity factor of the potentiation (NL_P) and depression (NL_D):

$$\{\begin{array}{c}{G}_P=K(1-e^{-N{L}_P\times P_n})+G_{min}\\ G_D=G_{max}-K(1-e^{-N{L}_D(p_{max}-P_n)})\\ K=\frac{G_{max}-G_{min}}{1-e^{-NL\times P_{max}}}\end{array}$$ 1

, where the G_P and G_D are the conductance values after each potentiation and depression. G _max and G _min are the maximum and minimum conductance values, respectively. P_n and P _max are the normalized pulse number and maximum normalized pulse number (P _max = 1), respectively. K is a function of NL that fits the G_P and G_D functions within the range of G _max, G _min, and P _max. When the NL is zero, the conductance update is ideally linear.

2.4. Trap Distribution Analysis

The trap distribution of four different conductance states, which were established by appropriately biasing the device using the pulse switching method, was analyzed using the TMSCLC method. Current density–voltage (J-V) curves of four different states were measured at 300, 310, 320, 330, and 340 K. The conventional activation energy can be obtained from the voltage curve by calculating the gradient of the Arrhenius plots for the four resistance states. This conventional activation energy was then corrected to the energy difference between the dominant energy (quasi-Fermi level E_f) and conduction band edge (E_c). Then, the first and second derivatives of the smoothed ln J-ln V curves at 300 K are used to calculate J­(E_c-E_f). Python then performs a deconvolution process to obtain the trap distribution curve. Supplementary Note 1 provides a detailed explanation of the TMSCLC method.

3. Results and Discussion

3.1. The Gradually Changing I–V Characteristics of the AZTA Memristor

Figure a illustrates the typical I–V characteristics of the AZTA resistance switching memory device in DC sweep mode. The voltage sweep sequence is set from 0 → −4 V → 0 → 4 V → 0. With a compliance current of 1 μA, the device is converted from the high resistance state (HRS) to the low resistance state (LRS) during the sweep in the negative voltage region. A double-logarithm plot of Figure a, presented in Figure S2, suggests that the SCLC conduction mechanism governs the device in both HRS and LRS. In the negative bias region, the SET (switching from HRS to LRS) occurs when the voltage exceeds the trap-filling limit voltage (V_TFL) in the SCLC conduction mechanism. Then, a RESET occurs in the positive bias region, returning the device to HRS. The resistance ratio of HRS and LRS is ∼ 500 at the read voltage (V_read) of 0.5 V, which can store a logic ″0″ or ″1″ for nonvolatile memory applications. The reason why the device is SET at a negative voltage and RESET at a positive voltage, and the role of each layer has been studied in the authors’ previous publications, which are briefly reviewed as follows. , The ∼ 5 nm naturally oxidized AlO _x layer acts as an essential layer that provides a Schottky barrier between the bottom electrode and the resistive switching TiO _x layer. In contrast, no such barrier exists (electrons can tunnel through the ultrathin ZrO₂ layer fluently upon application of bias) between the top electrode and the TiO _x layer. These asymmetric potential barriers result in the e-BRS. As presented in Figure S2a of the SI, when a negative bias is applied to the top Al electrode, electrons tunnel through the ultrathin ZrO₂ layer and flow into the TiO _x layer, filling the traps and leading to conductance switching from HRS to LRS (negative bias SET behavior). In contrast, electron injections are effectively suppressed by the naturally oxidized AlO _x layer if a positive bias is applied, resulting in the insufficient charge injection to fill the traps. Besides, the previously trapped electrons in the TiO _x layer can be flushed out toward the top electrode when the top electrode is positively biased, resulting in RESET of the device. However, if a protective layer is absent between the top Al electrode and TiO _x layer, oxygen can also migrate toward the active Al electrode, resulting in low uniformity. , Therefore, the role of the ultrathin ZrO₂ layer is to effectively block oxygen migration in the TiO _x , which can significantly improve the uniformity and endurance of the device. It also prohibits carrier loss during the data retention period with no applied bias. The XPS spectrum, TEM image showing the cross-sectional structure, and EDS mapping of the AZTA device have been reported in the authors’ previous publication to demonstrate the thickness and successful insertion of the ultrathin ZrO₂ layer, which significantly improves cycle-to-cycle variation, device-to-device variation, and endurance. The DC switching endurance test presented in Figure S3 of the SI indicates that the device can retain the effective resistance switching even after 10⁵ cycles.

1.

(a) Typical I–V curves with an I_cc of 1 μA. (b) The SET process involves gradually increasing the sweep voltage from −3.6 V to −4.1 V. (c) The RESET process involves gradually increasing the sweep voltage from 4.0 to 4.5 V. The I–V curves in the semilog scale within the low sweep voltage range are shown in the inset figures. (d) The SET and (e) RESET processes in pulse operation mode, with input voltages of −4 and 4 V, respectively. The interval and pulse length are both 1 ms.

As previous work primarily focused on enhancing the endurance and uniformity of DC characteristics, this work further explores the analog switching performance of the device. Figures b- e illustrate the analog switching behavior of the AZTA under both DC and pulse switching conditions. Among those figures, Figures b and c show the SET and RESET I–V curves of the analog switching under DC mode, respectively. The sweep voltages are applied in the following sequences: first to sixth for the set and seventh to 12th for the reset. With the SET stop voltage decreasing from −3.7 V to −4.2 V, the resistance value gradually decreases from 9.0 × 10⁹ Ω to 5.4 × 10⁷ Ω at V_read = −0.5 V. Subsequently, a continuous RESET process is performed with the RESET stop voltage increasing from 3.9 to 4.4 V and the resistance value increases from 6.5 × 10⁷ Ω to 7.2 × 10⁹ Ω at V_read = 0.5 V. Both processes showed gradually changing resistance with the increasing applied voltage magnitude when the voltage is higher than V_TFL. Such gradual conductance switching is visible in the inset figures of Figures b and c. Furthermore, Figure S4 of the SI shows gradual conductance switching under a constant DC set stop voltage of 3.6 V, indicating that analog conductance switching can be achieved once the voltage exceeds V_TFL.

On the other hand, Figures d and e show the real-time gradual changing behavior of the current under the 4 V and 1 ms pulse mode for the SET and RESET processes, respectively. These results demonstrate that pulses could progressively modulate the resistance of the AZTA device to achieve multiple states. Before and after the pulse-SET operation, the device conductance values, read at V_read = 0.5 V, were ∼ 0.28 nS and ∼ 4.92 nS, respectively. After the pulse-RESET operation, the device’s conductance value recovers to ∼ 0.30 nS, indicating that the device’s conductance can be set to a higher conductance state and reset back to the original conductance state by identical pulses. Modulation of voltage pulses to achieve LTP/LTD and STDP is presented in Sections and , respectively, followed by a detailed analysis explaining why conductance changes in this manner in Section .

3.2. LTP and LTD of the AZTA Memristor

Linear LTP and LTD of a synaptic device could make it ideal for ANN and SNN, especially in optimizing accuracy and reducing energy consumption of SNN learning that relies on real-time weight updates. Figure a shows a schematic diagram of the AZTA memristor, which mimics the function of an artificial synapse. The gradual conductance-changing property of the AZTA sample enables the fine-tuning of synaptic weight by adjusting the pulse amplitude, length, frequency, and number of input pulses. Here, a G_n/G₀ index is introduced to indicate the degree to which different stimuli affect synaptic plasticity, where G₀ represents the initial synaptic weight and G_n represents the synaptic weight after n stimuli. Figure b shows that the conductance can be effectively modulated by varying the pulse amplitude of the stimulus signal, specifically for negative pulses. When the absolute value of the applied pulse amplitude was less than 3.4 V, synaptic plasticity did not exhibit a noticeable change after applying five consecutive pulses, and the G_n/G₀ ratio remained at 1. In contrast, when the pulse amplitude exceeds 3.6 V, the conductance changes become more pronounced with increasing pulse voltage. This voltage is close to the V_TFL in the DC switching mode, demonstrating that only voltages that lead to trap filling can change the device’s conductance. Furthermore, larger voltage pulses can lead to higher current injection, thereby filling more traps in the band gap, resulting in a more significant change in conductance. Next, the modulating effects of the pulse length and frequency on the synaptic plasticity of the AZTA device are examined. Figure c illustrates the conductance changes resulting from a single pulse with varying pulse lengths. The results indicate that the pulse length should be greater than 500 μs to change the conductance, although the pulse amplitude (i.e., −4 V) is higher than V_TFL. This finding suggests that a sufficient number of charge carriers, specifically electrons, must be injected into the device to alter its conductance. The conductance change becomes more significant with the increasing number of electron injections. Furthermore, Figure S5 illustrates the relationship between the conductance change and the device area. It is found that the pulse length required for devices with different areas to reach the same conductance ratio is nearly proportional to the device area. This finding indicates that devices with larger areas typically require more charge injections. This area dependence of the pulse length, along with the area dependences of HRS and LRS under DC switching cycles reported in the author’s previous publication, can further prove that the underlying mechanism of the electroforming-free property should be the electron trapping/detrapping mechanism. Figure d illustrates the effect of pulse frequency on conductance. A higher pulse frequency can lead to a more pronounced conductance enhancement if the frequency exceeds 100 Hz. This result can also be attributed to a higher frequency of pulses, which increases the postsynaptic current and, consequently, the magnitude of charge injections. Therefore, Figures b–c evidence that the increment in conductance change can be determined by the total number of electrons injected into the device. A solid proof of this charge-filling model is presented in Section .

2.

(a) Schematic diagram of the AZTA memristor simulating the working mechanism of a biological synapse. Excitatory postsynaptic current (EPSC) under different (b) pulse amplitudes (The pulse length and interval are 500 μs with leading and training times of 100 μs), (c) pulse lengths (The pulse amplitude is −4 V), and (d) pulse frequencies (The pulse amplitude is −4 V and the pulse length is 500 μs), respectively. The leading and training times were not set in the pulse length and frequency tests for better comparison and calculation.

Based on the above results, a pulse length of 500 μs was selected to examine the long-term plasticity characteristics of the AZTA artificial synapses, as shown in Figure . The synapse cell should have a nearly linear response over the conductance range for efficient artificial synapses in neural network computing. For this purpose, NL_P and NL_D are introduced to evaluate the device’s performance. Smaller NL_P and NL_D values indicate a more linear change in conductance. Figure a shows the long-term potentiation characteristics of the AZTA synapses. The conductance increases rapidly initially and reaches a saturation value at larger pulse numbers. A higher pulse amplitude results in a higher saturation conductance. The NL_P decreases notably with the decrease of the applied pulse amplitude, and the best NL_P is obtained at −3.8 V. However, the saturation conductance at −3.8 V is too low for practical application. Therefore, a pulse amplitude of −4 V was selected for long-term potentiation tests. Here, the conductance ratio is ∼ 20 (initial conductance (G₀) and after 50 pulses (G₅₀) are ∼ 0.2 nS and 4.5 nS, respectively). The G₅₀ of the potentiation process was selected as the initial state of the subsequent depression test with different pulse amplitudes, as shown in Figure b. This figure illustrates that higher pulse amplitudes result in a faster discharge of the trapped electrons in the device, leading to a higher NL_D value. Therefore, the NL_D value of the conductance change is lower at relatively low pulse amplitudes, similar to the process of potentiation. In addition, Figures a, b, and S3 of the SI suggest that resetting to the initial state should require a larger voltage pulse amplitude than setting, resulting in asymmetric LTP and LTD behavior. The possible reason for this linear LTP is explained following the trap distribution analysis. Finally, Figure c presents the results of five consecutive long-term plasticity tests obtained under the optimized conditions of −4.0 V/500 μs for potentiation and 4.2 V/500 μs for depression. The pulse number was set to 30 to eliminate the effect of the conductance saturation region, thereby achieving optimal nonlinearity. Figure d presents the average results of these five consecutive cycles, indicating that the conductance variation of the AZTA synapse is highly linear, with NL_P and NL_D values of 0.17 and −0.70, respectively, which are significantly lower than the previously reported values. This asymmetric NL_P and NL_D is consistent with the discrepancy in the currents during SET and RESET regulation processes presented in Figures d and e. These will be used for SNN online learning simulation in Section . The conductance ratio achieved was ∼ 12.0 (G _min and G _max = 0.28 nS and 3.40 nS). Figure S6 of the SI shows the variation in device-to-device conductance. The energy consumption for one-step potentiation can be calculated as E_cons = V × Q, where V represents the input pulse amplitude (−4 V) and Q represents the charge flowing through the device, which is the area under the current–time graph. The E_cons for one step of the potentiation can be estimated as ∼ 1.4 nJ. Although the energy consumption for each spike update is higher than that of the human brain (∼fJ - pJ), it can be significantly reduced with a smaller device area. In addition, it is worth noting that this linear conductance variation is obtained under identical pulse test conditions, which is a critical merit of this device compared to previous reports. − The identical pulse condition eliminates the complexity of the control circuit for making nonidentical pulse conditions. − Notably, Figures S6 of the SI and 3e show that the linear potentiation and depression characteristics were retained even after 1000 pulse tests, demonstrating the outstanding ability of the AZTA synapses to maintain linearity. The mean values and standard deviations under each pulse number are presented in Table S1, which will be used for simulations in Section . In contrast, filamentary-type devices typically modulate resistance by setting different compliance currents or reset stop voltages, which are closely related to the partial formation or rupture of CFs. , Such a CF configuration requires more complicated pulse engineering to achieve linear LTP and LTD. Additionally, it requires asymmetrical pulses to restore the device’s resistance to its initial state, which can sometimes lead to permanent device degradation and reduced endurance. In short, AZTA can achieve linear LTP and LTD with a simple switching pulse configuration, thereby enhancing the device’s resilience to degradation.

3.

(a) Long-term potentiation characteristics under different pulse amplitudes from −3.8 V to −4.6 V. (b) Long-term depression characteristics under different pulse amplitudes from 3.8 to 4.6 V. (c) Five consecutive long-term plasticity tests with the pulse conditions of −4.0 V/500 μs and 4.2 V/500 μs for potentiation and depression, respectively. (d) The average results of five consecutive cycles with the conductance ratio of 12.0. (e) The potentiation and depression test after 1000 pulse cycles.

Figure S7 of the SI shows the result when the total input pulse length is constant (i.e., the input pulse amplitude is −4 V and the total pulse length is 8 ms), and the pulse length is equally divided into smaller pulse lengths (500 μs, 200 μs, 80 μs, and 32 μs) with the DC read operation after each pulse. The number of pulses for these tests is 16, 40, 100, and 250, respectively. With decreasing pulse length, increasing pulse number and DC reads, the reading conductance fluctuation increases significantly. In contrast, when inputting the pulse trains without the DC reading steps, even if the pulse length is divided into tiny equal parts, the conductance does not decay, as shown in Figure S8 of the SI. This finding also evidence that the conductance change of the device will remain intact if the number of electron injections is constant. In addition, it also suggests that the device can potentially achieve more operable conductance states if the switching and reading are carefully designed without affecting the device’s state. The fluctuation in Figure S7 of the SI can be attributed to testing artifacts rather than device characteristics. Frequent switching between pulse mode and DC reading mode can cause a transient response due to the switch box, which may affect the accuracy of the measurement results.

3.3. STDP of the AZTA Memristor

The intrinsic STDP-like property renders the device beneficial for SNN applications, as STDP is one of the most common learning methods in SNNs. In STDP, synaptic weight change between two neurons depends on the relative arrival times of pre- and postsynaptic pulses (Δt). If the presynaptic spike arrives before the postsynaptic spike, it can lead to LTP. Conversely, it can cause an LTD if the postsynaptic spike arrives earlier than the presynaptic spike. The following eq can describe the relationship between the change in weight and the time interval:

$$\mathrm{\Delta }W=\{\begin{array}{c}{A}_p\times \exp (-\frac{t_{post}-t_{pre}}{{\tau }_p}),t_{pre}-t_{post}<0\\ A_n\times \exp (-\frac{t_{pre}-t_{post}}{{\tau }_n}),t_{pre}-t_{post}\ge 0\end{array}$$ 2

where ΔW is the change in synaptic weight, A _p and A _n are learning constants for potentiation and depression, respectively, and τ_p and τ_n are time constants corresponding to the potentiation and depression of the synaptic connection. Figure a illustrates the method for testing the intrinsic STDP behavior of the AZTA device. For the LTP test, two negative −4 V/1 ms pulses are applied. As the time intervals between the two pulses change, the device’s conductance changes are measured. The LTD test is performed similarly, except two positive 4 V/1 ms pulses with changing time intervals are applied. Figure S9 of the SI shows the postsynaptic current responses with different pulse intervals, indicating that a shorter time interval between two pulses results in a more significant current passing through the AZTA memristor, consistent with the frequency response presented in Figure d. Figure b shows the modulation of conductance by the AZTA memristor with different time intervals between two pulses. This conductance response of the AZTA synapse assembles the typical STDP learning by the exponential decay-fitted equation:

$$\frac{\mathrm{\Delta }W}{W}\times 100\%=\{\begin{array}{c}22.5\times \exp (-\frac{t_{post}-t_{pre}}{9.35ms}),t_{pre}-t_{post}<0\\ -15.4\times \exp (-\frac{t_{pre}-t_{post}}{10.1ms}),t_{pre}-t_{post}\ge 0\end{array}$$ 3

, where W is the initial conductance of the device. The device exhibits intrinsic STDP behavior, as evidenced by the current increasing with decreasing pulse intervals, as shown in Figure S9 of the SI. The shorter interval induces a more significant charge injection and, consequently, higher trap filling in the bandgap, resulting in a more substantial change in conductance.

4.

(a) When the presynaptic pulse reaches the synapse first, potentiation will be performed. Conversely, depression will be performed if the postsynaptic pulse reaches first. (b) Percentage of conductance change after different pulse intervals.

3.4. TMSCLC Analysis of the AZTA Trap Distribution

This section describes the microscopic origins of the AZTA device’s specific electrical properties by examining its TMSCLC behavior. A brief review of the SCLC conduction mechanism and the important equations necessary for this work can be found in Supplementary Note 1 of the SI.

In this work, four different states of AZTA are obtained by continuously applying the identical pulse trains illustrated in Figure a. The conductance state changes from State 1 to State 4 by applying three trains of ten −4 V/500 μs pulses. Figure b shows the I–V curves of the four states under a DC sweep operation from 0 to 0.6 V. The conductance value at a V_read of 0.5 V for four states increases linearly (0.21 nS, 1.32 nS, 2.30 nS, and 3.37 nS, inset figure) with the increasing number of pulse trains. The retention curves of these four states are measured at room temperature and presented in Figure S11 of the SI, which suggests that all these intermediate states can retain their resistance for over 10⁵ s at room temperature. However, it is worth noting that the lower resistance states typically have shorter retention because of the low activation energy, as suggested by Figure S11 of the SI, which is an unavoidable problem of eBRS memristors and worth further optimization to enhance their thermal operation stability. Subsequently, the I–V curve in Figure b is replotted on a double-logarithmic scale, revealing that all four states follow trap-limited SCLC conduction. The slope values in the trap-filling region of all states are not simply 2 (from 3.7 to 1.6), indicating that an exponential rather than a single-level trap distribution is present in the bandgap, as suggested by Mark Helfrich’s model. This exponential distribution of trap states suggests that the activation energy calculated from the Arrhenius plot cannot be treated as the trap depth for a single-energy-level trap. Thus, the previous work that used this conventional activation energy to explain the conductance-switching mechanism of AZTA oversimplified the problem. To more accurately model the conductance-switching mechanism of AZTA and explain the possible reason behind the linear LTP behavior, the trap distribution in the bandgap of the MIM ReRAM device was first analyzed by a method proposed by Schauer et al. Supplementary Note 2 of the SI provides a detailed analysis process. This method can analyze the trap distribution without affecting the conductance state of the device because the memristor will not be SET if the voltage is lower than V_TFL. Therefore, the I–V curves of the four states were measured in the voltage range below 0.6 V, from 300 to 340 K (Figure S10a of the SI). The activation energy-voltage (E _a-V) curve (i.e., Figure d) can be obtained from Arrhenius plots in Figure S10b of the SI. The deconvolved trap distribution of the four states can then be analyzed from the J-V curve of the four states at 300 K, as shown in Figure d, with the results plotted in Figure e. The original state (State 1) exhibits a highly reasonable fit (R² = 0.999) to the exponential decay function suggested by MH’s model, as given by Equation S5, indicating the high reliability of the trap distribution analyzed using the TMSCLC method. Supplementary Note 1 of the SI provides a detailed description of the derivation steps. Moreover, the TiO _x layer deposited at ambient temperature via reactive sputtering is found to be amorphous by TEM. This amorphous layer could result in exponential trap distribution in the bandgap (more precisely, the energy region between the electron and hole mobility edges). , Hence, this trap distribution analysis is reasonable and can serve as a critical analysis technique for electron trapping/detrapping ReRAM devices that demonstrate the SCLC conduction mechanism.

5.

(a) Four different conductance states were obtained by continuously applying the same pulse trains. (b) The I–V curves of the four states under a DC sweep mode from 0 to 0.6 V. The conductance of four states at the read voltage of 0.5 V is shown in the inset figure. (c) The double-log plot of I–V curves in four states. The red and yellow lines represent the fitting of the hopping and SCLC mechanisms, respectively. The intersection point of the two lines is the transition voltage. (d) The activation energies of four states are obtained from Arrhenius plots in Figure S7 of the SI. (e) The trap distribution of four states was analyzed from the TMSCLC method. The exponential fitting of the trap distribution in State 1 confirms the hypothesis that the trap has an exponential distribution within the bandgap. (f) An exponential fitting curve indicates that the energy difference between the band edge and the highest occupied trap level decreases exponentially with the number of pulses. (g) The consistency between the experimental results and the modeled equation supports the assumption that charge injection by electrical pulses preferentially fills the deep traps. As there is an exponential trap distribution, the deep traps will be filled after 20 pulses, leaving only the shallow traps near the band edge. This behavior results in a linear change in conductance with pulse numbers ranging from 20 to 50.

Then, trap distributions of all four states show that the traps are gradually filled by pulses, with deep traps being filled preferentially as all States 2, State 3 and State 4 have lower trap density at deep trap levels than that of State 1 (Figure S12 of the SI shows detailed trap distribution of four states). It is worth noting that the analyzed trap distributions of all states represent only a portion of the distribution in their respective states, as the applied voltage is limited to 0.6 V, which restricts the obtainable information on traps. A higher voltage scan can result in a change of state, especially at high temperatures. Nevertheless, it can still be inferred from Figures c-e that the trap distributions of States 1 and 2 follow exponential distributions. At the same time, States 3 and 4 can be regarded as having shallow trap levels near the band edge. This assertion is based on the following two points: 1. The slopes of the ln J-ln V curves for States 1 and 2 are higher than 2, whereas States 3 and 4 approach 1 in Figure c; 2. Figure d shows that the measured activation energies at 0.05 V for the four states decrease exponentially with the number of pulses. This measured activation energy at a very low voltage (0.05 V) can be regarded as the difference between the highest occupied trap energy of all states and the conduction band edge. States 3 and 4 have only 0.15 and 0.11 eV, respectively. Figure e shows that the corrected quasi-Fermi energy level (an energy level that dominates the increment of space charge concentration) of States 3 and 4 at 0.05 V is very close to the band edge (less than 0.04 eV).

Thus, a single-level trap distribution model can be constructed to illustrate how the conductance changes with pulse number after 20 pulses, where State 3 represents the state achieved after 20 pulses. As the J-V equation for a single shallow-level trap model is presented in equation S2 of the SI, the conductance ratio between two states is inversely proportional to the total trap density between them. The total trap density of different states can be estimated by assuming that the measured activation energy at 0.05 V is close to the difference between the highest occupied trap energy and the conduction band edge. Therefore, their total trap density can be estimated simply using the total N_trap subtracted by the integration of Equation S5 of the SI up to the measured activation energy:

$$N_t=N_{trap}-{\int }_{E_{\mathrm{a}}}^{\infty }5.80\times {10}^{25}\exp (-\frac{E_{\mathrm{a}}}{0.0679})dE=3.94\times {10}^{24}(1-\exp (-\frac{E_{\mathrm{a}}}{0.0679}))$$ 4

The activation energy E _a at 0.05 V for the four states can be related to the pulse number, as 0, 10, 20, and 30 pulses are used to potentiate the device. Figure f shows that E _a exhibits exponential decay with pulse numbers at −4 V. The fitted equation is

$$E_{\mathrm{a}}=0.217\exp (-\frac{n}{20})+0.0671$$ 5

, where n is the number of pulses. Therefore, the conductance ratio between states after n pulses, G_n, and State 3 (i.e., the state after 20 pulses G₂₀) can be calculated by the equation:

$$\frac{G_n}{G_{20}}=\frac{N_{t20}}{N_{tn}}=\left(\frac{0.8977}{1-\exp (-\frac{0.217\exp (-\frac{n}{20})+0.0671}{0.0679})}\right)$$ 6

Figure g shows the modeled ratio change versus the pulse number, indicating that the model accurately fits the experimentally measured data. The modeled conductance ratio change exhibits high linearity between 20 and 50 pulses, indicating that the linear conductance change can be attributed to the specific SCLC conduction mechanism and single-shallow level trap distribution, provided that identical pulse amplitudes, lengths, and numbers are carefully selected.

For pulse numbers smaller than 20 pulses, State 1 and State 2 demonstrate exponential distributions. As the total trap density N_trap can be estimated by eq , the J-V relation is, therefore, a combination of Equations S4 of the SI and 4:

$$J=N_0\mu e^{1-l}{\left(\frac{\epsilon }{3.94\times {10}^{24}\left(1-exp\left(-\frac{E_a}{0.0679}\right)\right)}\frac{l}{l+1}\right)}^l{\left(\frac{2l+1}{l+1}\right)}^{l+1}\frac{V^{l+1}}{L^{2l+1}}$$ 7

Assuming that for a small number of pulses, n, the trap distribution does not change significantly, and thus there is a negligible change for l. The conductance at 0.5 V is, therefore, only proportional to ${\left(\frac{1}{(1-\exp (-\frac{E_{\mathrm{a}}}{0.0679}))}\right)}^l$ . This can be expanded by reciprocal expansion as the exponential term is very close to 0:

$${\left(\frac{1}{\left(1-exp\left(-\frac{E_{\mathrm{a}}}{0.0679}\right)\right)}\right)}^l=1+l\times exp\left(-\frac{E_a}{0.0679}\right)$$ 8

The above equation can then be expanded using a Taylor series expansion, thus yielding a linear change in conductance with E _a. As E _a only changes in a very small range and is almost linear with pulse numbers when the pulse number is small, this suggests that conductance may also change linearly with pulse numbers. Figure a shows that a small pulse amplitude can result in a very small NL_p (a 3.8 V pulse leads to an NL_p of 0.43), which supports the idea that the conductance change will be relatively linear if the trap distribution does not undergo a significant change under small electron injection.

Figure is a schematic diagram that summarizes the analysis in this section. The device’s original state has an exponential trap distribution, and the highest trap level filled is 0.29 eV. At this deep trap level, the trap distribution changes trivially, resulting in a linear change in conductance under small pulse numbers and low electron injections. Then, the trap distribution changes significantly with increased electron injections under electrical pulses, which preferentially fill deep traps, causing the trap distribution of the device to transition from an exponential distribution to a single-level distribution. This primarily gives rise to a nonlinear change of conductance. Finally, the trap distribution becomes a single-level trap distribution, resulting in a linear change in conductance with the pulse number, provided that the pulse width and amplitude are carefully selected.

6.

A schematic diagram showing how the trap distribution changes with pulses

3.5. Performance Evaluation of the AZTA Artificial Synapse in SNN

Current studies that report linear synaptic devices tend to use ANN to evaluate how linearity could benefit classification accuracy. ,− However, an ANN typically employs global backpropagation to update the weights, and a write-and-verify algorithm has been proposed to compensate for the effects brought by the nonlinearity of the synaptic memristor. This algorithm employs iterative approaches to ensure that the weight is updated accurately to the target weight during training. Although high linearity can still facilitate faster classification due to a less iterative process in the algorithm, the nonlinearity will not have a significant negative impact on the overall classification accuracy of the network. In contrast, SNNs that use local weight updates during learning have a higher demand for linearity. Therefore, a two-layer temporal encoding SNN adapted from Sun et al. was constructed for MNIST data set classification to demonstrate the AZTA device’s suitability for efficient on-chip learning, as shown in Figure a. The AZTA synaptic device’s properties have been utilized in the high-level Python simulation to evaluate its performance. Specifically, the network employs quantized temporal encoding, a winner-take-all (WTA) mechanism, and simplified nonlinear STDP unsupervised learning for classifying the MNIST data set. A pseudocode can be found in Supplementary Note 3 of the SI. This code first crops the image in the MNIST data set into 24 × 24 = 576 pixels, encoding the intensity of each pixel into three quantized values that carry temporal information (t_in). The quantization is used here because the calculation of t_in originally involves complex computations, which cause a high computational burden. Sun et al. demonstrated that using this quantization will largely reduce the hardware computation cost without degrading the performance of the SNN. The quantized input spikes are then forward passed into the network, causing the membrane voltage to change and reach a threshold value of V_th. The postsynaptic neuron then generates an output spike at the t_out. The postsynaptic neuron with the smallest t_out will update all the synaptic weights connected to it (WTA mechanism) via simplified nonlinear STDP, where the synapse having t_out – t_in > 0 (presynaptic spike arrives earlier than the postsynaptic spike) will be potentiated via nonlinear LTP, and nonlinear LTD for those having t_out – t_in ≤ 0. The nonlinear LTP and LTD weight update equations can be derived from eq by assuming that only one pulse is applied to the device in every LTP and LTD. Therefore, the change in conductance is related to the current conductance state G_pn by eq from calculating G_pn+1 - G_pn:

$$\{\begin{array}{c}\mathrm{\Delta }{G}_P=[K-(G_{pn}-G_{min})]\left[1-\exp \left(-N{L}_P\times \frac{1}{\mathrm{\Delta }P}\right)\right]\\ \mathrm{\Delta }{G}_D=-[K-(G_{\max }-G_{pn})]\left[\exp \left(-N{L}_D\times \frac{1}{\mathrm{\Delta }P}\right)-1\right]\\ K=\frac{G_{max}-G_{min}}{1-e^{-NL\times P_{max}}}\end{array}$$ 9

, where G_pn is the current weight, ΔP is the total number of pulses (ΔP = 30, as shown in Figure d), and NL_P/NL_D are 0.17 and −0.7, respectively. In the network, the conductance can be mapped proportionally to the synaptic weight, allowing the maximum and minimum weights to be tuned to maximize accuracy. They are tuned as 6 and 0, respectively, in the Python simulation to achieve the best classification accuracy. After each update, the V_th is increased by ΔV to suppress the overly repetitive firing of the same output neuron. The tuned hyperparameters are listed in Table S2 of the SI. After training is completed, all output neurons are labeled by majority vote (i.e., the most frequent label of the sample that causes them to spike first). Finally, 1000 test samples are then randomly selected from the test data set to perform the inference. The classification accuracy after each epoch is presented in Figure b. By setting the output neuron number to 800, the network converges rapidly and reaches 90% classification accuracy after only 4 epochs. The convergence remains stable and reaches the best accuracy of 93.7% after 17 epochs. This is only 1.3% lower than the CMOS implementation of this temporal SNN, where each synapse has 9-bit data stored in dynamic random-access memory (DRAM) and utilizes a linear STDP scheme. This finding suggests that the single AZTA device has the potential to replace nine DRAM devices without significantly sacrificing performance in this SNN.

7.

(a) Schematic diagram of the two-layer SNN: pixels of input images in MNIST are cropped into 24 × 24 = 576, and the intensity of each pixel is then encoded into presynaptic time (t_in). The forward pass calculates time for each postsynaptic neuron (t_out). Then, all synaptic weights connected to the first spiking postsynaptic neuron, which has the minimum t_out, are updated using the simplified nonlinear STDP rule, as shown in eq . (b) Ten thousand training samples from the MNIST training data set are randomly selected and passed into the SNN in each epoch. Additionally, 1000 test samples are randomly selected to evaluate the classification accuracy after each epoch. Classification accuracy reaches around 90% after only 5 epochs when the number of output neurons is 800, achieving the best accuracy of 93.7% after 17 epochs. (c) The Gaussian Noise Ratio is defined as the ratio between the standard deviation of each weight and the current weight. AZTA has a low noise ratio, which results in minimal degradation of classification accuracy.

Figure S12 and Table S3 of the SI make a comparison of the synaptic performance between AZTA synapses and other synaptic devices when they are used in the SNN simulation. Their nonlinearity factors are calculated using the same model presented in this work (eq ) and are simulated within the SNN framework. After tuning the hyperparameters for all models, the best accuracies achieved are presented in both Table S3 and Figure S9 of the SI. The results show that the AZTA device achieves comparable accuracy to that of a perovskite memristor, which has demonstrated extremely high linearity (NL_P/NL_D = 0.002/0.0015). This performance is attributed to SNN being reported as tolerable to certain nonlinear factors. The nonlinearity of the AZTA device is small enough to saturate the accuracy that could be achieved by the SNN, thus indicating the high performance of AZTA. Apart from nonlinearity factors, noise after each update can also harm the network performance. Considering that the device conductance fluctuates and demonstrates Gaussian Noise after each update, the Gaussian Noise Ratio (GNR), which is the ratio between the standard deviation of each conductance and the conductance after each pulse, has been calculated using data from 1000 cycles presented in Table S1 of the SI. The GNRs during potentiation are mostly within the range of 0.02 – 0.3, with only three states having GNRs around 0.35. Moreover, the GNRs during depression completely fall within the range of 0.05 – 0.3. The noise ratio is then incorporated into the learning part of the Python code to evaluate its effect on classification accuracy. Figure S13 of the SI indicates that high GNRs can result not only in low classification accuracy but also in failure to converge after several epochs. By considering the highest accuracy achieved for each GNR value, Figure c shows that the low GNR of AZTA results in a negligible degradation of classification accuracy.

4. Conclusions

In conclusion, the nonfilamentary and e-BRS AZTA memristor has excellent potential for simulating artificial synapses in neuromorphic computing. By controlling the amplitude, length, and frequency of applied pulses, the weight of the synapse can be precisely regulated. As a result, the AZTA synapse exhibited highly linear and symmetric LTP and LTD. Furthermore, the synaptic weight variation remained consistent with the initial trend even after 1000 pulse cycles. The mechanism behind linear LTP is thoroughly studied by analyzing the trap distribution of four different states by the TMSCLC method. The reconstructed trap distribution model coincides well with the MH’s model, demonstrating the high reliability of the analysis. The model equations then indicate that both the deep exponential trap distribution region and the shallow single-level trap distribution can contribute to high linearity, and the transition between them causes nonlinearity. The careful selection of pulse amplitudes and the conductance range can result in a linear change in conductance with increasing pulse numbers.

Moreover, this unique conduction mechanism avoids the complicated pulse engineering problem in many CF-based RRAMs. Therefore, it exhibits tremendous potential for both low-power consumption and high-speed operation in ANN and SNN applications. The nonlinearity factors and pulse numbers have been utilized in the SNN simulation to demonstrate the performance of AZTA in SNN on-chip learning. The results indicate that the low nonlinearity factor falls within the tolerable region of SNN, and the device achieves its best accuracy of 93.7%. This accuracy outperforms many SNN networks and is only 1.3% lower than the CMOS-implemented architecture, which uses a linear weight updating rule. It suggests that the AZTA device has the potential to replace the 9-bit DRAM synapse without sacrificing too much performance.

Finally, although a reliable trap distribution is inferred from the TMSCLC spectroscopy, it is worth further investigation to reveal the trap distribution experimentally through well-established trap-sensitive spectroscopies, such as DLTS. Such an investigation will require a meticulously designed system of DLTS because the conventional DLTS equations are unsuitable for memristors. In addition, further optimizations of the retention and uniformity of the AZTA device to meet industrial standards are favorable. Meticulous annealing and electrode engineering are worth investigating as future research. ,

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsami.5c09911.

• Structural images of the device, schematic diagrams and the double-logarithmic fitting of the SCLC mechanism, DC endurance plot over 10⁵ cycles, analog switching characteristics at DC mode, area dependency of the pulse length, variation of the device to device in conductance, conductance switching with constant pulse length (DC read after each pulse SET), conductance switching with constant pulse length (no DC read after each pulse SET), EPSC characteristics with different pulse intervals, temperature test and Arrhenius fitting, retention curves of intermediate states, trap distribution of four states, nonlinearity comparison, mean values and standard deviations of all states in 1000 cycles, hyperparameters in SNN simulation, synaptic performance comparison, review on SCLC mechanism and validation of trap distribution reliability, TMSCLC analysis method, SNN pseudo code (PDF)

†.

Yu Lin Zou and Xiang Yuan Li contribute equally to this work.

This study was supported by the National Research Foundation of Korea (No.2020R1A3B2079882).

The authors declare no competing financial interest.