Large-scale complementary carbon nanotube integrated circuits for harsh radiation environments

Abstract

Silicon-based integrated circuits operating in radiation environments require additional and complex hardening configurations, leading to performance lags compared to the International Roadmap for Devices and Systems. Carbon nanotubes (CNTs), with their ultrastrong chemical bonds and nanoscale dimensions, offer substantial potential for high-performance, radiation-tolerant electronics. However, the challenges associated with radiation-tolerant fabrication processes have hindered the development of macroelectronics using complementary CNT transistors (CNTFETs). In this study, we successfully fabricated radiation-tolerant, highly symmetric, and uniform CMOS building blocks, implementing various logic gates (inverters, NAND, and XOR gates) and ring oscillators (ROs) with 5, 11, and 501 stages. After irradiation up to 6 Mrad(Si), all devices maintained rail-to-rail outputs, and notably, the 501-stage RO, comprising 1004 CNTFETs, showed minimal delay variation (10.3 ± 0.8 ns). This work demonstrates the radiation-tolerant of large-scale CNTFETs, paving the way for their potential replacement of silicon-based FETs in radiation-heavy environments.

CNTFET-based large-scale integrated circuits maintain robust performance post–6 Mrad(Si) irradiation.

INTRODUCTION

Advanced integrated circuits (ICs), benefiting from enhanced performance and integration achieved through transistor scaling (1–3), face substantial challenges in extreme environments such as high temperatures, pressures, and toxic atmospheres (4). While most of these issues can be addressed through enhanced packaging processes, similar strategies often fall short in radiation-heavy settings (5), such as deep-space exploration, nuclear power facilities, and radiation-based medical treatments. High-energy photons and ions can penetrate shielding layers, causing damage to channel materials and even triggering reactions within packaging materials (exacerbating the impact of irradiation). Irradiation-induced malfunctions or permanent damage to transistors notably reduce the reliability of these circuits, posing potential risks to critical equipment. To date, radiation-hardened ICs often require additional processing steps and more complex configurations than standard devices, leading to a lag behind the International Roadmap for Devices and Systems.

Carbon nanotubes (CNTs), known for their ultrastrong chemical bonds and nanoscale dimensions, are considered ideal materials for achieving high radiation tolerance (6, 7). Experiments on transistors based on semiconducting CNTs (6–10), or carbon nanotube field-effect transistors (CNTFETs), have shown that trapped charges can be induced in insulation layers (e.g., Si/SiO₂ substrates and gate dielectric layers). These trapped charges degrade the electrical performance of CNTFETs by shifting the threshold voltage (V_th), reducing carrier mobility (μ), and increasing gate current leakage (I_gs). To mitigate these issues, polyimide and ion gel were selected as the substrate and gate dielectric layer, respectively. This approach achieved a recorded total ionizing dose (TID) of 15 Mrad(Si) in P-type CNTFETs (7). Further analyses indicate that the substrate plays a more critical role in degrading device performance (11). By introducing a bottom-gate electrode to shield the electrostatic field from the substrate, a laser-equivalent TID of 10 Mrad(Si) was achieved for CNTFETs fabricated using a complementary metal-oxide semiconductor (CMOS)–compatible process (6). Despite these advances, further efforts are required to investigate the radiation response of large-scale complementary CNTFET circuits, which are essential for practical, radiation-tolerant electronic systems.

With the development of advanced techniques for material deposition (12–15) and device fabrication (16–20), various CNTFET-based logic gates (21–23), medium-scale ICs (24–26), and large-scale systems (27–29) have been implemented. However, most of these ICs rely solely on P-type devices to build CMOS circuits, while common circuit paradigms require the inclusion of N-type devices for low power dissipation and high noise margin. Current doping-free strategies involve air-sensitive low-work-function metals (30, 31), which are generally unsuitable for radiation environments. In addition, recent advancements based on aligned CNT arrays suffer from insufficient homogeneity (12), limiting the large-scale fabrication of high-performance CNTFETs. Irradiation-induced trapped charges within the Si/SiO₂ substrate degrade the electrical behavior of CNTFETs with a top-gate configuration (32), which is commonly used for its high gate efficiency (12, 15, 20, 29, 33). These challenges collectively present pronounced obstacles to the construction of complementary, large-scale, and radiation-tolerant ICs based on CNT materials.

In this work, we used an electrostatic doping strategy to fabricate local bottom-gate (LBG) complementary CNTFETs using solution-derived CNT network films. By leveraging these high-yield, high-uniformity, and high-symmetry CMOS building blocks, we successfully demonstrated various logic gates, including inverters, Not AND (NAND), and Exclusive OR (XOR) gates, all of which exhibited correct rail-to-rail Boolean functionalities. Moreover, these CNTFETs and logic gates showed remarkable radiation tolerance, maintaining their performance up to 6 Mrad(Si) at a dose rate of 300 rad(Si)/s. This performance demonstrated distinct superiority over silicon-based devices (34–38) and matched the level of CNTFETs reported in the literature (6–9, 32, 39, 40). To further validate the radiation response, we tested a 501-stage ring oscillator (RO) composed of 1004 transistors. The ultralow stage delay was maintained throughout the 6 Mrad(Si) irradiation process, averaging 10.3 ± 0.8 ns. Therefore, by using CMOS-compatible fabrication processes, we successfully verified the radiation tolerance of complementary CNTFETs at the large-scale level, paving the way for their application in radiation-heavy environments.

RESULTS

Design of radiation-tolerant CMOS building blocks

The cumulative radiation dose is typically quantified as the total energy absorbed per unit mass of material, measured in grays (Gy, the SI unit) or rads (1 rad = 0.01 Gy = 0.01 J/kg) (4). In our experiments, the dose rate was consistently maintained at 300 rad(Si)/s for all devices, and the specific TID was controlled by varying the irradiation time. The γ rays, which originate from the decay of cobalt-60 (⁶⁰Co), have energies of 1.17 and 1.33 MeV. These high-energy emissions are inherently destructive and can cause temporary or permanent damage to electronic devices through ionizing processes. In the case of CNTFETs, the damage typically begins with the generation of electron-hole pairs within the insulators, rather than in the metals or CNT channels (7). Because of the considerably higher mobility of electrons compared to holes (4), most electrons can rapidly migrate out of the insulator. A small fraction of these electrons may recombine along their migration path, while holes are often trapped by bulk defects or interface states, leading to degradation in the device’s electrical performance, such as shifts in the V_th and mismatches in CMOS building blocks.

To address this issue, complementary FETs with LBG architecture were designed and fabricated using solution-derived uniform CNT network films on a 4-inch (10.16-cm) Si/SiO₂ substrate (Fig. 1A). The device polarity is achieved through a CMOS-compatible electrostatic doping method (41–43). The fabrication process involved patterning and depositing the LBG electrode consisting of a Ti/Au (1/40 nm) stack. Following this, a 10-nm-thick HfAlO_x gate dielectric layer was grown using atomic layer deposition (ALD). After depositing the CNT network film, oxygen plasma was used to define the channel region. The source/drain electrodes for both P-type metal-oxide-semiconductor (PMOS) and N-type MOS (NMOS) devices were set as a Ti/Pd/Au (0.5/20/20 nm) stack. Last, a 10-nm HfO_x layer was grown on top of the device’s surface to serve as both a doping and isolation layer. Figure 1B shows an optical image of the fabricated complementary circuits, which include individual CNTFETs, inverters, NAND gates, XOR gates, and different-stage ROs. Figure 1 (C and D) shows arrayed and individual CMOS devices, respectively, with a channel length/width of 4/30 μm. The scanning electron microscope (SEM) image in Fig. 1E confirms the high density of the deposited CNT network films. The high quality and homogeneity of the film were further verified by the Raman spectrum and disordered/graphitic (D/G) peak mapping distributions (inset of Fig. 1E and fig. S1). These results collectively implied the high current density and uniformity of the fabricated CMOS building blocks.

Fig. 1. Large-scale radiation-tolerant complementary CNT ICs.

(A) Schematic diagram showing the γ-ray irradiation process on large-scale complementary CNT ICs. The enlarged view illustrates CNT network film–based CMOS FETs. GND, round. (B) Photograph of the fabricated CNT devices with dimensions of $8.5\text{by}9.5$ mm. (C) Microphotograph of a typical CNT IC. Scale bar, 300 μm. (D) Microphotograph of a typical CNT CMOS FET. Scale bar, 10 μm. (E) SEM image of the deposited CNT network film. Scale bar, 200 nm. Inset: Raman spectrum of the deposited CNT network film. Laser wavelength, 532 nm.

Highly symmetric and uniform CMOS building blocks

In our fabrication processes, the ALD technique enabled us to modulate the polarity of CNTFETs by adjusting the oxygen content in the HfAlO_x and HfO_x insulating layers. Specifically, oxygen vacancies in these layers correspond to N-type doping of the CNT channel, while oxygen enrichment corresponds to P-type doping. Given palladium’s (Pd) large work function, it formed an ideal ohmic contact with hole-doped CNT channels. Conversely, for electron-doped channels with Pd contacts, electrons needed to tunnel to enter the channel. Despite this, the sufficiently narrow tunneling barrier width ensured that quasi-ideal ohmic contacts were still achievable for NMOS devices (Fig. 2A).

Fig. 2. Highly symmetric and uniform CMOS building blocks.

(A) Band diagrams of the Pd contact PMOS and NMOS devices in the “on” state. (B) Transfer curves of the PMOS (blue) and NMOS (red) devices, with |V_ds| varying from 0.2 to 2 V in steps of 0.2 V. (C) Output curves of the PMOS (blue) and NMOS (red) devices, with |V_gs| varying from 0 to 2 V in steps of 0.2 V. (D) Transfer curves of 150 PMOS (left) and 150 NMOS (right) devices, with V_ds set at −2 and 2 V, respectively. (E) Statistical analysis of the I_on, I_off, SS, and V_th for the PMOS (blue) and NMOS (red) devices shown in (D).

Electrical measurements were performed under room temperature and atmospheric conditions. Figure 2B shows the transfer curves (I_ds-V_gs) of the fabricated CMOS building blocks. The decreasing behavior of |I_ds| as |V_gs| is reduced from 2 to 0 V, observed for both PMOS (blue lines) and NMOS (red lines), clearly verifying the effective electrostatic doping of the CNT channels. The output curves shown in Fig. 2C demonstrated ideal current control and saturation for these CMOS building blocks. At low bias, linear relationships between I_ds and V_ds were observed for both PMOS and NMOS devices, confirming the quasi-ohmic contact in these devices. Assessing the on/off ratio at the saturated voltage (|V_ds| = 2 V for our devices), rather than the ultrasmall bias conditions, was more relevant for the following circuit applications (44); thus, values of 10^3.6 and 10^4.1 could be calculated from the transfer curves of PMOS and NMOS, respectively. On-state current density (I_on) of more than 2 μA/μm was achieved for both PMOS and NMOS devices at a −2 and 2 V supply voltage, respectively. This corresponds to an extracted transconductance of 58.1 μS for PMOS and 53.1 μS for NMOS. This comprehensive performance places our CNTFETs among the highest-grade CNTFETs based on CNT network films with micrometer-scale channel lengths (18, 20–22, 25, 29, 41–43, 45–47).

The symmetry between the PMOS and NMOS devices was clearly demonstrated by the nearly mirror-like output curves. A further statistical analysis of 150 PMOS and 150 NMOS devices revealed very close driving abilities of 2.26 μA/μm (PMOS) and 2.24 μA/μm (NMOS), with a difference of only 0.89% of each other. The similarity in I_off and subthreshold swing (SS) values collectively confirmed the high performance and perfect symmetry of the fabricated CNTFETs. The V_th of these enhanced devices were distinctly separated, with values of −0.21 V for PMOS and 0.36 V for NMOS. This separation ensured that electrons could not freely penetrate the CMOS circuits at any time, thereby enabling the low-power dissipation properties. In addition, the statistical measurements were conducted across a 25.5 mm–by–28.5 mm area using a semiautomated probe station. The results in Fig. 2 (D and E) indicated that I_on, I_off, SS, and V_th exhibited minimal performance fluctuations. This uniformity is largely attributed to the reliability of the electrostatic doping strategy and the optimized device fabrication processes. These factors laid a solid foundation for the preparation of large-scale circuits.

High noise margin CMOS devices with TID tolerance up to 6 Mrad(Si)

γ-Ray irradiation was performed on the aforementioned CMOS building blocks. After each irradiation, transfer curves were measured to assess the performance shifts in these devices. It is important to note that displacement testing may induce the release of relatively shallow-level trapped charges from their trap centers at room temperature, potentially leading to partial recovery of irradiation effects before electrical measurements. To mitigate this, irradiation test processes similar to those used for Si FETs were followed. Specifically, all samples were promptly preserved in dry ice (−78.5°C) after each irradiation; the interval between consecutive irradiation sessions were kept under 24 hours; and electrical measurements at room temperature were conducted within 1 hour.

We statistically analyzed the irradiation performance of 25 PMOS and 25 NMOS devices. Figure 3A shows the transfer curves at irradiation doses of 0, 3, and 6 Mrad(Si). Devices of the same polarity exhibited highly consistent variations, highlighting the remarkable uniformity and stability of the fabricated FETs. Both PMOS and NMOS devices showed a negative V_th shift, accompanied by a decrease in I_on for PMOS and an increase in I_on for NMOS devices, respectively. Figure 3C statistically illustrates the changes in V_th and I_on with respect to the irradiation dose. These trends can be attributed to the positive trapped charges induced by γ rays within the insulating layers, which could be further optimized through thinning gate dielectric thickness and refining device architecture (note S1 and fig. S2). Trapped charges at shallow energy levels can be released through high-temperature annealing processes. Figure S3 demonstrates the transfer curves of a typical device after annealing for 10 min at temperatures ranging from 30° to 300°C. As the annealing temperature increased, the electrical performance of the device initially deteriorated, possibly due to the redissociation of electron-hole pairs caused by thermal energy. However, the performance gradually recovered, although it did not fully return to the preirradiation state, indicating the presence of unreleased deep-level trap charges. Notably, a pronounced recovery was observed at 141.8°C, suggesting a high concentration of trapped charges at this energy level. When the annealing temperature was increased to 175°C, the V_th shift was further reduced to within 0.2 V (10% of V_DD), indicating successful release of most of the residual trapped charges. Figure 3D benchmarks the TID versus I_on of our results against reported values (6–10, 32, 40). This highlights that our devices achieve a large TID value of 6 Mrad(Si) while maintaining a high current density exceeding 2 μA/μm. In particular, our fabrication process is compatible with CMOS technology (note S2), which is critical for the development of large-scale ICs.

Fig. 3. γ-Ray irradiation on complementary CNTFETs.

(A) Transfer curves of 25 PMOS and 25 NMOS devices irradiated at 0, 3, and 6 Mrad(Si), respectively (|V_ds| = 2 V). (B) Transfer curves of a typical PMOS and NMOS device irradiated at 0, 3, and 6 Mrad(Si), respectively (|V_ds| = 2 V). (C) Statistical analysis of the changes in V_th and I_on for 25 PMOS and 25 NMOS devices irradiated from 0 to 6 Mrad(Si). (D) Benchmarking of the TID versus I_on for our results compared to reported radiation-hardened CNTFETs (6–10, 32, 40), highlighting the notable improvement in both radiation tolerance (TID) and driving capability (I_on), as well as the compatibility with the silicon CMOS process. (E) Voltage transfer curves of 25 CNT CMOS inverters, demonstrating abrupt switching from V_IN = 0 V to V_IN = 2 V. Left inset: Photograph of a typical fabricated CNT CMOS inverter. Scale bar, 30 μm. Right inset: Circuit diagram of the CMOS inverter. (F) Voltage transfer curves of a typical inverter irradiated at 0, 2, 4, and 6 Mrad(Si), respectively. (G) Butterfly curves of the fabricated CMOS inverter irradiated at 4 Mrad(Si). NM_H and NM_L are labeled in the dashed line boxes. Right inset: V_IN-dependent voltage gains of a typical inverter irradiated at 4 Mrad(Si). (H) Statistical analysis of the transition voltage (V_T), gain, NM_H, and NM_L for the devices shown in (E) irradiated from 0 to 6 Mrad(Si).

With the radiation-tolerant, highly symmetric, and uniform PMOS and NMOS devices, high-performance CMOS circuits were further designed and fabricated using similar fabrication processes. A total of 25 devices were tested and plotted in Fig. 3E, demonstrating a 100% yield and nearly uniform transition voltages (V_T) of 1.2 V. As the radiation dose increased, V_T progressively shifted to the negative side. Concurrently, static power consumption exhibited substantial enhancement—reaching ~5 μW at 6 Mrad(Si)—while dynamic power remained stable throughout irradiation (fig. S4). This behavior corresponds to an enhancement in the driving capability of the NMOS devices and a reduction in that of the PMOS devices (Fig. 3F). The observed trend aligns well with the data presented in Fig. 3 (A to C). By performing butterfly curve testing on the fabricated inverters, we found that the preirradiation devices had a high-level noise margin (NM_H) of 0.37 V and a low-level noise margin (NM_L) of 0.78 V (fig. S5). At a radiation dose of 4 Mrad(Si), these values shifted to 0.65 and 0.54 V, respectively, accompanied by a voltage gain as high as 11.1 (Fig. 3G). The statistical results in Fig. 3H showed that, although V_T, NM_H, and NM_L exhibited noticeable changes with increasing radiation dose, even at 6 Mrad(Si), all devices still maintained correct logic functions, primarily due to the high noise margins of the fabricated CMOS devices.

Radiation-tolerant CNT ICs

NAND and XOR logic gates were further fabricated using the highly symmetric and uniform CMOS building blocks. At an operating voltage of 2 V, all tested devices (10 NAND and 10 XOR gates) demonstrated rail-to-rail outputs, achieving a 100% yield. In detail, Fig. 4C shows the output of the NAND gate, which returned a signal “0” only when both inputs were “1,” corresponding to the turning off of all PMOS devices. Figure 4F exhibits the output of the XOR gate, which returned a signal 0 only when the inputs were the same. Benefiting from the high noise margin of the fabricated CMOS devices, all logic gates maintained correct logic functionalities even after an irradiation dose of 6 Mrad(Si). This robust performance under high radiation doses underscores the effectiveness of the radiation-tolerant design and fabrication process used.

Fig. 4. γ-Ray irradiation on CNT circuits.

(A to C) Circuit diagram (A), photograph (B), and output characteristics (C) of the fabricated NAND gate with V_DD = 2 V. (D to F) Circuit diagram (D), photograph (E), and output characteristics (F) of the fabricated XOR gate with V_DD = 2 V. All logic gates maintained rail-to-rail outputs even after irradiation of 6 Mrad(Si). (G) Photograph of a typical 501-stage RO. Scale bar, 200 μm. (H) Output waveforms of the typical 501-stage RO irradiated at 0, 2, 4, and 6 Mrad(Si), respectively (V_DD = 2 V). (I) Dependence of the oscillation frequency ( $f_0$ ), stage delay ( ${\mathrm{\tau }}_{\text{SD}}$ ), average output voltage (V_ave), and peak-to-peak output voltage to supply voltage ratio (V_PP/V_DD) on TID with V_DD = 2 V. (J) Benchmarking of ${\mathrm{\tau }}_{\text{SD}}$ versus V_PP/V_DD for our results compared to reported CNT ROs with micrometer channel lengths (23, 26, 43, 48–54). The supply voltage is labeled in the unit of volts (V). (K) Comparison of the integration level of radiation-hardened CNT-based devices (6–9, 32, 39, 40, 55).

To sensitively reflect the influence of irradiation on circuit performance, ROs with different stages, including 5, 11, and 501 stages, were fabricated (note S3). Figure 4G presents a typical photograph of the 501-stage RO, which includes an additional inverter stage as an output buffer for electrical measurements. At a supply voltage of 2 V, the 501-stage RO exhibited periodic oscillatory behaviors with amplitudes reaching 80% of V_DD, which is crucial for high-quality signal readout. As shown in Fig. 4H and fig. S6, the oscillation frequencies (f₀) of the 5, 11, and 501-stage ROs were 300, 148, and 105 kHz, respectively. The stage delay can be estimated as ${\mathrm{\tau }}_{\text{SD}}=1/\left(2N{f}_0\right)$ , where N is the number of inverter stages. Notably, a relatively low stage delay of 9.48 ns was achieved for the fabricated 501-stage RO, which can be attributed to the highly symmetric and uniform CMOS building blocks as well as the optimal design of the transmission lines. Figure 4J benchmarks the stage delay versus the V_PP/V_DD ratio of our results against values in the literature for CNTFETs with micrometer channel lengths (23, 26, 43, 48–54). This comparison highlights the relatively low stage delay and high V_PP/V_DD values achieved in our devices. The γ-ray irradiation was further performed on these ROs. Even with the irradiation dose increasing to 6 Mrad(Si), all devices demonstrated correct output functions, with only slight variations in oscillation frequencies and a minimal decrease in output amplitudes, consistent with the irradiation results of individual CMOS devices. Careful analysis found that the irradiation-induced fluctuation in stage delay typically did not exceed 0.8 ns ( $7.9\%$ of ${\mathrm{\tau }}_{\text{SD}}$ ), thus highlighting the excellent radiation tolerance of the isolated CNTFETs and the high noise margin of the CMOS circuits.

To date, the number of FETs in reported radiation-tolerant carbon devices typically ranges from 1 to 6, including single FETs, single CMOS inverters, or single static random access memory (SRAM) cells. The successful demonstration of radiation-tolerant performance in a 501-stage RO has increased the number of FETs in these devices by at least two orders of magnitude (Fig. 4K). While current experimental and technological limitations prevent precise evaluation of the maximum reliably manufacturable circuit scale, this notable achievement represents a critical step toward the practical application of radiation-tolerant carbon-based devices. It should be emphasized that, although the logic gates and the 501-stage RO function well after irradiation doses of 6 Mrad(Si), the V_T of the corresponding CMOS circuits has been shifted. This raises the issue of irradiation failure criteria at the circuit level. Essentially, the irradiation-induced trapped charge leads to a shift in the V_th of a single component, which in turn results in a mismatch in the driving capabilities (I_on) of PMOS and NMOS transistors. This mismatch ultimately causes a shift in the CMOS transition voltage, increasing the risk of circuit failure. Ideally, as long as the noise margin of the CMOS circuit is not zero, ICs based on this design should be able to function properly. However, considering the complex environmental factors in real circuits, we have adopted a noise tolerance of 10% V_DD as a critical criterion for circuit failure in our work (note S4).

DISCUSSION

We have successfully implemented large-scale, highly radiation-tolerant complementary CMOS circuits using solution-derived CNT network films, achieving exceptional radiation performance up to 6 Mrad(Si) and a stage delay of approximately 10 ns in a 501-stage RO consisting of 1004 FETs. High-performance complementary CNTFETs were fabricated through a meticulously controlled electrostatic doping method, featuring high symmetry, uniformity, and stability. These characteristics ensure that devices of the same polarity exhibit similar irradiation behaviors. Both PMOS and NMOS devices showed irradiation-induced negative shifts in V_th, attributed to trapped positive charges in the insulation layers. Our LBG architecture effectively mitigates the impact of substrate charges, enabling a relatively high TID tolerance of 6 Mrad(Si). Moreover, these highly symmetrical CMOS building blocks provide a high noise margin for the CMOS inverter output. Various stage ROs, including a 501-stage RO with 1004 FETs, have been successfully fabricated. Operating at a supply voltage of 2 V, the 501-stage RO achieved an output amplitude of 80% of V_DD and exhibited an ultralow stage delay of 9.48 ns, substantially outperforming all micrometer-scale CMOS devices. Even after exposure to irradiation doses up to 6 Mrad(Si), all devices, including inverters, NAND, XOR, and ROs, maintain accurate logic functionalities with rail-to-rail output. This achievement represents a notable step forward in the development of robust and high-performance electronics for radiation-heavy environments.

MATERIALS AND METHODS

Preparation of semiconducting CNT solutions

Raw single-walled CNTs, synthesized using the arc-discharge method, were purchased from Carbon Solution Inc. Semiconducting CNTs were sorted using conjugated PCz (poly[9-(1-octylonoyl)-9H-carbazole- 2,7-diyl]) molecules. Specifically, PCz (200 mg) and raw CNTs (100 mg) were first mixed in the toluene solvent (100 ml). The mixture was then sonicated for 30 min using a top-tip dispergator (Sonics, VC500). After sonication, the solution was centrifuged at 30,000g for 2 hours to remove bundles and insoluble materials. Last, high-purity semiconducting CNTs were obtained from the supernatant.

Characterization of CNTFETs and ICs

Raman spectroscopy was performed on the HORIBA LabRAM HR Evolution spectrometer with a laser wavelength of 532 nm. SEM imaging was conducted on a Zeiss GENMINI SEM 500. Optical images were captured using a Nikon MM-400/L. Electrical performance was measured on a semiautomated probe station (MPI TS2000) equipped with self-made LabVIEW programs. For logic gate measurements, the input signal was generated by a signal generator (Agilent, 33622A), and the output signals were captured by an oscilloscope (Tektronix, TBS1202C).

γ-Ray irradiation on CNT-based devices

Cobalt-60 (⁶⁰Co) was used as the irradiation source, with a half-life of 5.27 years and decay producing two types of γ rays $({}_{27}{}^{60}\text{Co}\to {}_{28}{}^{60}\text{Ni}+{}_{-1}{}^0\mathrm{\beta }+{}_0{}^0\mathrm{\gamma })$ . The TID was directly proportional to the irradiation time, with a constant dose rate of 300 rad(Si)/s maintained in our experiments. Irradiation was conducted without applying any voltages to the CNTFETs and ICs. After each irradiation session, the samples were promptly preserved in dry ice at a temperature of −78.5°C. The interval between consecutive irradiation sessions did not exceed 24 hours. Postrecovery testing at room temperature was limited to 1 hour or less. During each heating cycle, a plasma fan was used to blow over the condensation on the sample box and device surface.

Supplementary Materials

This PDF file includes:

Notes S1 to S4

Figs. S1 to S6