A novel and optimized design of D-latch and D flip-flop for QCA-based digital systems

Abstract

Quantum-dot cellular automata (QCA) technology represents a promising approach in quantum electronics and nanoscale digital systems. Nevertheless, QCA-based circuits continue to face challenges related to minimizing cell count, optimizing area efficiency, and reducing delay. This study proposes a novel D-latch with set and reset capabilities, along with a rising-edge-triggered D flip-flop featuring similar functionalities, and a compact 4-bit shift register. The proposed D flip-flop employs 28 cells, occupies an area of 0.02 μm², and achieves a delay of 0.5 clock cycles. Similarly, the D-latch consists of 18 cells, occupies 0.01 μm², and demonstrates comparable delay performance. Relative to previous designs, the proposed D-latch shows a 34.87% reduction in cell count and a 60% decrease in area, while the D flip-flop exhibits improvements of 44.5% and 55.6% in these metrics, respectively. These results suggest enhanced compactness and efficiency compared to selected existing works, supporting the potential for low-power, high-density circuit implementations within QCA technology. All simulations were conducted using QCA Designer version 2.0.3, following established QCA design principles.

Introduction

QCA technology is based on an array of quantum dots organized as discrete cells in a grid structure. Each QCA cell typically comprises multiple quantum dots, within which electrons interact collectively. In this configuration, the movement of electrons between quantum dots induces frequency and phase variations in the circuit’s output signals. To regulate these variations and facilitate logic operations, a clocking mechanism is essential. In QCA circuits, clocking is achieved by applying an external clock signal directly to the QCA cells¹. By modulating the phase of the clock signal, electron transitions occur between quantum dots, enabling the execution of logic operations. This clock signal is typically applied electrically to the QCA cells and may be either alternating or pulsed. Through this mechanism, electron movement within the QCA structure becomes synchronized, ensuring coordinated operation across the circuit. As a result, various logic functions can be accurately controlled and synchronized. QCA technology has gained considerable interest due to its inherent advantages over conventional silicon-based systems, including higher operational speed, lower power consumption, and significantly reduced physical dimensions. These attributes make QCA a promising approach for the design of high-speed, energy-efficient electronic circuits^2–5. Reference⁶ illustrates the QCA cell model effectively. Each cell is typically fabricated from metal or semiconductor materials and consists of four quantum dots arranged at the corners of a square. Within the cell, two electrons are positioned diagonally in opposite quantum dots due to Coulombic repulsion, which prevents them from occupying adjacent locations. This diagonal configuration represents binary logic states, with the two possible polarizations corresponding to logic ‘1’ and ‘− 1’. In QCA circuits, data transmission occurs via electromagnetic interactions, rather than conventional current flow. In QCA technology, information propagation is controlled by a specialized clocking mechanism that synchronizes signal flow and logical operations across the circuit. This mechanism operates through four distinct phases: switch, hold, release, and relax. These sequential stages facilitate controlled electron transitions and ensure proper timing in logic execution. The primary logic components in QCA are the majority gate and the inverter (NOT gate). The majority gate performs a “majority voting” function, where the output reflects the most common value among its three inputs. This operation is mathematically expressed as M(A, B, C) = AB + AC + BC. By assigning a constant logic value (‘1’ or ‘0’) to one of the inputs, the majority gate can be configured to function as an AND or OR gate, offering high versatility in logic circuit design. Meanwhile, the NOT gate inverts the input signal, enabling the realization of complementary logic functions within QCA circuits⁷.

In QCA circuits, clocking plays a crucial role in synchronizing signal transitions and data processing. Clock-0, as one of the clocking phases, directly impacts how data propagates and is stored in the output. In the proposed design, Clock-0 is embedded in the output to ensure proper data transmission and processing. This embedding ensures that the stored data in the proposed latch or flip-flop remains stable, preventing potential instabilities or errors. Additionally, the QCA clocking mechanism enables stepwise and synchronized data transfer between cells. Thus, Clock-0 contributes to delay optimization, reduced energy consumption, and improved circuit reliability. As a result, integrating Clock-0 in the output enhances signal stability, minimizes errors, and ensures data integrity in the proposed design⁸.

Also, the ability to deploy this technology at nanometer scales allows for the integration of more electronic circuits in a single chip. In contrast, CMOS and VLSI technology use silicon and metal oxide semiconductor structures to make transistors and electronic circuits. These technologies also have their advantages, such as good performance and the ability to integrate large electronic circuits. Nevertheless, QCA technology is proposed as an innovative and advanced alternative to CMOS and VLSI due to its high speed, lower power consumption, and deployment capability at nanometer scales. And it can make important improvements in the performance and efficiency of electronic circuits in the future⁹.

These steps generally cover the clocking process in QCA technology, but there may be more details in the design and implementation of QCA circuits that depend on the specific characteristics of each circuit and the intended tasks.

As mentioned, designing digital circuits in QCA technology has many advantages. Latches are circuits that store the information in the data input (D) when the input clock is activated but flip-flops are sensitive to the rising edge, when the high edge of the clock appears, store the information in the data input (D) until the next edge of the input clock. Flip-flops and Latches are widely used in the construction of large digital circuits. For example, they are very effective for making counters, detectors, and other circuits. This article presents innovations that include:

• New latch design with reset capability with the least possible cell.

• New latch design with set and reset capability with very low area and energy consumption.

• New rising edge sensitive D-flip-flop design with reset and set capability with the least possible cell and smallest area.

• New design of four-bit shift register with very low time delay and small area.

The proposed work, while presenting optimized designs in QCA technology, has certain limitations. One significant limitation is that QCA technology is primarily in the simulation phase, and there is no commercial fabrication process available yet, making real-world implementation challenging. Additionally, the scalability of the proposed designs for larger and more complex circuits may introduce new challenges, such as increased signal delays and energy dissipation. Another limitation is the absence of traditional clocking mechanisms in the proposed designs, which may restrict their compatibility with certain QCA paradigms. Addressing these limitations requires further research in practical fabrication techniques, advanced clocking mechanisms, and testing the designs for larger digital systems. Despite these challenges, the presented work establishes a foundation for future innovations in QCA-based digital circuits. This article has several parts. In the first part, it examines the work of others to better visualize its new designs. In the second part, it introduces the proposed designs and explains the advantages of the design of this article compared to various references. In the third part, simulation results are presented to prove the high validity of the proposed designs. In the last part, it is said about the conclusion and suggestions for continuation.

Related work

Sequential and combinational circuits are two main types of electronic circuits that have important differences in their design and performance. In the following, we explain each of these two types of circuits.

Sequential circuits

Sequential circuits contain memory elements and their output state depends on the state of previous inputs and their internal state (state). In other words, the output of a sequential circuit depends not only on the current state of the input but also on its previous state. Memory elements such as flip-flops and registers are among the typical elements of sequential circuits. These circuits are widely used in applications that require information storage and management, such as memory circuits, control systems, and user interfaces.

Combinational circuits

Combinational circuits operate only based on the current state of their inputs and are not dependent on their previous state or internal state. The output of these circuits only depends on the current values of the inputs and the environmental conditions of the circuit, and as a result, they produce the output immediately and without delay. These circuits are used to perform logical operations such as addition, multiplication, Boolean logic, and so on. They are used in applications that require immediate processing of data and information.

In electronic applications, both sequential and combinational circuits are often used simultaneously to perform the required functions. For example, control circuits typically include a combination of these two types of circuits, where the combinational circuits perform logical operations, and the sequential circuits serve as memory and operation controllers. Latches and flip-flops are key memory elements in digital circuits that store the state of their inputs and retain this information until their clock signal is activated. Specifically, the behavior of a D-latch is determined by the type of clock input and control signal. Among these, the D-latch is well-known for its clock sensitivity. When the clock signal transitions from low to high, the data input (D) is transferred to the latch output. Since the latch retains this information as long as the clock is active, it can synchronize operations in digital circuits effectively. The D-flip-flop, another important memory element, operates similarly to the D-latch but is sensitive to the rising edge of the clock signal. When the clock signal transitions from low to high, the data input (D) is transferred to the output. Flip-flops like the D-flip-flop are commonly used in applications requiring synchronization and optimal behavior with clock signal transitions, such as counters and detectors.

Several studies have focused on designing simple D-latches, D-latches with set/reset functionality, and flip-flops^10–24. Table 1 summarizes the weaknesses of several existing D-latch and D-flip-flop designs, highlighting the key limitations such as high cell count, large area, and significant delay.

Table 1.

Comparison of previous D-latch and D-flip-flop designs and their weaknesses.

Reference	Design	Number of cells	Area (um²)	Delay (clock cycles)	Key weaknesses
12	Simple D-latch	48	0.05	1	High area and cost, making it economically unfeasible for practical applications.
17	D-latch for PFD design	28	0.03	0.5	Complex design with multiple gates, still not optimal in terms of scalability and simplicity.
10	D-latch (simple, set/reset)	30	0.02	1	High number of cells for set/reset functionality, resulting in larger area compared to other designs.
22	D-latch (simple, set/reset)	21	0.01	1.25	Despite reducing the cell count, the delay of 1.25 clock cycles limits its performance in high-speed apps.
24	Optimized D-latch	36	0.03	0.75	Higher delay compared to other optimized designs, not ideal for applications requiring low delay.
20	D-flip-flop (rising edge)	84	0.11	2.5	Excessive cell usage, high delay, inefficient for practical use due to high complexity and cost.
10	D-flip-flop (rising edge, reset)	53	0.04	2.25	High delay and excessive use of cells make it unsuitable for cost-effective, large-scale applications.
22	D-flip-flop (reset)	41	0.03	1	Large number of cells and area, not ideal for future implementations requiring small area and low cost.

As indicated in Table 1, various D-latch and D-flip-flop designs suffer from a variety of issues, such as high cell count, large area, and substantial delays. These factors make them less practical for large-scale, cost-sensitive, and high-speed applications. For instance, Hashemi et al.‘s D-latch design¹² suffers from a significant increase in area and cost due to the high cell count, which limits its practicality. Similarly, Alamdar’s design¹⁷ improves the delay but still involves a relatively complex circuit with multiple gates, making it less scalable. In contrast, our proposed design addresses these limitations effectively. By optimizing the number of cells and minimizing the area required for the latch, our design offers a more compact solution with a significantly reduced delay compared to existing designs. Additionally, our design strikes a balance between minimizing the delay and reducing the area, making it both cost-effective and suitable for high-speed applications. Unlike previous designs that suffer from high complexity and unnecessary gate usage, our approach ensures a more efficient use of resources, making it a more practical choice for modern digital circuits.

Moreover, our work improves upon the previous designs in terms of both functionality and performance. For example, while other designs such as those by Gholamnia et al.¹⁰ and Amirzadeh et al.²² focus on reducing the number of cells, they still face challenges in terms of delay and scalability. Our design not only reduces the number of cells but also significantly lowers the delay, which is crucial for applications where speed is critical. Therefore, our approach presents a more optimal solution compared to the designs reviewed in the literature.

In 2012, Hashemi and his colleagues were able to design a simple D latch with 48 cells, an area of , and Design a delay of one clock cycle¹². With this design, the size of the D latch circuit as well as its price increases greatly. As a result, it is not economical to make and use. In 2020, Alamdar designed a D latch with 28 cells, an area of , and a delay of 0.5 clock cycles for the design of a PFD (Phase-frequency detector)¹⁷. In this design, three majority gates and one not gate are used. It applied two inputs, data(D) and clock to one of the majority gates and then applied the inverted clock to one of the inputs of the second majority gate. The second input of the second majority gate is given to the output of the third majority gate so that it can make the output feedback to one of the inputs of the multiplexer so that the output of the circuit can keep its previous value when the clock is zero.

In 2018, Gholamnia and his colleagues designed a D-Latch with 30 cells, a delay of one clock cycle, and an area of , which are simple, set and reset, respectively¹⁰. The disadvantages of this design are a large number of cells for set and reset mode and a higher area than other references. In 2022, Amirzadeh and his colleagues were able to design D-latch with 21 cells, a delay of 1.25 clock cycles, and an area of um², which are simple, and also use set, and reset²². In this design, four majority gates and one not gate are used. Then, for optimization, they have reduced the number of majority gates to have a circuit with fewer cells and a small area. Finally, in 2024, Alghosi and his colleagues designed a latch with 36 cells, an area of um², and a delay of 0.75 clock cycles²⁴. In the simulation and results section, we will compare more articles in a table so that we can show the accuracy and optimality of our work.

The trigger of a flip-flop is the momentary changes caused by the change of the input clock, which is called triggering. Flip-flops read the data (D) value by changing the input clock level and keeping it until the next clock. In addition to simple D-flip-flops, Rising and Falling edge-sensitive D-flip-flops can be designed, which have many applications in the design and construction of PFDs, counters, etc. Here, some examples of D-flip-flops with reset and set, simple D-flip-flops will be studied so that you can have a better view of the designs proposed in this article. In 2014, a flip-flop with 84 cells, a delay of 2.5 clock cycles, and an area of um² was designed by Dutta²⁰. The disadvantages of this design are the high delay and the large number of cells. It can be said that this architecture is not cost-effective for construction in terms of area and the large number of cells. In 2018, Gholami and his colleagues designed a D-flip-flop with a rising edge that can set and reset the output using 53 cells, a delay of 2.25 clock cycles, and an area of um²¹⁰. This design also has the same problem of long-time delay and extra used cells, which cannot be used for construction in the future. In 2022, Amirzadeh and his colleagues designed a D-flip-flop with reset with 41 cells, a delay of 1 clock cycle, an area of , and a simple D-flip-flop with 34 cells²². This design has many cells and a large area, which can be said to be of little use for construction in the future. For more comparison in the results and simulation section, we review more and newer articles to have a better view of this domain.

In conclusion, our proposed design stands out by addressing the key drawbacks of existing D-latch and D-flip-flop designs, offering improvements in terms of area, delay, and scalability. These advancements make our design more suitable for practical implementation in modern digital systems, particularly in applications where low area, low delay, and high scalability are essential.

Proposed designs

In this section, we want to introduce the proposed designs that are done in the best possible way. This section has several sub-sections that fully describe each of these designs along with figures. By reading this section, researchers will get a good view of the proposed designs and get to know the proper performance of each design.

Figure 1 illustrates the overall design flow of the proposed QCA-based sequential circuit. As shown in the flowchart, the process begins with the design of a D-latch structure, continues with the development of a rising edge detector and the combination of these blocks to form D-Flip-Flop, and finally leads to the construction of a 4-bit shift register. The methodology focuses on optimization in terms of cell count, area, and latency.

Fig. 1.

Flowchart of the proposed QCA-based design methodology for sequential circuits.

Proposed optimized D-latch with reset

As explained in previous sections, latches are memory elements. Therefore, by using this type of memory element, binary information can be stored well. As a result, the design of latches is of special importance. We also know that to design the latch, we need a multiplexer, which this paper uses the multiplexer introduced in²⁵. Figure 2 shows a proposed D-latch with reset and set capability. The proposed structure has a clock input, a data input (D), and a reset pin. The operation of this proposed structure is as follows: when the input clock is in the state of one, the data input (D) value is directly displayed in the output. And then, when the input clock becomes zero, the output keeps its previous value until the one-dimensional clock. The reset pin is activated with zero. As a result, in the meantime, if the reset becomes zero, the output becomes zero. Even if the data (D) pin is one or zero. Figure 3 shows the block diagram of the proposed D-latch with reset capability. Using the same block diagram, we designed and implemented the structure in the QCA simulator, which Fig. 2 shows well.

Fig. 2.

Designing a proposed D-latch with reset capability.

Fig. 3.

Block diagram for the proposed D-latch block diagram with reset capability.

As Fig. 2 shows, the proposed D-latch has 18 cells, a delay of 0.5 clock cycles, and an area of . As a result, it can be said that this design is among the best and most optimal designs available among different authorities. Because it has very low energy consumption, a small area, and most importantly less number of cells.

Now, to check the stability of the circuit, consider Fig. 4 to perform the fault analysis of the proposed D latch with reset capability. According to Fig. 4, fault analysis is done by adding and removing cells. We are careful that the input and output cells do not play a role in adding or removing cells. As a result, the lost cells are: 3, 4, 5, 6, 7, 8, 10, 13, 14, 15, 16. And the added cells are: 1, 2, 9, 11, 12. According to Fig. 2 the actual output of D-latch with reset capability is 00110111000. To check the error by removing and adding each cell, their output is compared with the actual output. Table 2 presents the faults due to a single cell missing and additional defects. Table 2 shows that the total faults are 43 out of 176 bits. Therefore, this proposed basic design has 76% stability and 24% Fault.

Fig. 4.

Fault analysis for D-latch with reset capability.

Table 2.

Fault calculation for D-latch with reset capability.

Cell	Output (actual = 00110111000)	Fault
1	00110111000	0
2	00110100000	2
3	00110100000	2
4	01111100000	4
5	01001010000	6
6	01111100000	4
7	00110100000	2
8	00110100000	2
9	00110100000	2
10	00000000000	5
11	00000000000	5
12	01110100000	3
13	00110100000	2
14	00000010000	4
15	00110111000	0
16	00110111000	0

D-Latch design with reset and set capability

Figure 5 shows the block diagram of the proposed D-latch with reset and set capability. With this Fig. 6 block, we implemented the proposed D-latch with reset and set capability. The design was done in such a way that even by adding a pin set, the area, cell count and delay of the proposed circuit did not change. For this reason, this design is known as one of the most optimal designs.

Fig. 5.

Designing a proposed D-latch block diagram with reset and set capability.

Fig. 6.

Designing a proposed D-latch with reset and set capability.

Table 3 shows the set and reset function of this structure well. When the input clock is equal to 1 and the reset and set values are opposite to each other, the data input (D) value is directly transferred to the output. Now, if the clock value is 0 and set and reset are still the opposite of each other, the output will keep its previous value until if set and reset become 0 together, the output value will become 0, and if they become 1 together, the output will become 1. This circuit has wide applications for making or designing large circuits such as shift registers, PFDs, etc., so the smaller the structure of this circuit and the optimal time delay in terms of energy consumption, the more optimal our next circuits will be. The proposed structure in Fig. 6 has 18 cells, a delay of 0.5 clock cycles, and an area of um².

Table 3.

Set and reset function.

		OUT
0	0	0
0	1
1	0
1	1	1

D-flip-flop design with reset and set capability

One of the most important flip-flops in digital circuits is the D-flip-flop, whose input state appears as output at the moment when the clock signal changes from zero to one. This feature allows the edge-sensitive D-flip-flop to be used to synchronize and precisely control the operation of circuits when we need to synchronize with the edges of the clock signal. For example, rising edge-sensitive D-flip-flops are used in counters, registers, caches, and synchronization systems. This flip-flop makes the operation of the circuit be done at certain times and accurately and the information is stored correctly in the digital circuits. As a result, this flip-flop allows users to synchronize the circuits properly and perform the required operations at the right time.

As shown in Figure 7a, a rising-edge sensitive converter consisting of 11 cells with an area of µm² is used for our related design. In this converter, the initial clock value is majority gated with the non-active state of the previous clock, and then the rising-edge sensitive output is generated. The output of this converter remains in the zero-time region, and depending on the clocking regions of the latch, after connecting this converter to a D-latch, a rising-edge sensitive D flip-flop can be designed. This converter exhibits superiority in terms of dimensions, cell count, and stability compared to the converters presented in Refs^12,22,23. Equation (1) represents the performance of this converter. Figure 7b also shows the falling edge converter. Since the performance of the falling edge converter is exactly the opposite of the rising edge converter, as a result, we will use only the rising edge for the proposed designs. Table 4 shows how the rising edge converter works.

1

Fig. 7.

(a) Rising edge converter, (b) falling edge converter.

Table 4.

Function of the rising edge detection converter.

0	0	0
0	1	1
1	0	0
1	1	0

Now, with this proposed converter, it is possible to design a D-Flip-flop sensitive to the upper edge. As Fig. 8 shows, we designed a D-Flip-flop sensitive to the upper edge using the rules and pattern of QCA technology. The proposed D-flip-flop has a converter at the beginning of the structure, an AND gate at the output, an input clock pin, a reset pin, and a data input (D) pin.

Fig. 8.

Proposed design of D-flip-flop sensitive to rising edge with reset capability.

In the proposed flip-flop, when the input clock goes from zero to one, and the data input (D) has any value, the output stores the same value until the next edge of the input clock. And when the input clock goes from one to zero or the value of the input clock is zero, it does not affect the output. As a result, this structure is only sensitive to the upper edge of the input clock. In the meantime, if the reset value becomes zero, the output value will be zero. The proposed flip-flop in Fig. 8 has 28 cells, a delay of 0.5 clock cycles, and an area of um². Also, the multiplexer proposed in reference²⁵ has been used to design this flip-flop.

Figure 9 shows the proposed D-flip-flop with reset and set capability. The design of this structure has been done in such a way that even with the addition of a pin set, there is no change in delay, area, and the number of cells. The function of this circuit of this structure is the same as the structure of Fig. 8, with this difference, when the value of reset and set becomes zero, the output of any value it has before becomes zero. When set and reset both become one, the output value becomes one. Only when set and reset have different values (0, 1), the circuit continue its normal operation and work with the high edge of the input clock.

Fig. 9.

Proposed design of D-flip-flop sensitive to rising edge with reset and set capability.

The proposed structure of Fig. 9 has 28 cells, a delay of 0.5 clock cycles, and an area of um². It can be safely said that these proposed flip-flops are among the most optimal possible designs among different authorities. Because they have a small area and a very low delay and a low number of cells. Therefore, with this design, engineers and researchers are several steps ahead to be able to design and build well.

The architecture of the proposed D-flip-flop is based on a novel combination of majority logic gates in QCA technology. Unlike the previously reported edge detectors in^12,22,23, the proposed rising-edge converter utilizes a minimal and optimized configuration of 11 QCA cells. This new configuration offers a compact and efficient way to detect the rising edge of the clock signal and is structurally different from prior art. Moreover, the flip-flop integrates this converter along with an optimized reset and set logic, achieving improvements without increasing area or delay.

Proposed optimized shift register 4-bit

The 4-bit series shift register is a type of register in digital circuits, which usually consists of four latch elements (usually D latch) and is used to store and shift 4-bit data. These registers are often used in systems that need to store and process 4-bit data.

Applications of the four-bit serial shift register include the following:

• Data transfer: A four-bit shift register can be used to transfer data from one part of the circuit to another or from one device to another. This transfer operation can be serial or parallel.

• Data processing: The four-bit shift register can be used to perform processing operations on four-bit data. For example, it can be used as a unit to perform logical operations (such as increase or decrease, Boolean logic, etc.) or arithmetic operations (such as addition, subtraction, etc.) on four-bit data.

• Data Storage: These registers are used to store temporary data during data transfer or processing. For example, they can receive data that needs to be temporarily stored after one stage of processing and then send it to later stages of the circuit.

The main advantage of the four-bit series shift register compared to the less-bit registers is that they allow the storing and processing of more data, more accurately. Also, with the increase in the number of bits, the ability to process and store data increases, which facilitates the improvement of the efficiency and performance of digital systems.

As a result, as shown in Fig. 10, we designed and simulated a four-bit serial shift register with the least number of cells, a very small area, and a very low time delay in QCA technology. The function of this structure is as follows: when the input clock is active, the data input is directly transferred to the first output and then shifts to the next output with a slight delay.

Fig. 10.

Proposed design of 4-bit shift register.

The proposed structure of Fig. 10 has 83 cells, a delay of 0.5 clock cycles, and an area of um². We note that for the design of the proposed shift register, the multiplexer proposed in reference²⁵ has been used. As you can see, the proposed structure has few cells and very low delay. Which does not exist in any other reference with this cell value and shift register design delay. For this reason, the proposed design is considered among the best designs.

The proposed 4-bit shift register is designed using a unique majority gate arrangement. Although QCA shift registers have been studied before, such as in^12,22,23, the structure we propose uses our own optimized D-flip-flop cells and applies a custom interconnection strategy based on clock zone mapping, which has not been explicitly demonstrated in the previous works with the same logic arrangement. The design uses a sequence of newly arranged D-flip-flops that are sensitive only to the rising edge, and maintains optimal delay (only 2 clock cycles total) and area (0.06 μm²) for the 4-bit version, which makes it distinct from previous implementations.

Simulations and results

In this section, we want to show the simulation results of the proposed designs. Simulating electronic circuits in software is a vital process for electronic designers and engineers. This process allows designers to verify their performance in a virtual environment before actually building and manufacturing circuits. With simulation, they can analyze the performance of circuits and become aware of possible errors and problems at earlier stages. In addition, the use of circuit simulation helps to save time and cost related to the construction and testing of circuits. Designers can virtualize a part of the design process that may be time-consuming and expensive, and reap the benefits of savings.

The simulation also allows designers to test different design denominators and apply the necessary optimizations to improve circuit performance and characteristics. This process allows them to identify potential problems and find appropriate solutions before actually building the circuits. In general, circuit simulation in software is a powerful tool to improve the design and development process of electronic circuits, which makes designers save time and achieve better performance for their products.

For this reason, the simulation of the designed circuits was done in the QCA Designer version 2.0.3 software, and to have high accuracy results in the software settings, we set the simulator engine to Coherence Vector and applied the vector manually.

A coherence vector processing engine provides the possibility of accurate dynamic simulations. Dynamic QCA simulations are usually based on the density matrix of Eq. (2). The modeling of cells in this processing engine is similar to the two-mode modeling. In addition, the simulations of the coherence vector processing engine are time-dependent and include the effects of energy dissipation. In this method, the coherence vector is the density matrix-vector of a cell¹⁷.

2

In Eq. (2), is an energy vector that shows the energy environment of the cell.

3

In Eq. (3), is the King’s energy between two cells and is defined as the energy of keeping two cells with opposite polarity together. Also, is the polarity of the cell, γ is the tunneling energy of the electrons inside the cell, which is controlled by the clock.

4

In the above equations, is Planck’s constant, T is temperature in Kelvin, and is Boltzmann’s constant. The coherence vector of each cell is accurately calculated using the above equations. For each cell, and are calculated step by step, and the coherence vector moves forward in time¹⁸.

Figure 11 shows the output of the proposed design of Fig. 2. As shown in the corresponding figure, the output matches the expected behavior described in the design methodology. This confirms the validity and accuracy of the proposed structure in terms of correct functional operation.

Fig. 11.

The output results of proposed D-latch with reset.

Figure 12 shows the output of the proposed latch with reset and set capability. As you can see, when the set and reset values become zero and one at the same time, the output value becomes zero and one, respectively. When the set and reset values are different from each other, the output shows its normal function. This shows the high accuracy of the proposed plan.

Fig. 12.

Simulation results of proposed D-latch with reset and set.

Figure 13 shows the output of the proposed flip-flop with reset capability. This figure confirms all our statements well and shows the accuracy of the design.

Fig. 13.

Simulation results of proposed flip-flop with reset ability.

Figure 14 shows the flip-flop output with reset and set capability. We can see that when the set value and reset value have a different value, the circuit provides its normal operation.

Fig. 14.

Output results of the proposed design Fig. 9.

You can see the output of the four-bit shift register in Fig. 15. According to this figure, the output is the same and they are shifted in the order of each other.

Fig. 15.

Output results of proposed 4-bit shift register.

The most important parameter in the designs of analog and digital circuits is energy consumption. As a result, in this section, we used QCAPro software to measure the energy consumption of our introduced circuits. Figure 16 shows the energy diagram of D-latch with set and reset capability. As you can see, the proposed design has the lowest energy consumption. According to Fig. 16, darker areas have more energy consumption and vice versa.

Fig. 16.

Energy diagram of the proposed design Fig. 6.

Figure 17 illustrates the energy consumption of the proposed D-flip-flop with reset and set functionality. As observed, the proposed design exhibits lower energy consumption compared to the referenced designs. This result indicates its potential for energy-efficient applications in QCA-based sequential circuits, particularly in scenarios where minimizing power dissipation is essential.

Fig. 17.

Energy diagram of the proposed design Fig. 9.

Figure 18 illustrates the energy profile of the proposed shift register. As shown, the design demonstrates one of the lowest energy consumption levels among comparable structures. This suggests that the proposed architecture may be a promising candidate for energy-efficient implementation in practical QCA-based systems, particularly where power constraints are critical. Its compact design and low power demand could also contribute to cost-effective fabrication and integration in industrial applications.

Fig. 18.

The energy dissipation map of the proposed 4-bit shift register.

Table 5 presents a comparative analysis of the proposed D-latch with several existing designs. As observed, the proposed D-latch achieves a reduced area and a smaller number of cells compared to the other designs included in the table. This comparison provides a clear overview of how the proposed structure performs in terms of design compactness, offering useful insights into its potential efficiency within QCA-based systems.

Table 5.

Comparison of the mentioned references with the proposed D-Latch.

Refs.	Cell count	Area (um2)	Latency (clock cycles)	Set input	Reset input
12	48	0.05	1	No	No
13	43	0.06	1	No	No
15	35	0.04	1	No	No
15	33	0.03	0.75	No	No
16	30	0.03	0.75	No	No
17	28	0.03	0.5	No	No
18	25	0.02	1	No	No
19	23	0.02	0.5	No	No
10	19	0.02	0.75	No	No
22	19	0.01	0.75	No	No
24	24	0.02	0.5	No	No
11	25	0.02	0.75	No	Yes
24	33	0.02	0.75	No	Yes
Proposed (Fig. 2)	18	0.01	0.5	No	Yes
10	30	0.02	1	Yes	Yes
24	36	0.03	0.75	Yes	Yes
22	21	0.01	0.75	Yes	Yes
Proposed (Fig. 6)	18	0.01	0.5	Yes	Yes

Table 6 provides a comparative analysis of the proposed D-flip-flop and other existing designs. The proposed structure demonstrates improvements in key metrics such as area, latency, and cell count relative to several referenced works. These results suggest that the design may offer a more resource-efficient solution under the evaluated conditions.

Table 6.

Comparison of the mentioned references with the proposed D-flip-flop.

Refs.	Cell count	Area ()	Latency (clock cycles)	Set input	Reset input	Triggered
20	84	0.11	2.5	No	No	Rising
22	34	0.03	1	No	No	Rising
22	37	0.03	1	No	Yes	Rising
Proposed (Fig. 8)	28	0.02	0.5	No	Yes	Rising
23	79	0.09	2.5	Yes	Yes	Rising
10	53	0.04	2.25	Yes	Yes	Rising
Proposed (Fig. 9)	28	0.02	0.5	Yes	Yes	Rising

While several designs in the literature introduce enhancements in QCA-based latch architectures, some limitations remain. For example, Ref¹¹ presents a D-latch using 25 cells with an area of 0.02 μm² and a latency of 0.75 clock cycles, incorporating a reset input. However, the lack of a set input could restrict its applicability in systems requiring complete asynchronous control. Likewise, Ref¹³ includes both reset and set capabilities but utilizes 43 cells with a 0.06 μm² area, making it less compact compared to the proposed structure.

Ref¹⁵ introduces two versions of a D-latch design, utilizing 35 and 33 cells, respectively. Both versions operate with latency values of 1 and 0.75 clock cycles, which are within a reasonable range. However, these designs do not incorporate asynchronous control features such as set or reset inputs, which may limit their functionality in systems requiring such control mechanisms.

Ref¹⁶ presents a design consisting of 30 cells with an area of 0.03 μm² and latency of 0.75 clock cycles. Similar to Ref¹⁵, this structure lacks support for essential control inputs, which might constrain its use in more complex or reconfigurable circuits.

Likewise, Refs^18,19 offer compact designs with 25 and 23 cells and an area of 0.02 μm². Their respective latencies of 1 and 0.5 clock cycles indicate good timing performance. Nevertheless, the absence of asynchronous inputs such as set and reset could reduce their suitability for applications requiring flexible state control.

These limitations indicate that while some existing works offer improvements in specific performance aspects such as area or latency, they often do not incorporate critical control features, which limits their practicality in complex applications. In contrast, the design proposed in this study aims to provide a more balanced approach by combining reduced cell count, compact area, low latency, and support for essential control functions. This combination contributes to a potentially more reliable and efficient solution for QCA-based digital systems.

Table 7 reports the energy consumption of the proposed circuits under different tunneling energy levels. As shown in the table, the designs exhibit relatively low energy consumption, which may contribute to their suitability for low-power QCA applications.

Table 7.

Energy dissipation of proposed D-latches, D Flip-Flops, and 4-bit shift register.

	Average switching energy dissipation			Average leakage energy dissipation
Figure 6		0.0050	0.0061	0.021	0.0115	0.0041
Figure 9		0.0021	0.0030	0.0437	0.0254	0.009
Figure 10		0.063	0.076	0.1245	0.0564	0.0123

Table 8 presents a comparison of the energy consumption of the proposed designs with those reported in other studies, evaluated at a tunneling energy of 0.5 EK. According to the data, the proposed designs demonstrate relatively low energy consumption, positioning them among the more energy-efficient solutions reported in the literature.

Table 8.

Comparing the energy consumption of the mentioned references with the proposed designs.

Refs.	Total energy dissipation 0.5 Ek
	D-latch	D flip-flop
10	0.01151	0.01969
22	0.04533	0.01366
24	0.01218	0.02188
Proposed design	0.0041	0.009

Several methods can be used to calculate the circuit cost function in QCA technology. In this part, I will calculate the cost of the proposed circuits using the best method. In this method, the time delay, which is in terms of clock cycles, and the circuit area, which is usually expressed in micrometers, are used. Which is defined as ²⁶. The unit of area delay cost is also . Table 9 shows the value of the cost function of the proposed plans.

Table 9.

The amount of cost of the proposed circuits.

Refs.	Area ()	Latency (cycle of clock)	Cost
Proposed (Fig. 6)	0.01	0.5	0.0025
Proposed (Fig. 9)	0.02	0.5	0.005
Proposed (Fig. 10)	0.06	0.5	0.015

Discussion

The simulation results presented in Tables 5 and 6 indicate notable improvements in area, cell count, latency, and control features for the proposed latch and flip-flop designs compared to selected prior works. To better interpret these findings, a detailed analysis of referenced designs is necessary to understand their limitations and how the proposed circuits address them. Table 5 compares several existing D-latch implementations. For instance, Ref¹³ reports a relatively high cell count of 43 and an area of 0.06 μm², lacking asynchronous control inputs. Similarly, Refs^15,16,18 offer moderate area and latency performance but do not support reset or set functionalities, which may restrict their applicability in dynamic logic environments. In comparison, the proposed designs, including both the basic and set/reset-enabled variants, utilize as few as 18 cells, occupy 0.01 μm², and achieve latencies as low as 0.5 clock cycles while integrating essential control features. Notably, the design illustrated in Fig. 6 incorporates both set and reset inputs, enhancing its suitability for complex sequential logic systems that require asynchronous state management.

Table 6 further highlights the advantages of the proposed D-flip-flop architectures. Designs such as those in Refs^10,23 report relatively high cell counts (53 and 79, respectively) and long delays (2.25 and 2.5 clock cycles), making them less suitable for high-speed or compact QCA applications. More recent designs, such as Ref²⁴, while showing improvements in area, do not fully integrate control features and exhibit higher cell counts compared to the proposed design. The flip-flop presented in Fig. 9 of this paper uses only 28 cells, occupies 0.02 μm², achieves a latency of 0.5 clock cycles, and supports both set and reset inputs. To the best of our knowledge, this combination of features has not been reported simultaneously in previous works. These improvements have significant implications for the design of QCA-based sequential circuits. By reducing physical resource requirements and supporting essential control signals, the proposed designs potentially enhance scalability, reduce power consumption, and improve reliability under practical implementation scenarios. Furthermore, they provide efficient building blocks for constructing more complex systems such as counters, registers, or phase frequency detectors in future QCA architectures.

In summary, the obtained results demonstrate competitive performance and contribute toward establishing more compact, low-latency, and fully functional latch and flip-flop designs within QCA technology. The proposed circuits address several critical gaps in existing literature and offer meaningful advancements in high-performance QCA sequential design. The designs incorporate both rising-edge and falling-edge triggered architectures, enhancing their versatility and potential applicability. However, despite these improvements, some limitations remain. For instance, the structures are primarily optimized for minimal area and latency, which may affect their robustness in noise-prone or highly asynchronous environments. Additionally, the designs have yet to be evaluated under various QCA clocking schemes, which could influence their behavior in larger and more complex systems. Future research should focus on integrating error-tolerant mechanisms and assessing these architectures under diverse clocking conditions to further establish their practical viability.

Conclusion

The primary objectives in designing digital circuits using QCA technology are to minimize cell count, reduce area occupation, lower propagation delay, and decrease energy consumption. This study addresses these objectives by proposing several novel digital circuits optimized according to these performance metrics. Specifically, a D-latch with set and reset functionalities was implemented using 18 cells, occupying an area of 0.01 μm² and achieving a delay of 0.5 clock cycles, corresponding to a 34.87% reduction in cell count and a 60% decrease in area compared to some previous designs. Similarly, a rising-edge triggered D-flip-flop with reset and set capabilities was developed, comprising 28 cells within a 0.02 μm² area and operating with the same delay, showing improvements of 44.5% in cell count and 55.6% in area over selected existing counterparts. Additionally, an efficient 4-bit shift register featuring low delay is introduced. These results indicate enhanced compactness and efficiency relative to earlier works, suggesting potential for further application in QCA-based digital circuits. Future studies may focus on extending these designs to larger-scale systems such as counters and detectors to evaluate scalability and practical implementation challenges.

Author contributions

Pezhman Kiani Vosta: Conceptualization, Methodology, Software, Validation, Formal analysis, Investigation, Resources, Writing - Original Draft, Visualization.Mohammad Gholami: Conceptualization, Methodology, Investigation, Resources, Writing - Review & Editing, Supervision.

Data availability

The data that supports the findings of this study are available from the corresponding author upon reasonable request.

Declarations

Competing interests

The authors declare no competing interests.