0.91 V reference, 3.3 ppm/°C Sub-BGR with second-order compensation and improved PSRR

Abstract

This work introduces the design and analysis of a Bandgap Reference (BGR) circuit with better temperature stability and reduced process variation. The second-order compensation method is implemented for design through an optimized error amplifier and a resistor network with a significantly better temperature coefficient performance. The startup mechanism is carefully designed for ensured strong and stable circuit performance under every variation of process-voltage-temperature (PVT). The proposed BGR is compared with conventional methods such as CM-BGR, Cascaded CM-BGR, Operational Amplifier based-BGR, and Sub-BGR with respect to Temperature Coefficient (TC), Power Supply Rejection Ratio (PSRR), and line regulation. The proposed Sub-BGR is shown to provide 3.33 ppm/°C (58.97–78.79% less) temperature coefficient, 1.12×–6.02× improvement in PSRR, and 96% improved line regulation with 723 µV variation, thus showing improved performance compared to Operational Amplifier based-BGR and Sub-BGR techniques, rendering the proposed BGR highly appropriate for high-precision analog and mixed-signal applications. The proposed BGR is simulated and implemented by Synopsys custom compile using 32 nm CMOS technology.

Introduction

Integrated circuits generally employ Bandgap Reference (BGR) circuits to produce a reference voltage independent of temperature. They find widespread application in voltage regulators, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and low-power very-large-scale integration (VLSI) circuits. The traditional BGR circuits employ bipolar transistors and operational amplifiers, but modern implementations embrace current sources of MOSFET technology and advanced biasing techniques to enhance power efficiency, accommodate process variations, and enable low voltage operations^1–3. The BGR generates a stable reference voltage (V_ref) against which the output voltage of the DC-DC converter is referenced⁴.

Conventional BGR circuits are optimized for the temperature range of − 40 °C to 125 °C. Beyond this, performance is degraded by increased leakage currents, mobility, and process variations. Improved BGR architecture needs to be developed with improved higher-temperature performance without increasing power consumption¹. To offer consistent performance, Bandgap Reference (BGR) circuits must overcome many challenges. To ensure the accuracy of a reference voltage remains stable over a wide temperature range, process variation and second-order thermal effects need to be compensated⁵. One of the major challenges at high temperatures is the leakage current phenomenon, which can result in circuit instability and long-term degradation. BGR circuits that are designed to perform optimally and reliably at high-temperature applications must successfully overcome these challenges. This work presents a Bandgap Reference (BGR) circuit with enhanced compensation for process variation. The novel topology is a two-stage operational amplifier (Op-Amp) configuration⁶, which improves the gain and stability of the BGR circuit, thereby allowing stable operation across various process conditions. For efficient thermal drift resolution, a novel temperature compensation scheme is employed, which includes a complex sum of complementary voltages and those proportional to absolute temperature^2,7–9. Simulations are extensively performed to analyze the performance of the BGR across a wide temperature range, with particular emphasis on the stability and ruggedness of the BGR. Thus, the new design efficiently mitigates traditional limitations, allowing reliability at high temperatures¹⁰.

Existing BGR architectures have been critically analyzed with a focus on major design characteristics like temperature coefficient¹¹, line regulation⁴, power supply rejection ratio, supply current, and voltage range. Although most low-power BGRs are optimized, they are generally plagued by trade-offs like poor PSRR^12,13 or clipped operating voltage ranges. Other designs support high PSRR at the expense of higher power consumption or additional circuit complexity. This work emphasizes the gap that is targeted by the proposed architecture, presenting a balanced solution that enhances stability and robustness.

This paper explores the design and analysis of BGR circuits, emphasizing their temperature compensation mechanisms, process variation robustness, and suitability for ultra-low-power applications in IoT and high-speed computing systems. The organization of this paper is as follows. The detailed operation of conventional BGR Core circuits, which include CM-BGR and Cascaded CM-BGR are discussed in section “Conventional BGR core circuits design”. Proposed BGR for stabilization with startup circuit operation is discussed in section “Proposed BGR circuit design for stabilization with startup circuit”. Results and discussion about BGR core circuit design and performance parameters are discussed in section “Results and Discussions”.

Conventional BGR core circuits design

The detailed operation of conventional Bandgap Reference (BGR) Core circuits, including the Current Mirror BGR (CM-BGR) and the Cascaded Current Mirror BGR (Cascaded CM-BGR), is discussed in this section. These architectures are analyzed in terms of their temperature compensation mechanisms, process variation tolerance.

Conventional BGR core

Integrated circuits (ICs) must operate reliably in harsh environmental conditions, ranging from hot desert temperatures to sub-zero polar temperatures. To operate stably under such conditions, a Bandgap Voltage Reference (BGR) Core has been designed to generate a temperature-independent reference voltage, as shown in Fig. 1. The BGR circuit is essential to maintain stable operation by demonstrating process independence, stable operation over different semiconductor fabrication processes, voltage independence, minimizing variations due to supply fluctuations, and temperature independence, to operate reliably over a broad temperature range, usually from − 40 to + 125 °C¹⁴. The basic principle behind a BGR circuit is the generation of two voltages with opposite temperature coefficients to attain thermal stability. One such voltage is the Complementary to Absolute Temperature (CTAT) voltage, derived from the base-emitter voltage (V_BE) of a bipolar junction transistor (BJT). The V_BE voltage is of negative temperature coefficient, reducing by about − 2 mV/°C with a rise in temperature¹⁵. This CTAT voltage, from a diode-connected BJT, forms the foundation for temperature compensation in BGR circuits to provide a stable reference voltage over changing environmental conditions¹⁶.

Fig. 1.

Band gap reference core circuit. A design using NPN transistor.

So, V_BE is negative temperature co-efficient (− 2mv/°C).

The second one is PTAT Voltage (Proportional to Absolute Temperature). Derived from the thermal voltage (V_T = kT/q), which increases linearly with temperature at a rate of approximately + 0.087 mV/°C. By scaling this voltage appropriately, its temperature coefficient can be matched to that of VBE. A PTAT voltage generator achieved by subtracting the VBE of two BJTs operating with a current density ratio N⁷.

So, V_T is positive temperature co-efficient 0.087mv/°C)

The sum of these voltages, appropriately weighted, yields a temperature-independent reference voltage.

The output reference voltage is given by.

VREF = VBE + V_T⋅ln (N) = constant, which independent of PVT variations (when slope of CTAT = PTAT).

where ln (N) is a scaling factor determined by the ratio of slopes(m = 2/0.087 = 23). So, N should be very large in millions of transistors should be connected in the 2^nd stage.

Robust cascaded current mirror-based Bandgap Reference (BGR) circuits

A conventional current mirror and a stable cascaded current mirror-based BGR circuit are analysed in this section for improving stability against variations of Process, Voltage, and Temperature (PVT)^13–15. A single-stage BGR circuit based on current mirrors can be seen in Fig. 2a. The circuit consists of a PMOS current mirror (M1-M2) and a transistor-based BGR core (Q1-Q5). Temperature compensation is achieved by combining proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages through the resistor R_BGR.

Fig. 2.

Schematic and simulation results (a) CM-BGR (b) V_{BGR_OUT1} simulation for different R_BGR values (c) cascaded CM-BGR (d) V_{BGR_OUT2} simulation for different RBGR values (e) The simulation results for the variation of BGR output against the variations of supply voltage.

The cascaded current mirror-based BGR¹⁷ with its robust structure shown in Fig. 2c is comprised of two additional current mirror stages (M11-M22 and M33-M44) to achieve better current replication. As a result, the output reference voltage (V_BGROUT2) has enhanced immunity to supply variations.

Figure 2b, d illustrate the impact of R_BGR variation on V_BGROUT1 and V_BGROUT2. Similarly, the Single-stage current mirror and the Cascaded current mirror have linear relationships between V_BGR and R_BGR with varying sensitivity slopes, at 37.236 μV/Ω and 42.246 μV/Ω, respectively¹². Due to the greater slope obtained in the cascaded current mirror structure, it may be possible to obtain proportional to absolute temperature compensation (PTAT) for smaller R_BGR values.

The stability of BGR across an operating temperature range is shown through Fig. 2b, d. Figure 2e also shows how V_{BGR_OUT1} and V_{BGR_OUT2} with varying supplies (V_DD) compared to each other. A stable bandgap reference (BGR) topology, by virtue of using cascaded current mirrors, has less sensitivity to the supply voltage noise. Supply voltage is changed from 0 to 4 V, simulations are carried at various process corners as well as over a − 40 °C and 125 °C temperature range making use of the 65 nm CMOS process.

Figure 3 shows the effect of startup resistance variations on the BGR circuit output and the startup transistor biasing characteristic^13,16. In Fig. 3a, the BGR output voltage (V_BGROUT1) is studied versus various startup resistance (Rs) values. For lower Rs values (regions S1 and S2), the output is shifted away from the expected value and remains at around 3.2 V, which shows proper startup functioning, due to improper biasing of NM4. Thus, it is operated in a linear region as given in Fig. 3c. Nevertheless, as Rs increases above a critical value (around 20kΩ), the BGR output begins producing a constant 1.3 V (from Fig. 3b) (regions S3 to S5), which indicates that the startup circuit successfully biases the BGR properly at high resistance values, when NM4 is biased to run in the saturation region. Figure 3c shows the biasing voltage (V_GS) of the startup transistor NM4 versus different Rs values. At the beginning, NM4 is in the linear and saturation regions, allowing proper circuit startup. However, as Rs increases above a certain value, NM4 switches to the cutoff region, disabling the startup circuit and causing startup failure. This analysis verifies that choosing an optimum startup resistance is crucial in ensuring reliable BGR operation.

Fig. 3.

The BGR output (a) against the variations of startup resistance (b) with startup circuit (c) Biasing voltage of startup transistor (VNM4).

As shown in Fig. 4a, without the startup circuit, BGR fails to initialize correctly and stays in a metastable state, while with the startup circuit, it reaches the correct operating voltage of 1.3 V, as shown in Fig. 4b. A startup circuit is required to pull a small current at the beginning of operation in order to force the BGR into its correct operational state in Fig. 4c. Once the startup circuit is turned on, the startup transistor (NM4) pulls down on the V_X4 node, which turns on the PMOS load transistors (M1, M4), taking the BGR from the zero-current state into the active operating region. During this stage, the biasing voltage VNM4 for the NM4 is very high which guarantees its conduction. The startup circuit must turn off once BGR settles so that unnecessary power dissipation does not take place when NM5 is turned on by a high potential at V_X3, pulling down the N4 node, consequently turning NM4 off and ensuring that the startup circuit is disabled after initialization. After stabilization of the BGR core, the startup circuit acts as a normal turn-off circuit that prevents any unnecessary power from being consumed, as is seen from the startup transistor (I_NM4) reverting to zero at 120 µs.

Fig. 4.

The BGR output (a) without startup circuit (b) with startup (c) current through startup transistor (INM4).

Figure 5 presents the output occurrence graphs of CM-BGR and Cascaded CM-BGR under a supply sweep at 4 V. The results indicate that the Cascaded CM-BGR is able to maintain its target output voltage of 1.05 V, thus demonstrating its stability against supply changes. On the other hand, the CM-BGR demonstrates large deviations in its output voltage, tending towards higher supply levels in the samples. Such deviations indicate that the CM-BGR is more sensitive to supply changes, thus less stable.

Fig. 5.

Output occurrence plots of CM-BGR and cascaded CM-BGR.

BGR circuit design using operational amplifier

Operational amplifiers are used in applications where there is high gain and high speed. A differential input and differential output multi-stage configuration makes the circuit highly stable. With this configuration, differential signals are amplified and common-mode signals and noise are rejected simultaneously¹⁸. Differential inputs, V+ and V −, are connected to transistors M9 and M10 as shown in Fig. 6. A differential voltage can be translated into a differential current by these transistors, which form a differential pair. Transistors M1, M2, M3, and M4 also form the current mirror circuit, which provides the active load impedance of the differential pair.

Fig. 6.

Schematic of 2-stage operational amplifier.

The first stage consists of the differential pair (M5, M6) and the current mirror load (M1, M2). The gain of this stage is

A2 is the gain of the second stage (Common Source Amplifier)

1

2

Figure 7a, b illustrates how the phase response of the circuit changes when frequency is altered. Phase margin, or the phase shift from − 180°, is highly significant in establishing the stability of the amplifier.

3

Fig. 7.

Characteristics of operational amplifier (a). Phase response (b). Gain response between outputs to differential input nodes (c) gain response between cascading nodes (d) overall gain.

At differential gain, differential gain is the difference between the Vout gain and the gain of V+, V−, with intermediate nodes (Vy1, Vz1) considered. Ripples and peaks at high frequencies indicate parasitic effects or insufficient compensation. A sudden voltage gain vs. frequency spike in Fig. 7c might indicate resonances or noise coupling within the circuit. A plot of CMRR (Fig. 7d) illustrates the difference between the differential signal and the interference resulting from common-mode signals. The higher the CMRR, the higher the rejection by a differential amplifier of common-mode signals and noise.

A BGR circuit generates stable voltage that is independent of temperature, supply voltage, and process variations. Q1, Q2, Q3, Q4, Q5 and Q6 generates the CTAT voltages (VBE1, VBE2). R1 determines the current I1, which is proportional to the voltage difference VBE1–VBE2. R2 scales the PTAT current to generate the required voltage at the output. The operational amplifier enforces a virtual short condition, ensuring that the voltages at its inputs are equal¹⁹.

Operational Amplifier-based Bandgap Reference (BGR) circuit functions based on the production of a process-insensitive and temperature-stable reference voltage^7,20,21. The operational principle of this circuit is the integration of two voltage terms with opposite temperature coefficients: the base-emitter voltage (VBE) of a bipolar junction transistor (BJT), with a negative temperature coefficient, and thermal voltage (Vt)⁷. The nomenclature is derived from the resistor network that exhibits a positive temperature coefficient. The operational amplifier provides for proper biasing by equating the voltages at its input terminals (V_BE1, V_X), thus ensuring the desired current flow through the BJT network as shown in the Fig. 8a. The current is copied across multiple transistors (M0, M1, M2) to provide a voltage proportional to absolute temperature (PTAT), which is then added to the complementary-to-absolute-temperature (CTAT) results, producing an effectively temperature-insensitive output voltage. The resistive ratio determines the PTAT voltage value, allowing precise reference voltage adjustment, typically to 1.2 V. MOSFET-based current sources offer a stable bias condition, with minimal supply voltage sensitivity. Figure 8b shows the relation between R_BGR and slope of V_BGROUT3 for the range of temperature − 40 °C to 125 °C. R_BGR is adjusted to 139KΩ bring PTAT strength which equals to CTAT. The simulation results demonstrate the range of R_BGR for which slope of V_BGROUT3 is constant²².

4

Fig. 8.

(a) Band Gap reference circuit design1 using single operational amplifier (b) V_{BGR_OUT3} simulation for different R_BGR values.

Sub-BGR circuit design using operational amplifier

The circuit shown in Fig. 9a is a sub-BGR, which produces constant reference voltage through current summing technique^5,9. The sub-BGR is achieved using bipolar junction transistors (BJTs) (Q1–Q5) to produce base-emitter voltages (V_BE) with negative temperature coefficient (CTAT). The R1 resistor is used to produce a current with positive temperature coefficient, since the differential CTAT voltage (V_BE1–V_BE2) produces a voltage drop across it, which essentially produces a proportional-to-absolute-temperature (PTAT) current. Since V_X is a CTAT voltage, the voltage drops across R2 produces a CTAT current. The sum of PTAT and CTAT currents flow through M1 to make the resulting overall current constant²³. M2 mirrors the constant current to resistor R0, where the combined CTAT and PTAT components produce a stable reference voltage at V_BGROUTC1. A PMOS current mirror (M1) supplies stable bias currents to facilitate proper circuit operation. An operational amplifier keeps equal voltages (V_BE1 and V_X) at its inputs to facilitate proper generation of the PTAT current. The PTAT current, produced by the difference between the base-emitter voltages (V_BE1 and V_BE2) of the BJTs and scaled by resistor R1, is summed up with the CTAT current at the output node to facilitate temperature-compensated reference current²⁴. This current, when passed through RBGR, produces a stable output voltage (V_BGROUTC1).

Fig. 9.

(a) Sub-BGR circuit design1 using Operational Amplifier (b) V_{BGR_OUTc1} simulation for different R_PTAT values.

Figure 9b plots the output voltage (V_BGROUTC1) variation with temperature for different R_PTAT values, which reflects the effect of R_PTAT on temperature stability and the operation of the bandgap reference. The ideal bandgap reference should have a stable output voltage irrespective of the temperature change, with proper temperature compensation¹⁹. When R_PTAT is scaled PTAT behavior is dominated and slope of output voltage (V_BGROUTC1) is also changes, thus R_PTAT is determined based on the V_BGROUTC1 slope.

Proposed BGR circuit design for stabilization with startup circuit

The startup circuit shown in Fig. 10a allows the bandgap reference (BGR) to switch from the zero-conduction state to its nominal operating state. Current mirror MM1 and MM2 constitute a current mirror that takes current from MS1, which further regulates the node-Na voltage. Node-Na is used specifically in the determination of the conduction state for MS2. With the reduction of the node-Na voltage, MS2 goes to a state of conduction, which allows the voltage Vx to rise, thereby allowing the BGR core circuit to enter conduction mode. Error amplifiers are also responsible for serving as the determining components during startup by reducing the Es voltage when the BGR core does not conduct. Transistors M1, M2, M3, and M4 conduct at reduced Es voltage levels, transferring the BGR circuit to its operating state. Conduction initiates, and Es is regulated by the error amplifier to keep the BGR in a stable state, thereby allowing the BGR core to obtain a prescribed reference voltage.

Fig. 10.

(a) Proposed stable Band gap Reference Circuit with startup circuit (b) Simulation results of BGR output for different load conditions.

Node Vy of the Bandgap Reference (BGR) circuit is a summing node for Proportional to Absolute Temperature (PTAT) and Complementary to Absolute Temperature (CTAT) currents. The PTAT current occurs across the resistor R_PT as a result of the voltage difference between the base-emitter voltages (V_BE1, V_BE2) of the transistors Q1 and Q2. From loop L1, the voltage across RPT is the difference of these CTAT voltages, thus effectively creating a PTAT voltage. Hence, the current through R_PT is PTAT in nature. Nodes Vz and Vx are biased by transistors M1 and M3 such that they are at an equal potential. The error amplifier also plays a substantial role in further balancing Vy and Vx, thus making Vy a CTAT node, creating a CTAT current through resistor R_CT. This process helps in second-order compensation by balancing Vy and Vx to counteract curvature in temperature response. Furthermore, the action of the error amplifier and the Q1–Q2 transistor pair in the L1 loop also helps in second-order compensation, significantly improving the stability of the BGR circuit compared to the traditional method. This enhanced compensation process helps in better temperature stability and robustness in the generation of the reference voltage⁵. In traditional BGR circuits, PTAT and CTAT voltages are merely added together, which causes slight deviations due to nonlinear temperature effects. The second-order compensation (through the L1 loop and error amplifier) properly compensates for temperature-induced deviations, thus ensuring better stability. This results in an enhanced and robust Bandgap Reference with negligible temperature drift over a wide range of operations.

The simulation result of Fig. 10b describes the impact of R_PT on Bandgap Reference Output Voltage (V_BGROUTP). The plot describes the behavior of V_BGROUTP with varying levels of R_PT and temperature. The upper half of the plot describes how with the rise in R_PT, the slope of the output voltage line reduces, eventually reaching zero when R_PT is 653 Ω. This is an indication that at this resistance value, PTAT and CTAT components are in a perfect balance, thus reducing temperature-related drifts. The lower half of the plot also confirms the same by presenting a constant reference voltage over the temperature range, thus proving the efficacy of second-order compensation. The efficiency of proposed BGR in terms of temperature coefficient (TC), line regulation, Power Supply Rejection Ratios (PSRR) is discussed in the results section.

Results and discussions

A study of the stability and reliability of reference voltages in different BGR architectures is based on three key parameters: Line Regulation, Power Supply Rejection Ratio PSRR, and Temperature Coefficient TC. As a measure of circuit performance, these metrics play an important role in assessing its performance in varying supply conditions and environmental fluctuations.

Temperature coefficient

In BGR circuits, temperature coefficient (TC) represents how sensitive the reference voltage is to temperature variation^13,20,25. For high-precision applications, a lower TC value indicates better thermal stability.TC is typically measured in ppm/°C, plotted in Fig. 11 and calculated using Eq. 5²⁶.

5

where Vf (Voltage at high temperature), Vi (Voltage at low temperature), Vm (Nominal voltage).

Fig. 11.

BGR output against the temperature sweep (a). CM-BGR with TC 8.12 ppm/°C (b) Cascaded CM-BGR with TC 15.7 ppm/°C (c) Operational Amplifier based-BGR with TC 13.1 ppm/°C (d) Sub-BGR with TC 10.9 ppm/°C (e) Proposed BGR with TC 3.3 ppm/°C.

Temperature difference as 165 °C (− 40 °C to 125 °C) (assumed constant across all BGRs).

Figure 11a indicates that the CM-BGR has a moderately temperature-sensitive characteristic, as reflected in the curved temperature response. The temperature coefficient calculated as 8.12 ppm/°C reflects moderate stability under varying temperatures; however, this may not be sufficient for high-precision use. In Fig. 11b, it is seen that the cascaded CM-BGR structure adds an additional layer of temperature dependence, and hence a higher temperature coefficient of 15.72 ppm/°C, reflecting a greater variation of output voltage with temperature variation. Comparing the Operational Amplifier based-BGR with the cascaded CM-BGR, it is seen that the Operational Amplifier based-BGR possesses a feedback loop designed to introduce temperature compensation. However, it is not capable of achieving optimal implementation of temperature independence, as reflected in a temperature coefficient of 13.1 ppm/°C in Fig. 11c.

Sub-BGR architecture is thermally more stable than CM-BGR and cascaded CM-BGR with a temperature coefficient of 10.9 ppm/°C (as shown in Fig. 11d), which is an indicator of reduced temperature sensitivity. For avoiding nonlinearity in VBE, a quadratic PTAT component has been incorporated. The optimum temperature coefficient of 3.33 ppm/°C (as shown in Fig. 11e) is offered by the proposed BGR, which is an indicator of enhanced temperature stability. The proposed BGR and the CM-BGR are the optimum choices for applications requiring high temperature stability.

Line regulation

BGR circuit stability is a critical performance characteristic. Line regulation is a key indicator of how the output voltage (V_BGROUT) varies with supply voltage variations^{1,13,21,22,27}.

As shown in Fig. 12, different Bandgap Reference (BGR) topologies have different output voltage responses to supply voltage changes. Left-hand graphs (Fig. 12a, c, e, g, i) indicate output voltage versus supply voltage, while right-hand graphs (Fig. 12b, d, f, h, j) indicate statistical occurrence plots of line regulation values, reflecting process, voltage, and temperature variations.

Fig. 12.

Output against the supply voltage sweep (a). Output of CM-BGR (b) line regulation occurrence plot of CM-BGR (c). Output of Cascaded CM-BGR (d) line regulation occurrence plot of cascaded CM-BGR (e) output of Operational Amplifier based-BGR (f) line regulation occurrence plot of Operational Amplifier based-BGR (g) output of sub-BGR (h) line regulation occurrence plot of sub-BGR (i) output of Proposed BGR (j) line regulation occurrence plot of Proposed BGR.

The conventional current mirror bandgap reference (CM-BGR) has a very large output voltage fluctuation (ΔV_BGROUT1) of 0.34179 V, which is an indication of its sensitivity to supply voltage variation. In line regulation histogram, it shows a mean of 173.61 mV with a standard deviation of 16.174 mV, indicating high variations that make it less ideal for applications where high accuracy is required.

The cascaded CM-BGR favors increased stability, reducing ΔV_BGROUT2 to 0.062813 V and producing a mean line regulation of 137.33 mV with a standard deviation of 12.271 mV, contributing to enhanced resistance to supply fluctuations. The operational amplifier-based bandgap reference (Operational Amplifier based-BGR) shows moderate supply variation sensitivity, with ΔV_BGROUT3 reading 0.073366 V. The feedback mechanism supports stability, as shown by the histogram, which shows a mean line regulation reading of 51.299 mV with a standard deviation of 25.92 mV. The sub-bandgap reference (sub-BGR) further improves performance by recording a very low ΔV_BGROUTC of 0.027811 V, which is due to its current cancellation strategies that counteract supply dependence. Its line regulation distribution shows a mean of 18.218 mV, which is an indicator of the stable reference voltage. Compared to other designs, the new BGR Architecture has a ΔV_BGROUTP of only 1.0803 mV and therefore confirms that it has almost zero response to supply voltage change. The mean line regulation is seen to have a value of 723.83 uV with a variation of 132.6 uV. Further enhancement can be seen by using low-threshold voltage MOSFETs and second-order current compensation.

Power supply rejection ratio

Frequency response plots of several Bandgap Reference (BGR) architectures are shown in Fig. 13, along with their corresponding Power Supply Rejection Ratios (PSRR). The PSRR of BGR architecture is an indication of its ability to reject power supply fluctuations from various sources, and it is measured in decibels (dB)^{1,3,8,9,28,29}.

Fig. 13.

PSRR calculation for (a) CM-BGR with − 13.6@100 Hz (b) Cascaded CM-BGR with − 55.03@100 Hz (c) Operational Amplifier based-BGR with − 63.5@100 Hz (d) Sub-BGR with − 73.03@100 Hz (e) Proposed BGR with − 81.9@100 Hz.

For CM-BGRs operating at a frequency of 100 Hz, there is a PSRR of approximately − 13.62 dB, as shown in Fig. 13a. A low PSRR indicates that architecture is highly sensitive to power supply fluctuations¹³. In applications where CM-BGR structures are cascaded in a cascade topology, the PSRR is boosted to − 55.034 dB, as shown in Fig. 13b. With an increase in output impedance in cascading, the amplitude of noise targeted towards the output branch is diminished. Operational amplifiers have a feedback mechanism that controls the reference voltage, hence reducing supply sensitivity and loop gain, resulting in an architecture that is immune to noise. Therefore, a BGR that employs operational amplifiers integrated can boost the PSRR to − 63.541 dB, as shown in Fig. 13c. A Sub-BGR is identified with a Power Supply Rejection Ratio (PSRR) of − 73.032 dB, as shown in Fig. 13d. The accuracy of reference voltages is improved when the process of biasing is done with high accuracy, thereby reducing supply variations. As shown in Fig. 13e, the proposed BGR structure can realize a PSRR of − 81.983 dB at lower frequencies. The reference voltage shows a better ability to reject noise in the supply when sophisticated biasing techniques are used in combination with second-order current compensation techniques.

Supply current

Tables 1, 2, 3, 4 and 5 present the total supply current consumption for different Bandgap Reference (BGR) architectures, including CM-BGR, cascaded CM-BGR, Operational Amplifier based-BGR, sub-BGR and proposed BGR. Table 6 presents the comparison of key performance metrics for different BGR architectures.

Table 1.

Calculation of total supply current through operating current components of each transistor in CM BGR.

CM-BGR	region	id	Transistor parameters under operation
			vth	vdsat	gm	gds	Vgs	Vds
M1	Saturation	− 6.9566 u	− 589.0554 m	− 235.7525 m	47.9235 u	209.6814n	− 839.9337 m	− 2.1962
M2	Saturation	− 6.7469 u	− 589.0554 m	− 235.7525 m	46.6855 u	21.6871 u	− 839.9337 m	− 839.9337 m
M01	Saturation	− 6.8971 u	− 589.0554 m	− 235.7525 m	47.5746 u	3.9844 u	− 839.9337 m	− 1.8085
M3	Saturation	6.9566 u	503.0549 m	130.5466 m	93.5362 u	78.9062 u	625.9778 m	625.9778 m
M4	Saturation	6.7469 u	503.3464 m	126.4141 m	92.3075 u	166.5582 n	620.4112 m	1.9767

Total supply current (neglecting stat-up) = Id (M1) + Id (M2) + Id (M01) = 20.61uA.

Table 2.

Calculation of total supply current through operating current components of each transistor in Cascaded-CM BGR.

Cas-CM-BGR	Region	id	Transistor Parameters Under operation
			Vth	Vdsat	gm	Vgs	Vds
M1	Saturation	− 4.9802 u	− 589.0554 m	− 204.6248 m	39.9746 u	− 799.3181 m	− 799.0912 m
M2	Saturation	− 4.9802 u	− 589.0554 m	− 204.6248 m	39.9748 u	− 799.3181 m	− 799.3181 m
M01	Saturation	− 4.9804 u	− 589.0554 m	− 204.6248 m	39.9761 u	− 799.3181 m	− 800.8057 m
M11	Saturation	− 4.9802 u	− 589.0554 m	− 204.7972 m	39.9474 u	− 799.5451 m	− 726.2245 m
M22	Saturation	− 4.9802 u	− 589.0554 m	− 204.6248 m	39.9748 u	− 799.3181 m	− 799.3181 m
M3	Saturation	4.9802 u	611.0734 m	116.3595 m	75.9776 u	704.5368 m	704.5368 m
M4	Saturation	4.9802 u	611.0782 m	116.5007 m	75.9455 u	704.7455 m	631.4249 m
M33	Saturation	4.9802 u	501.3364 m	114.0085 m	74.9280 u	600.9655 m	600.9655 m
M44	Saturation	4.9802 u	501.3364 m	114.0091 m	74.9281 u	600.9664 m	600.7577 m
M02	Saturation	− 4.9804 u	− 589.0554 m	− 203.4952 m	40.1446 u	− 797.8305 m	− 1.2979

Total supply current (neglecting stat-up) = Id (M1) + Id (M2) + Id (M01) = 14.60 uA.

Table 3.

Calculation of total supply current through operating current components of each transistor in operational amplifier based-BGR.

OPAMP-BGR	Region	id	Transistor Parameters Under operation
			Vth	Vdsat	gm	Vgs	Vds
M0	Saturation	− 4.9916 u	− 589.0554 m	− 200.3807 m	40.6877 u	− 793.7229 m	− 2.8308
M1	Saturation	− 4.9916 u	− 589.0554 m	− 200.3807 m	40.6876 u	− 793.7229 m	− 2.8307
M2	Saturation	− 4.9134 u	− 589.0554 m	− 200.3807 m	40.1322 u	− 793.7229 m	− 2.1433

Total supply current (neglecting stat-up) = Id (M0) + Id (M1) + Id (M2) = 14.89 uA.

Table 4.

Calculation of total supply current through operating current components of each transistor in Sub-BGR.

Sub-BGR	Region	id	Transistor Parameters Under operation
			vth	vdsat	gm	Vgs	Vds
M0	Saturation	− 14.114 u	− 589.0554 m	− 200.3807 m	49.6877 u	− 1.9885	− 2.7597
M1	Saturation	− 14.114 u	− 589.0554 m	− 200.3807 m	49.6876 u	− 1.9885	− 2.7598
M2	Saturation	− 14.84 u	− 589.0554 m	− 200.3807 m	49.1322 u	− 1.9885	− 2.5758

Total Supply Current (neglecting stat-up) = Id (M0) + Id (M1) + Id (M2) = 43.06 uA.

Table 5.

Calculation of total Supply current Through operating current components of each transistor in Proposed-BGR.

BGR-Proposed	region	id	Transistor Parameters Under operation
			vth	vdsat	gm	Vgs	Vds
M1	Saturation	− 10.114 u	− 589.0554 m	− 200.3807 m	49.6877 u	− 1.9715	− 2.7597
M2	Saturation	− 10.114 u	− 589.0554 m	− 200.3807 m	49.6876 u	− 1.9715	− 2.7598
M3	Saturation	− 10.84 u	− 589.0554 m	− 200.3807 m	49.1322 u	− 1.9715	− 2.5758
M4	Saturation	− 10.114 u	− 589.0554 m	− 200.3807 m	49.6876 u	− 1.9715	− 2.7598
ME1	Saturation	− 3.24 u	− 589.0554 m	− 200.3807 m	49.6876 u	− 1.6885	− 1.8085
ME2	Saturation	− 1.84 u	− 589.0554 m	− 200.3807 m	49.1322 u	− 1.3885	− 1.8085

Supply Current (neglecting stat-up) = Id (M1) + Id (M2) + Id (M3) + Id (ME1) + Id (ME2) = 46.26 µA.

Table 6.

Comparison of key performance metrics for different Bandgap reference (BGR) architectures.

Performance parameters	CM-BGR	Cascaded CM-BGR	Operational amplifier based-BGR	Sub-BGR	Proposed BGR
Supply voltage	1.3–4 V	2–4 V	2–3.8 V	1.8–3.8 V	1.8–3.8 V
Supply current	20.61 µA	14.60 µA	14.89 µA	43.06 µA	46.26 µA
Reference voltage	1.49	1.152	1.154	0.724	0.91
Temperature coeff(ppm/°C)	8.12	15.7	13.101	10.90	3.33
Line regulation (mean-μ) (SD-σ) (σ/μ)	(176 mV)	(137 mV)	(51 mV)	(18 mV)	(723 uV)
	(16 mV)	(12 mV)	(25 mV)	(5 mV)	(132 uV)
	(0.09)	(0.087)	(0.45)	(0.27)	(0.18)
Power supply rejection ratio (PSRR)	− 13.6	− 55.03	− 63.54	− 73.03	− 81.9

Conclusion

The proposed BGR circuit shows significant improvement in performance over traditional architecture. It shows an improvement in temperature coefficient by 58.97–78.79%, which significantly improves thermal stability. The line regulation is also enhanced by about 80%, which keeps voltage variations very low for supply variations. The PSRR is also enhanced by 1.12× to 6.02×, which renders the circuit highly insensitive to power supply noise. Although the supply current of the proposed BGR is 1.07× to 3.17× higher than some existing architectures, it is a good trade-off given the significant improvements in stability and accuracy. Overall, the proposed BGR architecture shows an impressive improvement in temperature stability, PSRR, and line regulation at the same reference voltage and operating voltage range. These improvements render the circuit an attractive candidate for high-precision, low-power analog and mixed-signal applications.

Author contributions

Conceptualization, software simulation, formal analysis, writing—original draft preparation: Ch. Ganesh. Validation, resources, supervision: Sateesh Kumar S, A Shanthi; Validation, resources: S Shaik Shoukath Vali.

Funding

The authors received no specific funding for this work.

Data availability

The data supporting the findings of this study are available upon reasonable request from the corresponding author.

Declarations

Competing interests

The authors declare no competing interests.