A 266-nW, 4.9-μV_rms Noise, Wideband Neural Recording Amplifier With Folding-Current-Reuse Operational Transconductance Amplifier

Abstract

This letter presents a nano-watt, low-noise, AC-coupled wideband neural recording amplifier. The nano-watt power consumption has been achieved with 1) doubling of the transconductance by using folding current transistors in a folded-cascode operational transconductance amplifier (OTA) as input transistors (folding-current-reuse (FCR) technique), that also nulls their contribution to output noise and 2) dual supplies where the high and low voltages are assigned for low and high current consuming branches, respectively. Also, the proposed FCR technique indirectly contributes to low power consumption by forming low impedance nodes, which is a difference from a conventional current-reuse OTA in a two-stage amplifier that requires Miller compensation. The amplifier with the FCR technique has been fabricated in a 180 nm standard 1P6M CMOS process. The fabricated chip has been experimentally verified both in benchtop and in vitro using a commerical silicon microelectrode. The amplifier consumes extremely low power of 266 nW from 0.4 and 0.6 V supplies, with the input referred noise of 4.9 µV_rms in a wide bandwidth from 0.09 Hz to 7.56 kHz and exhibits 1% THD with an 2.4 mV_pp input and an 40 dB closed-loop gain.

I. Introduction

Number of simultaneous recording channels in neural interfaces has been increased from a few tens to a few hundreds for the last decade, and recently reached a few thousands [1–3]. This advancement has enabled a massively parallel neural recording in vivo, that is fundamental for understanding of neurons and the interactions among multiple neurons [4]. However, though the success in scaling neural recording interfaces up to date, lower power operation is still one of the most urgent requirements to be further pursued for higher scalability in fully implantable devices.

A power consumption in implantable neural interface has a strict limit of < 80 mW/cm² or temperature rise by the power dissipation should be < 0.5–1.0 °C, because excessive power consumption can lead to irreversible tissue damage by heat [5–6]. Higher power consumption can also increase volume of a system constrained by size and/or weight of energy sources, such as batteries, supercapacitors, or energy harvesting transducers, resulting in a limited implantability.

On the other hand, for qualified neural recordings, low noise performance is highly required due to the high dynamic range requirement imposed by small extracellular action potentials (ExAPs, a few tens of μV) on top of large local field potentials (LFPs, a few mV). The input referred noise (IRN) of neural recording interface circuits should not exceed 10 µV_rms [7].

In general, noise and power performance in integrated circuits has a trade-off relationship, and this trade-off is also strictly imposed for the design of neural recordins amplifiers. For example, an extremely low power consumption of 77 nW, has been achieved using a two-stage amplifier with the minimal branch currents, but showing too high IRN of 14.3 µV_rms [8]. Another work achieved 805 nW with an IRN of 3.5 µV_rms by using the minimal number of transistors, however such low IRN was derived by the bandwidth of 4.7 kHz, which is insufficient for ExAP recordings, while sacrificing other essential performance, such as total harmonic distortion (THD) and power supply rejection [9]. To break the trade-off, numerous neural recording amplifier topologies and design strategies have been proposed. A representative technique is a current-reusing scheme where a bias current in vertically stacked two complimentary transistors is shared, doubling transconductance $\left(G_{\text{m}}\right)$ in an amplifier, consequently suppressing power of IRN by ~2. [10] and [11] achieved the IRN of 5.71 µV_rms and 3.2 µV_rms while consuming 800 nW and 730 nW of power, respectively, even though the bandwidth of [10] may be slightly insufficient to cover ExAPs. The current-reuse technique can be ultimately applied to multi-stacking of the complimentary transistors. [12] demonstrated the IRN of 5.5 µV_rms with the power consumption of only 250 nW by vertical stacking of three pairs of the complimentary transistors.

Although noise and power performance are important, there are other critical performance metrics for neural recording in-vivo. For example, enough bandwidth must be guaranteed in accordance with the target neural signals. Particularly, in order to capture fast-varying ExAPs, the high frequency bandwidth $\left(f_{\text{H}}\right)$ of a neural recording amplifier should extend up to 7.5–10 kHz [7], which is also related to power consumption of an amplifier. The signal swing of an amplifier is of importance because linearity matters for neural signal analysis, in particular for LFPs, which require spectral analysis, and high gain has also to be implemented in a front-end amplifier to ease the designs of following circuits. Such large output swing or dynamic range (DR) of an amplifier is also related to the power consumption, albeit it is indirect.

This letter presents an ultra-low power of 266 nW, low IRN of 4.9 µV_rms, AC-coupled fully-differential wideband: 0.09 Hz–7.5 kHz neural recording amplifier of 40 dB inband gain, that can simultaneously record both LFP and ExAP. To achieve low power and noise, we analyzed one of the most widely adopted operational transconductance amplifiers (OTAs) for neural recordings: folded-cascode (FC)-OTA and relocated noisy folding transistors into the input pair, thereby nulling their noise contribution and doubleing $G_{\text{m}}$. This approach is very simple but powerful to reduce IRN without sacrificing other important performance, such as linearity and inband gain. The relocation of the folding transistor also forms low impedance path, thereby realizing wideband operation with low power consumption. In addition, we assigned two power supplies for the amplifier, according to the signal swings to minimize power consumption and to improve linearity. This letter is organized as follows. Section II describes the proposed OTA with the FCR technique and analyzes its noise, power and other important performance. Section III presents the experimental results including benchtop and in vitro tests. Finally, Section IV concludes this letter.

II. Neural Recording Amplifier Design

A. Folding-Current Reuse OTA

Fig. 1 (a) shows a baseline fully-differential FC-OTA. The main noise contributors of the OTA is the input differential pair $\left({\text{M}}_{1,2}\right)$ and folding current transistors $\left({\text{M}}_{3,4}\right)$. ${\text{M}}_{5,6}$ also contribute; but it effect is minor if the OTA is designed for low-power neural recordings, i.e., ${\text{I}}_{\text{D5,6}}<<{\text{I}}_{\text{D1,2}}$. In order to suppress IRN further, ${\text{M}}_{3,4}$ have been replaced by the source-degenerated ones, as shown in Fig. 1 (a). By doing so, both $1\text{/}f$ and thermal noises of ${\text{M}}_{3,4}$ will be substituted by the thermal noise of $R_{\text{S}}$, once the condition: $g_{\text{m3,4}}{R}_{\text{S}}>>1$ is met. This degeneration is effective, and the resulting power spectral density (PSD) of IRN becomes ~2/3, compared to the FC-OTA without degeneration. However, to meet the condition, $R_{\text{S}}$ should be large, thus the voltage drop accros $R_{\text{S}}$ becomes large when combined with a high bias current of ${\text{M}}_{3,4}\left({\text{I}}_{\text{D1,2}}+{\text{I}}_{\text{D5,6}}\right)$. Note that [13] used a large supply voltage of 2.8 V to accommodate the voltage drop, even taking the used legacy CMOS technology of 500 nm into consideration.

Fig. 1.

(a) A baseline FC-OTA with a $R_{\text{S}}$ degeneration (b) the proposed FCR-OTA, and the inset table shows the aspect ratio and roles of of transistors

In the proposed design, instead of using $R_{\text{S}}$ to null the noise contribution of ${\text{M}}_{3,4}$, they are used as an another input pair as shown in Fig. 1 (b) by applying inputs in their gates. The overall IRN of Fig. 1 (b) is now given as:

$$\overline{v_{ni}^2}\approx \frac{8kT\gamma }{{\left(g_{m1}+g_{m3}\right)}^2}\cdot \left(g_{m1}+g_{m3}\right)\approx \frac{4kT\gamma }{g_{m1}}$$ (1)

where $k$ is Boltzmann’s constant, $T$ is the absolute temperature, $g_{\text{m}}$ is transconductance of a transistor, and $\gamma$ is the thermal noise coefficient of a transistor, and $g_{\text{m1}}\approx g_{\text{m3}}$ has been assumed. The IRN, that is originally proportional to $g_{\text{m3.4}}$ in Fig. 1 (a), become proportional to $1\text{/}{g}_{\text{m3.4}}$ in Fig. 1 (b), and $R_{\text{S}}$ that requires large voltage headroom is also removed. Moreover, the power supply scaling in accordance with signal ampltiudes has also been used to minimize its power consumption, as shown in Fig. 1 (b). The signal swings in $v_{\text{on}}$ and $v_{\text{op}}$ are small ($v_{\text{op}}-v_{\text{on}}~3{\text{mV}}_{\text{pp}}$, when $v_{\text{inp}}-v_{\text{inn}}~3{\text{mV}}_{\text{pp}}$ in Fig. 3) due to the low impedance dominated by ${\text{M}}_{3,4\text{C}}\left(R_{\text{i2}}~1\text{/}{g}_{\text{m3C,4C}}\right)$, while the signal swing of output ($v_{\text{outp}}$ and $v_{\text{outn}}$) is large. Hence, ${\text{V}}_{\text{DDL}}$ can be smaller than ${\text{V}}_{\text{DD}}$. Specifically, 0.4 and 0.6 V have been assigned for ${\text{V}}_{\text{DDL}}$ and ${\text{V}}_{\text{DD}}$, respectively via a soft-charging dc-dc converter [14].

Fig. 3.

Fully differential, AC-coupled neural recording amplifier using the proposed FCR-OTA.

The final configuration of the proposed design $\left({\text{M}}_{1-4}\right)$ has a common with the existing current-reuse technique in a telescopic, two-stage [10–11], or stacking topologies [12]. The proposed design has the same current to transcoducance efficiency $\left(g_{\text{m}}\text{/}{I}_{\text{D}}\right)$ as the current-reuse OTA; but it definitely has advantage over it. The current-reuse technique in a two-stage, as shown in Fig. 2 (a) must have a Miller compensation capacitor $\left({\text{C}}_{\text{C}}\right)$ to split the closely located two poles in the high impedance nodes ($v_{\text{on,p/n}}$ and $v_{\text{outn,p/n}}$). The location of the 2^nd-splitted pole ($G_{\text{m2}}/C_{\text{L}}$, where $G_{\text{m2}}$: transconductance of the 2^nd-stage), playing a critical role in stability of the closed loop, is proportional to $G_{\text{m2}}$; in other words, to guarantee stability, $G_{\text{m2}}$ should consume relatively large current. In [10], to maintain nW-power consumption (~800 nW), the bandwidth of the amplifier has been sacrificed, instead of increasing the location of the 2^nd pole, failing to record fast varying ExAPs. The multi-stacking of the current-reuse schemes can provide better noise and current performance than this work due to the multiple current-reuse, as shown in Fig. 2 (b). However, it requires a complicated input bias network to accommodate the multiple inputs [12]. In addition, there is a severe headroom limitation. The two-stacked example requires $6\times {\text{V}}_{\text{DS}}$ ($\text{2×}{\text{M}}_1\text{,}\text{2×}{\text{M}}_3\text{,}{\text{M}}_0\text{,}\text{and}{\text{M}}_5$, compared with $5\times {\text{V}}_{\text{DS}}$ in this work), and each of ${\text{V}}_{\text{DS}}$ requires larger ${\text{V}}_{\text{DS}}$ than the ones in this work $\left({\text{M}}_{\text{3C}},{\text{M}}_5,{\text{M}}_{\text{5C}}\right)$ because ${\text{M}}_0$, ${\text{M}}_3$, and ${\text{M}}_5$ consist of the main current branch ($I_{\text{D}}$ in Fig. 2 (b)). Thus, [12] implemented a smaller closed-loop gain of ~18 V/V than that of this work (100 V/V) to avoid saturation of the amplifier or high nonlinearity; but it may result in a tight design of the following circuit blocks in terms of power and area.

Fig. 2.

(a) a conventional current-resue OTA in a two-stage topology, and (b) in a multi-stacking scheme, $R$ represent transimpedance amplifier.

B. AC-Coupled Neural Recording Amplifier

Fig. 3 shows the implmented fully-differential AC-coupled neural recording amplifier with the FCR-OTA as a proof-of-concept. The input $\left(C_{\text{in}}\right)$ and feedback $\left(C_{\text{f}}\right)$ capacitors are 15 pF and 150 fF for 40 dB closed-loop gain, respectively. $C_1$ is the load capacitor of 1.82 pF. $R_{\text{f}}$ and $R_{\text{b}}$ are pseudo resistors, realized using near off-state PMOS transistors [5]. To properly set the bias voltage for input transistors, a separate bias circuit $\left(V_{\text{CML}}\right)$ is implemented, and a common mode feedback (CMFB) circuit is also implemented to define the output dc bias; but they are not shown here for the sake of brevity.

III. Experimental Results

The AC-coupled neural recoding amplifier with the proposed technique has been fabricated in an 180 nm standard 1P6M CMOS technology. A chip microphotograph is shown in Fig. 4. Note that a soft-charing step-up DC-DC converter has also been fabricated with it to generate the dual supplies [14].

Fig. 4.

Die microphotograph of the neural amplifier with the proposed OTA.

A. Benchtop test

The current consumption of the amplifier was measured as 535 nA. The output branch with a CMFB consumes 260 nA from 0.6 V, and the input branch draws 275 nA from 0.4 V, resulting in a total power consumption of 266 nW. When the currents supplied by the dc-dc boost converter, the overall power consumption becomes 350 nW. The frequency responses including differential-mode (DM) and common-mode (CM) gains $\left({\text{A}}_{\text{DM}}{\text{,A}}_{\text{CM}}\right)$ are shown in Fig. 5 (a), both are 39.8 and −16.2 dB, respectively at midband. The high-pass cutoff $\left(f_{\text{L}}\right)$ and low-pass cutoff $\left(f_{\text{H}}\right)$ frequencies are 87.7 mHz and 7.56 kHz, those are suitable for recordings of LFP and fast-varying ExAPs. The spectral noise was also measured. As shown in Fig. 5 (b), the measured thermal noise floor is of $59\text{nV/}\surd \text{Hz}$ and $1\text{/}f$ noise corner frequency of 100 Hz. The IRN integrated over the signal bandwidth was 4.9 μV_rms, that has a good agreement with a time domain measurement (total 4 seconds measurement, showing only 50 ms) shown in Fig. 6 (a). Fig. 6 (b) depicts the measured THD with 1-kHz sinewave with various input amplitudes. Its THD is smaller than 1% up to 2.4 mV_pp of input amplitude, justifying its good coverage of LFPs. Since this work has strategically used the power supply levels as discussed, the amplier exhibited good THD performance even with a low supplies. Table I compares our work with other nW-power consuming wideband $\left(f_{\text{H}}>7.5\text{kHz}\right)$ neural recording amplifiers [11–12],[15–16]. In terms of the noise efficiency factor (NEF), there are a few better works than this work. The NEF reflects noise and current optimiztion in a given amplifier, but there are other important metics, such as gain and THD.

Fig. 5.

Measured characterstics of the neural recording amplifier: (a) spectral characteristics for A_DM and A_CM (b) IRN spectrum

Fig. 6.

Measured characterstics of the neural recording amplifier: (a) time domain IRN, (b) THDs with 1 kHz sinewave input

TABLE I.

Comparison to nW-power, Wideband Neural Recording Amplifier

		1[11]	2[12]	[15]	[16]	This work
Power (µW)		0.73	0.23	0.62	1.1	0.266
IRN (µVrms)		3.2	6.7	5.6	12.7	5.54
BW (Hz)	$f_{\text{L}}$	0.25	2	0.78	0.21	0.09
	$f_{\text{H}}$	10k	10k	9.8k	8.7k	7.56k
Supply (V)		0.45	0.9	0.77	1.2	0.4/0.6
Gain (dB)		40	25.4	40	49.2	40
Max. 1 kHz input @ 1 % THD (mVpp)		−	−	−	30.416	2.4
Area (mm2)		0.25	0.25	0.018	0.011	0.066
CMRR (dB)		73	84	−	> 40	4 56
NEF		1.57	1.26	3.0	4.92	1.79
PEF		1.12	1.43	7.39	29.0	1.60
Topology		AC-couple	AC-couple	AC-couple	AC-couple	AC-couple
Technology		180 nm CMOS	180 nm CMOS	22 nm FDSOI	180 nm CMOS	180 nm CMOS

¹Low-power mode

²Twp-stacked version

³Divided by 49.2 dB gain

⁴At 60 Hz

B. In vitro test

Fig. 7 shows the in vitro measurement setup (left) and a snapshot of the oscilloscope for the input, amplified outputs by a commercial LNA (SR560, Stanford Research) and our amplifier (right). For this in vitro test, a silicon microelectrode array (N1-A0-O36/18, NeuroLight Technology, LLC) with 1 MΩ impedance has been employed in a 1% phosphate buffered saline solution. The standard deviation of the difference between the outputs from the SR560 (reference) and implemented amplifier is ~15 μV, that is within a reasonable value considering the noises of the SR560, amplfier and electrode, when referred to the input.

Fig. 7.

In vitro experiment setup (left ) and resultant neural signal (right).

IV. Conclusion

We report an nW, AC-coupled wideband neural recording amplifier that can simultaneously records LFP and spike with a low IRN. The nW-power consumptiona and decent IRN have been achieved by the proposed FCR technique and the proper assignment of power supplies according to signal movements. The performance of the proposed LNA has been verified in a benchtop and in-vitro, showing 266 nW of power consumption, that is extremely low power consumption in wideband neural recordings (0.09 Hz~ 7.5 kHz) with a low IRN of 4.9 µV_rms. The LNA also shows a 1% linearity up to 2.4 mV_pp of 1 kHz sinusoidal input with 0.4 and 0.6 V supplies.