Ultrathin Gallium Oxide as Both Surface Passivation Layer with Conductive Filament Contacts and Alternative Gate Dielectric for 2D MOSFETs

Abstract

2D semiconductor devices undergo significant degradation upon exposure to ambient molecules and contaminants, necessitating effective passivation techniques for protecting both the contact and channel. In this study, ultrathin amorphous gallium oxide (GaO_X) layers are squeeze‐printed from liquid gallium and integrated with 2D tungsten disulfide (WS₂) channels, as both surface passivation layers with conductive filament (CF) contacts and alternative gate dielectrics, for WS₂/GaO_X field‐effect transistors. The ultrathin GaO_X bilayer gate dielectric exhibits a high critical electric field (≈7.9 MV cm⁻¹) and moderate dielectric constant (3.1). Electrical contacts to the GaO_X‐passivated channel are established through irreversible electroforming of the CFs within the ultrathin GaO_X bilayers at the contact region; these bilayers also serve as dielectric passivation layers in the gate and channel regions. The devices display excellent electrical characteristics, including good current saturation, low subthreshold swing (66.6–70.0 mV dec⁻¹), and ultralow hysteresis (0.10–0.12 V), and do not deteriorate after extended storage under ambient conditions. Moreover, this integration of ultrathin GaO_X with WS₂ enables reconfigurable dual‐input logic operations (OR, AND) using the top and back gates as inputs. This study underscores the potential of ultrathin and printable GaO_X layers as critical components for alternative dielectric and passivation applications in 2D nanoelectronics.

This study demonstrates that the liquid‐metal‐printed ultrathin gallium oxide serves as both a surface passivation layer and a gate dielectric for 2D electronic devices, where the Ohmic contacts to the channels are fabricated by conductive filaments via electroforming. The resulting devices exhibit excellent electrical characteristics and long‐term stability, demonstrating the great potential of ultrathin gallium oxide for 2D electronics.

1. Introduction

Transition metal dichalcogenides (TMDs) with nanoscale thicknesses exhibit high in‐plane mobility and tunable bandgaps, transitioning from direct to indirect and decreasing in size as the number of layers increases from monolayer to bulk form.^{[ 1 ]} These crystal layers have dangling‐bond‐free surfaces and can be efficiently isolated from bulk crystals through mechanical and liquid exfoliation techniques, facilitating the formation of high‐quality van der Waals heterostructures with other 2D materials, including TMDs, black phosphorus, and graphene. Devices based on TMDs exhibit customizable charge transport characteristics that can be tuned to n‐ or p‐type through various methods, such as charge‐transfer doping, substitutional doping, and chalcogen vacancy formation.^{[ 2 ]} Owing to these unique properties, TMDs can be applied in a wide range of homo‐ and heterojunction architectures, including field‐effect transistors (FETs), memory devices, and optoelectronic devices.^{[ 3} , ⁴ , ⁵ , ^{6 ]}

However, electronic devices based on TMDs undergo electrical and structural degradation upon exposure to ambient air, moisture, and processing‐induced contaminants because of the atomic thickness of TMDs.^{[ 7} , ⁸ , ^{9 ]} Ambient molecules are detrimental to the device performance of TMD‐based 2D FETs, causing significant hysteresis, unintended doping, and mobility reduction.^{[ 10} , ¹¹ , ^{12 ]} Additionally, organic residues and adsorbates can negatively impact device performance by acting as interfacial charge traps or scattering centers for carriers in TMD channels with high surface‐to‐volume ratios.^{[ 13 ]} To address these challenges, various passivation materials that can prevent degradation and ensure long‐term reliability of 2D TMD devices have been investigated. Amorphous boron nitride and molybdenum oxide passivation layers have been employed to enhance field‐effect mobility and ambient stability of TMD devices.^{[ 14} , ^{15 ]} Furthermore, aluminum oxide, hafnium oxide, and hexagonal boron nitride (h‐BN) have successfully served as both gate dielectrics and passivation layers for molybdenum disulfide (MoS₂) FETs, exhibiting high stability under ambient conditions with negligible hysteresis.^{[ 16} , ^{17 ]} However, these passivation approaches typically involve unscalable mechanical exfoliation of crystal flakes or expensive atomic layer or plasma‐assisted deposition processes that can introduce interfacial defects.^{[ 18 ]} Developing a passivation layer that does not rely on such methods and can also effectively function as a gate dielectric would simplify the fabrication processes and contribute to the advancement of highly reliable 2D TMD electronics.

Forming good electrical contacts to semiconductor channels is crucial for optimizing the performance of devices. Conventional metal contacts to TMD channels, fabricated prior to passivation, expose the channel material to ambient air and processing‐induced contaminants and often result in Fermi‐level pinning.^{[ 19 ]} Thus, several methods have been explored to establish robust electrical contacts to already‐passivated 2D TMD channels. Ultrathin passivation layers, such as monolayer h‐BN and aluminum oxide thin films, have been utilized as tunneling contact layers in tungsten disulfide (WS₂) FETs to mitigate Fermi‐level pinning and reduce Schottky barrier heights.^{[ 20} , ^{21 ]} Additionally, via contacts have been demonstrated for MoS₂ and graphene FETs by etching through h‐BN passivation layers.^{[ 22} , ^{23 ]} However, the performance of tunneling contacts is constrained by the intrinsic resistance of the tunneling insulators, and via contacts necessitate additional processes that may introduce defects into the channel material. An alternative approach involves electroforming of a conductive filament (CF) within an insulating passivation layer, which can viably achieve low‐resistance and clean electrical contacts to underlying passivated semiconductor channels. During electroforming, the insulating passivation layer experiences electrical breakdown, resulting in a drastic reduction in resistance as vacancies or metal atoms migrate to form CFs within the insulator. This technique has been successfully applied to various insulating oxide and nitride passivation layers, enabling the creation of highly stable Ohmic CF contacts with low contact resistances to the underlying channels.^{[ 24} , ²⁵ , ^{26 ]}

Post‐transition metals, such as gallium, indium, and tin, in their liquid states inherently react with oxygen in ambient air, forming self‐limiting native oxide layers on their surfaces through the Cabrera–Mott oxidation mechanism.^{[ 27 ]} This intrinsic property of liquid metals has spurred the development of ultrathin amorphous metal oxides as a novel class of 2D wide bandgap materials. They can be synthesized under atmospheric conditions using various liquid‐metal printing techniques and typically exhibit nanoscale thicknesses below 5–6 nm with large‐area uniformity.^{[ 28} , ²⁹ , ^{30 ]} Among these, ultrathin amorphous gallium oxide (GaO_X) stands out owing to its ease of fabrication stemming from the low melting point of gallium (29.76 °C), along with its large bandgap, high optical transparency, and unique insulating and passivating characteristics.^{[ 31 ]} Ultrathin GaO_X has recently been utilized as the gate dielectric layers for 2D devices based on WS₂ and MoS₂, demonstrating great promise as a low‐cost and high‐performance dielectric with potential scalability for 2D electronics.^{[ 32} , ^{33 ]} In addition, it has been investigated as a large‐area passivation layer for air‐sensitive 2D materials, providing protection against ambient molecules and contaminants while preserving their electrical and optical performance.^{[ 31} , ³⁴ , ^{35 ]}

In this study, we expand on the previous studies and integrate the liquid‐metal‐printed ultrathin GaO_X as an all‐in‐one dielectric into 2D WS₂ metal–oxide–semiconductor field‐effect transistors (MOSFETs), to serve as both passivation layer and gate dielectric. Large‐area ultrathin GaO_X layers are transferred onto WS₂ channels immediately after preparation, fully enveloping and passivating the entire channel surface against ambient air and contamination from subsequent fabrication processes. Electrical contacts to the passivated WS₂ channels are selectively established by electroforming CFs within the ultrathin GaO_X in the contact region, while these same layers serve as dielectric passivation layers in the gate and channel regions. Ultrathin GaO_X undergoes an irreversible electroforming process, resulting in highly stable CF contacts that exhibited near‐Ohmic behaviors. The WS₂/GaO_X MOSFETs fabricated with CF contacts exhibit excellent electrical characteristics with ambient stability and demonstrate reconfigurable dual‐input logic operations (OR, AND).

2. Results and Discussion

The fabrication procedure for the WS₂/GaO_X MOSFETs with CF contacts is depicted in Figure 1 . WS₂ multilayers transferred onto Ti/Pt bottom electrodes were immediately passivated with ultrathin GaO_X, which was prepared using the liquid‐gallium squeeze‐printing technique. The ultrathin GaO_X layers were dry‐transferred twice onto the WS₂ channels to form ultrathin GaO_X bilayers. Detailed fabrication and transfer procedures for the ultrathin GaO_X layers are presented in Figure S1 (Supporting Information) and the Experimental section. Ti/Au drain and source top electrodes and Ni/Au top‐gate electrodes were fabricated on the contact and gate regions, respectively. CFs were created within the ultrathin GaO_X bilayers at the contact regions using the top and bottom electrode pairs to establish direct drain and source contacts to the passivated WS₂ channels. The WS₂/GaO_X MOSFETs utilize the ultrathin GaO_X bilayer as 1) a gate dielectric in the gate region, 2) a passivation layer in the channel region, and 3) a contact layer with CFs in the contact region. Optical microscope images at the bottom of Figure 1 illustrate the fabrication procedure for one of the four fabricated WS₂/GaO_X MOSFETs. The optical microscope images for all the fabricated devices, along with the thickness profiles of the WS₂ multilayer channels ranging from 5.8 (≈8 layers) to 9.8 nm (≈14 layers), are presented in Figure S2 (Supporting Information).

Figure 1.

Schematic (top) and optical microscope images (bottom) illustrating the fabrication process of WS₂/GaO_X MOSFETs with CF contacts. The ultrathin GaO_X bilayer serves as a gate dielectric, passivation layer, and CF contact layer for the 2D WS₂ channel. Scale bars in the optical microscope images are 10 µm.

The crystallinity of the passivated WS₂ multilayer channels in the WS₂/GaO_X MOSFETs was analyzed using micro‐Raman spectroscopy with a 532‐nm laser (Figure 2a). The E¹ _2g and A_1g peaks at 351 and 420 cm⁻¹ correspond to the in‐plane and out‐of‐plane vibrational modes of multilayer WS₂, respectively.^{[ 36 ]} In comparison with the previously reported values of E¹ _2g (355 cm⁻¹) and A_1g (417 cm⁻¹) peaks for monolayer WS₂, the multilayer WS₂ used in this work exhibited decreased E¹ _2g and increased A_1g peaks, which is consistent with previous reports.^{[ 37 ]}

Figure 2.

Characterization of the WS₂ channel and the ultrathin GaO_X monolayer and bilayer. a) Raman spectrum of the WS₂ multilayer channel in a WS₂/GaO_X MOSFET. XPS spectra obtained from an ultrathin GaO_X bilayer showing the b) Ga 2p_3/2 and c) O 1s regions. d) AFM height profile and image of ultrathin GaO_X monolayer and bilayer prepared on a Si/SiO₂ substrate. The height profile was measured along the white dotted line shown on the AFM image, whose scale is identical to that of the x‐axis (distance). e) Capacitance–voltage characteristics and f) dielectric breakdown characteristics of the ultrathin GaO_X bilayer obtained from a vertical Pt/GaO_X/graphene MIM device. The insets show the respective schematics of the device and measurement setup.

The chemical composition of the ultrathin GaO_X bilayer was examined using X‐ray photoelectron spectroscopy (XPS). Figure 2b,c illustrates the XPS profiles obtained from a large‐area GaO_X bilayer prepared on a Pt surface, corresponding to the Ga 2p_3/2 and O 1s regions, respectively. The Ga 2p_3/2 region (Figure 2b) is deconvoluted into peaks representing gallium‐to‐oxygen (Ga─O) bonds and metallic gallium at binding energies of 1118.4 and 1116.3 eV, respectively.^{[ 38} , ^{39 ]} The O 1s region (Figure 2c) is deconvoluted into peaks at binding energies of 531.2 and 532.6 eV, corresponding to oxygen‐to‐gallium (O─Ga) bonds and oxygen vacancies (O_V), respectively.^{[ 40 ]} The metallic gallium peak in the Ga 2p_3/2 region can be attributed to residual liquid gallium droplets around the periphery of the ultrathin GaO_X bilayer, as illustrated in Figure S3 (Supporting Information). The stoichiometry of the ultrathin GaO_X bilayer was estimated from the ratio of the Ga─O and O─Ga peak areas in the Ga 2p_3/2 and O 1s spectra, respectively. A gallium‐to‐oxygen ratio of 42%:58% was obtained, corresponding to the sub‐stoichiometric chemical composition of Ga₂O_2.8. This result implied that the ultrathin GaO_X bilayer, fabricated through stacking of squeeze‐printed ultrathin GaO_X monolayers, contained O_V. This is in good agreement with the O_V peak observed in the O 1s region (Figure 2c) and results of previous studies, in which native gallium oxides formed on the surface of liquid‐gallium droplets exhibited oxygen‐deficient chemical compositions.^{[ 41} , ^{42 ]}

The thickness and morphology of the squeeze‐printed ultrathin GaO_X layers were analyzed using atomic force microscopy (AFM). Figure 2d illustrates the height profile of the ultrathin GaO_X monolayer (≈4.7 nm) and bilayer (≈10.1 nm), with the corresponding AFM image presented in the inset. An optical microscope image and enlarged AFM image of the ultrathin GaO_X layers are shown in Figure S4 (Supporting Information). The thickness of the ultrathin GaO_X bilayer is slightly higher than twice that of the ultrathin GaO_X monolayer because of the formation of van der Waals gap between the ultrathin layers, which has been previously observed for stacked ultrathin metal oxide layers.^{[ 29 ]} The ultrathin GaO_X layers also exhibited highly uniform surfaces with a low root‐mean‐square roughness of 0.4–0.6 nm, which makes them ideal for forming heterostructures with atomically clean interfaces with 2D materials.

A vertical Pt/GaO_X/graphene metal–insulator–metal (MIM) device was fabricated to investigate the dielectric properties of the ultrathin GaO_X bilayer. Figure 2e presents the capacitance–voltage characteristics of the MIM device, obtained at a frequency of 100 kHz. The MIM device with the ultrathin GaO_X bilayer insulator exhibited a steady capacitance across the gate voltage range of −1 to+1 V. The dielectric constant of the ultrathin GaO_X bilayer was 3.1, which was estimated using Equation (1):

$$C_i={\epsilon }_0{\epsilon }_r\frac{1}{d}$$ (1)

where C_i , ɛ₀, ɛ_r, and d denote the capacitance per unit area, vacuum permittivity, dielectric constant, and insulator thickness, respectively. The dielectric constant of the fabricated GaO_X bilayer (3.1) was lower than that (≈10) of amorphous gallium oxide with higher thicknesses (≥50 nm), whereas it was comparable to that (≈3.6) of other squeeze‐printed ultrathin GaO_X layers with similar thicknesses.^{[ 43} , ⁴⁴ , ^{45 ]} This result can be attributed to the dead‐layer effect observed in capacitors with ultrathin insulators, where the local dielectric constant at the metal–insulator interfaces decreases drastically, thereby reducing the dielectric constant.^{[ 46} , ⁴⁷ , ^{48 ]} The dielectric constants of several insulating oxides with ultrathin thicknesses (≤10 nm) are reportedly lower than their bulk values.^{[ 49} , ⁵⁰ , ^{51 ]} The leakage current of the MIM device is illustrated in Figure 2f. The ultrathin GaO_X bilayer exhibited a dielectric breakdown voltage of +8 V, which corresponded to a high critical electric field of ≈7.9 MV cm⁻¹. This critical electric field was comparable to that of a previously reported atomic‐layer‐deposited amorphous gallium oxide film (≈7.6 MV cm⁻¹) with a thickness of 40 nm as well as to the theoretical value (≈8 MV cm⁻¹) of a β‐phase gallium oxide crystal.^{[ 52} , ^{53 ]}

The cross‐sectional structures of the WS₂/GaO_X MOSFETs with CF contacts were investigated using transmission electron microscopy (TEM). Figure 3a illustrates a side‐view schematic of the device, depicting the gate region (blue), channel region (gray), and contact regions with CFs (red) and without CFs (orange). Figure 3b–e presents the corresponding TEM images of these regions in the device, designated by the color of the dashed borders. The ultrathin GaO_X bilayer formed a high‐quality heterointerface with the WS₂ channel in all the regions (Figure 3b–e) and displayed high uniformity with a distinct bilayer structure in regions without CFs (Figure 3b,c,e). In contrast, the ultrathin GaO_X bilayer in the contact region with CFs (Figure 3d) exhibited a deformed structure, indicating the formation of CFs inside the insulating layer. Additionally, the ultrathin GaO_X exhibited distinct amorphous characteristics compared to the crystalline WS₂, as demonstrated by the high‐resolution TEM images presented in Figure S5 (Supporting Information).

Figure 3.

Cross‐sectional structure of the WS₂/GaO_X MOSFET and the electroforming process of CF contacts. a) Side‐view schematic of the WS₂/GaO_X MOSFET illustrating the top‐gate region (blue), channel region (gray), and contact regions with (red) and without (orange) CFs. TEM images of the device showing the b) top‐gate region (blue), c) channel region (gray), d) contact region with CFs (red), and e) contact region without CFs (orange). Scale bars are 5 nm. f) Electrical characteristics of the ultrathin GaO_X bilayer in a Pt/WS₂/GaO_X/Ti contact structure of a WS₂/GaO_X MOSFET during the electroforming process. The inset is a schematic of the contact structure and the electroforming process. Back‐gated output (I_DS −V_DS ) characteristics of representative WS₂/GaO_X MOSFET (#1) g) before and h) after the electroforming process. The insets are schematics of the device before and after the electroforming process, with the utilized terminals marked in red. i) Magnified current–voltage curves of the electrical characteristics shown in Figure 3f, with dotted arrows indicating the sweep direction of each curve.

The CF contacts to the passivated WS₂ channels in the WS₂/GaO_X MOSFETs were created by electroforming. The representative electrical characteristics recorded during the electroforming process under a compliance current (I_comp) limits of 0.1, 1, and 5 mA are illustrated in Figure 3f. Figure 3i displays the magnified current–voltage curves corresponding to the electrical characteristics presented in Figure 3f, where the sweep direction of the curves is illustrated by the dotted arrows. The ultrathin GaO_X bilayers exhibited a continuous and irreversible decrease in resistance during the electroforming processes, even after the I_comp limit was increased and irrespective of the polarity of the applied biases (Figure 3i). This irreversible electroforming can be explained by the formation of permanent CFs in binary metal oxides.^{[ 54} , ^{55 ]} Under electric fields with increasing strengths, a current pathway created within the insulator becomes narrower with the increasing current density, resulting in localized Joule heating. The local temperature gradient subsequently changes the atomic structure of the metal oxide in the vicinity of the current pathway, typically causing inward migration of O_V via the Soret effect and resulting in the formation of a permanent CF. The irreversible CFs observed in the oxygen‐deficient ultrathin GaO_X bilayer can be ascribed to the permanent aggregation of O_V due to the localized Joule heating resulting from the repeated application of a strong external electric field.

The stability of the irreversible CFs formed within the ultrathin GaO_X bilayers was examined by performing identical measurements after 324 days under a I_comp limit of 5 mA. The representative electrical characteristics recorded after 324 days (Figure S6, Supporting Information) demonstrated the stability of the irreversible CFs, which maintained their low‐resistance characteristics. The back‐gated electrical characteristics of the WS₂/GaO_X MOSFETs were investigated before and after electroforming to confirm the effectiveness of the CF contacts. Figure 3g,h shows the back‐gated output (I_DS −V_DS ) characteristics of a representative device before and after the formation of CF contacts, respectively. The back‐gated electrical characteristics of all the devices before and after electroforming are shown in Figure S7 (Supporting Information). Following the formation of the CF contacts, the devices exhibited significantly improved electrical characteristics compared with those measured before electroforming. Devices with CF contacts demonstrated excellent gate controllability with an on/off current ratio (I_on /I_off ) of 10⁶–10⁷ and near‐Ohmic conductivity, which were consistent with the characteristics of previously reported 2D TMD devices with h‐BN passivation layers and CF contacts.^{[ 26 ]} These results indicate that forming CFs in ultrathin GaO_X bilayers is an effective method for creating contacts for 2D passivated semiconductor channels.

The top‐gated electrical characteristics of the WS₂/GaO_X MOSFETs, utilizing ultrathin GaO_X bilayers as the gate dielectric, were analyzed after the formation of CF contacts. Figure 4a presents the transfer (I_DS −V_TG ) and gate leakage (I_GS −V_TG ) characteristics of the representative device at V_DS = +0.1, +0.5, +1.0, and +2.0 V. Figure 4b,c show the output (I_DS −V_DS ) characteristics and double‐sweep transfer (I_DS −V_TG ) characteristics at V_DS = +1.0 V, respectively. Top‐gated electrical characteristics for all the other fabricated devices are presented in Figure S8 (Supporting Information). The representative device exhibited n‐type depletion‐mode characteristics with a threshold voltage (V_th ) of −1.8 V and a high I_on /I_off of ≈10⁷. Moreover, the device showed a low subthreshold swing (SS) of 70.0 mV dec⁻¹ and minimal hysteresis (+0.12 V). The output curves of the device displayed distinct current saturation characteristics, with low knee voltages below V_DS = +0.5 V. Gate leakage current (I_GS ) during device operation was minimal (≤1 pA). The field‐effect mobility (µ _FE ) of the device was 41.7 cm² V⁻¹ s⁻¹, which was calculated from the plot of $\sqrt{I_{DS}}$ versus V_TG using Equation (2):

$${\mu }_{FE}=\frac{2}{C_i}\frac{L}{W}{\left(\frac{\partial \sqrt{I_{DS}}}{\partial V_{TG}}\right)}^2$$ (2)

which is a modified approximation for drain current in the saturation regime of a MOSFET ($I_{DS}=\frac{1}{2}{\mu }_{FE}{C}_i\frac{W}{L}{(V_{TG}-V_{th})}^2$), where L and W denote the channel length and width, respectively.^{[ 56 ]} The transfer curve measured at V_DS = +1.0 V was utilized for plotting $\sqrt{I_{DS}}$ versus V_TG to ensure current saturation. The other fabricated devices exhibited similar electrical characteristics with depletion‐mode operation (Figure S8, Supporting Information), featuring a high I_on /I_off of 10⁶–10⁷ and µ _FE of 40.6–142.4 cm² V⁻¹ s⁻¹. All the devices demonstrated current saturation with low knee voltages (≤+1.0 V) and excellent SS in the range of 66.6–70.0 mV dec⁻¹, alongside minimal hysteresis (≤+0.12 V). The FET parameters for each device are summarized in Table S1 (Supporting Information). The interface state density (D_it ) of the WS₂/GaO_X interface of all the devices was calculated to be as low as 2.1–3.1 × 10¹¹ cm⁻² eV⁻¹ using Equation (3):

$$SS=\ln \left(10\right)\frac{k_{B}T}{q}\left(1+\frac{q{D}_{it}}{C_{ins}}\right)$$ (3)

where k_B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and C_ins is the capacitance per unit area of gate insulator.^{[ 33 ]} The outstanding transfer characteristics of these devices can be attributed to the high‐quality WS₂/GaO_X interface which preserves the transconductance and switching speed of the conducting channel by reducing interfacial charge scattering, as well as the quality of the exfoliated multilayer channels.^{[ 57 ]} Ultrathin GaO_X has a large bandgap (≈5.1 eV) and forms type I band alignment with n‐type WS₂ with a sizable conduction band offset, as depicted in the band diagram of the WS₂/GaO_X/Ni structure in Figure S9 (Supporting Information).^{[ 1} , ^{31 ]} Because of this band structure and the high critical electric field (≈7.9 MV cm⁻¹), the ultrathin GaO_X bilayer can effectively function as a dielectric barrier for the WS₂ channel. The current saturation characteristics observed in the WS₂/GaO_X MOSFETs can be attributed to the pinch‐off of electrons at the drain end of the channel and are crucial for circuit applications owing to their ability to enhance the voltage gain.^{[ 56} , ⁵⁸ , ^{59 ]} Moreover, the low knee voltages (≤+1.0 V) reduce power consumption, facilitating low‐power operations.

Figure 4.

Top‐gated electrical characteristics of WS₂/GaO_X MOSFETs with CF contacts. a) Top‐gated transfer (I_DS −V_TG ) and gate leakage (I_GS −V_TG ) characteristics of representative WS₂/GaO_X MOSFET (#1) at different V_DS . The inset shows a schematic of the device, with the utilized terminals marked in red. b) Output (I_DS −V_DS ) characteristics and c) double‐sweep transfer (I_DS −V_TG ) characteristics at V_DS = +1.0 V of representative WS₂/GaO_X MOSFET (#1). d) Top‐gated transfer (I_DS −V_TG ) and leakage current (I_GS −V_TG ) characteristics at different V_DS , e) output (I_DS −V_DS ) characteristics, and f) double‐sweep transfer (I_DS −V_TG ) characteristics at V_DS = +1.0 V of the identical device after 324 days of storage under ambient conditions.

To investigate air stability, the representative device was stored under ambient conditions (temperature of 25 ± 2 °C and relative humidity of 20 ± 5%) for 324 days following the initial measurement, and its top‐gated electrical characteristics were re‐evaluated. Figure 4d depicts the transfer (I_DS −V_TG ) and gate leakage (I_GS −V_TG ) characteristics of the representative device at V_DS = +0.1, +0.5, +1.0, and +2.0 V, measured after 324 days. Figure 4e,f present the output (I_DS −V_DS ) characteristics and double‐sweep transfer (I_DS −V_TG ) characteristics at V_DS = +1.0 V, respectively, of the same device stored for 324 days. The device maintained excellent transfer characteristics with a low SS of 70.4 mV dec⁻¹, a high I_on /I_off (≈10⁷), and minimal hysteresis (≤+0.09 V). The current saturation characteristics persisted, and the knee voltages slightly increased but remained below V_DS = +0.8 V. The device exhibited consistent V_th and µ _FE , with a small V_th shift of ≈0.6 V and comparable µ _FE of 42.0 cm² V⁻¹ s⁻¹. A slight increase in I_GS (≤8 pA) was observed under positive V_TG at low V_DS (≤+0.5 V); however, it was otherwise negligible (≤1 pA). Table 1 summarizes the FET parameters of the representative device initially and after 324 days. The slight changes observed in V_th , I_{GS ,} and hysteresis can be attributed to minor initial charge trapping effects induced by O_V in the ultrathin GaO_X, which occurred between day 0 and day 50 and remained minimal over an extended period up to 324 days (Figure S10, Table S2, Supporting Information).^{[ 60 ]} To further evaluate the stability of the WS₂/GaO_X MOSFET with CF contacts, the electrical characteristics of the representative device stored under ambient conditions for 324 days were analyzed under varying temperatures (25, 50, 75, 100, and 125 °C) which are presented in Figure S11 (Supporting Information) and summarized Table S3 (Supporting Information). The electrical characteristics of the device were largely preserved even at elevated temperatures, with I_on /I_off (10⁶–10⁷), hysteresis (≤+0.09 V), µ _FE (42.0–56.5 cm² V⁻¹ s⁻¹), and saturation characteristics remaining consistent. A small shift in V_th and an increase in SS from 70.4 to 81.5 mV dec⁻¹ were observed at higher temperatures, which can be attributed to the elevated operating temperature.

Table 1.

FET parameters (field‐effect mobility (µ _FE ), subthreshold swing (SS), on/off current ratio (I_on /I_off ), and threshold voltage (V_th )) of representative WS₂/GaO_X MOSFET (#1) with CF contacts, calculated from top‐gated electrical characteristics obtained during the initial measurement (day 0) and after 324 days of storage (day 324) under ambient conditions.

device #1	µ FE [cm2 V−1 s−1]	SS [mV dec−1]	Ion /Ioff	Vth [V]
day 0	41.7	70.0	≈107	−1.8
day 324	42.0	70.4	≈107	−1.2

Overall, the electrical characteristics of the WS₂/GaO_X MOSFET did not degrade significantly after 324 days of ambient storage and even under high temperatures up to 125 °C, highlighting the effectiveness of ultrathin GaO_X as a dielectric passivation layer for 2D devices as well as the viability of the CF contacts. Despite its low dielectric constant (3.1), the incorporation of ultrathin GaO_X enabled satisfactory device performance, which is comparable to that of higher‐κ dielectrics (Table S4, Supporting Information).^{[ 32} , ⁶¹ , ⁶² , ⁶³ , ⁶⁴ , ⁶⁵ , ⁶⁶ , ⁶⁷ , ⁶⁸ , ⁶⁹ , ⁷⁰ , ^{71 ]} The relatively lower drain current and µ _FE observed from the devices can be attributed to the higher contact resistance of the CF contacts, estimated to be 99.8–164.3 kΩ·µm using the Y function method,^{[ 72} , ^{73 ]} which is higher than that of 2D devices with conventional contact methods (Table S5, Supporting Information).^{[ 1 ]} Future optimization of the CF contact process can further reduce contact resistance while retaining the advantage of 2D channel passivation, which minimizes contamination and prevents device performance degradation from ambient exposure.^{[ 9 ]} With its demonstrated functionality and stability, the ultrathin GaO_X exhibits great potential for integration into large‐scale 2D electronics, which can be realized through scalable optimization of the liquid‐metal‐printing process as demonstrated by Kong et al.^{[ 74 ]}

The excellent switching performance of the WS₂/GaO_X MOSFETs can be further tailored using a global back gate to control carrier density. Figure 5a displays the top‐gated transfer (I_DS −V_TG ) characteristics of a different device at V_DS = +2.0 V under varying V_BG . Evidently, V_th showed a consistent negative shift as V_BG was increased during dual‐gate operation. The device maintained satisfactory switching characteristics with V_BG ranging from −10 to +16 V, including a high I_on /I_off of 10⁶–10⁷ and SS of 67.3–80.7 mV dec⁻¹, indicating effective carrier modulation through the dual‐gate structure without compromising the electrical performance. Stable dual‐gate operation enabled reconfigurable logic applications such as OR and AND gates, with V_TG , V_BG , and I_DS serving as inputs 1, 2, and output, respectively. Figure 5b presents a contour plot of I_DS against V_TG and V_BG derived from the transfer curves of the dual‐gate device presented in Figure 5a. Current outputs below and above a threshold of 1 nA were defined as outputs “0 (off)” and “1 (on),” respectively (represented by the dotted line (stone gray) in Figure 5a). Based on this threshold, appropriate values of V_TG (input 1) and V_BG (input 2) were assigned to demonstrate OR and AND gate logic operations, as depicted in Figure 5c,d, respectively. In both these operations, V_BG = −6.0 and +6.0 V were assigned as “0” and “1” for input 2, respectively. For the OR gate operation, V_TG = −1.2 and −0.4 V were assigned as “0” and “1” for input 1, respectively, whereas for the AND gate operation, V_TG = −1.8 and −1.0 V were assigned as “0” and “1” for input 1, respectively. The dual‐gated WS₂/GaO_X MOSFET demonstrated efficient reconfigurable logic operations of OR and AND gates, requiring minor adjustments to input 1 (V_TG ) to alter the logic outcomes. These results collectively highlight the significant potential of ultrathin GaO_X layers, which can be integrated into nanoscale semiconductor devices with excellent switching and current saturation characteristics and reconfigurable logic capabilities, for application in 2D dielectric and passivation.

Figure 5.

Demonstration of dual‐gate logic operations of WS₂/GaO_X MOSFETs with CF contacts. a) Top‐gated transfer (I_DS −V_TG ) characteristics of WS₂/GaO_X MOSFET (#2) obtained under varying V_BG . The inset shows a schematic of the device, with the utilized terminals marked in red. b) Contour plot of I_DS against V_TG and V_BG . Demonstration of c) OR and d) AND gate logic operations of the device with a current threshold of 1 nA.

3. Conclusion

This paper reports the feasibility of applying liquid‐metal‐printed ultrathin GaO_X as both a surface passivation layer with CF contacts and an alternative gate dielectric in 2D MOSFETs. In this study, the highly uniform GaO_X bilayer, with a thickness of ≈10.1 nm, formed an atomically clean interface with the WS₂ channel and exhibited a high critical electric field of ≈7.9 MV cm⁻¹, along with a modest dielectric constant of 3.1. Direct passivation of the 2D WS₂ channels using ultrathin GaO_X bilayers ensured their high stability against ambient air and processing‐induced contamination, while irreversible electroforming of CFs within the ultrathin GaO_X enabled the creation of near‐Ohmic drain and source contacts to the passivated 2D TMD channel. The ultrathin GaO_X bilayer also exhibited a promising performance as an alternative dielectric material, exemplified by the excellent fast‐switching and current saturation characteristics of WS₂/GaO_X MOSFETs, which remained highly stable after 324 days of storage in ambient conditions. Stable dual‐gate operation of the WS₂/GaO_X MOSFETs enabled reconfigurable logic gate (OR, AND) operations, highlighting the versatility and potential of ultrathin GaO_X bilayers in 2D device applications. The versatility of the liquid‐metal‐printed ultrathin GaO_X layers demonstrated in this study positions them as essential components for future nanoelectronics, particularly in both dielectric and filament‐forming passivation applications for 2D semiconductor devices.

4. Experimental Section

Preparation of the Ultrathin GaO_X and Its Dry‐Transfer

The preparation and dry‐transfer of ultrathin GaO_X monolayers are illustrated in Figure S1 (Supporting Information). Initially, 1.5 g of polypropylene carbonate (PPC; Sigma–Aldrich) and 10 g of anisole (anhydrous, 99.7%, Sigma–Aldrich) were mixed to form a solution, which was stirred at 60 °C for 12 h to prepare a PPC solution. Transparent polydimethylsiloxane (PDMS) films (Gel‐Pak) were placed on glass slides, and the PPC solution was spin‐coated onto these films at 5000 rpm for 60 s; the coated films were subsequently baked at 100 °C for 10 min. Liquid‐gallium (99.9995%, Sigma–Aldrich) droplets were placed on the PDMS/PPC films heated to 40 °C. The droplets were firmly compressed with another PDMS film supported on a glass slide to form ultrathin GaO_X monolayers on the PDMS/PPC films. These fabricated ultrathin GaO_X monolayers were dry‐transferred onto target substrates using the PPC film as a sacrificial layer.

Upon complete contact of an ultrathin GaO_X monolayer with a target substrate, the substrate temperature was raised to and maintained at 90 °C for ≈5 min to soften the PPC film, facilitating its separation from the PDMS film. Throughout the removal of the PDMS film, the PPC film remained and secured the ultrathin GaO_X monolayer on the target substrate, preventing its detachment. The remaining PPC film on the ultrathin GaO_X monolayer and substrate was eliminated by submerging in acetone for ≈30 min. This procedure was repeated twice to construct ultrathin GaO_X bilayers on WS₂/GaO_X MOSFETs and Pt/GaO_X/graphene MIM device.

Device Fabrication

The fabrication procedure of the WS₂/GaO_X MOSFETs is depicted in Figure 1. Ti/Pt (5/15 nm) bottom electrodes were prepared on 525‐µm Si substrates with a thermally grown 300‐nm SiO₂ layer using electron‐beam lithography, electron‐beam evaporation, and lift‐off processes. WS₂ multilayer flakes were mechanically exfoliated from bulk WS₂ crystals (HQ Graphene, typical carrier density: ≈10¹⁴ cm⁻³) and were aligned with and dry‐transferred onto the prepared Si/SiO₂ substrates with Ti/Pt bottom electrodes to form device channels. The samples were subjected to thermal annealing under high vacuum (≈9 × 10⁻⁷ Torr) at 200 °C for 2 h to eliminate interfacial bubbles and polymeric residues. Ultrathin GaO_X bilayers were then formed on the WS₂ channels as described previously. Ti/Au (20/80 nm) top electrodes for drain and source terminals were deposited on the contact region (above the Ti/Pt bottom electrodes), while Ni/Au (20/80 nm) gate electrodes were deposited on the channel region using electron‐beam lithography, electron‐beam evaporation, and lift‐off processes. Drain and source CF contacts to the WS₂ channel were established by electroforming CFs. During the electroforming process, alternating forward (0 to +10 V) and reverse (0 to −10 V) double‐sweep measurements were performed consecutively to induce a concentrated electric field, causing electrical breakdown in the insulating ultrathin GaO_X bilayers to create the CFs. Biases up to ±10 V were applied to the top electrodes (Ti/Au), while the corresponding bottom electrodes (Ti/Pt) in the same contact region were grounded. The I_comp limit during the electroforming process was sequentially increased from 0.1 to 1 mA and subsequently to 5 mA.

A Pt/GaO_X/graphene MIM device was prepared on a Si/SiO₂ substrate with prepatterned Ti/Pt (5/45 nm) bottom electrodes. An ultrathin GaO_X bilayer was prepared on the Ti/Pt bottom electrode as described earlier. A multilayer graphene flake was mechanically exfoliated from a bulk graphite crystal (HQ Graphene) and dry‐transferred onto the Pt/GaO_X structure to complete the Pt/GaO_X/graphene MIM device.

Material Characterization

The structure and morphology of the ultrathin GaO_X layers, WS₂ multilayer flakes, WS₂/GaO_X MOSFETs, Pt/GaO_X/graphene MIM device, and substrates were investigated using an optical microscope (BX53M, Olympus). Back‐scattering micro‐Raman spectroscopy was performed employing a 532‐nm laser (Greenphoton KFL Series; Omicron‐Laserage Laserprodukte GmbH) to assess the crystallinity of the WS₂ multilayer channels. AFM (NX10, Park Systems) analyses were conducted to determine the thickness of the WS₂ multilayer channels and the thickness and the root‐mean‐square roughness of the ultrathin GaO_X monolayers and bilayers. The chemical composition of the ultrathin GaO_X bilayers was examined by XPS (Nexsa, Thermo Fisher Scientific), with an Al Kα monochromator as the X‐ray source. The surface of the ultrathin GaO_X bilayer sample was etched with Ar ions at 500 eV for 30 s prior to the XPS analysis to minimize the effect of surface contaminants. The XPS data were calibrated using the C 1s peak (284.8 eV) as the reference peak, and the Scofield sensitivity factors were used to calculate the chemical composition. Specimens for TEM (JEM‐2100F, JEOL) were prepared by focused‐ion‐beam (Quanta 3D FEG, FEI) milling of a fabricated WS₂/GaO_X MOSFET protected with a boron nitride layer.

Electrical Characterization

The current–voltage characterization of the WS₂/GaO_X MOSFETs and Pt/GaO_X/graphene MIM device was conducted using a semiconductor parameter analyzer (4155c, Agilent), connected to a probe station (MS Tech), at room temperature under low vacuum conditions (≈10 mTorr). The capacitance–voltage characterization of the Pt/GaO_X/graphene MIM device was performed using a precision LCR meter (4285A, Agilent), connected to a probe station (MS Tech), at room temperature under ambient conditions.

Conflict of Interest

The authors declare no conflict of interest.

Supporting information

Supporting Information

Moon S. and Kim J., “Ultrathin Gallium Oxide as Both Surface Passivation Layer with Conductive Filament Contacts and Alternative Gate Dielectric for 2D MOSFETs.” Small 21, no. 37 (2025): 21, 2410420. 10.1002/smll.202410420

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.