Reconfigurable Neuron and Synapse Operations in a Steep‐Switching Nonvolatile Transistor

Abstract

Neuromorphic systems that emulate the information transmission of biological neural networks face challenges in their integration owing to the disparate features of neuron‐ and synapse‐mimicking devices, leading to complex and inefficient system architectures. Herein, the study proposes a steep‐switching nonvolatile field‐effect transistor leveraging a CuInP₂S₆/h‐BN/WSe₂ heterostructure to enable reconfigurable neuron‐ and synapse‐modes by electrostatically modulating the carrier density of the channel to control its Fermi level, thereby facilitating leaky‐integrate‐and‐fire (LiF) neuron operation. In addition, an additional ferroelectric‐gating effect enhances the chemical potential of the channel through interactions between ferroelectric dipoles and channel carriers, allowing LiF operation at a reduced operating bias condition. The synaptic mode is activated by shifting the Fermi level of the channel toward the valence band, where the increased carrier density induces a screening effect that suppresses impact ionization and causes the device to operate predominantly through ferroelectric effects, enabling weight‐modulated synaptic functionality. A device‐to‐system level simulation of the spiking neural network is performed based on a single device neuron‐synapse integrated system, achieving an accuracy of 95.83% for human face recognition via lateral inhibition function of the neuron device. This study presents a promising approach for the development of a cointegrated and highly scalable neuromorphic computing technology.

This study demonstrates a steep‐switching non‐volatile field‐effect transistor capable of both neuron‐ and synapse‐mode operations within a single device structure. Uniquely, by electrostatically tuning the channel Fermi level via back‐gate bias, the device selectively switches between neuron and synapse modes under the same presynaptic input conditions, eliminating the need for pulse differentiation or structural separation.

1. Introduction

Neuromorphic computing is a paradigm that mimics the functions and structures of the human brain to achieve high computational efficiency and compact hardware integration.^{[ 1} , ² , ^{3 ]} With advances in neuromorphic research, various electronic device structures have been proposed to emulate the behavior of biological synapses and neurons.^{[ 4} , ⁵ , ⁶ , ^{7 ]} However, from the perspective of system integration, these approaches increase the structural complexity and energy consumption owing to differing operational requirements, such as device structure and operating conditions, between artificial neurons and synapse devices.^{[ 8} , ^{9 ]}

Most existing approaches use separate devices for the neuron and synapse functionalities to implement artificial neural networks, with most studies focusing solely on synaptic devices.^{[ 10} , ¹¹ , ¹² , ^{13 ]} This hinders the practical implementation of cointegrated neuromorphic computing, particularly because of the challenges in system integration arising from heterogeneous device structures.^{[ 14 ]} To address the challenges in system integration, Kim et al. demonstrated cointegrated neuron and synapse functionalities within a single device structure by leveraging the coexistence of tetragonal for volatile neuron behavior and orthorhombic for nonvolatile synaptic functionality in hafnium zirconium oxide.^{[ 15 ]} Although this approach demonstrates functional integration, it presents a major limitation in system design flexibility, as the device functionality becomes fixed once the material phase is determined.

To address the limitation of system design flexibility, researchers have focused on implementing neuron and synapse operations using a single device, primarily based on memristors.^{[ 16} , ¹⁷ , ¹⁸ , ^{19 ]} In memristive devices, reconfigurable neuron and synapse modes are achieved by modulating the strength of the conductive filaments depending on the applied voltage. Weak filaments formed under low voltages induce short‐term memory (STM) characteristics, enabling neuron‐like behavior, whereas stronger filaments formed under higher voltages result in long‐term memory (LTM) characteristics, facilitating synaptic functionality. These two‐terminal reconfigurable neuron and synapse devices represent an important milestone, as they were among the first to propose a direction for improving the flexibility of integrated neuromorphic systems. Despite these advances, several practical challenges remain unresolved. In particular, neuron and synapse operations intrinsically require different input voltage conditions. Consequently, building a fully integrated system based on such devices necessitates the application of multiple voltage levels across the entire system, which complicates circuit design and power management. This limitation highlights the necessity for a novel approach that enables selective neuron and synaptic mode activation under unified input conditions. Achieving reconfigurability via global control mechanisms rather than relying on local pulse‐strength variations presents a solution for a more scalable and integration‐friendly path toward practical neuromorphic hardware.^{[ 20 ]}

In this study, we propose a reconfigurable steep‐switching nonvolatile field‐effect transistor (SS‐NV FET) that addresses the integration challenges in neuromorphic systems by enabling both neuron‐ and synapse‐mode operations through channel carrier density modulation. The proposed device adopts a heterostructure that combines an h‐BN/WSe₂ impact ionization FET (I²FET) with a top ferroelectric layer of CuInP₂S₆. By tuning the channel Fermi level (E_f) via a back‐gate bias, selective activation of neuron‐ and synapse‐mode operations is achieved. In the neuron mode, channel E_f is maintained at an intrinsic Fermi level (E_i) to facilitate impact ionization‐induced carrier amplification. Moreover, the polarization of the ferroelectric layer enhances the additional energy of the channel, increasing the carrier acceleration energy, and reducing the operating voltage to 0.8 V. Consequently, the device exhibits a steep‐switching characteristics (subthreshold swing, SS = 6.53 and 7.34 mV dec⁻¹ in forward and reverse sweep, respectively) under room temperature, thereby demonstrating low‐power leaky‐integrate‐and‐fire (LiF) neuron operation. By contrast, in the synaptic mode, the channel is tuned to a highly p‐doped state, enhancing the screening effect, where a high carrier density in the channel reduces the electric field strength experienced by individual carriers. This suppresses the mean free path required for carrier acceleration, thereby inhibiting the initiation of impact ionization. Under these conditions, ferroelectric polarization allowed the device to exhibit a memory window (MW) of 2.48 V and emulated biological synaptic plasticity by demonstrating long‐term potentiation (LTP) and long‐term depression (LTD) characteristics with a conductance ratio (G_max/G_min = 30). Furthermore, we implemented a spiking neural network (SNN) by integrating this reconfigurable neuron‐ and synapse dual‐mode operation of our device. The SNN system was evaluated through unsupervised learning‐based device‐to‐system level simulation, achieving a high learning accuracy of 95.83% via the lateral inhibition neuronal function to improve the learning efficiency. This paper presents an efficient and practical approach for developing next‐generation neuromorphic systems with enhanced integration efficiency and learning performance.

2. Results and Discussion

2.1. Reconfigurable Neuron and Synapse Dual‐Mode Device

Figure  1a presents an overview of the device schematic and its reconfigurability, which is governed by channel carrier density (ρ) in our device. The proposed SS‐NV FET comprises a CuInP₂S₆(CIPS)/h‐BN/WSe₂ heterostructure fabricated on a heavily p‐doped SiO₂/Si substrate. A partially covered top gate divides the channel into two distinct regions: a gated region (left, red dashed line), where ferroelectric polarization in the CIPS layer increases the chemical potential with a gated region length (L_gated) of ≈3 µm; and an ungated region (right, blue dashed line) unaffected by polarization with ungated region length (L_ungated) of 0.312 µm. Detailed information on the device fabrication process, device dimensions, material composition, and thickness characterization can be found in Figures S1–S3 (Supporting Information). Global electrostatic modulation of the channel carrier density via back‐gate bias allows for selective switching between the neuron and synapse modes. The neuron mode is activated at the intrinsic carrier density to initiate impact ionization, whereas the synaptic mode utilizes a high p‐type doping to activate ferroelectric polarization switching.

Figure 1.

Overview of device structure and reconfigurable neuron and synapse. a) Schematic of the proposed SS‐NV FET constructed with CIPS/h‐BN/WSe₂ heterostructure. The carrier density of the WSe₂ channel layer acts as a switching key between the neuron‐ and synapse‐mode. Illustrations of the operating overview for b) neuron‐ and c) synapse‐mode in SS‐NV FET. WSe₂ channel energy band, carrier density dependence of impact ionization, ferroelectric bound charge induced hysteresis curve, and corresponding neuron and synapse characteristics.

Figure 1b illustrates the mechanism of the neuron‐mode operation. The electrostatic doping of WSe₂ is controlled via a back‐gate bias, which shifts E_F to the intrinsic energy (E_i) level. Under this condition, the holes injected from the drain are accelerated by a strong electric field in the ungated region, gaining sufficient kinetic energy to initiate impact ionization. This impact ionization process generates additional electron‐hole pairs, and the resulting secondary carriers are further accelerated, leading to carrier multiplication and a sharp increase in the drain current. This process is further enhanced by an increase in the chemical potential induced by the ferroelectric polarization‐bound charges in the top ferroelectric layer of the CIPS. These charges were modulated by the top‐gate voltage (V_GS(T)), enabling efficient impact ionization even under low operating bias conditions (Figure 3c). Consequently, our device operating in the neuron mode achieves energy‐efficient LiF neuron operation with sufficient firing current at a low operating voltage.

Figure 3.

Reconfigurable neuronal and synaptic functions in a single SS‐NV FET. a) Illustration of information transmission between presynaptic and postsynaptic neurons via a synapse, along with the corresponding LiF generation and synaptic weight modulation operation scheme of an artificial neuron and synapse using the reconfigurable SS‐NV FET. Upon receiving a unified presynaptic input signal, the operation mode of the neuron or synapse is determined solely by the channel carrier density controlled via V_GS(B). b) Reconfigurable STM (red, V_GS(B) = –3 V) and LTM (blue, V_GS(B) = –10 V) under a single pre‐synaptic pulse at fixed V_DS = 0.8 V, pulse intensity, V_P = −2 V, pulse width t_P = 10 µs. c) Reproducible LiF behavior induced by impact ionization under repeated pulses (V_P = −2 V) at V_GS(T), with fixed V_GS(B) = −3 V (CNP). d) LTM characteristics induced at the conditions of V_GS(B) = −10 V (non‐CNP). e) LTP/LTD curves of the SS‐NV device for 50 cycles (LTP under V_P = −2 V, t_P = 10 us, LTD under V_P = 2 V, t_P = 10 us) at V_GS(B) = −10 V, which is larger than CNP.

By contrast, in the synaptic mode shown in Figure 1c, the back‐gate bias induces an increased hole density in the WSe₂ channel by shifting the E_F closer to the valence band (E_v). This high carrier density increases carrier‐carrier interactions and the screening effect, which dissipates the energy of the injected holes and suppresses impact ionization. In this synaptic mode, the dominant mechanism transitions from impact ionization to ferroelectric polarization, and the CIPS ferroelectric layer becomes the dominant mechanism, allowing nonvolatile operation. It enables synaptic behavior with a wide‐range weight modulation suitable for emulating biological synaptic behaviors such as LTP and LTD characteristics.

2.2. Electrical Characteristics and Mechanisms of the SS‐NV FET

Figure  2a shows the I_DS‐V_GS(T) transfer characteristics under a dual V_GS(T) sweep ranging from 4 to −4 V with a fixed V_DS = 0.8 V and V_GS(B) = −3 V, corresponding to the charge neutral point (CNP), measured at room temperature. Here, CNP refers to the back‐gate bias condition in which the channel carrier density is intrinsic. A detailed analysis of CNP determination is provided in Figure S4 (Supporting Information). The steep‐switching characteristics in both sweep directions (subthreshold swing, SS = 6.53 mVdec⁻¹ in the forward and 7.34 mVdec⁻¹ in the reverse sweep) exhibit clockwise hysteresis and an MW (2.48 V), indicating the dominant contribution of ferroelectric behavior.^{[ 5} , ²¹ , ^{22 ]} The steep switching originates from impact ionization initiated by high‐energy hole carriers in the ungated region, generating electron−hole pairs and subsequent carrier multiplication.^{[ 23} , ^{24 ]}

Figure 2.

Electrical characteristics of the SS‐NV FET. a) I_DS‐V_GS(T) transfer characteristics of the SS‐NV FET. b) Comparison of V_DS between SS‐NV FET (red, CIPS/h‐BN/WSe₂) and baseline I²FET (black, h‐BN/WSe₂) at the same V_GS(T) and V_GS(B). c) Comparison for energy band structure between SS‐NV FET (black) and baseline I²FET (gray). The additional ferroelectric‐gating effect (E_FG ) in SS‐NV FET increases the potential energy drop in the ungated region for impact ionization (eV_a ). d) Contour plot representing impact‐ionization‐induced I_DS as a function of various V_DS and V_GS(T), compared of operating voltage region between baseline I²FET (white dashed line) and SS‐NV FET (yellow dashed line).

Figure 2b shows the role of the ferroelectric layer in facilitating impact ionization within the SS‐NV FET. It compares the electrical characteristics of two FETs: a baseline I²FET (h‐BN/WSe₂, the electrical characteristics of the baseline I²FET are provided in Figure S5, Supporting Information) and an SS‐NV FET (CIPS/h‐BN/WSe₂) in the presence of polarization‐induced bound charges in the SS‐NV FET. At V_GS(T) = −1.7 V and V_GS(B) = −3 V for CNP, the baseline I²FET initiates impact ionization at V_DS = 1.67 V, whereas the SS‐NV FET initiates at lower V_DS = 1.13 V, indicating a reduction in the operating V_DS of 0.54 V. The corresponding transfer curves under the impact‐ionization operating bias condition for the baseline I²FET and SS‐NV FET are presented in Figure S6 (Supporting Information). This reduction in the operation V_DS results from the energy‐band modification induced by the ferroelectric layer.

Figure 2c shows the energy band diagrams of the SS‐NV FET (black) and the baseline I²FET (gray). A key difference lies in the additional energy induced by the top ferroelectric layer in the SS‐NV FET, which leads to a band upshift in the gated region (blue area), denoted by the additional ferroelectric gating effect E_FG. This band upshift effectively increases the energy available to initiate impact ionization. The condition for triggering impact ionization via a potential energy drop in the ungated region is given by µ + eV _DS = eV _a > E _g, where V_a represents potential drop in the ungated region, E_g is energy bandgap of WSe₂, and µ denotes the chemical potential in the gated region.^{[ 23 ]} In the baseline I²FET, µ is interpreted as the built‐in potential formed at the boundary between the gated and ungated regions and is expressed as µ = eV_bi = E_g/2 + E_Fh . Here, E_Fh = ℏ²πρ / m_p is the Fermi energy associated with the hole carrier density (ρ) induced by electrostatic gating. However, in the developed SS‐NV FET, µ is enhanced by both electrostatic and ferroelectric gating and is expressed as µ = eV_bi = E_g/2 + E_Fh + E_FG . Here, E_FG = ℏ²πρ^*/m_p accounts for the additional hole carrier density (ρ^* ) induced by the additional ferroelectric‐gating effect. Consequently, SS‐NV FET can achieve impact ionization at a reduced V_DS, since a portion of the required energy is pre‐supplied by the increased µ, from 0.46 eV (baseline I²FET) to 0.48 eV (SS‐NV FET) (see detailed calculation of µ in Figures S7 and S8 and Note S1, Supporting Information).

Figure 2d shows a comparison of the impact ionization operating bias conditions between the baseline I²FET (black dashed line) and SS‐NV FET (white dashed line) as contour plots of I_DS as a function of applied V_DS and V_GS(T). A high current level indicates a steep‐switching regime. Impact ionization in the baseline I²FET occurs only at V_DS above 1.16 V, whereas the SS‐NV FET exhibits its onset at a significantly lower V_DS of 0.78 V. The results demonstrate a wider operational voltage region for impact ionization in the SS‐NV FET than in the baseline I²FET, highlighting the benefit of the additional ferroelectric gating effect. Specifically, the expansion of the operational voltage region toward the upper‐left shift indicates a direct reduction in the required operating voltage, which is attributable to the polarization‐induced enhancement of the chemical potential via ferroelectric gating. The electrical characteristics of the SS‐NV FET under suppressed impact ionization conditions (V_GS(B) = −10 V) and the corresponding energy band structure in synapse mode are presented in Figures S9 and S10 (Supporting Information). In summary, the SS‐NV FET demonstrates a reconfigurable operation between impact‐ionization‐driven steep‐switching nonvolatile memory and ferroelectric polarization‐driven nonvolatile memory, enabled through the synergistic combination of top ferroelectric gating and back‐gate‐controlled channel carrier modulation.

2.3. Reconfigurable Neuron and Synapse

Figure  3a illustrates the information transmission between the presynaptic and postsynaptic neurons through the synapse, highlighting the corresponding LiF generation and synaptic weight modulation operations using the reconfigurable SS‐NV FET. LiF generation occurs when the channel carrier density is tuned to the intrinsic level via V_GS(B), where a unified input signal applied to V_GS(T) is integrated and triggers a signal upon exceeding the threshold current. As demonstrated in Figures S11 and S12 (Supporting Information), the proposed reconfigurable device reliably generates spike signals based on impact ionization, validating its suitability for neuron functionality. This operation, wherein precise spike signals are generated only when necessary under a unified input condition, highlights the device's potential for energy‐efficient LiF neuron functionality. Synaptic weight modulation is activated when the carrier density is adjusted to the p‐type regime, enabling the presynaptic input received through V_GS(T) to be transmitted to the postsynaptic neuron. Figure 3b shows the reconfigurable STM and LTM behaviors under identical pre‐synaptic pulses in the SS‐NV FET, corresponding to artificial neuron and synapse operations, respectively. These distinct modes were realized under identical presynaptic pulse conditions by globally tuning the channel carrier density via V_GS(B).

In the neuron‐mode (red, V_GS(B) = −3 V and V_DS = 0.8 V), LiF behavior based on STM is observed, where a negative presynaptic pulse (presynaptic pulse intensity, V_P = −2 V; presynaptic pulse width, t_P = 10 µs) applied to the top gate triggers an I_DS spike, reaching the firing threshold (I_th) via impact ionization.^{[ 14} , ²⁵ , ^{26 ]} The back‐gate bias (V_GS(B) = −3 V) induces an intrinsic‐level carrier density in the channel, increasing the mean free path, the average distance a carrier travels before collisions occur, thereby allowing carriers to gain sufficient kinetic energy to initiate impact ionization.^{[ 27 ]} Consequently, a steep‐switching behavior is activated, enabling energy‐efficient LiF operation. In contrast, in the synapse‐mode (blue, V_GS(B) = −10 V and V_DS = 0.8 V), LTM behavior was observed under identical presynaptic pulse conditions. Here, the global back gate bias (V_GS(B) = −10 V) induces a high hole carrier density in the channel, reducing the mean free path and thus preventing carriers from gaining sufficient energy for impact ionization. Consequently, impact ionization is suppressed, significantly lowering the current level (≈2 nA) compared to the neuron‐mode STM current (≈80 µA). Instead, the polarization switching of the ferroelectric layer dominates, maintaining a stable nonzero current without being reset to 0 nA, thus clearly demonstrating robust LTM characteristics. These reconfigurable STM and LTM behaviors further demonstrate the reconfigurable functionality of the SS‐NV FET by simply tuning the channel carrier density while maintaining identical presynaptic pulse conditions.

Furthermore, our device can dynamically control the excitatory and inhibitory functions of neurons by leveraging the carrier density modulation capability provided by the ferroelectric property under the top gated region. The excitatory neuron function is activated when the channel carrier density is tuned to the p‐type region by applying −2 V to V_GS(T). Figure 3c shows the reproducibility of excitatory function of LiF neuron under the neuron‐mode (V_GS(B) = −3 V and V_DS = 0.8 V). The postsynaptic current of I_DS consistently reaches the firing threshold current (I_TH) of ≈80 µA across multiple pulses, demonstrating stable avalanche‐induced carrier multiplication and robust firing reproducibility. This consistent current level confirms that LiF behavior is driven by avalanche‐induced carrier multiplication, which reproducibly amplifies the carrier population under identical input stimuli. For the inhibitory function, the device is reconfigured by applying 2 V to V_GS(T), which shifts the channel carrier density toward the n‐type region. This suppresses the LiF operation and prevents spike generation (Figure S12, Supporting Information). The inhibitory function, analogous to biological lateral inhibition, enhances energy efficiency by activating only specific neurons and facilitates key learning mechanisms such as winner‐takes‐all,^{[ 8} , ²⁸ , ^{29 ]} which will be discussed in more detail later. Figure 3d, by contrast, presents the ferroelectric‐driven conductance accumulation characteristic in synapse‐mode (V_GS(B) = −10 V and V_DS = 0.8 V) under repeated identical presynaptic pulse conditions (V_P = −2 V, and t_P = 10 µs). Here, the impact ionization was suppressed owing to the reduced mean free path, allowing ferroelectric polarization switching to dominate, thus clearly exhibiting nonvolatile memory accumulation without returning to 0 nA. This ferroelectric‐based weight modulation behavior was also observed under positive pulse conditions (V_P = 2 V), indicating that the synaptic functionality can be reconfigured solely by adjusting V_GS(B). As shown in Figure 3e, the repeatable synaptic LTP and LTD characteristics are achieved under repeated input conditions (V_P = −2 V, and t_P = 10 µs pulses applied 25 times consecutively for LTP) and (V_P = 2 V, and t_P = 10 µs pulses applied 25 times consecutively for LTD), with fixed V_GS(B) at −10 V. The resulting synaptic weight change exhibited a high dynamic range, with a G_max/G_min ratio of ≈30, and reproducibility over 50 consecutive cycles. These results confirm the capability of the device as an analog‐symmetric synapse. Unlike previous studies that relied on varying V_P or t_P to transition from STM to LTM, the proposed device enables this transition under identical pulse conditions by modulating the channel charge density via back‐gate biasing. This approach offers a more biologically plausible neuromorphic system by emulating biological memory processes based on the frequency of stimulation rather than varying the input strength.

2.4. Facial Recognition Using SNN Based on Reconfigurable SS‐NV FET

To validate the system‐level functionality of the SNN based on our reconfigurable neuron and synapse devices, a device‐to‐system‐level simulation was conducted using the experimentally extracted electrical characteristics. As shown in Figure  4a, the SNN comprises two fully connected layers comprising 32×32 input neurons, 20 middle‐layer neurons, and three output neurons. The electrical characteristics of both the neuron and synapse operations extracted from the reconfigurable SS‐NV FET were incorporated into the simulation framework. The circuit schematic comprises SS‐NV FETs, where each device can be dynamically configured as either a neuron or a synapse by tuning the back‐gate voltage. Synaptic devices exhibit linearly tunable conductance states, which are used to analyze the impact of lateral inhibition on neuronal behavior at the system level (Figure S17, Supporting Information). A training dataset comprising facial images from three individuals, each with a resolution of 32 × 32 pixels, was employed. Each pixel was mapped to one of 1024 input neurons, and three output neurons were designated to represent the identities of the corresponding individuals (Figure S18, Supporting Information).

Figure 4.

a) Schematic of the SNN architecture based on reconfigurable SS‐NV FET comprising 1024 input neurons, 20 hidden‐layer neurons, and three output neurons, each representing a distinct individual. b) Visualization of synaptic weight distributions before and after training under conditions with and without lateral inhibition, demonstrating the modulatory effect of inhibition on synaptic plasticity. c) Recognition accuracy as a function of the number of training epochs, highlighting the performance improvement enabled by lateral inhibition.

In this SNN, unsupervised learning based on spike‐timing‐dependent plasticity (STDP) was implemented, in which synaptic weight updates occur as a function of the temporal correlation between pre‐ and post‐synaptic spikes. Pulse voltages corresponding to the intensity values of the input image were generated with specific timing and applied to reconfigurable synaptic devices (Figure S19, Supporting Information). These synaptic devices adjust their conductance (synaptic weight) according to the applied voltage and transmit weighted signals to post‐synaptic neurons. The neuron receiving the highest accumulated current generated a post‐synaptic spike, subsequently triggering additional synaptic weight updates in the connected synapses. Figure 4b presents the visualized synaptic array before and after training with and without lateral inhibition, showing the pattern‐recognition behavior of the output neurons. When lateral inhibition was enabled, the system achieved a high classification accuracy of 95.83% after 20 training epochs. By contrast, when the inhibition function was deactivated, the accuracy dropped below 55% (Figure 4c). This performance degradation is attributed to the simultaneous firing of multiple neurons in the absence of inhibition, leading to widespread, nonselective weight updates that obscure the output neuron's selectivity. These results demonstrate that an efficient SNN can be realized using our reconfigurable SS‐NV FETs, where selective reconfiguration into neuron and synapse roles enables stable and accurate learning performance.

3. Conclusion

In this study, we demonstrated the potential of a reconfigurable SS‐NV FET based on a CuInP₂S₆/h‐BN/WSe₂ heterostructure as a unified neuromorphic device capable of performing both neuronal and synaptic functions. The operational mechanism of the SS‐NV FET leverages the interplay between impact‐ionization‐driven steep switching and ferroelectric polarization gating. This dual‐mode reconfigurability occurs via electrostatic modulation of the channel carrier density via a back‐gate bias, enabling LiF neuron behavior or analog long‐term synaptic plasticity under identical input pulse conditions. The SS‐NV FET exhibited an ultrasteep subthreshold swing (SS = 6.53 and 7.34 mV dec⁻¹ forward and reverse sweeps, respectively) and a wide memory window of 2.48 V, demonstrating both low‐power spike generation and robust non‐volatile conductance modulation. The transition between the STM and LTM was controlled by tuning the Fermi level without altering the input stimulus, thereby providing a more biologically plausible memory operation model. Furthermore, we constructed an SNN comprising reconfigurable SS‐NV FETs. In this SNN, each device selectively modulates neuronal or synaptic features via back‐gate biasing. The SNN, trained using STDP, achieved a face classification accuracy of 95.83% after 20 training epochs via lateral inhibition, whereas disabling inhibition degraded accuracy to below 55%, confirming the importance of lateral inhibition neuron function in neuromorphic learning. These results demonstrate that the reconfigurable SS‐NV FET is a promising candidate for fully cointegrated scalable neuromorphic systems, offering energy‐efficient operation and biologically inspired functionality within a single hardware platform.

4. Experimental Section

Device Fabrication

SS‐NV FET/Baseline I²FET Fabrication: Both the SS‐NV and baseline I²FET were fabricated using a dry transfer method. WSe₂ and h‐BN flakes were mechanically exfoliated onto polydimethylsiloxane films and sequentially transferred onto a pre‐cleaned SiO₂/Si substrate. For the SS‐NV FET, an additional CuInP₂S₆ flake was exfoliated and transferred on top of the h‐BN/WSe₂ stack. Electron beam lithography and deposition were repeatedly employed to define the source/drain electrodes (Au), dielectric layer, and top‐gate electrode (Au). The ungated region where the impact ionization occurred was precisely defined by aligning the top‐gate electrode to leave an ungated length of 300 nm. The detailed fabrication process is shown in Figure S1 (Supporting Information).

Characterization

Optical microscopy (OM, Olympus BX51M) and field‐emission scanning electron microscopy (SEM, JEOL JSM‐7500F) were used to examine the shape and dimensions of the exfoliated flakes and fabricated devices. Raman spectroscopy with a 532‐nm excitation laser was used to characterize the heterostructure for material characterization. All the electrical measurements were conducted at room temperature on a probe station using a Keithley 4200 parameter analyzer.

Device‐to‐System Level Simulation

Facial recognition software simulations were conducted using MATLAB at the device‐to‐system level, incorporating the experimentally obtained electrical characteristics of the reconfigurable SS‐NV FET‐based neuron and synapse features. Key dynamic functionalities such as LiF, modulation of firing thresholds, and synaptic conductance adaptation were captured in behavioral models and implemented within our device‐system‐level simulation framework. Further details regarding the simulation structure are provided in Figures S17–S19 and Note S2 (Supporting Information). The source code supporting the SNN simulations presented in this work is publicly available at: https://github.com/IMCD‐Lab/Neuormoprhic‐simulation.

Test Images from the Yale Face Database

The facial images shown in Figure 4 were sourced from the Yale Face Database with full permission and in compliance with Yale's usage policy. The images were used to evaluate the classification performance of the neural networks.

Conflict of Interest

The authors declare no conflict of interest.

Supporting information

Supporting Information

Noh J., Kim Y. K., Kang S., Lee S.‐M., Jang B. C., and Lee S., “Reconfigurable Neuron and Synapse Operations in a Steep‐Switching Nonvolatile Transistor.” Small 21, no. 44 (2025): e05649. 10.1002/smll.202505649

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.