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. 2025 Dec 9;15:43453. doi: 10.1038/s41598-025-27283-4

High Performance Multiple Inversion Layer Selective Buried Triple Gate Vertical Trench Power MOSFET

M Ejaz Aslam Lodhi 1, Sajad A Loan 2,✉, Abdul Quaiyum Ansari 3, Shabana Urooj 4, Kiran Napte 5,✉
PMCID: PMC12690141  PMID: 41366263

Abstract

This paper analyses the various properties that governs a power MOSFET for a novel and unique vertical triple gate selective buried trench power MOSFET. Our recent work consists of a MOSFET having two lateral selective buried gates and a single vertical trench gate facing the drift region, resulting in a Triple gate power MOSFET (TGSBTPMOS). This unique combination of three gates results in significantly high device ON-state current and ultra-low ON resistance of about 0.38 mΩ.cm² in the voltage class of 78.8 V. Our proposed device has multiple inversion layers, which helps in enlarging the channel width and on-current of the device, resulting in better static state and switching performance compared to the conventional power MOSFET. 2-D Silvaco ATLAS simulation output has revealed the outperformance of the proposed device in all the areas governing power MOSFET, i.e., gate-to-drain charge (Qgd), device transfer and output (I-V) characteristic, Balliga’s Figure of Merits (FOM1 and FOM2). Furthermore, the proposed device achieves 4.86 orders of magnitude improvement in FOM1, 68.85% in Ron.sp, 94.54% in Qgd, and 98.34% in FOM2. Our proposed device is an enhancement in the existing state of the art and competes with the reported power MOSFET structure in terms of performance.

Subject terms: Engineering, Nanoscience and technology

Introduction

Power semiconductor devices are essential for determining power and energy efficiency in the medium-to-low voltage1. Due to their low conduction power loss, it is useful for high-switching speed devices. Potential parameters that measure power MOSFETs are high ON-current, low specific ON-resistance, high breakdown voltage, low gate charge, low switching, and conduction loss. Consequently, their tradeoff is essential in achieving the desired result. In earlier power devices that utilized lateral orientation, research concentrated on aligning the source and drain terminals horizontally, however, this suffered from very high specific on-resistance, mainly due to the large active area of the device.

The aforementioned issue was reduced through research into the newly existing state-of-the-art vertical power MOSFET. Vertical power MOSFET, consisting of a Trench gate structure, showed a remarkable decrease in device-specific on-resistance, since, a device with a Trench gate structure has many advantages, like no parasitic JFET, a shallow drift region, and an easy fabrication process. Previous research on semiconductor power devices has successfully demonstrated the advantages of using a double gate over a solo gate in overpowering the volatility of Vth caused by channel length fluctuations2. A very effective, zero-power-consumption evaporative cooling device for controlling heat produced by SiC MOSFETs running close to their current capacity was also demonstrated3. Recently, Unigate MOSFET32 was proposed demonstrating the scaling of the device at the cost of ON-resistance, however, the device performance degraded at higher cell pitch and high drift doping concentration. This was further continued in double gate power MOSFET. The local elevated impact ionization at the double gate corners4 influenced the device’s performance adversely, thereby affecting the BV-Ron and Qgd-Ron tradeoffs of the device. Hafsa et al.33 introduced the new selective buried power MOSFET with two gate, analyzing the power tradeoffs, but the device grieved from abrupt fluctuations in the electric field when moving in the gaps of the two lateral gates.

This led to research on multi-gate power 34‚35 MOSFETs to improve the tradeoffs and channel control for preeminent device performance. Recently, planar devices with triple gate have revealed a different dimension in the ongoing research due to their outstanding control over the gate with high on-current5. Triple gate nanowire transistors using 4 H-SiC (0001) MOSFETs and.

3D gate structures were reported in recent times in6, with good Ion/Ioff and Vth. However, this device suffered from the rise in input capacitance and high gate leakage. Devices using double-diffused MOS (TED MOS) trench-etched technology.

7 showed improvement in parameters like channel mobility and figure of merit. Ramamurthy et al.8 studied triple gate MOSFET using FinFET structure with sub-micron multiple channels for high device current. Still, parameters like better gate-to-channel coupling, tradeoff, and device ON-current are the top priority and a matter of concern.

This paper studies deeper inside the performance of our recent published work on a new selective buried vertical triple gate trench power device9. The current work targets on the enhancement of the gate control over the channel, being the fundamental property of any MOSFETs. Our present device consists of a three trench gates, incorporating a single and two lateral edge, facing each other, selective buried gates fronting toward the drift region, referred to as Selective Buried Triple Gate Vertical Trench Power MOSFET (TGSBTPMOS), with excellent gate engineering and gate control, with multiple inversion layers, resulting in high device on-current and a noteworthy reduction in device specific ON-resistance (Ron.sp). As a result, it creates a possible way to discard any further improvements in the inversion layer channel’s mobility.

The novelties of the proposed device9 are outlined in a pointwise format. The anticipated device is comprised of compound inversion layers that are established in the dual channel regions located overheads the two laterally oriented gates, as well as along the both side of the sidewalls adapted to vertically on the trench gate, concurrently. Secondly, every channels back uniformly to the electrical current spreading from the device’s surface to the bottom- mounted drain terminal in the drift region, at the drain-side. This results in an elevated proposed power device current density, which subsequently reduces the Ron.sp, as illustrated below. Thirdly, the two selective buried gates are exclusively designed in the channel (p-body). This configuration effectively reduces the cell pitch requirement of gate-to-drain9 capacitance (Cgd), as the gate is positioned at a greater distance from the bottom drain. The increased p-base length enhances device performance by mitigating the base-effect associated with the parasitic BJT. Additionally, the channels created are absolutely secluded from the drift region, as they are positioned at a distance except at the lateral ends of the two gates. This configuration mitigates the risk of unintended activation of the device at lower drain voltages, given that the buried gates are not deeply embedded within the n-drift region. The purpose is solely to activate the device, rather than to decrease the drift region resistance and substantially minimize switching losses.

This paper appears in various sections. First section illustrates the device configuration and mechanism, with on-off operation, highlighting the unique property of the proposed device. Next section shows the simulation result with discussion, using 2-D ATLAS11 simulation software, of the proposed and conventional structure supported by various discussion and analysis. Comparison of TGSBTPMOS with other various commercial Si Power MOSFET, is discussed in the further Section. The next section discusses the proposed fabrication process flow of the proposed device (TGSBTPMOS). This paper concludes in the last section.

Device configuration and mechanism

Figure 1 illustrates the two-dimensional schematics of our proposed device, TGSBTPMOS. The proposed device consists of a upright trench polysilicon gate and two buried polysilicon gates laterally aligned, constituting the triple gate power MOSFET. Figure 2 illustrates the fundamental conventional trench MOSFET (CTPMOS) sourced from10. The electrical physiognomies of the two aforementioned devices are analyzed using Silvaco ATLAS 2D11, incorporating numerous structural dimension factors listed in Table 19.

Fig. 1.

Fig. 1

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Cross-sectional depiction of triple gate selective buried vertical trench power MOSFET (TGSBTPMOS)9.

Fig. 2.

Fig. 2

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Conventional trench power MOSFET (CTPMOS)10.

Table 1.

Various parameters9 taken for both conventional trench power MOSFET (CTPMOS) and triple gate selective buried trench power MOSFET (TGSBTPMOS).

Parameters Conventional (CTPMOS) Proposed (TGSBTPMOS)
Cell pitch 3 μm 3 μm
Trench width 1 μm Lateral gate = 0.65 μm (each), Vertical gate = 1 μm
Trench depth 1.3 μm Lateral gate = 0.1 μm (each), Vertical gate = 0.45 μm
Gate oxide thickness 50 nm 50 nm
N + source width along vertical trench —- 0.334 μm
Source Doping 1e19/cm³ 1e19/cm³
Source depth 0.2 μm 0.5 μm
N-drift region doping 5.6e14/cm³ 5e15/cm³
p-body doping 1.7e17/cm³ 1.2e17/cm³
P + doping 2e19/cm³ 2e19/cm³
N + Drain doping 1e19/cm³ 1e19/cm³
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Figure 3 below demonstrates the device with the direction of the current flow (multiple inversion layer formation) with transfer and output characteristic representing electrical current output.The suggested innovative device features an extraordinary combination of vertically and laterally aligned buried polysilicon gates, introduced here for the first time. The detrimental impact of the parasitic n-p-n BJT transistor present in the traditional trench MOSFET is markedly mitigated in the suggested device, as demonstrated in our simulation results below. Consequently, the proposed device demonstrates a significant enhancement in the Ron.sp vs. Qgd20 and BV vs. Ron.sp trade-off20, eliminating the necessity to enlarge the device unit cell size and allowing for its miniaturization with minimum compromising on performance, a limitation observed in previous power devices.

Fig. 3.

Fig. 3

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Device electrical operation and inversion layer formation in the conducting phase.

Moreover, Figure 3 demonstrates the operational mechanism of the proposed device (TGSBTPMOS). During the on-state, several inversion layers are concurrently established with current flowing along the vertical trench sidewalls and laterally in the buried gate channel. This phenomenon produces a strong and even spreading of electrical current from the surface to the bottom drain terminal, leading to a significantly elevated on-current and a markedly low Ron.sp, as explained figure-wise below. Figure 4 (a) and (b) depict the distribution of electron carrier concentration in both devices. The electron carrier distribution in the suggested device encompasses a significantly greater area towards the drain compared to the CTPMOS, attributable to the presence of numerous conduction channels in the proposed device.

Fig. 4.

Fig. 4

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ON-state device operation mechanism analysis in the Proposed9 and Conventional device10 at Vds = 10 V, Vgs = 12 V: (a) and (b) Electron concentration distribution in the proposed device and Conv. MOSFET.

Simulation results with discussion

This study highlights the high performance of the Silicon based Triple Gate Power MOSFET architecture utilizing selective buried gate and trench gate technologies. The outcomes are juxtaposed with the Conventional structure (CTPMOS)10, utilizing 2D Silvaco (version V5.19.20. R) Atlas11 software, and various existing models, which include the impact ionization model (IMPACT SELB)11, concentration-dependent lifetime model (CONSRH), field-dependent mobility (FLDMOB)11, Auger recombination (AUGER), bandgap narrowing (BGN) and concentration-dependent mobility (CONMOB)11.

ON state characteristics of the proposed device

Figure 5 (a), (b), and (c) illustrates the breakdown voltage, transfer, and proposed device output characteristics compared with CTPMOS device. The characteristic indicates that the on-current of the suggested device is elevated by 26.3% relative to the CTPMOS device, attributable to the supplementary inversion channel in the proposed device, which therefore diminishes on-resistance. This is further analyzed by measuring the off current in the two devices, using the logarithmic scale (form) of the Ids-Vgs curve, in Figure 6. Our proposed device is formed with source formed at both the N + region and P region (upper portion of the proposed device) by placing the source terminal on both said regions. By this, a significant risk of parasitic npn transistor is suppressed, thereby getting a reduced risk of parasitic npn activation in our proposed device, hence, very low leakage current. The proposed device has very low off current compared to the conventional device. Furthermore, the breakdown characteristics indicate a 23.13% increase in the magnitude of handling the voltage of the proposed TGSBTPMOS, signifying a notable enhancement in the Ron.sp-BV tradeoff. To measure the breakdown voltage (BV) which occurs for Vgs = 0 V, the junction that is formed inside the power device plays a very important role, from the device physics point of view. This junction (depletion region) which is formed at the p-body/n-drift region interface and its extension, decides the significance of the breakdown voltage. We note that in the conventional (CTPMOS) device, this depletion region extends at a very large value, eventually merging with the source region, unlike the proposed (TGSBTPMOS) device. This causes the CTPMOS device to experience a premature breakdown at reduced reverse voltages, hence, a lower value of BV compared to the proposed (TGSBTPMOS) device. Moreover, this deeper extension of depletion region up to the source region is lacking in our proposed device, since, due to two lateral gates facing each other, the junctions formed at the source-body and drift-body interfaces in the proposed device are orientated in different directions. This configuration prevents the junction from extending and merging deeper, resulting in improved breakdown performance in the proposed device. Figure 5 (d) illustrates the correlation between device on-resistance and applied gate voltage, revealing a markedly low resistance across all gate to source voltage (Vgs) values. Figure 7 and Figure 8 predicts the electric field and the impact ionization generated in the two discussed devices, before the breakdown of the two devices.

Fig. 5.

Fig. 5

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(a) Breakdown (off state) voltage characteristic (b) Input Characteristics (c) Output Characteristics (d) variation of device ON resistance with applied gate voltage, for proposed and conventional device.

Fig. 6.

Fig. 6

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Drain current (vs. Vgs) in the logarithm scale (form) for proposed and conventional device.

Fig. 7.

Fig. 7

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Electric field of the two devices before breakdown.

Fig. 8.

Fig. 8

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Impact ionization of the two devices before breakdown.

Additionally, the projected device has been optimized through modifications to the lateral and vertical gate dimensions, with corresponding observations of the Baliga figure of merit (FOM)9. Optimization is necessary because it plays a dynamic role in device electrical performance, and it is a preeminent condition for analyzing the design of a device by using a set of selected criteria. These may comprise making the most of factors, which include changes in device dimensions, doping, and different metalwork functions. We changed the length and depth of the lateral and vertical trench gate since its value directly influences the channel characteristics and the FOMs. The lateral gate length (Lg) was varied from 0.45 to 0.75µm while keeping the trench gate depth (Tg) constant. Similarly, Tg was varied from 0.45 to 1.2µm (three equal steps) while keeping Lg constant. The most optimized device FOMs were at Lg = 0.65µm and Tg = 0.45µm while keeping the cell pitch at 3.0µm for both devices, respectively, avoiding keeping the two lateral gates facing each other too close, as it alters the electric field  

32 and disturbs the Ron-BV tradeoff. Furthermore, when the gate length is reduced while reducing the cell pitch, the close interaction of source and gate corners increases the corner effect, resulting in an increased electric field at the gate corners. A high impact ionization at the corners of the two gates thus reduces the breakdown strength of the device. Hence, degrades the performance of the proposed device. Additionally, reducing cell pitch of the device reduces its ON current. As a result, the specific ON resistance increases, which disturbs the tradeoff BV-Ron and Qgd-Ron. This paper extracts all the simulations at the optimized device values. Moreover, we simulated the proposed device to analyze the electrical characteristics with same threshold values and doping with CTPMOS device. The on-current for the proposed device decreased, but it was still higher than the conventional MOSFET.

Gate charge and capacitance analysis

The extracted gate voltage-transient time characteristic for the TGSBTPMOS and CTPMOS device using the circuit12, is illustrated in Figure 9. Figure 10 presents a detailed view of the gate charge (Qgd) simulation curve. The switching speed and loss of power MOSFETs are directly related to the gate-to-drain charge (Qgd)9. The proposed device exhibits a lower Qgd and demonstrates comparability with other documented literature. Figure 10 illustrates that the low values of Qgd, whereas Figure 11 and Figure 12 explains the abridged gate-drain overlap and an effective protecting effect in the proposed device. A total of 104 cells have been utilized in parallel9, with a constant current9 of 10µA applied as input to charge the gate to.

Fig. 9.

Fig. 9

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Gate charge simulation output with circuit12.

Fig. 10.

Fig. 10

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Mixed mode circuit simulation result for proposed and conventional device, with detailed view.

Fig. 11.

Fig. 11

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Depletion region depth representation w.r.t buried gate and its value at Vds = 2 V, 15 V and 30 V for Cgd measurements.

Fig. 12.

Fig. 12

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Dependence of depletion region depth (d) formation at drain voltage vs. gate-drain Capacitance (Cgd) for the proposed and conventional MOSFET.

extract Qgd during the simulation process. The gate charge for the proposed device measures 3.63 pC, in contrast to 66.6 pC for the CTPMOS structure. This represents a reduction of 94.54% in gate charge and parasitic effects when compared to the CTPMOS device. Thus, removing unwanted parasitic capacitance in our proposed device is significant. Also, the simulated outcome of Cgd-Vds of the proposed (TGSBTPMOS), as seen in Figure 12, outperforms the conventional device, showing significantly low Cgd values for all the values of Vds.

To understand the physics and physical mechanism behind the decrease in Cgd and Qgd, we first understand the role of the depletion region behind the realization of capacitance. We present the more informative diagram (below) to understand the impact of depletion region depth on Cgd (and Qgd). In the Figure 11, we show how the depletion region depth is formed below the buried gate in our proposed device (TGSBTPMOS). We present the one-sided (lateral gate_1) phenomenon since the device is symmetrical. In this fig, depletion region depth is represented w.r.t buried gate and its value at Vds = 2 V, 15 V and 30 V. The depletion region depth is termed d2, d15, and d30 at Vds = 2 V, 15 V, and 30 V and tTG and tCONV for the proposed (TGSBTPMOS) and conventional trench depth, respectively. Also, shown is the simulated value in terms of its thickness (falling from the buried gate), since the capacitance value depends on the d’s value (depletion region depth in µm). Next, we show the simulated depletion region depth “d” and its corresponding value of Cgd, in Figure 12 below. We extracted the depletion region depth with the corresponding value of gate-drain Capacitance (Cgd) for the proposed and conventional MOSFET, at a drain voltage of 2 V, 15 V, and 30 V. This is carried out for all the vertical and lateral gates of the proposed (TGSBTPMOS) and the conventional MOSFET. Inside the Figure 12, the inset Fig. a, Fig. b, Fig. c, Fig. d, gives the corresponding values of the depletion region depth, for the lateral and vertical gates for the proposed device and Fig. e represents the same for the conventional trench device depleton depth. A continuous decrease in gate-drain Capacitance (Cgd) with an increase in depletion region depth (d), at Vgs = 0 V and Vds = 0 V to 30 V, is observed here. The Cgd values for all three gates of the proposed device are considerably lower than those of the conventional device.

Additionally, to investigate the risk of activation of parasitic n-p-n transistor, we simulated our projected device alongside the traditional CTPMOS by extracting the breakdown voltage (BV) in relation to the variation in the concentration of the p-body region doping, as illustrated in Figure 13. Due to the deeper extension of the formed junction and the negative effects of parasitic BJT activation, the breakdown voltage of the conventional (CTPMOS) device significantly decreases when the p-body doping concentration drops below 4e16/cm³. These devices, both old and new, show how the breakdown voltage varies with the concentration of doping in the channel (p-body). The graph illustrating the extracted values of breakdown voltages indicates that the breakdown show of the proposed device remains unaffected by variations in p-body doping, due to the differing orientations of the source and drift body junctions, which results in a reduced parasitic n-p-n effect. A significant decline in performance is observed in the conventional device.

Fig. 13.

Fig. 13

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Change in breakdown voltage along with p-body doping in the proposed and the conventional (CTPMOS) structures.

Furthermore, to conduct a more in-depth analysis of the parasitic BJT effects on device performance, we extracted the hole concentration produced by impact ionization beneath the gate oxide. The parasitic BJT enhances hole current due to impact ionization, thereby degrading device performance13. The hole concentration measured at the trench gate oxide interface of the proposed structure is compared with that of the CTPMOS, as illustrated in Figure 14. Figure 14 illustrates a reduced hole concentration in the channel region of the proposed device, attributed to the distinctive lateral and vertical gate configuration. The suppression of the BJT parasitic effect leads to a notable reduction in hole concentration within the channel region. Therefore, the proposed device demonstrates superior control of parasitic BJTs compared to the conventional counterpart.

Fig. 14.

Fig. 14

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Various device regions’ hole concentration distribution for the TGSBTPMOS and CTPMOS structures, in the vertical position.

Moreover, it is not worth individually analyzing the three crucial performance factors (i.e., BV, Qgd, and Ron.sp). Consequently, Baliga’s20 FOM1 and FOM2, precisely characterize the device’s performance and the trade-offs among the three parameters. Comparison in terms of tradeoffs20 is the best technique to analyze the different types of devices to check their performances. As observed from Table 2, our proposed device significantly enhances the extracted Baliga’s21 FOM1 and FOM2, when compared with the CTPMOS device.

Table 2.

Performance comparison of baliga’s FOMs for proposed (TGSBTPMOS) and conventional (CTPMOS).

Figue of merits (FOM) Conventional (CTPMOS) Proposed (TGSBTPMOS)
FOM1 (BV 2/Ron) 3.36 (MW/cm²) 16.34 (MW/cm²)
FOM2 (Ron. Qgd) 270.84 (mΩ.nC) 4.5 (mΩ.nC)
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Comparison of TGSBTPMOS with other various commercial Si power MOSFET

The benchmarking of Balliga’s20 FOM1, for the proposed device (TGSBTPMOS) against the ideal silicon limit and other documented devices as per the literature, within the 0–110 V power MOSFET range, as seen in Figure 15, includes the specific device on-resistance (Ron.sp) and breakdown voltage (BV) values of the proposed device. The graph clearly demonstrates that the proposed TGSBTPMOS device has superior performance relative to other devices accepted in the writings. The display presents various technical literatures for the specified structure along with their corresponding BFOM21 values.

Fig. 15.

Fig. 15

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Specific ON-resistance (Ron.sp) in relation to breakdown voltage (BV), juxtaposed with the ideal silicon limit line of the projected (TGSBTPMOS) device, associated to other all types power transistors, alongside the equivalent Baliga’s FOM1.

Figure 16 show the benchmark amongst the Vth-Ron.sp- IONmax of the proposed structure against various transistors as per the reported literature. With the best of our knowledge, our work presents a combination of lateral buried and vertical trench gates using Si, for the first time, forming the triple gate power MOSFET. Hence, we have been motivated to associate our device9 with various type of power transistors for wider and above better understanding. Our proposed device demonstrates significantly low Ron.sp and high IONmax (among Si) on the Vth scale compared to many devices, except few reported.

Fig. 16.

Fig. 16

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Benchmarking of Vth with IONmax and RON.SP of the TGSBTPMOS against various power transistors.

literatures (based on GaN and SiC). Moreover, to facilitate a comprehensive understanding, the percent enhancement of several parameters of the proposed device relative to the CTPMOS device, is illustrated in Figure 17. The 2D ATLAS simulated results demonstrate that the suggested device excels in all critical parameters of a trench-gate power MOSFET, with only a few additional, non-complex production steps required.

Fig. 17.

Fig. 17

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Improvement in the performance of TGSBTPMOS over conventional device.

Proposed process flow with device schematics

Figure 18 illustrates a potential process flow for the proposed device, designated as “TGSBTPMOS”. The fabrication technologies, aligned with the current fabrication patterns and device dimension values, have been optimized effectively, as previously documented in the literature. The first step involves the accurate growth of a lightly doped n-region through epitaxial methods on a predominantly n-doped substrate, as illustrated in Figure 18 (A) and (B). The oxidation mechanism24 for the deposition of the SiO2 layer, as exemplified in Figure 18 (C), is preferred. This is followed by the deposition of n + Poly-Silicon25,26 gate over the oxide, which includes selective process etching steps to define the trench22,27,28, as shown in Figure 18 (D) and (E). After marking the trenches with thermal oxide, the hard mask can be selectively etched. Moreover, trench windows can then be made by selectively patterning and etching. Finally, a thorough thermal oxidation process is conducted, as shown in Figure 18 (F). Moreover, epitaxial Si is further grown using a seed window28,29 to create the proposed device’s top portion, Figure 18 (G)37. Additionally, the procedure employed to construct a vertical gate mirrors that utilized for the fabrication of the two lateral gates, as illustrated in Figure 18 (H)-(I)29. Subsequently, ion implantation is employed to establish p-body, n + and p + regions. This process is followed by metallization to form contacts for the drain, gate, and source terminals28,30,31, as illustrated in Figure 18 (J). Fabrication of our proposed device consisting of integrating multiple selective buried gates and trench gates could pose significant process integration and alignment challenges. Possible solutions include the use of sophisticated lithography techniques, such as extreme ultraviolet (EUV) lithography, which can improve alignment accuracy and perilous dimension (PD) control by enabling the production of smaller and more precise features. However, the need for exact overlay alignment may be lessened by introducing self-aligned processes, in which the alignment of one layer is decided by the one before it. We mentioned above the outlines of the potential process flow of the TGSBTPMOS, which is analogous to the conventional process.

Fig. 18.

Fig. 18

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Process flow (fabrication) for the proposed TGSBTPMOS device9.

Conclusion

A cutting-edge silicon-based triple-gate MOSFET (TGSBTPMOS) is further investigated. The proposed device features several inversion layer channels in both lateral and vertical sidewalls. We introduce, for the first time, a hybrid configuration of buried and trench gates, resulting in the triple gate power MOSFET. The proposed device exhibits superior performance regarding ON-current and reduced particular ON-resistance. The 2D simulation outcomes indicate that the proposed device overtakes the traditional (CTPMOS) MOSFET across all parameters governing power semiconductor devices. The elevated ON- device proposed current and markedly small specific ON-resistance of the proposed device eliminate the need for enhancements in inversion layer channel mobility. The optimal dimensional parameters for the device’s lateral and vertical trench gates are 0.65 μm and 0.45 μm, respectively, with a cell pitch of 3.0 μm. The innovation of our proposed device arises from the conducting channels established not only in the laterally orientated p-body region but also along the vertical sidewalls adjacent to the vertical trench gate, completely isolated from the drift region, resulting in a minimal gate-to-drain charge value through characterization circuit implementation. The suggested triple-gate MOSFET introduces additional dimensions to contemporary multi-gate methodologies aimed at minimizing switching and conduction losses in semiconductor power devices.

Acknowledgements

Princess Nourah bint Abdulrahman University Researchers Supporting Project number (PNURSP2025R79), Princess Nourah bint Abdulrahman University, Riyadh, Saudi Arabia.

Author contributions

Conceptualization, M.E.A.L. and S.A.L.; methodology, M.E.A.L. and S.A.L.; software, M.E.A.L.; formal analysis, A.Q.A. and S.U.; investigation, A.Q.A., S.U. and K.N.; resources, S.A.L. and S.U.; data curation, M.E.A.L.; writing-original draft, M.E.A.L.; writing-review and editing, S.U., S.A.L. and K.N.; visualization, A.Q.A. and K.N.; supervision, A.Q.A. and S.A.L.; project administration, A.Q.A.; funding acquisition, S.U. and K.N. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Princess Nourah bint Abdulrahman University Researchers Supporting Project number (PNURSP2025R79), Princess Nourah bint Abdulrahman University, Riyadh, Saudi Arabia.

Data availability

The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding author.

Declarations

Competing interests

The authors declare no competing interests.

Footnotes

Publisher’s note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Contributor Information

Sajad A. Loan, Email: sajad@iu.edu.sa

Kiran Napte, Email: kiran.napte@pccoer.in.

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Data Availability Statement

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