A two-stage dc–dc converter with high voltage gain and reduced current ripple for efficient PV energy harvesting

Abstract

PV systems require a dc–dc converter to operate at the maximum power point (MPP). However, switching based operation of these converters causes ripple current. This ripple current causes a voltage ripple due to the I-V characteristics of the PV panel. Both current and voltage ripple lead to power ripple and reduce the average energy extracted from the PV system. In this study, a two-stage boost converter (PTS-BC) topology is designed. The first stage, configured as an interleaved TP-BC fixed at , drastically suppresses the input current ripple, while the second stage, operating as a conventional SP-BC, regulates the output voltage. The key novelty of this architecture stems from the use of dedicated stages for ripple cancellation and voltage regulation, thereby ensuring ripple-free PV input current across the entire duty range without requiring bulky input capacitors. The design has been validated through simulations and experimental studies performed on a 450 W PV prototype system. Within the examined operating range, duty cycle (D) changes from 10% to 80%, the PTS-BC provides a 12% and a 17% ripple reduction in input current ripple and power ripple, respectively, compared to conventional converters such as single phase boost converter (SP-BC), two phase boost converter (TP-BC), etc. In addition, PTS-BC requires significantly lower D than SP-BC and TP-BC for the same output voltage, thereby reducing conduction losses and voltage stress on switching devices in a two-stage configuration. The PTS-BC reaches a peak efficiency of approximately 98%, representing improvements of about 0.7% and 1.6% over the TP-BC and SP-BC, respectively. These results confirm that the proposed topology offers superior energy conversion performance and makes it a strong candidate for high-performance PV systems that require low input ripple and high efficiency.

Introduction

In recent years, renewable energy sources have played a crucial role in meeting the growing energy demand. Among these sources, PV systems^1,2 have become one of the most widely used sources. The performance of PV systems is related not only to environmental conditions such as irradiance and temperature³ but also to the efficiency of the power electronics converter topologies used and the maximum power point tracking (MPPT) algorithms^4,5. Due to their switching based operating principle, power converters draw ripple current⁶ in addition to the average dc input current. An input capacitor provides this ripple current⁷, which is typically provided and not drawn from the power source. However, over time, the capacitance of a capacitor may decrease due to factors such as aging, temperature, or overloading⁸. When the input capacitor cannot provide the necessary ripple current, the ripple is drawn directly from the source. In PV systems, the non-linear current-voltage (I-V) characteristics of the panels cause voltage ripple⁹ and, consequently, power ripple, which leads to a decrease in the total energy collected over time.

In this regard, dc–dc boost converters are considered a promising candidate because they inherently draw continuous^10,11 current from the source. The single-phase boost converter (SP-BC) is widely used due to its simple structure and low cost; however, its high input current ripple can cause significant power ripple on the PV side. Increasing the number of converter phases^12,13 is an effective method to make a lower input current ripple. The two-phase boost converter (TP-BC) can significantly reduce the ripple current at a certain duty ratio (particularly at 50%) through phase-shifting techniques. However, this advantage is only maintained within a limited duty ratio range.

In addition to ripple issues, the voltage gain of conventional boost-type topologies strongly depends on high duty cycle operation. Operating at high duty cycles increases conduction losses, thermal stress, and the risk of inductor core saturation¹¹ while complicating control dynamics. Moreover, high duty ratios raise voltage stress on switching devices, requiring components with higher voltage ratings, which can reduce system reliability. As reported in¹⁴, cascaded interleaved converter structures can alleviate such limitations by distributing the voltage gain across multiple stages, thereby reducing the stress on individual switching devices.

Recent studies in the literature have proposed various advanced boost converter topologies to address ripple, voltage gain, and efficiency challenges. Examples include the Nonisolated Ultrahigh Step-up DC–DC Converter (NUSC)¹⁵, the High-Boost Interleaved DC–DC Converter (HIC)¹⁶, the Noninverting DC–DC Converter (NC)¹⁷, the Multiphase Stacked Interleaved Converter (MSIC)¹⁸, the Two-stage Hybrid Isolated DC–DC Boost Converter (TSHIDBC)¹⁹, the Coupled-Inductor Based Buck–Boost Converter (CIBC)²⁰, the Quadratic Boost Converter (QBC)²¹, the Soft-Switched High-Gain Converter with Coupled Inductor (SSHGBC)²², the Three-Level Buck–Boost Converter (TLBBC)²³, the Interleaved Boost Converter (ICBC)²⁴, and the Enhanced Multiphase Interleaved Converter (EMIBC)²⁵. These converters have demonstrated high voltage gain, reduced current ripple, and efficiency improvements, making them suitable for PV and FC applications. However, they often require a larger number of components, complex control strategies, or bulky passive elements. In contrast, the proposed PTS-BC achieves ripple-free input current and regulated output with a simpler cascaded structure, representing a distinct alternative among the existing solutions.

Previous studies have shown that increasing the number of series-connected PV panels in a string leads to several challenges, including partial shading effects, voltage imbalances, and mismatch losses^26–29. Strings with a high number of PV panels are more sensitive to shading and can experience power losses ranging from 15% to as high as 70%^28,29. Partial shading may cause multiple peaks in the power–voltage curve, complicating MPPT operation and preventing optimal power extraction^26,29. Bypass diode activation under these conditions may also lead to voltage imbalances²⁶. Grouped string voltage balancing (GSVB) reduces these shading-related losses and voltage ripple by decreasing the number of series-connected panels while increasing the number of parallel strings, thereby improving system stability and energy harvesting efficiency^2,26.

The two-stage converter topology has provided a solution to these problems. They can operate at lower input voltage levels, reducing the required number of series-connected PV panels. This both decreases shading losses and reduces high-voltage isolation requirements on the PV side. For example, in a single-stage converter supplying a 200 V dc bus, two series-connected PV panels at approximately 100 V each may be required to operate at a 50% duty ratio. If one panel experiences shading, the power output of the second panel is also limited, reducing total energy production. In contrast, a two-stage converter could use a single 50 V panel at the input and still supply the same 200 V bus, with both stages operating at 50% duty ratio. In this case, shading affects only the shaded panel. In large PV arrays, reducing the number of series-connected panels by half not only alleviates shading-related losses but also minimizes PV-side high-voltage isolation problems. In addition, by distributing the overall voltage conversion across two cascaded stages, the PTS-BC reduces the required duty ratio of each stage. Lower duty ratios shorten the conduction interval of the switches, which theoretically mitigates conduction losses and contributes to higher overall efficiency. Table 1 summarizes the comparison between single- and two-stage configurations. Here, and denote the overall input and output voltages of the converter. and represent the voltage gains of the first and second stages, respectively, while is the total gain. and indicate the conduction intervals (duty ratios) of the first and second stages. Finally, and correspond to the switch voltage stresses.

Table 1.

Comparison of single- and two-stage boost operation for the same overall conversion

Topology	Number of stages		Voltage gain		Conduction interval	Voltage stress
SP-BC TP-BC	1	50 V		200 V		V
PTS-BC	2	50 V		200 V		V V

In this study, a novel two-stage boost converter (PTS-BC) topology is proposed. The PTS-BC offers both to reduce input current ripple and voltage/current regulation at the output. Also, improve voltage gain in PV systems. In the proposed structure, the first stage cancels the input ripple, while the second stage regulates the output voltage/current. Both simulation and experimental results show that the PTS-BC offers significant ripple reduction and efficiency improvements compared to conventional SP-BC and TP-BC topologies.

In this study, a novel two-stage boost converter (PTS-BC) topology is proposed. The PTS-BC not only reduces input current ripple but also provides voltage/current regulation at the output and improves voltage gain in PV systems. In the proposed structure, the first stage cancels the input ripple, while the second stage regulates the output voltage/current. Unlike conventional approaches, where SP-BC or TP-BC are used alone, the PTS-BC combines a TP-BC stage fixed at for ripple cancellation with a conventional SP-BC stage dedicated to output regulation. This functional separation of tasks highlights the novelty of the topology, enabling ripple-free PV input current without bulky capacitors while maintaining efficient voltage regulation. In contrast to existing cascaded or interleaved converters, the PTS-BC uniquely integrates ripple cancellation and voltage regulation into a unified two-stage architecture. Both simulation and experimental results confirm that the PTS-BC offers significant ripple reduction and efficiency improvements compared to conventional SP-BC and TP-BC topologies.

This paper is organized as follows: “Impact of ripple in PV systems” presents a comparative analysis of the ripple characteristics in different converters. “Development and analysis of the proposed two-stage boost converter” gives details about the design process of the PTS-BC. “Simulation results” compares the ripple performance of three converter types through simulations. “Experimental setup and results” provides the experimental validation of the proposed converter. Finally, the conclusions of the study are summarized in the “Conclusion”.

Impact of ripple in PV systems

The PV panel’s energy is transferred to the dc bus via a dc–dc converter, as illustrated in Fig. 1. The energy is then delivered to the grid and a battery storage system. Among the commonly used dc–dc converters, the boost type has an advantage in drawing continuous current from the input power source. Fig. 2 shows an example PV and control system. In this configuration, the PV current and voltage are continuously monitored as ADC signals by the control unit. The control unit generates suitable control signals (PWM Signals) to operate the converter and ensure that the panel operates at the MPP, thus maximizing the total harvested energy. Such closed-loop control structures play a critical role in improving system efficiency, especially under varying irradiance and temperature conditions. However, due to the switching operation of the converter, ripple current occurs at the PV panel side. The current ripple causes a voltage ripple across the panel terminals, and both effects result in a power ripple. As a result, both the average power output and overall energy yield are negatively affected. Suppose the input current ripple exceeds a certain level. In that case, the resulting voltage ripple at the PV terminals can become significant enough to impair the control performance, potentially leading to instability in regulating the operating point. This defined problem is the primary motivation of the present study.

Fig. 1.

Block diagram of grid-connected and battery-supported PV system

Fig. 2.

Block diagram of the control principle of the PV system

dc–dc converters operate based on the switching principle of semiconductor devices, which are periodically turned on and off during the switching period. The current drawn from the input terminal has an average and a ripple component. While the average component is directly supplied from the source, the ripple component is provided by a parallel input capacitor. This capacitor can fail to provide the required ripple component due to improper design, aging, or fault conditions. The ripple current is also drawn directly from the power source. In the case of an ideal voltage source, where the output voltage remains constant regardless of current variation, this ripple current does not affect the voltage. However, when the input source is a PV panel, the ripple current leads to a corresponding voltage ripple due to the nonlinear I-V characteristics of the panel. As a result, a simultaneous ripple in both current and voltage produces a more significant power ripple at the output. The ripple on PV power output depends on the terminal current and voltage, as demonstrated through the following equations. According to the classical single diode equivalent circuit model of a PV cell³⁰, the terminal current is defined as:

1

where and represent the terminal current and voltage of the PV array, respectively. is the photocurrent generated by the incident radiation, and is the diode saturation current. and denote the series and parallel resistances of the equivalent circuit. The parameter n is the diode ideality factor, and is the thermal voltage. As seen in Eq. 1, the PV current and voltage are interdependent variables. The input current and voltage of PV terminals can be expressed as follows:

2

3

where and denote the average (dc) components, while and represent the ripple components of current and voltage, respectively. Under these conditions, the power drawn from the PV panel becomes:

4

Substituting Eq. 2 and Eq. 3 into Eq. 4 yields:

5

6

The first term of Eq. 6, , represents the average power. However, the second and third terms ( and ) introduce power variations due to ripple interacting with average values. The final term (), a product of two ripple components, can significantly contribute to power ripple. If these ripple components are not suppressed, they can cause a reduction in the average power extracted from the PV array.

Table 2 shows electrical characteristics of the PV panel used in the study. The open-circuit voltage represents the terminal voltage under zero current, and the short-circuit current indicates the maximum current under zero voltage. The , corresponds to the operating condition where the PV panel delivers the highest output power, calculated as the product of and . Fig. 3 is given to explain the phenomenon of the study. This figure shows the current-voltage (I-V) characteristic curve of a PV panel. The subplots in the figure display the time-domain variations of PV current (top), voltage (bottom), and power (middle). Due to the switching nature of the dc–dc converter, current, voltage, and power have periodic ripple within each switching cycle. Although the theoretical maximum power , the average power and energy are decreased.

Table 2.

Electrical Characteristics of the PV Panel

Description	Parameter	Value
MPP power	()	449.29 W
Open circuit voltage	()	49.24 V
MPP voltage		42.97 V
Short circuit current		11.32 A
MPP current		10.47 A

Fig. 3.

Current and voltage ripple effect on power ripple of the PV panel

In the literature, there are some methods to reduce input current ripple in PV systems. One such technique involves increasing the number of DC-DC converter phases. Several studies focus on boost DC-DC converters. Fig. 4 presents a comparative analysis of the normalized input current ripple values for the SP-BC, TP-BC and PTS-BC as a function of D.

Fig. 4.

Normalized input current ripple curve of the SP-BC, TP-BC and PTS-BC

As observed in Fig. 4, the ripple current in SP-BC remains constant at its maximum value across the entire duty cycle range, since the input current is equal to the inductor current and normalizes to unity. In contrast, in the TP-BC topology, the input current is the sum of two inductor currents, which are equal in magnitude and phase-shifted, as expressed in Eq. 7. The corresponding ripple factor³² of the TP-BC is then given in Eq. 8. As a result, the ripple decreases as D approaches 50%, reaches zero exactly at , and then increases again beyond this point³¹. This behavior arises from the cancellation of ripple components between interleaved phases due to the phase shift.

7

8

In the proposed PTS-BC, the first stage, configured as a TP-BC, is fixed at , ensuring complete ripple cancellation at the PV side, while the second stage operates as a conventional SP-BC with varying duty ratios to regulate the output and perform MPP tracking. This mechanism, illustrated in Fig. 13, keeps the PV input current nearly ripple-free and enables continuous operation at the MPP, thereby explaining the drastic improvement achieved by the proposed topology.

Fig. 13.

Steady-state current and voltage waveforms of the proposed PTS-BC.

Development and analysis of the proposed two-stage boost converter (PTS-BC)

This section introduces the design of the PTS-BC structure. Since the new architecture eliminates the limitations and combines the advantages of both SP-BC and TP-BC topologies, the section first presents the SP-BC and TP-BC in detail. Then it provides a comprehensive explanation of the PTS-BC.

Single phase dc–dc boost converter (SP-BC)

SP-BC is a fundamental boost topology that is widely used in PV systems. The structure shown in Fig. 5 includes a switch (), an inductor (), a diode (), an input () and an output () capacitor. The energy from the PV panel is transferred to the output through and . The output current and voltage are regulated by PWM control of the . While the simple and low cost of the structure offer significant advantages, there is a high ripple in the input current.

Fig. 5.

Circuit topology of SP-BC

Figure 6 shows the control block diagram of SP-BC. The instantaneous and are monitored by the maximum power point tracking (MPPT) controller continuously, and D is generated to ensure operation at the MPP. This reference D= value is compared with a carrier signal with a frequency of 50 kHz and phase angle of to generate the PWM signal () driving the switch.

Fig. 6.

Control block diagram of SP-BC

Two phase dc–dc boost converter (TP-BC)

The TP-BC structure shown in Fig. 7 provides both a reduction in the input current ripple observed in the SP-BC topology and an increase in the power capacity of the converter. In this structure, there are two parallel boost phases, each consisting of switches (, ), inductors (, ), and diodes (, ). At the input and output, there are an input capacitor () and an output capacitor () shared by both phase legs. The energy is transferred from the PV panel to the output through inductors and diodes of both phase legs. The two-phase legs can be controlled by a phase-shift control technique to reduce the input current ripple. In this way, more energy can be harvested from the PV panel compared to the SP-BC topology.

Fig. 7.

Circuit topology of TP-BC

Figure 8 shows the control block diagram of the TP-BC. Similar to the SP-BC, the and are continuously monitored by the MPPT controller, which generates a D to maintain operation at the MPP. This D is compared with two carrier signals operating at 50 kHz, with a phase shift of between them. The D is equal for both and . The PWM signals ( and ) control and .

Fig. 8.

Control block diagram of TP-BC

Proposed two-stage boost converter (PTS-BC) topology

The PTS-BC structure, shown in Fig. 9, is composed of two cascaded stages: TP-BC in the first stage and SP-BC in the second stage. In the first stage, the TP-BC enables nearly ripple-free current extraction from the PV panel, while the energy is stored in the intermediate capacitor (). This stored energy is then transferred to the load through the SP-BC in the second stage, which provides current and/or voltage regulation at the output terminals. As a result, the ripple reduction at the PV side achieved by the TP-BC, combined with the output regulation capability of the SP-BC, allows for more effective energy harvesting from the PV panel.

Fig. 9.

Circuit topology of PTS-BC

The operating modes of the proposed dc–dc converter are defined by the switching states of , , and . Accordingly, eight distinct switching combinations can be formed. In the analysis presented, it is assumed that when a switch turns off, the corresponding inductor discharges and its current decreases; conversely, when the switch turns on, the inductor charges and its current increases. The corresponding operating states are illustrated in Fig. 10, the associated current ripple formulas are presented in Table 3, and detailed mode descriptions are provided below.

Fig. 10.

Equivalent circuits of operating modes of PTS-BC: (a) , and are off (b) is on, and and are off (c) is on, and and are off (d) and on, and is off (e) is on, and and are off (f) and are on, and is off (g) and are on, and is off (h) , and are on

Table 3.

Inductor current ripple equations for each operating mode

Mode
(a)	0, 0, 0
(b)	1, 0, 0
(c)	0, 1, 0
(d)	1, 1, 0
(e)	0, 0, 1
(f)	1, 0, 1
(g)	0, 1, 1
(h)	1, 1, 1

Mode (a) In this mode, all switches (, , ) are turned off. Under this condition, the PV panel transfers energy to the output via the inductors and diodes. The , , and currents decrease since they are not being charged during this interval.

Mode (b) In this mode, only is turned on. In the first stage, the current drawn from the PV panel is utilized both to charge and to transfer energy to the . is charged through the -, and its current increases during this interval. Meanwhile, is charged via the -. In the second stage, supplies energy to the output through the -. The currents in and decrease, because they are not being charged during this interval.

Mode (c) In this mode, only is turned on. The operating behavior is similar to mode (b), but with the current primarily flowing through the -, charging inductor and increasing its current. Simultaneously, the is charged via the -. In the second stage, continues to supply energy to the output through the -. The currents in and decrease, which are not being charged during this interval.

Mode (d) In this mode, both and are turned on. As a result, the PV panel supplies current to both and through the - and -, respectively. This leads to an increase in the currents of both inductors, allowing simultaneous energy storage in and . In the second stage, continues to deliver energy to the output via the -. The current in , which is not being energized during this interval, continues to decrease.

Mode (e) In this mode, only is turned on. Although and are off, the PV panel remains connected to the circuit through the paths involving - and -. Therefore, the current from the PV panel can still charge . In the second stage, is charged through the -, and its current increases during this interval. The currents in and , which are not being energized during this interval, continue to decrease.

Mode (f) In this mode, both and are turned on. In the first stage, the current drawn from the PV panel is utilized both to charge and to transfer energy to the . is charged through the -, and its current increases during this interval. Meanwhile, is charged via the -. In the second stage, is charged through the -, and its current increases similarly to mode (e). The currents in , which are not being energized during this interval, continue to decrease.

Mode (g) In this mode, and are turned on. In the first stage, the current drawn from the PV panel is utilized both to charge and to transfer energy to , similarly to mode (c). In the second stage, is charged through the -, and its current increases similarly to mode (e). The currents in , which are not being energized during this interval, continue to decrease.

Mode (h) In this mode, all switches are turned on. In the first stage, the current drawn from the PV panel is utilized both to charge and , and to transfer energy to , similarly to mode (d). In the second stage, is charged through the -, and its current increases similarly to mode (e).

Table 3 shows the inductor current formulas for whole modes. Each formula are denoted by , , and , where represents the corresponding mode (, , ). Here, and represent the D of the first stage, while corresponds to the D of the second stage. and are switching periods of the first and second stages, respectively.

Figure 11 illustrates the control algorithm of the PTS-BC, which integrates the control strategies of the TP-BC (first stage) and the SP-BC (second stage). In this study, the duty cycle () of the first stage in the TP-BC is specifically chosen as 50%. This is equal for both and . The is compared with two different phase-shifted carrier signals (50 kHz, and ) to generate interleaved PWM signals ( and ) for and , which nearly eliminates the input current ripple drawn from the PV panel. The MPPT controller continuously monitors the and and calculates a second stage reference duty cycle () to provide operation at the MPP. = is used to control . It should be noted that the converters in this study were operated in open-loop mode to allow a fair comparison of ripple characteristics under identical duty ratios across different topologies. With closed-loop MPPT control, each converter would settle at different duty ratios, making a one-to-one comparison impossible. Therefore, dynamic response analysis was not included, as the main objective is to assess ripple reduction rather than transient behavior.

Fig. 11.

Control block diagram of PTS-BC

The component values used in the design of the proposed PTS-BC topology are listed in Table 4. The input side electrical parameters, such as maximum voltage, current, and power, are compatible with the PV panel specifications previously summarized in Table 2. The proposed PTS-BC topology is fundamentally derived from the conventional SP-BC and TP-BC converters; therefore, the basic design relations of SP-BC and TP-BC can be applied in the development of the PTS-BC as well³³. The voltage gain of the boost converter is related to the duty cycle D and can be expressed by Eq. (9).

9

where is the PV input voltage and is the converter output voltage. The inductor current ripple of the boost stage is given by Eq. (10).

10

where is the switching frequency and L is the inductance. From Eq. (10), the required inductance value for a given ripple current can be calculated by Eq. (11).

11

The output voltage ripple of the boost stage is related to the output current , as expressed in Eq. (12).

12

where is the output capacitance. Finally, the required output capacitance value can be obtained from Eq. (13).

13

where is the effective output resistance. In interleaved boost converters, the current and voltage ripple expressions are modified due to phase-shifted operation. For example, the input current ripple and output voltage ripple can be obtained from Eq. (14) and Eq. (15), respectively³⁴.

14

15

where is the input current occupancy ratio, is the fluctuation period of the input current, and N is the number of interleaved phases. For the interleaved structure, and can be calculated using Eq. (16) and Eq. (17).

16

17

where is the conduction interval of the switch and is the switching period. As can be seen from the interleaved ripple expressions of Eq. (14) and Eq. (15), the required values of L and C are further reduced due to the ripple cancellation effect compared to the single-phase case.

Table 4.

Proposed PTS-BC Component Parameters

Description	Parameter	Value
Maximum input dc bus voltage		49.24 V
Maximum input dc current		11.32 A
Nominal power		449.29 W
Switching frequency		50 kHz
Inductor current ripple		20 %35
Inductance		500 35
Inductance resistance		40
Input capacitance		21.43 nF
Input capacitance resistance		75
Intermediate capacitance		11.3
Intermediate capacitance resistance		4
Output capacitance		11.3
Output capacitance resistance		4

The inductor ripple current³³ is typically selected within 20–40% of the rated current. In this work, the lower bound of 20% of the current ripple specified in Table 4 was adopted as the design criterion. With the chosen inductance of 500 H, the ripple current remains well below this limit across the whole duty range. The same inductance value is used for all inductors in the system. A Magnetics core (type 0078617A7) was selected, with a nominal value of 189 . In Eq. (18), the inductance value formula depends on the core cross-sectional area.

18

where N is the number of turns, the required number of turns was calculated as 52 to achieve 500 H. At higher currents, the effective decreases, which increases the required number of turns and the winding losses. In interleaved operation, however, the current per inductor is reduced, allowing the use of smaller inductors with lower volume and loss, thereby improving efficiency. A photograph of the fabricated inductor is shown in Fig. 12.

Fig. 12.

Photograph of the prototyped inductor.

In this study, no strict target for output voltage ripple was imposed, as the primary objective is to investigate the PV-side current ripple in the two-stage architecture rather than to minimize the output voltage ripple. Therefore, relatively small capacitor values were selected for both and , each chosen as 11.3 F (Table 4), ensuring that their impact on the PV-side input ripple remains negligible. The input capacitance was also intentionally minimized, since the objective of this work is to eliminate or significantly reduce the need for bulky input capacitors and to evaluate the PV-side current ripple directly. According to³³, the role of the input capacitor is to smooth the supply ripple voltage during operation, and its value may be increased if the input source is noisy. In this study, however, such smoothing is deliberately avoided to prevent masking the inherent PV current ripple. In addition, a small capacitor is required in the MATLAB/Simulink model for the PV source to operate correctly, as the simulation either fails to converge or produces errors without it. It should also be noted that the values of L, and C reported in Table 4 correspond to the actual component values used in the design and implementation, rather than only theoretical calculations.

Comparison of the proposed PTS-BC with existing converter topologies

Table 5 summarizes the design characteristics and performance indicators of the proposed PTS-BC relative to conventional converters (SP-BC, TP-BC) and recent state-of-the-art topologies reported in the literature. While several advanced converters (e.g., MSIC, TSHIDBC) achieve strong ripple suppression, they often require a larger number of components and more complex control. In contrast, the PTS-BC attains excellent ripple suppression and the highest reported efficiency with a comparatively moderate hardware complexity.

Table 5.

Comparison of the proposed PTS-BC with other existing converter topologies

Feature	SP-BC	TP-BC	NUSC15	HIC16	NC17	MSIC18	TSHIDBC19	PTS-BC
Number of Switches (S)	1	2	1	2	2	6	6	3
Number of Diodes (D)	1	2	5	6	5	–	4	3
Number of Inductors (L)	1	2	2	2	4	3	3	3
Input Capacitor ()	1	1	–	–	–	–	–	1
Intermediate Capacitor ()	–	–	3	5	2	1	1	1
Output Capacitor ()	1	1	1	1	1	1	1	1
Control complexity	Easy	Medium	Easy	Medium	Medium	High	High	Hard
Ripple suppression Capability	Poor	Moderate	Good	Good	Good	Excellent	Good	Excellent
Switch voltage Stress	High	High	Low	Low	Low	Low	Low	Low
Efficiency (%)	96.4	97.3	96.0	96.25	96.53	96.11	95.5	98.0
Hardware cost	Low	Medium	High	High	High	High	High	High

Simulation results

In this section, detailed simulation results are presented to characterize the voltage, current, and power behavior of the converters under different operating conditions. The dc–dc boost converter, the SP-BC, TP-BC, and the proposed PTS-BC topologies were modeled in MATLAB/Simulink for circuit-level performance evaluation.

In the first analysis, Fig. 13 presents the gate signals (, , and ) together with the corresponding steady-state current and voltage waveforms of the proposed PTS-BC. While and are operated at , is operated at . In all current and voltage figures, the waveforms are normalized and expressed in per-unit (p.u.), with the average value of each variable indicated on the plots. The purpose of this normalization is to compare the percentage ripple of currents and voltages directly. For current waveforms, the per-unit scale is set to 0.8–1.2 to represent ±20% ripple, while for voltage waveforms the scale is set to 0.99–1.01 to represent ±1% ripple. The inductor currents of the first stage, and , are equal in magnitude with an average value of 5.23 A and are phase-shifted, resulting in the complete cancellation of the PV current ripple. As a result, the PV current remains nearly ripple-free with an average value of 10.46 A. Although the current of the second-stage inductor, , contains ripple, this ripple does not propagate to the PV side. Instead, provides output regulation with an average current of 5.13 A. The PV voltage, , is maintained at 42.95 V and remains essentially ripple-free. The intermediate voltage , representing the link between the two stages, and the final output voltage are stabilized at 85.76 V and 143 V, respectively. Both exhibit only small ripples, which remain below 1% under the applied duty ratios. These results confirm that the PTS-BC effectively suppresses input current ripple while maintaining regulated output voltages, thereby validating the effectiveness of the proposed two-stage architecture.

In the second analysis, the dc–dc boost converter, the SP-BC, TP-BC, and proposed PTS-BC topologies were modeled in MATLAB/Simulink for circuit-level performance analysis, as illustrated in Fig. 14. The study focused on current, voltage, and power ripple over a wide range of D. From Fig. 14(a), it can be observed that the SP-BC exhibits a PV current ripple of approximately 14% at . In the TP-BC topology, the current ripple slightly increases to about 5% at , decreases to zero at , and rises again to around 9% at . Throughout the entire duty-cycle range, the TP-BC achieves lower current ripple compared to the SP-BC. In contrast, the proposed PTS-BC maintains an almost zero current ripple under all operating conditions. As depicted in Fig. 14(b), the PV voltage ripple follows a similar trend but exhibits higher ripple magnitudes. Nevertheless, the PTS-BC once again provides nearly zero voltage ripple across the entire duty-cycle range. Moreover, Fig. 14(c) presents the corresponding PV power ripple characteristics, where the SP-BC, TP-BC, and PTS-BC achieve approximately 17%, 5%, and 0% power ripple, respectively. Since the power ripple indicates the loss in the harvested power, the proposed PTS-BC introduces almost no power degradation, confirming its superior ripple-free performance.

Fig. 14.

PV panel output ripple variation as a function of D for different converter topologies: (a) current, (b) voltage, and (c) power.

Fig. 15 shows the output power of PV depending on D. As shown, the proposed PTS-BC topology has a nearly constant power of approximately 449 W across the entire D range. In contrast, the SP-BC topology shows a significant decrease in output power as the D increases. The TP-BC topology achieves the maximum output power of 449 W only D at 50% but falls beyond this D. These results confirm that ripple suppression is directly correlated with the ability to extract maximum power from the PV panel. The advantage of the PTS-BC topology provides ripple-free power transfer for the entire D range.

Fig. 15.

PV panel output power variation as a function of D for different converter topologies.

Figure 16 presents PV panel output parameters (current, voltage, and power ripple) as a function of switching period. The analysis is conducted for three different D values: 40%, 50%, and 60%. Each column corresponds to a different D, while each row represents a different output parameter: PV current (top row), PV voltage (middle row), and PV power (bottom row). The SP-BC (Fig. 16(a1)) exhibits a high current ripple with the increasing D. The TP-BC (Fig. 16(a2)) achieves zero current ripple specifically at 50% D, where the current components from the two phases effectively cancel each other out. However, at 40% and 60%, D has a ripple component. In contrast, the PTS-BC (Fig. 16(a3)) achieves nearly zero current ripple across all examined D. In the SP-BC (Fig. 16(b1)), voltage ripple becomes particularly high at 60% D. TP-BC (Fig. 16(b2)) can suppress voltage ripple effectively at 50% duty, but shows moderate ripple at other values. Similarly, the PTS-BC (Fig. 16(b3)) maintains an almost constant voltage across all operating conditions, like current. The power plots shown in Fig. 16. In the case of SP-BC (Fig. 16(c1)), the instantaneous output power decreases as low as 420 W below the theoretical 450 W MPP. TP-BC (Fig. 16(c2)) provides a nearly constant power output at 50% duty, but exhibits ripple at other values. The proposed PTS-BC (Fig. 16(c3)) provides constant, ripple-free power output in all three D.

Fig. 16.

Variation of PV panel output parameters as a function of time: PV current at (a1) D=40%, (b1) D=50% and (c1) D=60%; PV voltage at (a2) D=40%, (b2) D=50% and (c2) D=60%; PV power at (a3) D=40%, (b3) D=50% and (c3) D=60%.

Experimental setup and results

This section provides a detailed overview of the experimental evaluation process for the proposed PTS-BC topology. First, the experimental setup and prototype are described, followed by the test procedure. Finally, the experimental results are presented. In the results, , , and the related PWM signals are measured for different D using an oscilloscope. These measurements are followed by a summary plot of the input current ripple versus D, serving as the experimental verification of the simulation based results in Fig. 14(a). Furthermore, the voltage gain characteristics of the PTS-BC are examined for varying D, and the overall system performance is assessed through efficiency maps.

An experimental laboratory setup (Fig. 17) is established to validate the simulation results. This section is focused on the current ripple, voltage gain, and efficiency under different D. A PV simulator (Chroma 62100H-600S) is used to emulate the behavior of a real solar panel. The simulator is configured to mimic the electrical characteristics of the 450 W PV panel used in simulations. The prototype of the PTS-BC is at the center of the figure. A resistive load is connected at the output of the converter to emulate varying load conditions. Input and output electrical parameters are monitored using a differential voltage probe (Pintek DP25) and a current probe (TCPA3000). These probes are connected to a Tektronix MDO34 oscilloscope. An auxiliary power supply is used to feed the gate driver and control circuits. An ST-LINK/V2 programmer is connected to the control board for microcontroller programming.

Fig. 17.

Experimental setup used for testing.

Figure 18 shows the detailed view of the PTS-BC. The PTS-BC is composed of the control and power stage. The control stage includes an STM32H750 microcontroller. The microcontroller performs real-time sensor processing and generates PWM signals to gate drivers (1ED020I12B2XUMA1). The power stage consists of three parallel boost converter legs. Each includes a SiC MOSFET and a SiC diode. The SiC MOSFET (C3M0045065K, rated at 650 V, 49 A) can operate 50kHz switching frequency with minimum switching and conduction losses thanks to the fast dynamic behaviour (low turn-on delay of 9 ns, rise time of 12 ns, turn-off delay of 18 ns, and fall time of 6 ns) and low conduction resistance (45 ). a SiC diode (E3D20065D, 650 V, 56 A) also contribute efficient working condition its zero reverse recovery current proporty. These semiconductors are mounted on heatsinks (CR401-75VE) by using a clip (CLA-T247-21E) and cooled by fans to provide safe thermal operation. Each phase leg includes a discrete 500 boost inductor with ferrite toroidal core (Magnetics 0078617A7). The intermediate and output dc buses are filtered using high-frequency 10 film capacitors (BLH106K551A072). First stage input1 and input2 are electrically shorted and connected to the same PV input terminal. Similarly, first stage output1 and output2 are shortened and connected to the second stage input. The first and second stages establish the series cascade structure. A dedicated capacitor () is connected across the first stage output and second stage input. The output of the second stage is connected to an output capacitor . An isolation amplifier (AMC1301) is used for voltage sensing, while hall effect transducer (CAS 25-NP) is used for current sensing. Signal conditioning circuits that provide level shifting and protection are used between sensors and the microcontroller’s ADC inputs.

Fig. 18.

Hardware prototype of the proposed PTS-BC converter.

Under real operating conditions, the solar irradiance on the PV panel surface is not constant, which makes it difficult to maintain steady power generation. Therefore, in the experimental tests, a programmable PV simulator was used to emulate a solar panel under standard test conditions, ensuring a constant irradiance and enabling constant power. The simulator output was set according to the PV panel parameters listed in Table 4. Three converter topologies, which are SP-BC, TP-BC, and PTS-BC, were tested at the MPP. While the D was experimentally evaluated for SP-BC and TP-BC over the range of to , the PTS-BC topology was tested only up to for its second stage. Beyond this point, the output voltage exceeded the safe operating limits of the available resistive load bank, and further testing was avoided. Since the first stage of the PTS-BC is dedicated to eliminating input current ripple, it was operated at a fixed , while the second-stage duty cycle was varied between and during the tests.

As illustrated in Fig. 19, current waveforms ( and ) were acquired using ac coupling mode on the oscilloscope for three different values of D (, , and ). PWM signal of the related switch is also shown with D. The was approximately 10.47 A. While the SP-BC topology (a1, a2, a3) exhibits relatively high ranging between 0.653 A and 0.972 A, the TP-BC topology (b1, b2, b3) demonstrates improved ripple suppression. The starts at 0.234 A when , reaches a minimum of 0.043 A at , where phase cancellation is most effective, and increases again to 0.303 A at . In general, the in TP-BC remains below that observed in SP-BC, particularly near the optimal . The PTS-BC topology (c1, c2, c3) achieves the best ripple performance, maintaining nearly constant between 0.050 A and 0.061 A. These ripple values are comparable to the ideal 50% condition of TP-BC, confirming that PTS-BC effectively maintains low-ripple operation over a wide D range. Additionally, in the (c1, c2, c3), the , which represents the current drawn by the second stage from the first, is also measured. While the increases from 1.31 A to 1.97 A as D increases, it does not introduce any distortion or additional ripple to the . As seen from here, the first stage of the PTS-BC ensures ripple-free current extraction from the PV panel as intended before.

Fig. 19.

Experimental current and PWM waveform observations for SP-BC (a1) , (a2) , and (a3) ; TP-BC (b1) , (b2) , and (b3) ; and PTS-BC (c1) , (c2) , and (c3) . (CH1: ; CH2: (PTS-BC only); D1: ; D2: ; D3: . Vertical scale: 200 mA/div; horizontal scale: 10 s/div.)

Figure 20 presents the experimentally measured input current ripple as a function of D for the SP-BC, TP-BC, and PTS-BC topologies. Unlike the waveform observations shown in Fig. 19, which focus on three representative cases (, , and ), this figure summarizes ripple measurements conducted over a wider range of D. The results exhibit strong agreement with the simulation based trend shown in Fig. 14(a), experimentally confirming the superior ripple mitigation capability of the PTS-BC topology across a broad operating range. Specifically, in the SP-BC topology, the ripple magnitude increased from approximately 1.9% at to 11% at . In the TP-BC topology, reached nearly zero at . Except for D at 50% values, the ripple increased but remained below that observed in the SP-BC. In contrast, the proposed PTS-BC maintained nearly 0.5% across the entire tested range, closely matching the ripple condition calculated in simulation.

Fig. 20.

Experimental PV panel output current ripple variation as a function of D

Figure 21 illustrates the experimental voltage gain of the SP-BC, TP-BC, and PTS-BC topologies as a function of D. It is observed that the PTS-BC achieves higher voltage gain levels compared to the other two topologies at significantly lower D. For example, while PTS-BC can achieve at , the SP-BC and TP-BC require for same . This significant reduction in D provides the enhanced efficient working capability of the two-stage architecture.

Fig. 21.

Experimental voltage gain as a function of D.

Figure 22 illustrates efficiency maps for the SP-BC, TP-BC, and PTS-BC. Although conduction losses were not measured separately, the experimental efficiency maps confirm the overall efficiency improvement of the PTS-BC. These improvements are consistent with the theoretical expectation that lower duty ratios reduce switch conduction intervals, thereby decreasing conduction-related losses in addition to switching. The horizontal axis denotes the D, the vertical axis represents the corresponding , and the third dimension efficiency (). Efficiency is encoded using a color gradient ranging from to . In these efficiency maps, the maximum efficiencies observed for the SP-BC, TP-BC, and PTS-BC circuits are 433 W with 96.4%, 437 W with 97.43%, and 438.2 W with 98%, respectively. The PTS-BC demonstrates good performance by achieving higher output power with better efficiency.

Fig. 22.

Experimental efficiency maps of (a) SP-BC, (b) TP-BC, and (c) PTS-BC topologies.

Conclusion

This study analyzed the simulation and experimental results of dc–dc boost converter topologies used in PV systems. The conventional SP-BC and TP-BC, as well as the proposed PTS-BC, are examined. Unlike conventional SP-BC and TP-BC, the proposed PTS-BC employs dedicated stages for ripple cancellation and output regulation. This architectural distinction uniquely enables ripple-free PV input current without bulky input capacitors, highlighting the novelty and practical significance of the two-stage approach.

The PTS-BC demonstrated good current ripple suppression across the entire D range. maintain below 0.06 A. In comparison, the TP-BC achieved similar low ripple levels only at , while the SP-BC failed to reach such low ripple values at any operating point. Even when the first-stage output current () exhibited ripple, as shown in the measured waveform, the PTS-BC maintained ripple-free operation at the PV side.

Experimental results also showed that the PTS-BC achieves the same voltage gain at a significantly lower duty ratio compared to conventional SP-BC and TP-BC. This two-stage structure distributes the voltage conversion, which both lowers the duty ratio and reduces the voltage stress across each switch, since the voltage difference between input and output is shared across two stages. Operating at a lower duty ratio also shortens the switch conduction interval, which theoretically reduces conduction losses and contributes to higher overall efficiency. Although conduction losses were not measured separately, the observed efficiency improvement in the experimental maps is consistent with this expectation. It should also be noted that, since EMI is strongly dependent on switching stress, dv/dt, and layout-related factors, it was not analyzed in this work and is left for future investigation. Nonetheless, the reduced voltage stress observed in the PTS-BC may also contribute to improved EMI performance, which will be investigated in future studies. Consequently, the PTS-BC not only improves conversion efficiency but also enables higher output power and enhanced energy harvesting over time from the PV system.

The PTS-BC reaches a peak efficiency of approximately 98%, representing improvements of about 0.7% and 1.6% over the TP-BC and SP-BC, respectively. The PTS-BC achieves the most balanced performance among the evaluated topologies. Although it increases the component count and control complexity compared to the SP-BC and TP-BC, its aforementioned advantages make it particularly suitable for high-performance PV applications.

Author contributions

H.A. conceived and designed the study, carried out the simulations and experiments, analyzed the data, and prepared the manuscript. The author reviewed and approved the final version of the manuscript.

Funding

This work was supported by The Scientific and Technological Research Council of Türkiye (TÜBİTAK) under Project No. 120E365.

Data availability

All data generated or analyzed during this study are included in this published article

Declarations

Competing interests

The authors declare no competing interests.