Subthreshold Schottky-barrier transistor based on monolayer molybdenum disulfide

Abstract

While the internet of things (IoT) enhances global connectivity through trillions of sensors, the sensory signals are weak and require precise amplification and rapid transmission via thin-film transistor (TFT) interfaces, which must uphold high voltage gain and wide operating frequency range. In this work, we demonstrate a source-gated transistor (SGT) architecture integrating chemical vapor deposition (CVD)-grown monolayer MoS₂ with thin high-k dielectrics. This transistor achieves subthreshold operation with high intrinsic gain and wide operating frequency range, even at an 80 nm channel-length (L_CH). The optimization of output resistance, transconductance and subthreshold swing yields an SGT intrinsic gain exceeding 2.4×10³, with no degradation as L_CH scales from 1000 nm down to 80 nm. Additionally, benefitting from the ultra-short 80 nm L_CH, microwave measurements show a high cut-off frequency of 208 MHz in the subthreshold regime. A monolithically integrated common-source amplifier operating in the subthreshold regime exhibits a high gain of 249 V/V at low supply voltage (0.5 V) and ultra-low power ( ~ 0.17 nW), indicating a promising path toward a universal high-performance transistor solution for high gain, high frequency, and ultra-low power applications.

Thin film transistors with high voltage gains and operating frequencies are required for internet of things applications. Here, the authors report short-channel source-gated transistors based on monolayer MoS₂, showing intrinsic gain exceeding 2.4×10³ and cutoff frequencies up to 208 MHz in the subthreshold regime.

Introduction

The Internet of Things (IoT) has the ability to provide every human access and communication to the world in unprecedented ways, thanks to the deployment of trillions of sensors^1,2. This vast network of interconnected sensors enables the collection, exchange, and analysis of data by converting physical and chemical signals, e.g., light³, pressure⁴, temperature⁵, etc., into small amplitude analog electrical signals, giving way to improved efficiency, enhanced decision-making, and innovative implementations across multiple application domains. These weak output signals generated by sensors typically need high-precision amplification coupled with high-speed transmission by thin-film transistor (TFT)-based sensor-interfaces for subsequent signal processing and conditioning⁶. This requires TFT interface circuits to maintain a high voltage gain and low equivalent input noise across a wide frequency range to make them suitable for IoT implementations⁷.

In conventional TFTs, the channel length modulation effect causes a continuous rise in current after the TFT is saturated, which lowers the output resistance (R_OUT) and reduces the intrinsic gain (A_i = g_m × R_OUT, where g_m is the transconductance)⁸. To address this problem, two improved TFT structures have been proposed: the source-gated transistor (SGT)⁹ by Shannon et al. in 2003 and the Schottky barrier thin-film transistor (SB-TFT)¹⁰ by Lee and Nathan in 2016. These architectures generally create a Schottky barrier between the source contact and the semiconductor, so that the I_DS is mainly dominated by the source barrier height controlled by the gate voltage (V_GS) and is almost unaffected by the drain terminal, resulting in high R_OUT and high A_i. Numerous subsequent reports have demonstrated such structures using silicon^11–13, indium gallium zinc oxide (IGZO)¹⁴, organic^7,15 and molybdenum disulfide (MoS₂)¹⁶ channel materials. They all achieved high gains.

However, most if not all demonstrated TFTs operating in subthreshold exhibit low operating frequencies (<1 kHz), primarily limited by low current¹⁷ and long channel lengths (>10 µm)¹⁴ or low channel mobility^7,15. To maintain high gain over a wider operating frequency range, the critical limitation lies in achieving high gain at higher frequencies. In conventional approaches, frequency performance is enhanced by aggressively scaling the channel length or adopting self-aligned structure^18,19 to minimize gate parasitic capacitance. Such approaches are limited to improving cut-off frequency, however, at the cost of sacrificing intrinsic gain due to exacerbated short-channel effects (SCEs).

As discussed earlier, both SB-TFT and SGT exhibit strong immunity to SCEs, indicating great promise for high-frequency operation. Compared to the SB-TFT, the SGT is more immune to SCEs due to the insulating layer added between the source metal and semiconductor layer. This enhances vertical gate control and improves the shielding effect of the source on the drain field. Notably, with MoS₂, which offers high mobility, atomic-layer channel thickness, and strong gate control capability^20–25, better SGT scaling becomes possible. In addition, the SGT can operate in the subthreshold regime to achieve low power²⁶. Therefore, by synergistically selecting the SGT structure and MoS₂ as the channel material to minimize SCEs, and incorporating channel length scaling, coupled with gate dielectric engineering and subthreshold operation, it is possible to achieve high frequency operation without compromising high gain at low power consumption.

In this article, we demonstrate an 80 nm channel-length SGT based on chemical vapor deposition (CVD) of monolayer MoS₂, with high intrinsic gain, high cut-off frequency, and operating in the subthreshold region. The SGT structure lends itself to a high source barrier, and a wide channel potential barrier is formed. The MoS₂ SGT exhibits pinch-off regions occurring at both source and drain, leading to high output resistance (R_OUT > 10¹¹ Ω) in the subthreshold region. In addition, transconductance (g_m) is improved by systematic optimization, by virtue of high mobility monolayer MoS₂, thin gate dielectric and short-channel length. The overall optimization of g_m and R_OUT leads to an intrinsic gain (A_i = g_m × R_OUT) that is over ~2.4 × 10³ with no degradation when L_CH is scaled from 1000 to 80 nm. In addition, the device also exhibits small subthreshold swing (SS) (~70 mV/dec), small drain-induced-barrier-lowering (DIBL) effect (~7.3 mV/V), high transconductance efficiency (g_m/I_DS) (~38 S/A), low leakage current (below 10⁻¹² A/μm), and high on/off ratio (over 10⁹) at L_CH = 80 nm. Besides, microwave measurements demonstrate a cut-off frequency of 208 MHz and a maximum oscillation frequency f_MAX of 211 MHz of the SGT operated in the subthreshold regime at L_CH = 80 nm. Finally, we further demonstrate a common-source amplifier operating in the subthreshold regime that exhibits a high gain of 249 V/V at low-supply voltage (0.5 V) and low power (~0.17 nW). This outperforms existing technologies using silicon, organics, oxides and other 2D materials, and provides for a universal high-performance transistor solution for high gain, high frequency and low power applications.

Result

Device structure and operating mechanism of MoS₂ SGT

The schematic view of the MoS₂ SGT device structure is shown in Fig. 1a. Contrary to the conventional MoS₂ TFT, where the source/drain contacts are ohmic, in SGTs, the Schottky source contact increases the source barrier height, and the external gate is augmented at the source to increase the source barrier width. In device fabrication, CVD atomically thin one-layer (1 L) MoS₂ was chosen as the channel material. Detailed material information, including atomic force microscopy (AFM), Raman spectra and Photoluminescence (PL) spectra characterizations, are shown in Supplementary Figs. 1, 2, indicating the monolayer nature of MoS₂. We performed electrical tests on conventional MoS₂ TFTs and mobility (μ_FE) extracted is 29.3 cm²V⁻¹ s⁻¹ (Supplementary Fig. 3), which confirms the high quality of the MoS₂. The back gate used molybdenum (Mo) grown by magnetron sputtering and was patterned by dry-etching to ensure flatness and reduce leakage current. Palladium/Gold (Pd/Au) and Nickel/Gold (Ni/Au) fabricated using electron-beam evaporation (EBE) were chosen as the source/drain contacts because of their work function matching with the MoS₂ channel to form Schottky source-contact and ohmic-drain-contact, respectively. The temperature-dependent measurements and barrier-height extractions²⁷ supporting the contact behavior analysis are presented in Supplementary Fig. 4. As for the dielectric layer, hafnium oxide (HfO₂) and aluminum oxide (Al₂O₃) were chosen owing to their excellent dielectric properties, low gate leakage current and low-temperature atomic-layer deposition (ALD) growth process capable of precisely controlling thickness. All key lithography steps are done by electron-beam lithography (EBL). The detailed fabrication process is shown in Supplementary Fig. 5. To guarantee that the device is developed with no damage between individual layers during the fabrication process, this is confirmed by high-resolution transmission electron microscopy (HRTEM) with energy-dispersive X-ray spectroscopy (EDX) element mapping, which are shown in Fig. 1b and Supplementary Fig. 6, respectively. The TEM images indicate that the interfaces of all layers are sharp and clear, and it’s obvious that the MoS₂ channel is a single layer. EDX analysis demonstrates that all elements are distributed uniformly and without interdiffusion. And the TEM image confirms the geometry of the MoS₂ SGT, where the channel length (L_CH) is 80 nm, and the external gate distance (d) is 50 nm.

Fig. 1. Proposed MoS₂ source-gated transistor (SGT).

a Schematic image of the MoS₂ SGT structure. L_CH represents the channel length and d represents the external gate distance. b Cross-section transmission electron microscopy (TEM) image of the MoS₂ SGT for L_CH = 80 nm. Scale bar, 20 nm. c Comparison of the energy band diagrams of the proposed structure (orange line) and traditional structure (purple line) operating in the subthreshold region with long channel (top) and short channel (bottom), respectively. Φ (Φ’) represents the Schottky source barrier height of the long channel (short channel). W(W’) represents the channel potential barrier width of the long channel (short channel). E_C and E_F represent the conduction-band minimum and the Fermi level, respectively. E_Long and E_Short represent the drain-to-source electric field of the long channel and short channel, respectively. V_DS, V_GS, and V_TH represent the drain-to-source voltage, gate-to-source voltage, and threshold voltage, respectively. d Correspondence between cut-off frequency and low-frequency gain in different types of transistors. TFT represents the thin-film transistor, and CMOS represents the complementary metal oxide semiconductor field-effect transistor.

Before further electrical investigation of the MoS₂ SGT, a mechanism comparison between the SGT and conventional TFT was made to clarify that the SGT possesses better immunity to drain control. We compare the energy band diagram between SGT and conventional TFT in Fig. 1c. In the SGT, better immunity to drain electric field comes from two aspects: higher Φ and wider W, where Φ is the Schottky source barrier height and W is the channel potential barrier width without drain voltage influence, which are directly related to the source Schottky contact and source external gate, respectively. At the same drain voltage, the drain electric field will increase with the shortening of the channel length. Unlike the conventional TFT, where the channel barrier decreases dramatically due to the increase in drain field, the presence of the Schottky source and external gate in the SGT shields the effect of the drain electric field and thus better maintains the height of the channel barrier. More specifically, we analyzed the specific role of the source barrier and the external gate as V_DS increases until the TFT saturates. The comparison between the proposed pinch-off mechanism and the conventional pinch-off mechanism is shown in Supplementary Fig. 7. For conventional TFTs, with increasing V_DS, the carrier concentration at the drain terminal decreases until pinch-off, at which point, the I_DS reaches saturation. For SGT, at small V_DS, the source barrier is reversed to deplete carriers under the source, until all carriers induced by V_GS are depleted, whereby the first depletion region occurs at the source, and V_DSAT is defined²⁸. As V_DS increases, the excess V_DS cannot affect the electric field of the depletion region under the source barrier in the presence of an external gate. But, instead expands the depletion envelope towards the drain direction and lowers the carrier density in the drain, like in the conventional TFT. Then the second depletion occurs at the drain with further increasing V_DS. With both the source and drain depleted, a larger output resistance is expected in the SGT compared to the conventional TFT. TCAD (Sentaurus, Synopsys) simulations of the carrier concentration and electric field confirm the mechanism of device operation (see Supplementary Fig. 8 for details). In addition to simulation results, we compare the electrical performance of the SGT and conventional TFT (Supplementary Fig. 9). From the transfer curves in log-scale and linear-scale (Supplementary Fig. 9a, b), we can see that SGT exhibits larger V_TH and lower I_DS mainly due to the source barrier. The DIBL extracted from the zoom-in transfer curves in the subthreshold region shows a reduction in DIBL in SG TFT by 57% (from 16.7 to 7.3 mV/V). From the output curves in small and large V_GS-V_REF (Supplementary Fig. 9e, F), in which reference voltages (V_REF) are chosen by the V_GS at I_DS = 10^-10A/μm, V_REF equals 0 and −0.5 V for SGT and conventional TFT, respectively. And we can see the output curves are flatter in the SGT. More precisely, the extracted R_OUT (Supplementary Fig. 9g) from Supplementary Fig. 9e is observed to be increased in SG TFT by about 25X at V_GS-V_REF = 0 V. Multiplied with the extracted transconductance (g_m) in Supplementary Fig. 9d, the intrinsic gain as a function of V_GS-V_REF generated in Supplementary Fig. 9h is given by the following equation: A_i = g_m × R_OUT. Compared with conventional TFT, the A_i increased in SGT by about 17X at V_GS-V_REF = 0 V. Taken together, these experimental results also further confirm the mechanism. For SGT, the source/drain geometry asymmetry shows it can operate in two biasing configurations: the source-gated configuration and the drain-gated configuration as shown in Supplementary Fig. 10. From the comparison of the transfer curves and output curves corresponding to the two biasing configurations, we can see that in the drain-gated configuration, the device exhibits smaller output resistance, higher current and larger DIBL, which are mainly due to two aspects. On the one hand, the Schottky barrier is forward-biased to enlarge the carrier concentration under the drain. On the other hand, the drain external gate induces carriers in the region beneath the drain, which is quite different from the source external gate depleting carriers in the region beneath the source. Finally, we compare the low-frequency gain and operating frequency range (−3 dB bandwidth) performance of silicon metal oxide–semiconductor field-effect transistors (MOSFET), long channel SGT, short channel SGT, long channel TFT, and short channel TFT in Fig. 1d. We conclude that the short channel SGT is able to maintain high low-frequency gain over a wider operating frequency range, making it more favorable for its application in sensor-interface circuits.

Subthreshold performance trends with channel length scaling

To demonstrate the gain versus frequency of MoS₂ SGTs operating in the subthreshold region as the channel length (L_CH) decreases, we measured MoS₂ SGT with different L_CH from 1000 nm down to 200 nm. Figure 2a shows the corresponding transfer (I_DS–V_GS) characteristics, where I_DS is the drain-to-source current, and V_GS is the gate-source voltage. From the transfer curves, we can see that when L_CH is scaled down from 1000 to 200 nm, the subthreshold characteristics of the MoS₂ SGT remain almost unchanged while the on-state current slightly increases. We extracted the transconductance (g_m) from the transfer curves at V_GS = 0 V, which shows an increasing trend with L_CH scaling, as shown in Fig. 2c. Figure 2b depicts the corresponding output (I_DS–V_DS) characteristics, where V_DS is the drain-source voltage. The output curves are very flat in the saturation region, depicting a very large R_OUT. We extracted R_OUT from the output curves at V_GS = 0 V. This is shown in Fig. 2d. The R_OUT decreases as L_CH scaled, and are all larger than 10¹¹ Ω. Next, the intrinsic gain as a function of L_CH is generated in Fig. 2e following the relation: A_i = g_m × R_OUT. It is observed that the A_i is maintained at a high value (about 3900) and does not degrade severely as L_CH scaled. The A_i vs. L_CH results prove that the SGT possesses a better immunity to short-channel effects and maintains very high output resistance (R_OUT) and thus a high intrinsic gain. To comprehensively evaluate the A_i, we make a comparison of A_i vs. L_CH between this work and different TFTs, including other 2D material TFTs^16,29–31, metal oxide TFTs^10,14,32, organic TFTs^7,15,33,34 and Si MOSFET^35,36 (see Supplementary Table 1 for details). It shows that the fabricated MoS₂ SGT in this work has high A_i amongst the different TFTs despite the short L_CH, demonstrating strong voltage amplification ability and the potential for sustained scaling. In addition to the intrinsic gain, the cut-off frequency (f_T), i.e., the frequency where a TFT’s short circuit current gain drops to 1, can limit the actual gain bandwidth product of amplifiers^19,29,37. To evaluate the frequency performance of the MoS₂ SGT, we have conducted on-chip microwave measurements using an R&S vector network analyzer ZNL3 in the range of 5 kHz–3 GHz. For frequency measurements, the MoS₂ SGTs were fabricated on a highly resistive silicon substrate (>20 kΩ·cm) to minimize the parasitic capacitance. The small-signal current gain h₂₁ extracted from the S-parameters measured at different L_CH from 1000 nm down to 200 nm is shown in Fig. 2g. The DC bias of the V_GS and V_DS are 0.5 and 1.0 V, respectively, ensuring that the SGT operates in the subthreshold regime. The h₂₁ decreases with frequency with a slope of −20 dB/decade, which is consistent with the frequency characteristics of traditional semiconductor TFTs³⁸, and we can see that the f_T increases as L_CH decreases, and when L_CH = 200 nm, f_T equals 87 MHz. In addition to f_T, the maximum oscillation frequency (f_MAX), defined as the frequency at which the power gain is equal to one, is another important figure of merit defining the frequency performance of a TFT. Figure 2h illustrates the unilateral power gain U^1/2 versus frequency for SGTs corresponding to Fig. 2g, and the maximum oscillation frequency (f_MAX) equals 100 MHz at L_CH = 200 nm. Further, by analyzing the relationship between f_T and L_CH, a 1/L² dependence is observed in our devices (Fig. 2i), confirmed from the relation³⁹,

$$f_T=\frac{g_m}{2\pi \left(C_{gs}+C_{gd}\right)}$$ 1

Fig. 2. Relationship between intrinsic gain and cut-off frequency in MoS₂ SGT operating in the subthreshold region as L_CH decreases.

a Transfer characteristics (I_DS–V_GS) at channel lengths (L_CH) of 1000, 800, 600, 400, and 200 nm. I_DS represents the drain current. b Output characteristics (I_DS–V_DS) corresponding to (a). Extracted transconductance (g_m) (c), output resistance (R_OUT) (d), and intrinsic gain (A_i) (e) corresponding to (a, b). f Benchmarks of A_i vs. L_CH for state-of-the-art TFTs for this work. HZO GI, ferroelectric HfZrO_x gate insulator. g Small-signal current gain |h₂₁| versus frequency for five SGTs at channel lengths of 1000, 800, 600, 400, and 200 nm, respectively. V_GS and V_DS is biased to 0.5 and 1.0 V during the frequency measurement process, respectively. f_T represents the cut-off frequency. h Unilateral power gain U^1/2 versus frequency for SGTs corresponding to (g). i f_T extracted from (g) as a function of L_CH.

Here, g_m is the transconductance, C_gs and C_gd are the gate-to-source and gate-to-drain capacitances, respectively. Equation (1) shows that the value of f_T is proportional to g_m/(C_gs+C_gd), as g_m and C_gs+C_gd are proportional to W/L and W·L, respectively. Thus, f_T would be independent of channel width, and the relationship between f_T and L is 1/L². We can see that when L_CH is scaled down from 1000 nm to 200 nm, f_T increases from 26 to 87 MHz, which is about 3.3 times larger. If we roughly estimate the frequency characteristics of SGT in a long channel (e.g., 10 µm) based on the 1/L² correlation, it is about 2.3 MHz, which is 1/37 of that at 200 nm. This poor frequency characteristic of SGT is not conducive to high-frequency operation. Therefore, we need to shorten the L_CH of the SGT in pursuit of a larger f_T.

Subthreshold performance of 80 nm MoS₂ SGT

Based on the above-subthreshold performance of SGTs, we observe that as the channel length decreases, the SGT can effectively suppress the short-channel effect without a significant decrease in the intrinsic gain, and we also observe that the frequency response significantly improves if the channel length is further shortened. As the next step, we further reduce the channel length of the SGT with the prospect of achieving high intrinsic gain and high frequency performance. We fabricated and measured ultra-scaled MoS₂ SGT as shown in Fig. 1b with channel width/length (W/L) = 500/80 nm, and an external gate distance (d) of 50 nm. Figure 3a shows the transfer characteristics at different V_DS (0.1, 0.7, and 1.0 V), and shows that the threshold voltage (V_TH) is about 0.9 V based on a linear fit to the transfer curve at V_DS = 0.1 V (Supplementary Fig. 11). Several interesting features were observed in the subthreshold region, including a small drain-induced-barrier-lowering (DIBL) effect. The DIBL was about 7.3 mV/V, calculated from the V_REFS drift from V_DS = 0.1 V to V_DS = 1.0 V. The subthreshold swing (SS) at V_DS = 0.1 V was about 70 mV/dec, in which SS is extracted from over two decades of I_DS. More importantly, a high transconductance efficiency (g_m/I_DS) is observed (Supplementary Fig. 12). This represents the efficiency of converting the bias current into an equivalent transconductance. In the subthreshold region, the highest g_m/I_DS was ~38 S/A, which approaches the theoretical limit of q/k_BT (i.e., 38.7 S/A at T = 300 K). Here, q is the elementary charge, k_B the Boltzmann constant, and T the temperature. For analog TFT circuits, a high g_m/I_D is essential for an amplifier circuit to reduce the power consumption without compromising its high-amplification performance. In addition to its good subthreshold characteristics, the ultra-scaled MoS₂ SGT also exhibits low leakage current (I_OFF < 10⁻¹²A/μm), relatively large on-state current (I_ON > 10⁻⁴A/μm) at V_DS = 1.0 V, high on/off ratio of over 10⁹, and a normalized g_m of 171.8 μS/μm (Supplementary Fig. 12). Besides, nearly negligible hysteresis is observed, confirming the excellent interface quality (Supplementary Fig. 13). Consistent with the small DIBL in the transfer curves, we have also observed very flat saturation output curves measured at different V_GS (from -0.2 V to 0.5 V, 0.1 V step) in Fig. 3b. The measured R_OUT is above 10⁸ Ω at V_GS = 0.5 V. The extracted g_m (black circles) and R_OUT (blue circles) of the MoS₂ SGT operating in the subthreshold region, are shown in Fig. 3c. The A_i calculated as a function of V_GS is shown in Fig. 3d. The A_i of the MoS₂ SGT remains almost bias independent when operating in the subthreshold region. Compared with TFTs of other 2D materials and oxides, and the Si-MOSFET, the A_i of the MoS₂ SGT is much higher and at least two orders of magnitude higher than the Si-MOSFET at the commercial 65 nm technology node⁴⁰. Further, in order to estimate the device uniformity, we measured 56 MoS₂ SGTs with L_CH = 80 nm (the transfer characteristics and statistical results are shown in Supplementary Fig. 14). Supplementary Fig. 14b shows that the subthreshold voltage (V_TH) is uniformly distributed around 1.08 V, where V_TH is extracted by linear extrapolation. Supplementary Fig. 14c shows over 96% (54 out of 56) of the devices with SS (over one decade of I_DS) less than 100 mV/dec with I_ON of all devices over 10 μA/μm (Supplementary Fig. 14 d). The above discussion clearly shows that good DC performance is achieved at L_CH of 80 nm. To further evaluate the frequency performance, we measure the f_T and f_MAX using the aforementioned method. The small-signal current gain h₂₁ and unilateral power gain U^1/2 extracted from the S-parameters measured at different DC biases are shown in Fig. 3e, f, respectively. The DC bias of the V_DS is fixed at 1.0 V, while the DC bias of V_GS varies from 0.5 to 2 V in steps of 0.5 V. The relationships of f_T and f_MAX with V_GS extracted from Fig. 3e, f are shown in Fig. 3g. We can see that in subthreshold operation (i.e., V_GS = 0.5 V), the f_T is 208 MHz and f_MAX is 211 MHz. Although the SGT exhibits a lower f_T than previously reported MoS₂ transistors with comparable channel lengths that employed a top-gate structure optimized for high-frequency operation³⁷, this behavior is inherent to its source barrier-controlled conduction mechanism and subthreshold operation of the SGT. The design intentionally prioritizes high intrinsic gain and low power consumption, as required for sensor-interface circuits in IoT applications, where weak analog signals require high-gain and low-power amplification over moderate bandwidths². Nevertheless, future optimization, including shortening the source length, refining the gate-overlapped source region that controls the Schottky barrier injection⁴¹ (as detailed in Supplementary Fig. 15), and minimizing parasitic gate-to-source/drain overlaps without affecting the intrinsic SGT operation, could further enhance the high-frequency performance. In addition, although we can see that a better frequency response can be obtained by biasing the device in the above-subthreshold region, this obviously increases power consumption and reduces intrinsic gain. Equally important is the noise behavior since this determines the detection accuracy of the transistor amplifier circuit. We measured the noise current power spectral density of SGTs with different channel lengths operating in the subthreshold region, as shown in Fig. 3h. We find that the shorter the channel length, the higher the current noise at the same bias current (I_DC = 100 nA). The extracted relation between the current noise and the channel length at a frequency of 100 Hz is shown in the inset of Fig. 3h. For the SGT with the shortest channel length (L_CH = 80 nm), its current noise at different I_DC in the subthreshold region (Fig. 3i) shows a relatively low current noise. This clearly favors the application of SGT in low-power amplification circuits.

Fig. 3. MoS₂ SGT subthreshold performance with sub-100 nm channel.

a Transfer characteristic of MoS₂ SGT with L_CH of 80 nm at V_DS  =  0.1, 0.7, and 1.0 V. Dashed lines denote gate leakage current. DIBL represents the drain-induced barrier lowering, SS represents the subthreshold swing, and I_GS represents the gate leakage current. b Output characteristics of the device in (a). From top to bottom, V_GS is 0.5 V down to −0.2 at −0.1 V step. c Extracted values of g_m (black circles) and R_OUT (blue circles) as a function of V_GS at V_DS  = 1 V, scaled by 10¹¹ and 10⁻⁸, respectively, for better visual comparison. d Intrinsic gain (A_i = g_m × R_OUT) calculated from (c) as a function of V_GS. e Small-signal current gain |h₂₁| versus frequency for the MoS₂ SGT, where V_DS = 1.0 V and V_GS changes from 0 to 2 V in step of 0.5 V. f Unilateral power gain U^1/2 versus frequency for the MoS₂ SGT, where V_DS = 1.0 V and V_GS changes from 0.5 to 2 V in steps of 0.5 V. f_MAX represents the maximum oscillation frequency. g f_T and f_max as a function of V_GS. h Measured current noise of MoS₂ SGTs for different L_CH, where the direct current biases (I_DC) is 100 nA. Inset: current noise as a function of L_CH at f = 100 Hz. i MoS₂ SGT current noise measured at different I_DC for L_CH = 80 nm.

High-gain and low-power amplifiers based on MoS₂ SGTs

Based on the above measurement results, MoS₂ SGTs operating in the subthreshold region have high intrinsic gain, excellent g_m/I_D and good uniformity, indicating enormous potential for low-power, high-amplification applications. Based on this, we integrated MoS₂ SGTs to realize a common-source amplifier circuit, which is known to be one of the most basic circuits in analog TFT circuits. As for n-type-only technology, there are two kinds of amplifier circuit configurations: enhancement–enhancement mode (EE) amplifier and enhancement-depletion mode (ED) amplifier. A comparison of the amplification performance of an amplifier based on these two different modes is given in Supplementary Fig. 16. The equivalent circuit diagrams are shown in Supplementary Fig. 16a and Fig. 16c, and the derived small-signal model results in Supplementary Fig. 16b, d. The small-signal voltage gain (A_V = V_OUT/V_IN) of the enhancement-depletion mode amplifier (g_m1(R_OUT1//R_OUT2)) is obviously larger than that of the enhancement–enhancement mode amplifier (g_m1/g_m2). The experimental results in Supplementary Fig. 17 confirm this. Thus, to obtain a higher A_V, the ED mode was selected for the connected configuration with MoS₂ SG TFTs as the drive and load transistors to obtain higher R_OUT simultaneously, and thereby higher gain. Figure 4a shows the equivalent circuit and optical image of an ED mode amplifier using two MoS₂ SGTs with the same dimensions (W/L = 500/80 nm). The abrupt voltage transfer characteristic and high noise tolerance of the amplifier at V_DD = 0.5 V are seen in Fig. 4b. The amplifier achieves full swing output, and its voltage transition occurs at 0.5 V_DD with symmetric noise margin, low NM_L and high NM_H. The total noise margin, defined as (NM_L + NM_H)/V_DD, reaches up to 80%. From the inset of Fig. 4b showing the power to ground current (I_DD) at V_DD = 0.5 V, and the peak I_DD is ~0.34 nA. Figure 4c displays the amplifier’s gain of 249 V/V at V_DD = 0.5 V, and the gain increases to 694 V/V, 1099 V/V and 1511 V/V at V_DD = 1.0, 1.5, and 2.0 V, respectively (Supplementary Fig. 19). It is worth noting that in addition to high gain, this amplifier exhibits low power consumption (peak power ~0.17 nW) through the entire operation process at V_DD =  0.5 V. Next, we measured amplifiers with MoS₂ SGTs of different channel lengths (L_CH = 200, 400, 1000 nm). We observe that they all exhibit high gain and low power consumption (<1 nW). Detailed results are presented in Supplementary Figs. 20–22. Besides, during the measurement process, we found that amplifier gain increases with decreasing the sweep step (Supplementary Fig. 23a–f). This observed increase with a smaller step size originates from the numerical differentiation process and reflects a purely mathematical convergence toward the intrinsic small-signal gain, rather than any physical trapping effect, as confirmed by the additional measurements showing that the gain is independent of the sweep speed (Supplementary Fig. 23h, i). We measured at a 0.5 mV step due to measurement noise limitation, but we suppose a higher gain can be measured with a smaller sweep step. Therefore, we attribute the high gain and low power consumption to transistors operating in the subthreshold region with relatively high g_m and high R_OUT, which are unique properties of MoS₂ SGTs. And the gain and power comparison results between MoS₂ SGTs and conventional TFTs confirm it (see Supplementary Figs. 17, 18 for details). With L_CH scaling down from 1000 nm to 80 nm, the gain of the respective amplifiers at V_DD = 1.0 V are summarized in Fig. 4d. We can see a slight decrease in gain as L_CH decreases, although it still remains at a high level. Figure 4e benchmarks the A_V of amplifiers based on 2D materials^{29–31,42–49}, metal oxides⁵⁰, Si^51,52, and organics³³ under V_DD = 1.0 V to include more references (see Supplementary Table 2 for details). The gain outperforms the other amplifiers by at least one order of magnitude at similar L_CH. With V_DD scaled from 2 to 0.5 V, the gain of the corresponding amplifiers at L_CH = 200 nm are summarized in Fig. 4f, and the relationship of gain with V_DD is presented in Supplementary Fig. 20e. Figure 4g compares the power consumption of amplifiers based on 2D materials^{30,42,43,48,49,53}, metal oxides^10,47, Si⁵¹, and organics^7,33,54 (see Supplementary Table 2). The MoS₂ SGT amplifier reported here consumes lower power at smaller L_CH, showing great promise for low-power applications. A comprehensive comparison with V_DD, L_CH, and A_V (Supplementary Fig. 24), demonstrates that the results presented here achieve the optimal balance between low power consumption, high-amplification gain and scalability.

Fig. 4. Integrated amplifier based on MoS₂ SGTs.

a Equivalent circuit (left) and optical microscope image (right) of the enhancement-depletion mode amplifier arrays; scale bar, 500 μm (upper), 100 μm (bottom). I_DD represents the power to ground current, V_IN represents the input voltage, and V_OUT represents the output voltage. b Noise margin of amplifier at V_DD = 0.5 V (V_OH highest output voltage, V_OL lowest output voltage, V_IH highest input voltage, V_IL lowest input voltage). Inset: I_DD as a function of input voltage of amplifier at V_DD = 0.5 V. c Output voltage (black), amplifier gain (blue) and power consumption (red) as a function of input voltage for the amplifier in (b) under V_DD = 0.5 V. d Amplifier gain versus L_CH scaling from 1000 to 80 nm at V_DD = 1.0 V. e Benchmarking A_v as a function of channel length (L_CH) for amplifiers based on 2D materials, metal oxides, organic, Si and MoS₂ (this work) for V_DD = 1.0 V. The extracted data were listed in Supplementary Table 2. f Amplifier gain versus V_DD scaling from 2.0 V to 0.5 V at L_CH = 200 nm. g Benchmarking power consumption as a function of L_CH for amplifiers based on 2D materials, metal oxides, organic, Si and MoS₂ (this work). The extracted data were listed in Supplementary Table 2.

Discussion

A CVD monolayer MoS₂-based source-gated transistor is demonstrated with high intrinsic gain and high cut-off frequency operating in the subthreshold region. Using a Schottky source contact and an external gate at source, a high source barrier and a wide channel potential barrier is formed. Thus, the I_DS is immune to V_DS modulation, leading to high output resistance (R_OUT > 10¹¹ Ω) with an intrinsic gain (A_i = g_m × R_OUT) maintained above ~2.4 × 10³ with no observable degradation when the channel length is scaled down from 1000 to 80 nm. More importantly, the shortened channel length leads to an increase in the cut-off frequency. A cut-off frequency of 208 MHz is achieved in subthreshold operation for a channel length of 80 nm. We further demonstrate a voltage amplifier operating in subthreshold exhibiting a high gain of 249 at low-supply voltage (0.5 V) and low power (~0.17 nW). The MoS₂ source-gated transistor reported here outperforms transistors of existing technologies based on silicon, organics, oxides and other 2D materials, and provides a universal high-performance transistor solution for high gain, high frequency and low power consumption applications.

Methods

Fabrication of MoS₂ SGT

The fabrication process flow of MoS₂ SGT is shown in Supplementary Fig. 5. Firstly, a 30 nm Mo gate metal was deposited by magnetron sputtering on 300 nm SiO₂ grown on silicon substrates and then patterned by inductively coupled plasma (ICP) dry-etching process using SF₆/C₃F₈ plasma. Then, a 6 nm HfO₂ dielectric layer was deposited on the Mo gate electrode by ALD (BeneQ TFS 200) at 300 °C with tetrakis (ethylmethylamino) hafnium (IV) (TEMAH) and H2O as the Hf and O precursors, respectively. The growth rate of HfO₂ at 300 °C is 0.76 Å per cycle. It was then patterned by the ICP dry-etching process using BCl₃ plasma. After low-power O2-plasma treatment for 2 min, the CVD monolayer MoS₂ was transferred onto the target substrate by using wet transfer methods and then patterned by reactive ion etching (RIE). Then, the drain contact was patterned by electron-beam lithography (EBL), and a bilayer metal stack of 20 nm/20 nm Ni /Au was deposited by electron-beam evaporation and lift-off. Next, a 1.6 nm Al seed layer was deposited by thermal evaporation. The Al layer was then oxidized in air to obtain a thin Al₂O₃ film, which promotes the nucleation of ALD Al₂O₃ for complete coverage of the MoS₂. Subsequently, 5 nm Al₂O₃ was deposited by ALD process at 200 °C with trimethylaluminum (TMA) and H2O as the Al and O precursors. The growth rate of Al2O3 is 1.05 Å per cycle, and then patterned by EBL and etched by the wet-etching method using CD26 solution (alkaline developer). Finally, the source contact was patterned by EBL, and a bilayer metal stack of 20 nm/20 nm Pd/Au was deposited by electron-beam deposition and lift-off to complete fabrication of the MoS₂ SGT.

Detailed monolayer MoS₂ film deposition procedure

Monolayer MoS₂ was purchased from SixCarbon Technology, Shenzhen. The growth of monolayer MoS₂ was carried out using a typical chemical vapor deposition (CVD) process: MoO₃ powder (99.999% purity) and sulfur powder (99.999% purity) as the sources of molybdenum and sulfur source, respectively. Using a dual-temperature zone tube furnace with a tube diameter of 80 mm, in which the MoO₃ temperature is raised to 650 °C, the sulfur temperature is raised to 180 °C, and using argon gas as the growth carrier gas, a continuous monolayer of MoS₂ on a silicon oxide substrate was achieved within 10 min sulfuration time at atmospheric pressure.

Transfer of monolayer MoS₂

To fabricate the MoS₂ SGT, the as-grown monolayer MoS₂ film was transferred from the silicon oxide growth substrate to the HfO₂/Mo/SiO₂/Si substrate using a PMMA (polymethyl-methacrylate) assisted wet transfer process. Firstly, PMMA photoresist was spun onto the growth substrate at 4000 RPM for 60 s and allowed to sit overnight to ensure good PMMA/MoS₂ adhesion. Second, the edges of the spin-coated film were then scratched using a razor blade and the substrate was immersed in deionized water at room temperature. The sample was then moved from the deionized water to obtain a monolayer of MoS₂ with PMMA. Third, the monolayer MoS₂ with PMMA was transferred to the target HfO₂/Mo/SiO₂/Si substrate. Finally, the PMMA photoresists were washed out in acetone and isopropanol successively.

MoS₂ film characterization

Atomic force microscope (Bruker Multimode 8) is carried out for determining the thickness and roughness of a 0.8-nm monolayer MoS₂ film. The measurement is performed in the “ScanAsyst in Air” mode with a scanning frequency of 0.7 Hz and the accuracy is about 512 lines/sample (scanning region is divided into 512 lines and 512 points are picked up in one line).

Device characterization

The cross-section transmission electron microscope (TEM) sample is fabricated by using an FEI Scios 2 dual-beam focused ion beam (FIB) system. A platinum layer is in situ deposited to protect the target region, and the surrounding area is then etched with a 30-kV acceleration voltage and a 7-nA ion beam to form the lamella. The lamella sample is transferred to a TEM grid in the FIB chamber. The TEM images are acquired by using a high-resolution spherical aberration correction transmission electron microscope (JEM ARM300F) with energy-dispersive X-ray spectroscopy (EDX) mappings. DC electrical characterization was carried out under a vacuum of about 1.3 × 10⁻³mbar in the Lake Shore vacuum low-temperature probe station and using a Keithley 4200 A Parameter Analyzer. The AC performance of our devices was analyzed in terms of S-parameters, from which the current gain (h₂₁) and power gain (G_max) were calculated. f_T was defined as the frequency at which h₂₁ reached unity (0 dB), while f_MAX was defined as the frequency at which G_max reached 0 dB. A probe station (Cascade Summit 1100), semiconductor analyzer (Agilent B1500), ground-signal-ground (GSG) probes, coaxial cables and vector network analyzer (Agilent N5247B) were used to measure the performance of the MoS₂ SGT. First, the GSG probes and coaxial RF cables were calibrated using the off-wafer short-open-load-through (SOLT) standard procedure. The semiconductor analyzer was used to provide DC bias, including V_gs and V_ds for MoS₂ SGT. The gate and drain were defined as ports “1” and port “2”, respectively, and then two-port S-parameters (S₁₁, S₁₂, S₂₁, S₂₂) were measured using the VNA.

Author contributions

Ming L., L.L., A.N., G.Y., and Menggan L. conceived the research and designed the experiments. Menggan L. fabrication the device and carried out the performance measurement. Menggan L., J.N., R.Z., K.C., W.L., F.L., and Z.W. helped with the data analysis. Menggan L. and G.Y. co-wrote the paper. C.J., D.G., and N.L. discussed the results and gave valuable suggestions. All authors commented and discussed the manuscript.

Peer review

Peer review information

Nature Communications thanks the anonymous reviewers for their contribution to the peer review of this work. A peer review file is available.

Data availability

The Source data underlying the figures of this study are available with the paper. All raw data generated during the current study are available from the corresponding authors upon request. Source data are provided with this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-025-67347-7.