Enhancing uniformity in HARC etching via edge bias voltage and structural impedance variations in a rectangular voltage waveform

Abstract

In the semiconductor industry, plasma etching has become a key process for fabricating precise and reliable patterns with high aspect ratios capacitors (HARC), allowing for complex device architectures. During continuous etching operations, the focus ring gradually erodes as a crucial component for maintaining plasma uniformity, particularly at the wafer edge. This degradation results in plasma instability and sheath distortion at the edge, leading to non-uniform etch profiles, tilting, and reduced productivity. This study investigates the effect of applying a separated DC edge bias to achieve more uniform plasma conditions and highly directional ion incidence by controlling the plasma sheath potential. The implementation of localized DC voltages at the edge enhanced etching uniformity and mitigated tilting issues, thereby showing the formation of well-defined and vertical trench. However, high DC voltages exceeding 280 V generated harmful current flow from the edge to the wafer center, which triggered plasma instability and impaired precise sheath control. This electrical interference and etching non-uniformity were alleviated by modifying the impedance ratio of the focus ring to the wafer chuck. As a result, the proposed approach is expected to improve etching efficiency and overall yield in fabrication of next-generation memory devices.

Supplementary Information

The online version contains supplementary material available at 10.1038/s41598-026-36323-6.

Introduction

With the continuous shrink of memory cells, plasma dry etching is becoming an important key process to fabricate high aspect ratio capacitors (HARC) in semiconductor fabrication process^1–4. This formation of structures with a high aspect ratio in a limited area may cause various etching defects such as bending and bowing of sidewalls, which directly leads to the degradation of devices as well as the reduction of yield^5,6. Recently, the asymmetric distortion of the pillars mainly occurs due to the tilting phenomenon in the edge of an electrostatic chuck (ESC)⁷. To resolve this problem and, simultaneously, achieve high yield, it is essential to build a high directional plasma environment that has ion flux with strong ion energy enough to reach the bottom surface and avoid the loss of ion flux by broad angular distribution⁸. Fine tuning the potential gradient within the inner sheath enables the uniform ion incident angle and planarity over the entire wafer surface^9,10. This property could be adjusted by controlling the gas composition, operating pressures, or temperatures of the process; however, power plays a crucial role in maximizing ion energy by enhancing the sheath potential at peripheral regions of the plasma^11,12.

Recently, the usage of tailored bias waveform for low frequency (LF) has been introduced as an effective strategy to modulate the characteristics of ion energy and angular distribution. By shaping the applied bias or source waveform, the characteristics of plasma sheath can be modified, thereby enabling more precise control over the plasma-surface interaction in the capacitively coupled plasma (CCP) discharge^13–15. Computational and experimental analyses have demonstrated that the application of a rectangular bias waveform induced significant variations in plasma sheath due to the abrupt transitions between on and off states^16,17. As this sharp bias transition influences the sheath expansion and collapse behavior, the ion energy distribution can be efficiently tuned to produce narrow ion energy.

In addition, as the most conventional method, a focus ring has also been developed to be optimized to adjust the plasma sheath characteristics at the edge. The ring is a structure installed around the wafer to maintain the etch and deposition uniformity and equipment protection. Recently, this geometry aimed to minimize the temporal variation in ion incident angles over time because the ring is also damaged by ion sputtering or chemical reaction. The proper rings could respond to the time-varying characteristics of sheath thickness during the RF cycle. Specifically, by tailoring the ring’s height and the gap to find an appropriate central point matched to the plasma, it was feasible to obtain uniform etch profile at the edge^18,19. Moreover, unlike the facility improvement, the materials of those rings could be modified to have better erosion resistance in etching, thereby extending their lifetime²⁰. Common rings are not only made of silicon-based materials like the silicon (Si) wafer but also have (100)-oriented structure. Some improvements can be accomplished by changing the lattice planes such as (110) or (111), which have higher resistance owing to dense atom density. Meanwhile, it has been also accepted as another solution to replace Si with silicon carbide based polycrystalline materials²¹. Its remarkable endurance to electrical and thermal stress greatly enhances the durability of focus rings even during a high-power plasma process. However, as memory devices continue to scale down, the etching process gradually requires much higher power usage, making it difficult to retain sheath potential through the focus ring alone²². Because advanced etching techniques are necessary as a trend in the development of the next generation devices, other studies should be suggested beyond the design of focus rings.

In this work, we reported the effect of a separated DC rectangular waveform bias voltage at the edge on the fabrication of high aspect ratio trenches. The formation of intact trenches at the edge could be realized by applying the DC voltage to the electrode of the edge side owing to the advantages of rectangular waveform and its independent control. It indicated that the DC rectangular bias at the edge not only enhances the directivity of the ion flux but also contributes to the mitigation of tilting and asymmetric etching problem through an increase in sheath potential. However, despite these benefits, the additional installation of electrode at the edge near the electrode of the center led to an electric interference when engaging excessive voltages at the edge, thereby making the plasma unstable and difficult to control plasma properties and, especially, plasma sheath. This phenomenon was observed over a voltage of 280 V via the measurement of current passing the plasma from DC controllers at the edge and wafer. To prevent this electrical interference in the plasma, the impedance ratio of the focus ring to wafer chuck was modified by changing the materials of the inner components in the chamber. As a result, at an impedance of 1.31, a low deformation ratio of critical dimension (CD) at the edge was obtained even at a high voltage of 300 V. Finally, this technique is anticipated to enhance the efficiency of the etching process at the edge site and ensure high pattern planarity as well as yield rates during the fabrication of high aspect ratio structures.

Methods

Experimental detail

A capacitive coupled plasma (CCP) etching system (Vigus 7, Tokyo Electron Ltd.) was used for etching silicon dioxide (SiO₂) 300 mm wafer, as shown in Fig. 1a. A voltage of 7 kW with a high frequency (HF) of 40.0 MHz was applied to source and electrodes to generate plasma. The separated two electrodes were installed at the bottom of the wafer and edge sides to effectively modulate the ion energy. A rectangular waveform was used with a LF of 400 kHz via DC bias controllers. For SiO₂ etching process, gas mixtures of C₄F₆, C₄F₈, O₂, and NF₃ were injected at an operating pressure of 15 mTorr. The double DC voltages for the wafer and edge zones were applied from 4500 V to 6500 V and 0 V to 600 V, respectively. All SiO₂ wafer etching processes were performed at a temperature of 80 ℃. The etch profiles depending on different DC voltages were obtained using field emission scanning electron microscopy (FE-SEM) measurements (Hitachi SU9000). All high aspect ratio trenches were fabricated with optical emission spectroscopy (OES)-based end point detection process. Tilting evaluation and hole size measurement were carried out via FE-SEM (Hitachi CZ5600). The boundaries of the bottom surfaces were defined by analyzing a gray level threshold derived from SEM measurement. The detail etch rate was estimated using thin film thickness measurement system (KLA Aleris 8350) after conducting etching processes for 20s. Impedance measurement of wafer chuck and focus ring was conducted using DC generator controllers. Additionally, for each region, the measurement of the current passing through the plasma was conducted with rectangular wave bias controllers in Fig. 1b.

Fig. 1.

(a) Schematic illustration of capacitive coupled plasma (CCP) system with dual DC bias electrodes, (b) Electrical circuits for current measurements at the edge and wafer via DC generator controllers.

Computational detail

In this study, the Hybrid Plasma Equipment Model (HPEM) plasma simulation was performed to investigate plasma behavior and evaluate spatially resolved plasma sheath potential²³. A power of 1200 W with a HF of 40 MHz was applied to the CCP reactor. A voltage of 500 V with a frequency of 400 kHz was set to DC electrodes for the wafer center and the edge. For the working gas, only argon (Ar) plasma reaction was considered with a total of 5 reaction processes (Supplementary Table 1), not involving other gases that were used in the experiment. It was because we mainly focused on the relative change of the sheath characteristics induced by the impedance variation of the focus ring, although the discharge physics and chemistry can vary significantly depending on the gas mixture. Based on the previous other research, the influence of focus ring geometry on plasma sheath could be estimated via electrostatic and geometrical studies rather than dependent on the specific plasma chemistry²⁴. Therefore, the simulation under Ar plasma conditions is still valid as physically meaningful and representative method for investigating the sheath characteristics. The Ar plasma simulation was proceeded with a flow rate of 300 sccm and an operating pressure of 10 mTorr. The materials of focus ring in this simulation were changed to silicon and quartz to figure out the influence of impedance ratio and the edge bias on local plasma behavior. Si was set with a relative permittivity of 11.8 and electrical conductivity of 0.1 S/m, while quartz had a relative permittivity of 4.7 and electrical conductivity of 1 × 10^{− 6} S/m, respectively.

Results and discussion

In etching equipment, the focus ring has been widely utilized to keep even plasma conditions and concentrate plasma onto a wafer. However, it can easily be etched and eroded because the ring is also exposed to the strong plasma environment. This expendability eventually causes the critical deformation of plasma sheath profile over HF operating times, as presented by Fig. 2a. This temporal variation leads to the difficulty of controlling plasma properties, resulting in the occurrence of various defects and lower yield rates. As a result, the formation of tilted trenches at the edge of the wafer was confirmed from the top view FE-SEM images (Supplementary Fig. S1). Therefore, it is essential to implement either the development of a focus ring with extended durability or the advanced technique for precise plasma control.

Fig. 2.

Schematic illustration for (a) the variation of plasma sheath by erosion of focus ring over time and (b) plasma sheath compensation by applying edge bias voltages. (c) Conventional RF Sinusoidal waveform and (d) Rectangular bias waveform. (e) Schematic illustration of etched trenches with different ion incident angles. The blue and red lines presented CD1_Inside and CD2_Outside, respectively. Inclination was defined as the value obtained by subtracting CD2_Outside from CD1_Inside. (f) The temporal variation of measured Inclination with and without the DC edge bias during the operating time.

To overcome the limitation and improve efficiency of this etching process, independent DC bias voltage was applied at the edge side, as shown in Fig. 2b. Supplying independent DC bias to individually structured electrodes is expected to modulate the sheath potential near the edge. Unlike low frequency sinusoidal waveform typically used to control ion energy, we employed a tailored voltage waveform to both the wafer and edge electrodes, thereby inducing a narrow ion energy distribution^17,25. Sinusoidal waveform in Fig. 2c has been mostly utilized in conventional CCP systems for generation of plasma. This shape inherently brings out bias potential non-uniformity between peak and valley, making in the broad ion energy and incident angle reaching to the wafer^26–28. This becomes especially pronounced in the edge region. In contrast, a rectangular waveform, as one of tailored waveforms, can ensure the constant voltage difference between wafer potential and plasma potential by means of rapidly periodic on/off cycling pulses, as shown in Fig. 2d. It is worth noting that its operating principle effectively compensates for asymmetric plasma sheath from center to edge and, simultaneously, produces a way narrower ion energy as well as angular distribution, which in turn promote both yield and reproducibility. Moreover, dual DC bias electrodes with the rectangular waveform would contribute to the significant delay for the erosion of focus rings as well as the precise etching for the fabrication of vertical pillars (Supplementary Fig. S2).

Generally, the plasma sheath is not planar at the boundary of the wafer or focus ring, causing ions to reach substrate with obliquely angle rather than perpendicularly. Figure 2e shows the schematic illustration for the tilting phenomenon to provide a comprehensive understanding of the relationship between plasma sheath and etch profile. It can be confirmed that the tilting is strongly associated with non-uniform ion trajectories and sheath distortion according to plasma sheath profile^29,30. There are three types of etching profiles depending on the angle of incident. In this work, to estimate the intensity of tilting issues, “Inclination” is defined as the difference between CD1_Inside and CD2_Outside, where CD1_Inside and CD2_Outside refer to the CD measured toward the inside of the wafer and the outside of the wafer, respectively; thus, Inclination = CD1_Inside - CD2_Outside. If the Inclination was 0 nm, the vertical holes are valid, and the etching process was appropriately achieved. However, when the Inclination was less than − 0.5 nm, the pillar began excessively tilted toward the wafer center. As shown in Fig. 2f, the Inclination at the edge region gradually decreased to −0.5 nm over HF process time without the DC edge voltage. It indicated that the deterioration of the focus ring distorted the local plasma sheath, thereby altering the etching profile. Meanwhile, the application of the independent DC bias allowed the ring to remain operational as the extreme tilting phenomenon of the etched holes was not observed in the measured Inclination. Furthermore, in order to figure out the quality of the etched holes totally, the relationship between Inclination and deformation was investigated, where deformation is defined as the ratio of the minor axis to the major axis in the circular (Supplementary Fig. S3). A deformation ratio closer to 100% means a more circular hole shape. A progressive reduction in the deformation value implied a transition from the circular to an elliptical shape. In hence, the result indicated that by modulating the ion incident angle enough to maintain proper tilting, the circular shape could be also preserved with minimal deformation. It is worth noting that ensuring an Inclination of 0 nm is critical to prevent surface irregularities and trenches misalignment, thereby reducing defects and improving device yield. Furthermore, this emphasizes the importance of controlling the plasma sheath potential, particularly at the edge of the wafer.

To examine the effect of separated DC bias voltage, an evaluation of Inclination was carried out near the edge side from 141 mm to 147 mm and close to the center from 115 mm to 141 mm depending on the different voltages (0 V, 50 V, 100 V, 200 V, and 300 V), as shown in Fig. 3a. With increasing DC voltages at the edge, the tilting issue was significantly improved enough to exhibit vertically cylindrical profiles. In conditions where the DC voltage was not applied, the etching profiles had tilting phenomenon by weak sheath potential. It indicated that applying the bias effectively compensated for the sheath potential that was deformed by the eroded focus ring, particularly beyond 140 mm. However, the voltage over 300 V was possible to create too strong electric fields to affect the sheath at the center as well as trigger another tilting problem. An excessively positive Inclination also led to such tilting in the etch profile. Finally, this result demonstrated that the implementation of independent voltages could effectively modulate plasma sheath and ion directivity, resulting in high uniformity. Figure 3b presents the top view FE-SEM images of all trenches at the edge side according to the different DC bias voltages. Yellow dot lines in the SEM images indicated bottom surfaces inside the hole as indicative of tilting phenomenon, helping confirm direct visual tilting behaviors and etch profiles. It implied that the closer the bottom circles were to the center, the less tilting occurred. The SEM image of trench etched at 100 V exhibited the most ideal circular shapes while other samples had several ellipses or slightly deformed circular. Additionally, Fig. 3c displays the cross-sectional FE-SEM images of trenches at the edge region with and without DC edge bias. Unlike the sample with uniformly etched holes, the presence of partially etched holes implied that the diminished plasma potential in that region resulted in weak and broad ion energy, which could not strike a deep bottom³¹. In other words, DC bias is considered as an appropriate method to compensate for plasma sheath potential and maximize etch quality. To estimate the etch uniformity with and without the application of DC bias at the edge, top view FE-SEM images of each region were compared in Fig. 3d. In the absence of additional edge bias, uneven hole geometries and irregular trench depths were confirmed in good accordance with the micro-structure in the cross-sectional FE-SEM images. In contrast, the introduction of edge bias effectively suppressed the incomplete etching and enabled uniform patterns across the entire wafer.

Fig. 3.

(a) The measured Inclination over the center to the edge depending on the different edge DC bias voltages (0 V, 50 V, 100 V, 200 V, and 300 V) at an operating time of 80 h. (b) Top view FE-SEM images of as fabricated trenches depending on DC edge bias voltage. The yellow dot line presents the bottom of the hole. Inset figures depicted the top view. (c) Cross-sectional FE-SEM images and (d) top view FE-SEM images with and without an edge bias of 120 V. Scale bar presents 0.5 μm.

As such, controlling plasma sheath at the edge is important to mitigate tilting problems. However, since the focus ring underwent inevitable erosion and wear during HF operating time, it was still necessary to extend and adapt the operational voltage range to maintain constant etching condition. The requested DC voltages are to increase to control the tilting. Therefore, further investigation for dual DC bias should be proceeded. Despite the above technical advantages of applying DC edge voltages, significant transitions in current and potential from the edge to the wafer center were observed under high voltage conditions. In order to detect and analyze these electrical changes during the etch process, actual output voltages were measured via the DC bias controllers in Fig. 4a. The actual output voltage is a real voltage used for plasma processing with considering various impedances of surrounding instruments and plasma. Monitoring it with set voltages can spot the changes of the plasma or equipment issues. A discrepancy of about 50 V began to appear after approximately 350 h. This voltage difference was probably due to the occurrence of electrical interaction between the center and the edge. Figure 4b presents the measured current passing through the plasma from DC controllers at the edge and wafer. Under the same voltage condition, the plasma sheath potential that is generated at the wafer would diminish by a reduction in output voltage over HF operating time while the sustained high voltages at the edge led to a substantial edge current. As a result, a remarkable increase in the current near the wafer was observed after 380 h because of the undesirable current flow toward the wafer. This current affected the output voltage at the edge, showing that the output voltage was saturated at the same time. Such electrical interference would eventually break the uniformity of the bias potential at each zone and then trigger irregular ion directionality and energy distribution. By applying a DC bias voltage from 0 V to 600 V, the etch rate across the wafer was evaluated to investigate the effect of this electrical interaction on etch profile, as shown in Fig. 4c. The higher edge voltages led to a remarkable increase in etch rate at the middle of the wafer from 120 mm to 138 mm while the etch rate at the edge gradually dropped. This trend indicated that too high voltages caused imbalances in plasma potential by the uncontrollable sheath gradient. Furthermore, while the measured Inclination distribution at the edge region remained nearly constant between 0.4 nm and − 0.2 nm, the deformation ratio started to rapidly decrease at an operating time of 400 h, suggesting that nonuniform sheath potential locally alter ion trajectories (Supplementary Fig. 4). It implied that the variations in the sheath led to irregular and uneven etching of the hole profiles. Figure 4d displays the measured current at the wafer side and the edge side as a function of DC edge voltages. As the edge voltage increased, the current measured at the center exhibited a sudden rise of approximately 5.2% beyond 450 V, whereas only an increase of nearly 2% was observed prior to this threshold. This behavior was attributed to the intensified electrical interaction between two regions at high voltages.

Fig. 4.

(a) The measured voltage and set voltage during HF operating time. (b) The measured current at the edge and the wafer side at an edge voltage of 280 V during HF operating time. (c) Etch rates across the wafer depending on the different DC edge voltages. (d) The measured current as a function of DC edge voltages at the edge and the wafer side.

Understanding an external circuit for peripheral parts of a focus ring and wafer chuck helps to figure out and solve this electrical interference in the plasma^32–34. Figure 5a shows simple schematics for the structural parts of CCP plasma system depending on suggested models and corresponding equivalent circuit diagrams. Basically, the ESC was installed under the wafer chuck and focus ring to supply voltages. The wafer chuck, composed of ceramic materials, was surrounded by the focus ring and cover ring, which was made of silicon to reduce plasma discontinuity. According to these components, each equivalent circuit was expressed with several capacitances of interfaces and ceramics, and ground at the bottom shield ring. In addition, each model consists of dominant capacitances corresponding to the quartz (C_iso) and ceramic components (C_ceramic) in the circuit. The isolation capacitances in the red box determines the degree of electrical coupling between the focus ring and the electrodes, thereby influencing the impedance ratio and sheath characteristics. Therefore, one approach is to modify the impedance ratio of the wafer chuck and the edge side by changing the capacitance of peripheral parts such as isolators. Impedance ratio can be calculated by Eq. (1).

Fig. 5.

(a) Schematic of the peripheral parts (wafer chuck, focus ring, cover ring, and isolators) and corresponding equivalent circuits diagram. The three images on the right present three suggested models in this work. (b) Etch rates across the wafer at a DC edge voltage of 280 V according to three different models. (c) Deformation ratio of etched holes depending on three models. The deformation ratio data sets in Supplementary Fig. 3 and Fig. 5 were acquired under distinct DC conditions; normal bias compensation in Supplementary Fig. 2 and uncorrected operation in Fig. 5.

1

Three models were designed with an impedance ratio of 1.11, 1.17, and 1.31, respectively. Note that Model 1 was not used as a reference but rather one of the evaluated models. Model 2 and 3 exhibited a higher impedance ratio than Model 1 as the surrounding components were replaced with Si to strengthen the conductivity toward focus ring. Figure 5b shows the etch rates across the wafer under an edge voltage of 300 V according to the suggested three models to investigate the correlation of impedance ratio with etching properties. The conditions in Fig. 5c differ from those previously validated in Fig. 4. In the case of Fig. 5c, the experiment was performed after the chamber was cleaned to remove any contamination that could occur when the components were changed. Furthermore, since the etch rate typically varies depending on the environmental conditions at the operating time, it is essential to focus on the gradient of etch rate variation under comparable conditions. Especially, the etch rate gradient in the outer beyond 140 nm (edge side) is reduced compared with Fig. 4c, indicating that the uniform etch profile was obtained even at a high voltage. Deformation ratio was also greatly improved with an increment in impedance ratio in Fig. 5c. As the impedance ratio of the focus ring gradually increased to 1.31, the hole shape became more circular, reaching a high deformation ratio of 86%. Consequently, variations in dielectric configuration can significantly impact the behavior of plasma sheath across the entire wafer. Additionally, the HPEM plasma simulations demonstrated that modifying the impedance ratio significantly affected the plasma sheath potential when the material of the focus ring was changed from quartz to Si, as shown in Fig. 6. Plasma density and plasma potential distribution for two different focus rings were investigated under an edge voltage of −500V applied to the electrode of the edge. In the silicon case, the focus ring became partially conductive, allowing transmission of potentials through the surface. Given that the sheath boundary is defined as the position where the plasm potential is zero, this electrical continuity with the electrode led to a deeper sheath potential and enhanced plasma density near the edge. In contrast, when the focus ring was made of quartz, its dielectric nature induced electrical isolation between the plasma and the electrodes, resulting in thinner sheath and more uniform plasma density than the case of silicon. The sheath thickness (t) near the focus ring was expanded in the case of the focus ring with Si when comparing it to the focus with quartz. This modification can be explained by the following Eq. (2)³⁵.

Fig. 6.

Plasma density and plasma potential distribution of two models with (a, c) Si-based focus ring and (b, d) quartz-based focus ring under applying an edge voltage of −500 V.

2

According to the equation, increasing the applied V_DC results in the formation of thicker plasma sheath at the edge side. The enhanced sheath thickness allows the plasma boundary between the wafer and the edge to shift outward. Furthermore, the relatively high impedance ratio of the focus ring over the wafer chuck strengthens the electric field in the vertical direction, resulting in improved tilting problems as well as the electrical inference. Therefore, compensation of the plasma sheath potential could be simultaneously achieved through applying DC bias and changing the impedance ratio of the focus ring.

Conclusion

This work successfully demonstrated that applying an independent DC edge voltage was an effective method for enhancing plasma uniformity and accomplishing more directional ion trajectories during plasma etching. By modulating the plasma sheath potential at the wafer edge, the approach mitigated tilting problem, which generally occurred at the edge because of the plasma distortion and instability. The highly vertical trenches fabricated with DC voltages were confirmed through top view FE-SEM images unlike the etching profile without additional voltages. However, excessive DC voltage above 280 V triggered electrical interference and broke plasma sheath stability, resulting in the etching non-uniformity. These adverse effects were resolved by optimizing the impedance ratio of the focus ring to the wafer chuck. At an impedance of 1.31, a low CD deformation ratio was confirmed even under a high DC voltage of 300 V. 2D plasma simulation further revealed that using a Si-based focus ring generated a thicker plasma sheath compared to quartz, leading to a stronger electrical field and more stable sheath control. Finally, this method offers a promising pathway to reduce tilting and improve operating efficiency in the plasma etching process.

Supplementary Information

Below is the link to the electronic supplementary material.

Author contributions

C. Park and J. Cho contributed equally to this work and conceived the project. J. Um performed plasma simulation. All authors discussed the results and reviewed the manuscript.

Funding

This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (2022R1A3B1078163). This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (2022R1A4A1031182). This work was supported by the Technology Innovation Program (Public-private joint investment semiconductor R&D program(K-CHIPS) to foster high-quality human resources)(RS-2023-00235484, “Development of High Quality MX2 Materials and Processes through In-situ Defect Analysis”) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea)(1415187770).

Data availability

The datasets generated and/or analyzed in this study are available from the corresponding author on reasonable request.

Declarations

Competing interests

The authors declare no competing interests.