Nanogate ferroelectric transistors with ultralow operation voltage of 0.6 V

Abstract

Ferroelectric field-effect transistors (FeFETs), as an electric field–driven nonvolatile memory, offer extremely low power consumption and high speed. Despite efforts, FeFETs have not been successfully scaled down to sub–5-nanometer-node technology, with their operational voltage exceeding 1.5 V, making them unable to match monolithic logic cores. Our study used metallic single-walled carbon nanotubes as gate electrodes to shrink the gate length of molybdenum disulfide FeFET to 1 nanometer. This nanogate approach leads to an electric field concentration and enhanced ferroelectric–to–metal-oxide semiconductor capacitance coupling, resulting in a reduced operating voltage of 0.6 V, below the conventional ferroelectric coercive voltage. The nanogate molybdenum disulfide FeFETs exhibit superior memory performance, with a substantial current on/off ratio of 2 × 10⁶ and a rapid programming speed of 1.6 nanoseconds. This study demonstrates the immunity of nanogate FeFETs to short-channel effects, highlighting the notable potential of ferroelectric electronics for enabling superior scaling, performance, and energy efficiency in sub–1-nanometer-node chips.

The nanogate enables 0.6-V operation in FeFETs by concentrating the electric field.

INTRODUCTION

Integrated circuits (ICs) have now successfully entered the sub–3-nm-node technology, with state-of-the-art silicon logic transistors featuring a minimal gate length of 15 nm, operating at a low supply voltage of 0.7 V, and with a small delay of 1 ps (1–5). However, as a pivotal part of Von Neumann’s computing architecture, the nonvolatile memory technologies have lagged far behind the logic parts over the past decades (6–13), and the commercial flash memory is restricted by a logic-incompatible large supply voltage of more than 5 V and a large latency of millisecond write speed (11, 12, 14, 15). Ferroelectric field-effect transistors (FeFETs), a promising type of nonvolatile memory, feature a nondestructive readout, ultrafast nanosecond write speed, low-power consumption driven by electric field, and a three-terminal gate-control configuration benefiting from easy access to memory blocks (12, 16–19). To date, FeFETs have been successfully integrated with a 22-nm planar fully depleted silicon-on-insulator complementary metal-oxide semiconductor (CMOS) platform, demonstrating their compatibility with advanced semiconductor processes (17). However, all reported FeFETs have large operating voltages limited to larger than 1.5 V (12, 17, 19, 20–22). While this value is lower than the supply voltage of flash memory, it is still far higher than that of state-of-the-art logic ICs (0.7 V) as shown in Fig. 1A (23). Thus, extra charge pump circuits are necessarily required lying between the logic cores and FeFET units, which sacrifices the integration density and introduces large latency in massive data transfer (12) (Fig. 1B). This will also hinder the application of ferroelectric technology in energy-efficient in-memory computing and artificial neural networks. In the future sub–1-nm-node technology, a formidable challenge for ferroelectric electronics is how to lower the operating voltage of FeFETs to match the power supply level of logic ICs, specifically 0.7 V (Fig. 1C).

Fig. 1. Voltage mismatch between logic core and memory.

(A) The operating voltage for charge trap (CT) flash (5 V) (12, 22) or FeFETs (1.5 V) (12, 17, 19–21) is greater than the supply voltage of logic core (0.7 V) (23), thus requiring the voltage transition with charge pump circuits in (B). This burdens the power and latency of artificial intelligence chips. (C) The key solution for the future is to reduce the memory voltage to below 0.7 V to facilitate data transfer.

Efforts are made to find ways to save the voltage of ferroelectric memories. Because the transition between logic states “0” and “1” is accomplished by electric field–driven flipping of the ferroelectric polarization, any method that enhances the electric field within the ferroelectric layer is advantageous in lowering the operating voltage of FeFETs. Here, we drew inspiration from the design of vacuum electronic devices (24–29), in which nanotips such as carbon nanotubes (CNTs) and nanowires are widely used as field-emission cathodes to focus the electric field. Therefore, in this work, the nanotip field enhancement mechanism is introduced in our FeFETs, and a metallic single-walled carbon nanotube (m-SWCNT) is used as the gate electrode to enhance the electric field around the nanogate and to reduce the operating voltage.

Our FeFETs feature a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure, with a 1-nm-diameter m-SWCNT as the gate, two-dimensional (2D) ferroelectric CuInP₂S₆ (CIPS) as the ferroelectric layer, multilayer graphene (Gr) as the floating gate, hexagonal boron nitride (h-BN) as the dielectric layer, and molybdenum disulfide (MoS₂) as the semiconductor channel. Our fabricated nanogate MoS₂ FeFETs are measured to operate at an ultralow voltage of 0.6 V, the lowest voltage of any FET-configuration memories to date, reducing the voltage of a FeFET below that of state-of-the-art logic transistors (0.7 V). This ultralow gate operating voltage breaks the intrinsic ferroelectric coercive voltage limit of the CIPS layer, due to the SWCNT-gate electric field enhancement effect. Our nanogate FeFETs exhibit desirable memory characteristics, including a good current on/off ratio as high as 2 × 10⁶ and a fast-programming speed of 1.6 ns with a 3-V voltage. This discovery reveals that nanogate FeFETs can thrive at the future angstrom-node technology, characterized by logic-compatible ultrasmall voltage, ultrafast programming speed, and immunity to gate-scaling limits (short-channel effects).

RESULTS

Theoretical simulations of nanogate and normal-gate MoS₂ FeFETs

The Technology Computer-Aided Design (TCAD) simulated device is composed of a gate electrode with 1-nm length, 14-nm-thick CIPS as the ferroelectric layer, 2-nm-thick Gr as the floating gate, 5-nm-thick BN as the dielectric layer, and 2D MoS₂ as the semiconductor channel (Fig. 2A). For comparative analysis, a device with a similar structure but a normal gate is also simulated (Fig. 2B). The basic operating principle of a FeFET is to store information about the polarization direction of the ferroelectric layer. Applying adequate voltage to the gate allows the reversal of the CIPS polarization direction and enables the accumulation (in a low-V_T state) or depletion (in a high-V_T state) of the channel. The TCAD-simulated electric field contour plot is shown in Fig. 2 (A and B). When the 1-nm gate electrode is biased at −0.6 V, a strong and highly localized electric field is generated in the CIPS layer around the nanogate (Fig. 2A), with a maximum electric field reaching 2.7 × 10⁶ V/cm (Fig. 2C, red), which is above the critical coercive field of the CIPS layer (5 × 10⁵ V/cm; fig. S1) and thus leads to the ferroelectric polarization flip in the CIPS layers. In comparison, for the normal-gate FeFET, the −0.6 V gate voltage only brings a weak and uniform electric field (Fig. 2B), with an electric field of ~1 × 10⁵ V/cm (Fig. 2C, blue), which is much lower than the coercive field of CIPS.

Fig. 2. Theoretical simulations of nanogate and normal-gate MoS₂ FeFETs.

(A) Electric field contour plot for a 1-nm gate FeFETs at a gate bias of −0.6 V shows a strong and highly localized electric field in the CIPS layer around the nanogate. (B) Electric field contour plot for a normal-gate FeFETs at a gate bias of −0.6 V shows a weak and uniform electric field in the CIPS layer. (C) Electric fields extracted from the CIPS along the x axis (left) and the y axis (right) of the nanogate (red) and normal-gate (blue) FeFETs show two different electric field distributions. (D and G) Electron density of the MoS₂ channel for the 1-nm gate (D) and normal-gate (G) FeFETs in the on and off states. The electron density in the MoS₂ channel of nanogate FeFET can be depleted from high concentration to low concentration by applying a voltage pulse of −0.6 V to the nanogate, while the electron density of the normal-gate FeFET shows a negligible change. S, source; D, drain. (E and H) Energy band diagrams for the 1-nm gate (E) and normal-gate (H) FeFETs in the on and off states. For the nanogate FeFET, a large energy barrier of 0.4 eV appears in the channel, and the device turns off by applying a voltage pulse of −0.6 V. For the normal-gate FeFET, the energy band profile hardly changes after applying a voltage pulse of −0.6 V. (F and I) The simulated drain current versus gate-to-source voltage (I_D-V_GS) curves for the 1-nm gate (F) and normal-gate (I) FeFETs. a.u., arbitrary units. The transfer curve of the nanogate FeFET exhibits a typical anticlockwise hysteresis loop with a large MW, while the normal-gate FeFET exhibits no MW, with gate voltage sweeping to ±0.6 V.

The electron density and the energy band profile in the MoS₂ channel are also TCAD simulated, corresponding to the on state and off state. In the on state of the nanogate FeFET, the whole MoS₂ channel is at a high electron density of 6 × 10¹¹ cm⁻² (Fig. 2D, top), with no barrier existing in the channel (red dotted line in Fig. 2E). After applying a voltage pulse of −0.6 V to the 1-nm gate electrode, the MoS₂ channel is depleted with the electron density decreasing to a low-density level of 1 × 10⁴ cm⁻² (Fig. 2D, bottom), a large energy barrier of 0.4 eV appears in the channel (blue line in Fig. 2E), and the device turns off. However, for the normal FeFET as a comparison, the electron density and the energy band profile hardly change after applying a voltage pulse of −0.6 V (Fig. 2, G and H). The simulated transfer curve of the nanogate FeFET, sweeping back and forth to ±0.6 V, exhibits a typical anticlockwise hysteresis loop with a large memory window (MW) (Fig. 2F); in contrast, the normal-gate FeFET exhibits no MW when sweeping the gate voltage to ±0.6 V (Fig. 2I). This simulation result indicates that the nanogate electric field enhancement mechanism effectively improves the energy efficiency and reduces the operating voltage of the nanogate FeFET lower than ferroelectric coercive voltage, even to an ultralow value of 0.6 V.

Ultralow operating voltage and electric field enhancement effect of nanogate MoS₂ FeFETs

Figure 3A presents the schematic diagram of a 1-nm gate length MoS₂ FeFET device, and the fabricated device is characterized by a cross-sectional transmission electron microscope (TEM) image (Fig. 3B) and false-colored scanning electron microscopy (SEM) image (Fig. 3C and figs. S3 and S4), confirming a vertically stacked Van der Waals MFMIS heterostructure, where m-SWCNT acts as the nanogate, CIPS as a ferroelectric layer, Gr as a floating gate, h-BN as a dielectric layer, and MoS₂ as a semiconductor channel.

Fig. 3. Device structure and electrical characterization of nanogate MoS₂ FeFET.

(A) Schematic of a nanogate MoS₂ FeFET. G, gate; S, source; D, drain. (B) Cross-sectional TEM image of a representative device. Scale bar, 5 nm. (C) False-colored SEM image of a representative device. Scale bar, 1 μm. (D) The conductance curves of a 1-nm gate length MoS₂ FeFET with 14-nm-thick CIPS at various gate voltage. The transfer curves exhibit typical anticlockwise hysteresis loops with large MWs when the operating voltage reaches ±0.6 V or higher. (E) Current on/off ratio and MW of the device as a function of the operating voltage. (F) Gate scaling schematics of MoS₂ FeFETs showing two electric field enhancement factors: C_Fe to C_MOS coupling enhancement and nanotip-induced electric field enhancement (NEFE). (G) Electric field in CIPS of a FeFET as a function of gate length and CIPS thickness, with the operating voltage fixed at 0.6 V. When reducing the gate length from 50 to 1 nm, the electric field of CIPS is enhanced (from dark brown line to orange line) without considering NEFE. By considering NEFE of the 1-nm SWCNT electrode, a more reasonable electric field (red line) corrected with an enhancement factor of 2.6 can exceed the nominal coercive field with a certain CIPS thickness range (from 6 to 47 nm). (H) Gibbs free energy landscape (left) and electric field (right) in 14-nm-thick CIPS of a FeFET as a function of gate length with gate voltage fixed at 0.6 V. The Gibbs free energy landscape of CIPS shows that the CIPS gradually trends to flip when scaling the gate lengths from 50 to 1 nm without considering NEFE (from dark brown line to orange line). By considering NEFE, the Gibbs free energy landscape evolves into having one energy minimum (red line).

Figure 3D shows the conductance curves of a typical nanogate MoS₂ FeFET using SWCNT as the gate. The drain conductance is acquired by sweeping the gate voltage (V_GS) forward and backward, with a fixed drain-source bias (V_DS) of 0.1 V. Figure 3E extracts the current on/off ratio and MW of our nanogate FeFET at different operating voltages from the conductance-voltage curves in Fig. 3D. When V_GS is swept back and forth to ±0.4 V, the current on/off ratio is 20 (the ratio of other devices in fig. S5F can be as high as 100), and its ferroelectric MW is 0.5 V; when further increasing the operating voltage to ±0.6 V or higher, the transfer characteristic exhibits a distinct counterclockwise MW, indicating that most CIPS ferroelectric polarization domains have flipped, and the nanogate FeFET exhibits a large current on/off ratio of nearly four orders of magnitude and a sizable MW of greater than 0.75 V. Another two nanogate FeFETs operating at the ultralow voltage of 0.6 V are shown in fig. S6. These transfer measurements demonstrate that our nanogate FeFET can operate at an ultralow voltage of 0.6 V.

The electric field in the ferroelectric layer of our nanogate FeFET is effectively enhanced with the scaling of the gate length, according to the simulations in Fig. 2. Further analysis reveals that this enhancement is contributed by the following two underlying factors (Fig. 3, F to H):

1) The capacitance coupling efficiency and voltage dividing ratio are improved. The gate stack of FeFETs can be modeled by a ferroelectric capacitance (C_Fe; here is CIPS dielectric capacitance) in series with metal-oxide semiconductor (MOS) capacitance (C_MOS; here represents the series of h-BN dielectric capacitance and MoS₂ semiconductor capacitance) (fig. S7A) (16, 19). The operating gate voltage V_GS of a FeFET is divided into a MOS voltage drop V_MOS and a ferroelectric voltage drop V_Fe, expressed as $V_{\text{GS}}=V_{\text{Fe}}\times (1+\frac{C_{\text{Fe}}}{C_{\text{MOS}}})$. Scaling the ferroelectric gate length is an effective way to reduce C_Fe/C_MOS and thus to improve the voltage dividing ratio (V_Fe/V_GS), thereby reducing the operating voltage of FeFETs (fig. S7, B and C), and this trend is also consistent with other previous reports on FeFETs (19). Figure 3G calculates the electric field in CIPS of a FeFET as a function of gate length and CIPS thickness, with the operating voltage fixed at 0.6 V. When reducing the gate length from 50 to 1 nm, the electric field of CIPS is effectively enhanced (from dark brown line to orange line in Fig. 3G). However, this first-order flat plate capacitor model is oversimplified to treat the actual ferroelectric capacitance of nanogate, and the calculated electric field around the 1 nm nanogate (orange in Fig. 3G) is underestimated, appearing not to exceed the coercive field value of CIPS (black dotted line in Fig. 3G).

2) The electric field enhancement effect generated around the 1-nm nanogate must be considered, and the actual electric field in CIPS has a further boost. First, we investigate the nanotip electric field enhancement effect through a two-terminal ferroelectric tunnel junction (FTJ) structure. We fabricated a 1-nm nanotip FTJ (CNT/CIPS/graphite) and a normal FTJ (monolayer Gr/CIPS/Graphite) as a comparison (fig. S8). The electrical measurement shows that a typical CNT-nanotip FTJ can be switched from the on state to the off state by applying a smaller operation voltage, which is 2.6-fold lower than that of normal FTJ (fig. S8D). This is consistent with TCAD theoretical calculations (fig. S8, A and B), confirming the electric field enhancement effect of the 1-nm SWCNT electrode. As a result, a more reasonably evaluated electric field (red line in Fig. 3G) in the CIPS layer is corrected with the enhancement factor (e.g., 2.6) of the nanogate, which exceeds the intrinsic coercive field within a certain CIPS thickness range (from 6 to 47 nm). This demonstrates that nanogate can reduce the operation voltage of FeFETs to below 0.6 V, which is consistent with our experimental results and TCAD simulation results.

The gate-scaling–induced electric field enhancement can be thermodynamically characterized using Gibbs free energy formalism. According to Landau-Ginzburg-Devonshire theory, the Gibbs free energy density (U) of a ferroelectric material can be described as

$$U=\mathrm{\alpha }{P}^2+\mathrm{\beta }{P}^4+\mathrm{\gamma }{P}^6-E·P$$

where α, β, and γ are the Landau parameters, which depend only on material, P is the polarization, and E is the electric field (30–32). Two energy minima correspond to two stable spontaneous polarization states, which can be switched by an external electric field. When scaling the gate lengths from 50 to 1 nm, with a gate voltage fixed at 0.6 V, the Gibbs free energy landscape of CIPS (Fig. 3H, left) shows that the CIPS gradually tends to flip, but the Gibbs free energy still maintains two energy minima (yellow lines), which implies that the CIPS does not gain enough energy to overcome the energy barrier. The black dashed line in Fig. 3H represents the free energy landscape of CIPS under a coercive field (500 kV/cm), corresponding to the critical state of polarization flip. By considering the nanogate-induced electric field enhancement, the electric field can be further enhanced to surpass the critical coercive field (Fig. 3H, right), and the Gibbs free energy landscape evolves into having one energy minimum (red line), which proves that the ultralow 0.6-V gate voltage can provide enough energy to overcome the energy barrier of polarization flip. Consequently, our nanogate FeFETs are highly energy efficient to concentrate the electric field and programming energy and only require ultralow voltage to reach the coercive field value of the CIPS layer.

Ultralow operating voltage below the nominal coercive voltage

We systematically investigated the electric field enhancement effect in nanogate FeFETs with varying CIPS thickness, considering conductance, on/off ratio, and MW (Fig. 4, A and B, and fig. S5). The extracted operating voltages of our nanogate FeFETs with different CIPS thicknesses are compared with those of other reported CIPS-based FeFETs (Fig. 4C) (16, 33–38). All of our nanogate FeFETs show an ultralow voltage smaller than the normal operating voltage (the coercive voltage of CIPS); in contrast, other reported FeFETs exhibit much higher voltages, at least twice the coercive voltage. Figure 4D shows the calculated voltage efficiency of our nanogate FeFETs and other reported CIPS-based FeFETs (16, 33–38). The voltage efficiency $\mathrm{\eta }$ is defined as

$$\mathrm{\eta }=\frac{\text{Nominal coercive voltage}}{\text{Gate voltage}}$$

in which the ferroelectric nominal coercive voltage is derived by multiplying the coercive field by the thickness of the ferroelectric layer. Conventionally, the operating voltage applied to the gate must be greater than the coercive voltage to enable the ferroelectric polarization to be flipped. In contrast, our nanogate FeFETs can operate at voltages lower than the nominal coercive voltage of the CIPS layer. As a result, the voltage efficiency of our nanogate FeFETs reaches as high as 125% and is the highest among all reported FeFETs. This benefits from the combination of the above two boosters (Fig. 3F): strong Fe-to-MOS capacitance coupling pushes the voltage efficiency close to 100% in the first stage, and then, the nanogate electric field focusing effect further promotes the voltage efficiency exceeding the 100% limit and even reaching 125%. In comparison, other FeFET devices have voltage efficiencies of less than 53%, resulting in much higher operating voltages and excess energy loss in a normal FeFET.

Fig. 4. Nanogate MoS₂ FeFETs with ultralow operating voltage exceeding the nominal coercive voltage.

(A) Conductance curves of 1-nm MoS₂ FeFETs with CIPS thicknesses of 14, 8, and 6.5 nm show low operating voltages (red) smaller than the CIPS coercive voltages (blue). (B) Current on/off ratio and MW as a function of the CIPS thickness. (C) Comparison of the operating voltage of our 1-nm gate length MoS₂ FeFETs with those of other CIPS-based FeFETs (16, 33–38). All of our nanogate FeFETs show an ultralow operating voltage, smaller than the coercive voltage of CIPS, while the other reported FeFETs exhibit much higher voltages above the coercive voltage. (D) Voltage efficiency of our nanogate FeFETs reaches as high as 125%, breaking the upper limit of a normal FeFET (100%), and is the highest among all reported FeFETs (16, 33–38). Data retention characteristics (E) and endurance characteristics (F) of our 1-nm gate FeFET; the device operates at a low voltage of 0.6 V (20-ns pulse width) and shows good retention and endurance characteristics.

The long-term stability of our nanogate FeFETs (with 14-nm-thick CIPS) operating at 0.6 V is shown in Fig. 4 (E and F). The retention characteristics show an on/off ratio above 1 × 10³ after 10⁴ s (Fig. 4E). The endurance characteristics of this device show negligible degradation in the on/off-state currents, maintaining an on/off ratio above 3 × 10³ after 10⁴ programs per erase cycles (Fig. 4F). When adopting a thicker CIPS of 70 nm, our nanogate FeFETs exhibit excellent nonvolatile memory characteristics: a high current on/off ratio above 2 × 10⁶, a large MW of 2.8 V, and long data retention time and high endurance (fig. S9). The channel current of on and off states shows negligible degradation, and the current on/off ratio remains above 8 × 10⁵ after more than 10⁴ s of retention time. We also investigated the endurance characteristics of the nanogate FeFETs; the channel current of on and off states shows negligible degradation, and the current on/off ratio remains above 4 × 10⁵ after 10⁴ cycles of writing and erasing. In addition, to exclude the possibility that the MW is caused by the interface charge traps in gate stacks, we fabricated and measured MoS₂ FETs with m-SWCNT as the gate, h-BN as the dielectric, and MoS₂ as the channel (fig. S10). The transfer curves show zero hysteresis with subthreshold swing of 70 mV/decades, indicating good electrostatic potential control and negligible charge traps at the van der Waals interfaces because of the absence of surface dangling bonds. The choice of an MFMIS structure with CNT-gate, CIPS, Gr, h-BN, and MoS₂ can effectively reduce the depolarization field and stabilize the polarization charge of CIPS, resulting in better and more stable device performance for nanogate FeFETs (fig. S11).

Ultrafast speeds of nanogate MoS₂ FeFET and benchmark with advanced FeFETs

Our 1-nm nanogate MoS₂ FeFETs can operate at ultrafast speeds of up to 1.6 ns (Fig. 5A and figs. S12 and S13). We measured a typical nanogate FeFET (with 33-nm-thick CIPS) with different pulse widths, ranging from 1 μs to 1.6 ns: (i) The nanogate FeFET can be switched to a high-resistance state by applying a 1-μs-width negative pulse with an amplitude of 1.05 V, which is very close to the dc operating voltage of 1 V (corresponding to 33-nm-thick CIPS; fig. S12, A and B). (ii) Programming successfully by applying a 100-ns-width pulse with an amplitude of 1.2 V. (iii) A total of 10-ns pulse width corresponds to the operating voltage increased to 2.4 V. (iv) The operating voltage increases to 3 V for a 1.6-ns-width pulse. The sub–10-ns ultrafast pulses require relatively larger operating voltages (Fig. 5, B and C) because better impedance matching is required to offset the transmission loss of signals (fig. S14, B to D) (39).

Fig. 5. Operating speed and benchmark of our nanogate MoS₂ FeFETs.

(A) I_D-V_GS curves of our nanogate FeFET, showing notable right shifts in the threshold voltage by applying voltage pulses with widths of 1 μs, 100 ns, 10 ns, and 1.6 ns. The CIPS thickness of this nanogate FeFET is about 33 nm. (B) The operating voltages as a function of pulse widths, showing an increase in voltage, as the pulse width is shortened from 1 μs to 1.6 ns. (C) The current on/off ratio as a function of the pulse voltage for various pulse widths. When applying pulses with widths ranging from 1 μs to 20 ns, the pulse operating voltage is similar to the dc voltage, while the sub–10-ns ultrafast pulses require relatively larger operating voltages. (D) Benchmark of the gate length and operating voltage of our nanogate FeFETs with other reported FeFETs (16–18, 27, 33, 38–56). Our nanogate FeFETs are the only ferroelectric devices with gate length below 10 nm and have the lowest operating voltage of 0.6 V. BTO, barium titanate; BST, barium strontium titanate; PVDF, polyvinylidene difluoride; PZT, lead-zirconate-titanate. (E) Benchmark of the switching speed of our nanogate FeFET with reported FeFETs (16–18, 42–47, 49, 52–56). Our nanogate FeFETs exhibit an outstanding writing/erasing speed of 1.6 ns. (F) Comparison of the switching energy of our nanogate FeFET with reported state-of-the-art FeFETs (17–19, 43, 46, 55, 56), with switching energies normalized by FET width, estimated by this equation (55): $E_{\text{switching}}=\frac{2P_{\mathrm{r}}\times \text{Area}\times V}{W}$, where $P_{\mathrm{r}}$ represents the remeant polarization, area represents the effective area of ferroelectric polarization flip, $V$ represents the operating voltage of FeFETs, and $W$ represents the channel width of FeFETs. IWO, indium tungsten oxide. (G and H) Comparison of current on/off ratios (G) and MWs (H) of our nanogate FeFETs with those of state-of-the-art FeFETs with sub–100-nm gate length (17, 18, 42–46, 54).

We benchmark the performance of our 1-nm gate length MoS₂ FeFETs against those of other reported advanced FeFETs using CIPS, Fe-HfO₂, polyvinylidene difluoride (PVDF), AlScN, and perovskite as gate ferroelectrics (16–18, 27, 35, 40–56) (Fig. 5, D to H). Figure 5D shows that our 1-nm nanogate FeFETs are the only ferroelectric device with gate length below 10 nm and have the lowest voltage value of 0.6 V among all FET-configuration memories reported to date, reducing the voltage of nonvolatile FET-memory be lower than the commercial state-of-the-art CMOS logic voltage (0.7 V); in contrast, other reported FeFETs have gate lengths more than 20 nm and high operating voltages above 1.5 V (16–18, 27, 33, 40–56). Figure 5E shows that our CIPS-based FeFETs have an outstanding writing and erasing speed of 1.6 ns with a voltage pulse amplitude of 3 V, which is three orders of magnitude faster than those of other published 2D CIPS-based FeFETs, rivaling the best HfO₂-based FeFETs (16–18, 42–47, 49, 52–56). At the low operating voltage of 0.6 V, the switching speed is 20 ns. Figure 5F compares the switching energy of our FeFETs with that of state-of-the-art FeFETs. The switching energy of our FeFETs is only 0.45 fJ/μm, which is one order of magnitude lower than the best-reported FeFETs (17–19, 43, 46, 55, 56). Figure 5 (G and H) compares the current on/off ratios and MWs of our FeFETs with those of other representative sub–100-nm FeFETs (17, 18, 42–46, 54). The operation voltage, on/off ratio, and MW are strongly dependent on the CIPS thickness. The nanogate FeFET with a 14-nm CIPS layer enables operation at 0.6 V, yielding an on/off ratio of nearly 10⁴ and an MW of 0.75 V, while the nanogate FeFET with a 70-nm CIPS layer requires 2 V to achieve an on/off ratio of 2 × 10⁶ and an MW of 2.8 V, rivaling the best HfO₂-based FeFETs (17, 18, 42–46, 54).

DISCUSSION

In summary, we introduced a nanogate MoS₂ FeFET with a physical gate length of 1 nm, operating at a logic-compatible voltage of 0.6 V. The key advancement involves using nanotip electric field focusing and strong Fe-to-MOS capacitance coupling. This enhancement improves voltage efficiency by up to 125% and substantially reduces the operation voltage below the nominal coercive voltage of ferroelectrics. The nanogate field enhancement is universal and can be extended to other mainstream ferroelectrics, such as Hafnium Zirconium Oxide (HZO) or perovskites (fig. S15) (31, 32). Furthermore, the electric field focusing effect can be leveraged in solid-state nanogate structures compatible with standard CMOS processes (figs. S16 to S18), enabling wafer-scale manufacturing. Advanced fabrication techniques such as atomic layer deposition enable the realization of solid-state nanogates, serving for ultralow voltage ferroelectric memory in both planar and 3D NAND configurations. Encouragingly, unlike conventional logic transistors facing scaling challenges to sub–10-nm gate length, our work establishes a scaling principle for FeFETs: the smaller, the better. Nanogate FeFETs leverage electric field spatial focusing for energy-efficient nonvolatile memory operation at ultralow voltages, and they are resistant to short-channel effects.

MATERIALS AND METHODS

Ferroelectric characterization of CIPS

We characterized the ferroelectric properties of CIPS parallel-plate capacitor using metal electrodes. The polarization-electric field (P-E) characteristics of CIPS capacitor show typical ferroelectric hysteresis loops with a moderate remnant polarization of ~4 μC/cm² (fig. S2A, left). The ferroelectric nature of the CIPS capacitor can also be confirmed by the sharp current peaks near the coercive field in the current density–electric field (J-E) hysteresis loops (fig. S2A, middle), which is an unambiguous signature of ferroelectric polarization switching. In addition to the P-E and J-E curves, the ferroelectricity of CIPS capacitor can also be verified by its capacitance-voltage (C-V) characteristic. The hysteresis in the C-V characteristics (fig. S2A, right) shows the typical butterfly shape, consistent with the P-E and J-E measurements. The endurance characteristics of CIPS capacitor were also investigated (fig. S2B). The ferroelectric polarization of the CIPS capacitor shows no degradation even after 10⁵ switching cycles (fig. S2B), demonstrating well stability. For accurate characterization of ferroelectric polarization, electrode areas generally need to be at least several tens of square micrometers (fig. S2, C to F). Characterizing the ferroelectric properties of CIPS with a nanotube electrode (fig. S2G, top) encountered a fundamental experimental hurdle: The ultrasmall electrode area (~0.001 μm² for a 1-μm-long CNT with a 1-nm diameter) yields an expected switching charge of only ~0.04 fC (fig. S2G, bottom). This value falls more than three orders of magnitude below the detection limit. Therefore, the commercial P-E tester is hard to reliably measure such a quasi-1D ferroelectric geometry. We performed theoretical simulations of the C-V curve for the CIPS capacitor with CNT electrode (fig. S2, H and I). The results reveal a typical butterfly-shaped curve (fig. S2I), confirming the ferroelectric polarization switching behavior, indicating the ferroelectric switching of CIPS capacitor with CNT electrode. These results confirm the ferroelectricity, robust endurance, and high stability of the CIPS.

m-SWCNT preparation

Long and aligned chemical vapor deposition–grown SWCNTs were transferred onto a highly p-doped silicon substrate with thermally grown SiO₂ (fig. S3A). The target Si/SiO₂ substrate was prepatterned with 5/40-nm-thick Ti/Au alignment markers for locating the transferred SWCNTs with SEM. The SWCNTs were contacted with 30-nm palladium, as the gate electrode by standard electron-beam lithography, electron-beam evaporation, and liftoff, and the redundant SWCNTs were etched by O₂ reactive ion etching using a hard mask (fig. S3B). The diameter of the SWCNT is determined by atomic force microscopy (fig. S3C). I_D-V_GS and I_D-V_DS measurements were performed to identify the electric characteristics of the m-SWCNTs using SiO₂ as the back gate dielectric (fig. S3, D and E).

1-nm gate length MoS₂ FeFET fabrication

To fabricate the 1-nm gate length MoS₂ FeFET, a thin CIPS flake was transferred onto the selected m-SWCNT on the Si/SiO₂ substrate using a transfer station with micrometer-resolution alignment under an optical microscope (fig. S4A). Graphene flake was released and transferred onto the CIPS flake (fig. S4B). The h-BN and MoS₂ flakes were then transferred onto the Gr flake (fig. S4, C and D). The sample with CNT/CIPS/Gr/h-BN/MoS₂ heterostructure was then soaked in acetone and isopropanol for 60 min, respectively, to remove potential organic residue. Last, the Ti/Au source/drain contacts were made to the MoS₂ channel to complete the device.

FTJ device fabrication

To fabricate the 1-nm nanotip FTJ, a thin CIPS flake and a multilayer Gr flake were transferred onto the selected m-SWCNT using mechanical exfoliation and dry-transfer methods. Then, the sample with CNT/CIPS/graphite heterostructure was soaked in acetone and isopropanol for 60 min, respectively, to remove potential organic residue. Last, the Ti/Au contact was made with Gr to complete the device.

To fabricate the normal FTJ, the Gr flakes were mechanically exfoliated on a silicon substrate with thermally grown SiO₂. Then, a thin CIPS flake was transferred onto the monolayer Gr on the Si/SiO₂ substrate. A multilayer Gr flake was then transferred onto the CIPS flake. The sample with monolayer Gr/CIPS/graphite heterostructure was then soaked in acetone and isopropanol for 60 min, respectively, to remove potential organic residue. Last, the Ti/Au contacts were made to Gr to complete the device.

Characterization and measurements

SEM imaging was performed using a Zeiss Sigma 300 SEM. A 1.5-kV accelerating voltage was used to image the devices and determine the location of the SWCNTs. The thickness of the as-exfoliated material and the diameter of SWCNT were determined by a Bruker Dimension Icon atomic force microscopy. The cross-sectional scanning transmission electron microscopy images and electron energy-loss spectroscopy mappings were obtained using a high-resolution spherical aberration correction TEM (JEOL ARM200F). Electrical measurements were performed in a probe station with a shielded enclosure using a Keithley 4200A-SCS Parameter Analyzer and an AVTECH AVIR-4D-B pulse generator. The dc signals were generated using a source-measure unit in the Keithley 4200A-SCS. The nanosecond voltage pulses were generated using an AVIR-4D-B pulse generator, and the voltage pulses were recorded with an Agilent DSO9104A oscilloscope.

Theoretical and TCAD simulations

In our device, the Gr layer plays a role in averaging the nonuniformity of potential due to the domain distribution in the ferroelectric layer. Thus, it is reasonable to use the 1D Landau-Khalatnikov model to calculate the ferroelectric characteristics (30, 31, 57). To simulate the whole ferroelectric device, we consider it as a series combination of a ferroelectric capacitor and a conventional MOSFET. For the ferroelectric capacitor part, the Gibbs free energy density is

$$U=\mathrm{\alpha }{t}_{\mathrm{f}}{P}^2+\mathrm{\beta }{t}_{\mathrm{f}}{P}^4+\mathrm{\gamma }{t}_{\mathrm{f}}{P}^6-V_{\mathrm{f}}P$$

where $\mathrm{\alpha }=-1.8{\mathrm{e}}^9 \mathrm{m}/\mathrm{F}$, $\mathrm{\beta }=6.25{\mathrm{e}}^{11}\frac{{\mathrm{m}}^5}{\mathrm{F}{\mathrm{C}}^2}$, and $\mathrm{\gamma }=1.08e^{13}\frac{m^9}{\mathrm{F}{\mathrm{C}}^4}$ are the Landau parameters, which are only dependent on the materials, $t_{\mathrm{f}}$ is the ferroelectric layer thickness, V_f is the voltage applied on the ferroelectric film, and P denotes the electrical charge of the ferroelectric layer. The equilibrium state of ferroelectric is determined by the minima of U

$$\frac{\mathrm{\partial }U}{\mathrm{\partial }P}=2\mathrm{\alpha }{t}_{\mathrm{f}}P+4\mathrm{\beta }{t}_{\mathrm{f}}{P}^3+6\mathrm{\gamma }{t}_{\mathrm{f}}{P}^5-V_{\mathrm{f}}=0$$

Then, the voltage across the ferroelectric film has the following form

$$V_{\mathrm{f}}=2\mathrm{\alpha }{t}_{\mathrm{f}}P+4\mathrm{\beta }{t}_{\mathrm{f}}{P}^3+6\mathrm{\gamma }{t}_{\mathrm{f}}{P}^5$$

For the MOSFET part, the 2D electrostatics are calculated using TCAD. The TCAD model is based on the classical drift-diffusion transport. The parameters for TCAD simulation defined in Table 1.

Table 1. Parameters for TCAD simulation.

m₀, free electron mass; ε₀, permittivity of vacuum.

Parameter	Value
Band gap of MoS2 (Eg)	1.8 eV
Effective mass of MoS2 (m*)	0.55m0
MoS2 Channel thickness (tMoS2)	0.65 nm
Affinity of MoS2 (χ)	4.2 eV
Contact metal workfunction (W)	4.3 eV
Thickness of h-BN (th-BN)	5 nm
Dielectric constant of h-BN (εh-BN)	5.1ε0
Thickness of CIPS (tCIPS)	14 nm
Dielectric constant of CIPS (εCIPS)	40ε0
Remnant polarization of CIPS (Pr)*	3.8 μC/cm2
Spontaneous polarization of CIPS (Ps)*	4 μC/cm2
Coercive electric field of 4 nm CIPS (tCIPS = 4 nm)†	1 V/nm
Coercive electric field of 14 nm CIPS (tCIPS = 14 nm)†	0.05 V/nm

^*(16, 36).

^†(60–62).

The simulation of the regular MOSFET part of the device can be performed independently without imposing boundary conditions because of the presence of the metallic intermediate Gr layer, where the potential is the same at any grid point, and this makes it possible to model the ferroelectric film with 1D Landau approach (58, 59). The 2D electrostatics for MOSFET and 1D Landauer model are solved self-consistently to simulate the ferroelectric FET.

Investigation of the nanotip-induced electric field enhancement effect

We performed the TCAD simulation of the electric field contour plots for two FTJs, one with a 1-nm CNT electrode and the other with a normal electrode, both of which have a 4-nm-thick CIPS layer as a ferroelectric barrier (fig. S8). When the two FTJs are biased at the same voltage (here set to 1 V), different spatial distributions of the electric field occur: A strong and highly localized electric field is obtained in the CIPS layer of the 1-nm FTJ (fig. S8A, top), whereas a uniform and low-intensity distribution of the electric field is formed by the normal FTJ with the normal bottom electrode (fig. S8A, bottom). The electric fields extracted along the x axis (fig. S8B, left) and y axis (fig. S8B, right) of the two FTJs show that the maximum electric field of the 1-nm FTJ reaches 6 × 10⁶ V/cm, which exhibits a 2.4-fold boost compared to that of the normal FTJ (2.5 × 10⁶ V/cm). Then, we fabricated a 1-nm FTJ using m-SWCNT as the bottom electrode, 4-nm-thick CIPS as the ferroelectric tunneling barrier layer, and multilayer Gr as the top electrode. The corresponding cross-sectional TEM image is shown in fig. S8C. As a comparison, the normal FTJ with a monolayer Gr as the bottom electrode was also fabricated. Electrical measurements show that a typical 1-nm CNT/CIPS/graphite FTJ can be switched from the on state to the off state by applying only a low voltage pulse of 1.5 V (fig. S8D, left), whereas a higher voltage pulse of 4 V is required for a normal monolayer Gr/CIPS/graphite FTJ (fig. S8D, right). These experimental results are in agreement with theoretical calculations, confirming the electric field enhancement effect of the 1-nm SWCNT electrode and its voltage-saving effect on the FTJ.

Supplementary Materials

This PDF file includes:

Figs. S1 to S18

Table S1