3D LineExplore: a 3D line exploration method for multi-layer PCB geometric routing

Abstract

With the rapid advancement of electronic technology and the growing complexity of integrated circuit design, Printed Circuit Board (PCB) routing has become increasingly challenging. Current multi-layer PCB routing mainly relies on grid-based methods like A*, which face resolution limitations and high computational cost, especially with fine grids required for high routability. Although grid-less approaches such as the line-expansion method have been proposed, they are largely limited to 2D and unsuitable for multi-layer routing. To address this, we propose a 3D line-exploration-based geometric routing method for multi-layer PCBs that overcomes grid resolution constraints, improves efficiency, and natively supports multi-layer routing. The method comprises three key components: a “radar”-inspired scanning algorithm that automatically identifies exploration points based on design rules and surrounding obstacles; an obstacle-avoidance heuristic path optimization algorithm that enables optimal path planning, including layer transitions and obstacle bypassing from the current exploration points; and a multi-pin net repair and wire-shape optimization module, which enhances routing capability and path smoothness while ensuring compliance with design constraints. Experiments on an open-source PCB dataset show that the proposed 3D LineExplore achieves over 98% routing success, with shorter wire lengths and higher efficiency than state-of-the-art methods and commercial tools including FreeRouting, ELECTRA, DeepPCB, and Optimized-3D-A*.

Introduction

With the rapid evolution of electronic technology and the growing complexity of integrated circuit design, Printed Circuit Boards (PCBs) play a critical role in modern electronic systems by enabling reliable electrical pathways among numerous components^1,2. Especially in high-density, multi-layer designs, routing not only directly impacts circuit functionality and performance of circuits but also represents the most time-consuming and challenging step in the PCB design process.

PCB automatic routing methods can be broadly classified into two types: modular routing techniques and universal PCB routing techniques. Modular routing techniques—such as escape routing,^3–6, bus routing^5,7,8, and layer assignment^9–11, primarily aim to address specific components or stage-specific problems. In contrast, universal PCB routing methods aim to develop an end-to-end solution to meet the requirements of global consistency in industrial-grade. Existing universal routing methods can be broadly categorized into two types: grid-based methods^12–16 and gridless methods^17–25, each exhibiting distinct limitations:

• Grid-based methods: This method relies on a fixed grid, and when the grid resolution does not match the actual component sizes or routing specifications, it may lead to accuracy errors. The fixed grid structure limits routing efficiency, especially in complex electrical designs that require numerous adjustments to achieve a viable routing solution.

• Gridless methods: Existing gridless routing methods are mostly limited to two-dimensional routing spaces and have difficulty supporting optimization for multi-layer routing.

These limitations highlight that improving routing completion rates while ensuring accuracy and efficiency remains a key bottleneck in applying existing methods to complex PCB designs.

To overcome this challenge, this paper proposes a 3D line-exploration-based geometric routing method for multi-layer PCBs. The objective is to compute effective exploration points within a multi-layer, gridless geometric space and then perform routing by conducting topological searches between these points. However, this approach faces several core challenges:

• A key challenge is determining effective exploration points without a fixed grid. In gridless routing, exploration points may vary from layer to layer, making it essential to ensure their effectiveness throughout the multi-layer space. If exploration points are too sparse, the solution space may be inadequate; if too numerous, it may revert to a grid-based method.

• In grid-based routing, two adjacent points are always connected. However, in gridless routing, obstacles may exist between exploration points. Ensuring the connectivity of selected exploration points and the continuity of the resulting paths is a key challenge in path planning.

• When searching for an optimal path via exploration points, the path must comply with the 135-degree angle design rule. However, paths from exploration point searches may not meet this rule.

To address the aforementioned challenges, this paper proposes a 3D line-exploration-based geometric routing method for multi-layer PCBs. The method aims to overcome the limitations of traditional grid-based partitioning by using continuous-space modeling and an adaptive path search mechanism, improving routing quality and efficiency. The following key techniques are proposed to address these challenges:

• To find exploration points, this paper proposes a ‘radar’-inspired scanning algorithm. It provides a feasible set of exploration points for the subsequent obstacle-avoidance heuristic path optimization.The algorithm ensures connectivity of paths generated from these points and efficiently filters candidate points to avoid redundant computation, offering a flexible and viable set of path candidates for subsequent route planning.

• To ensure both connectivity and optimality of the generated paths, this paper proposes an obstacle-avoidance heuristic path optimization algorithm. In the pathfinding process, the ‘radar’-inspired scanning algorithm is first used to identify a set of exploration points that support obstacle-avoiding connections, ensuring the connectivity of paths from these points. The obstacle-avoidance heuristic path optimization algorithm then selects the exploration points with the lowest total cost. This approach efficiently identifies the most promising path directions, enabling optimal layer transitions and obstacle avoidance using the current set of exploration points.

• To satisfy the 135-degree angle design rule, this paper proposes a wire-shape optimization algorithm for paths that violate this constraint. The algorithm dynamically adjusts the geometric layout of polyline segments, enhancing path smoothness and adaptability, while ensuring compliance with PCB design rules and constraints.

It is important to note that the proposed 3D LineExplore is a heuristic, one-pass routing approach that prioritizes efficiency and solution quality over guaranteeing global optimality.

The main contributions of this paper are summarized as follows:

• This paper proposes a 3D line-exploration-based geometric routing method for multi-layer PCBs. By operating directly in continuous space, the proposed method efficiently extends geometric routing capabilities from 2D planes to 3D multi-layer environments, ensuring high routing precision and computational efficiency without the resolution constraints inherent in grid-based approaches.

• This paper proposes a “radar”-inspired scanning algorithm and an obstacle-avoidance heuristic path optimization algorithm. By combining continuous-space path exploration with heuristic optimization, the approach significantly enhances routing feasibility and flexibility. In contrast to traditional 2D gridless methods, the proposed method selects inter-layer routing paths, effectively alleviating congestion on individual layers.

• The effectiveness of the proposed method was validated through experiments on 11 publicly available datasets, where we compared it with the Freerouting, ELECTRA, DeepPCB, and Optimized-3D-A* algorithms. Our method achieved an average 98% routing success rate, and outperformed the other methods in both runtime and path length.

Related work

As electronic systems evolve towards higher density, miniaturization, and multi-layer designs, the importance of PCB routing issues has become increasingly prominent. Automatic routing not only needs to ensure path reachability but also optimize multiple metrics, such as length, the number of via points, and operational efficiency. Early methods like Dijkstra, maze algorithms, line expansion, and A* algorithms achieved certain results in 2D grids, but as design requirements have become more complex, their limitations in spatial expression and computational efficiency have gradually become apparent. To overcome these limitations, the academic community has explored methods such as grid and gridless approaches, aiming to improve routing success rates while balancing efficiency and path quality.

Grid-based methods

Grid-based methods rely on a fixed grid structure and use minimum-cost grid search algorithms to determine routing paths. Li et al.¹⁷ proposed an optimized 3D A* algorithm that extends the traditional A* to three dimensions. By incorporating via diameter constraints during neighbor expansion, their method enhances adaptability in cross-layer routing. Lin et al.¹⁸ presented a complete 3D PCB autorouting approach that integrates parallel hierarchical escape routing (SER) with a region-based strategy. Their method constructs low-layer (LLG) and high-layer (HLG) grids on each layer and employs a SAT solver for path assignment and inter-layer connection management. Zhang et al.¹⁹ introduced a 3D global router, V-GR, which incorporates a via-aware cost function and applies rip-up and rerouting strategies to dynamically optimize routing, thereby improving wire length, via count, and resource utilization. He et al.²¹ proposed a gridless 2D routing method based on dynamic polygon partitioning and Monte Carlo tree search (MCTS). Using a two-stage process—global routing followed by detailed routing—their method achieves efficient pad-to-pad connections and demonstrates high completion rates and strong path quality for both BGA and non-BGA packages. Lin et al.²³ developed a general A*-based routing framework for multilayer PCB design. By combining 3D grid modeling, differential-pair-aware routing, and “dog-bone” via structures, their approach improves routing success while ensuring manufacturability. Li et al.²⁰ and FreeRouting²² introduced optimization techniques to address these challenges, but their overall efficiency remains low, particularly for large-scale PCBs.

Gridless-based methods

To overcome the limitations of grid-based modeling in flexibility and space utilization, gridless routing methods have been extensively studied. Mikami and Tabuchi¹² first proposed an improved line-expansion algorithm, using a breadth-first strategy from wire endpoints to ensure path completeness. This work laid the theoretical foundation for gridless routing. Finch et al.¹³ introduced a comprehensive gridless routing method for PCBs, employing rectangle expansion, obstacle modeling, and a multi-channel search mechanism. Their approach enables efficient routing of high-density circuits without relying on a fixed grid. Kong et al.¹⁴ addressed the bus escape problem with a gridless method based on the maximum disjoint rectangle subset (MDS), formulating the routing task as a longest-path problem on a directed acyclic graph (DAG). This approach ensures path validity, bus structure preservation, and spatial optimization. Tan Yan and Martin D. F. Wong et al.¹⁵ proposed a gridless routing framework based on bounded slack grids (BSG), transforming length constraints into a region-labeling problem and solving it via linear programming. This framework effectively accommodates complex topologies and high-frequency routing requirements. Youbiao He et al.¹⁶ developed a pad-centric 2D gridless routing method that integrates dynamic polygon partitioning with Monte Carlo tree search (MCTS), enabling a unified flow from global to detailed routing. The method performs fine-grained routing searches within arbitrarily shaped regions using an A*-based algorithm and improves routing success rate and path quality through local re-partitioning. It is particularly well suited to high-density designs involving irregular packages.

Problem statement

Optimization objective

Routability: Generally defined as the ratio of successfully routed pin pairs to the total number of pin pairs. A higher routability reflects greater reliability of circuit functionality. It can be calculated using the following formula:

1

where p denotes the total number of connected pin pairs, and denotes the number of successfully connected pin pairs. Ideally, we aim to make as close as possible to p, thereby improving the routing success rate.

Wirelength: This is another key metric for evaluating routing quality. It not only affects signal transmission but also directly influences power consumption. Total wirelength is computed by summing the lengths of all interconnections between pin pairs across each net. Specifically, for each net , the total length of all wire segments in its routing path is given by the following formula:

2

where denotes the set of wire segments in the routing path of net ni, represents the length of an individual segment e, and k is the total number of nets. The goal is to minimize total wirelength to reduce signal delay and power consumption.

Via count: The number of vias is a key indicator of the quality and manufacturability of PCB routing. Vias are used to connect traces across different layers, and their quantity affects manufacturing cost and signal integrity. Let denote the total number of vias across all nets. The optimization objective is to minimize , which can be expressed by the following formula:

3

where represents the number of vias used in net , and k is the total number of nets.

Runtime: Runtime measures the efficiency of a PCB routing algorithm and is especially critical in multilayer designs. An optimized algorithm must balance efficiency with routing quality, aiming to minimize runtime while ensuring high completion rate and short wirelength. Let denote the total computation time, defined as the duration from the start to the completion of the routing process. This can be expressed by the following formula:

4

where is the time when the algorithm begins execution, and is the time when routing is completed. A smaller indicates that the algorithm completes the routing task faster, reflecting higher efficiency.

Objective function: In the optimization process, the goal is to jointly optimize routability, wire length, via count, and runtime. The objective function is formulated as follows:

5

This formulation aims to maximize the routability while minimizing total wirelength, via count, and runtime, ensuring as many nets as possible are routed successfully and routing quality improves.

Constraint

Routing area constraint (keep-in): Let the routable area of the PCB layout be a rectangular region A with its bottom-left corner at (0, 0), width W, and height H. All routing traces and vias must entirely contained within the physical boundaries of the PCB. For any wire segment or via , the following condition must be satisfied:

6

Obstacle avoidance constraint (keep-out): Let O denote the set of obstacles on the PCB, and let represent the region occupied by an obstacle . Each wire segment and via must avoid all such obstacle regions. Specifically, the following condition must be satisfied:

7

Wire-to-wire spacing: In PCB routing, a minimum spacing must be maintained between any two wire segments on the same or adjacent layers to prevent signal crosstalk, short circuits, or other electrical interference. Let and denote two distinct wire segments, and let represent the Euclidean distance between their geometric centers. The following spacing constraint must be satisfied:

8

where denotes the minimum design spacing between wires. In this study, is set to 1 unit of length. This constraint ensures electromagnetic compatibility and manufacturing reliability by preventing unintended electrical coupling or physical overlap between adjacent traces.

Wire-to-pin spacing: During PCB routing, a sufficient clearance must be maintained between a wire and a pin to ensure soldering reliability and prevent electrical interference. Let denote a wire segment and denote a pin. The Euclidean distance between them must satisfy the following constraint:

9

where represents the minimum clearance between a wire and a pin. In this study, is set to 1 unit length for consistency in the constraint model.

Therefore, designing an efficient PCB routing algorithm requires optimizing routing paths under the constraints of layout boundaries, obstacle avoidance, and connectivity requirements, aiming to maximize the routability and minimize the total wirelength. Moreover, the algorithm should achieve high computational efficiency by minimizing the runtime required for routing.

Methodology

The framework of 3D LineExplore

This paper proposes a 3D line-exploration-based geometric routing approach for multi-layer PCBs, as illustrated in Fig. 1. The method aims to overcome the limitations of grid-based and 2D gridless routing methods.The method employs a “radar”-inspired scanning algorithm that dynamically explores the multi-layer space according to design rules and surrounding obstacles. It identifies effective exploration points within routable regions and generates a set of points that avoid obstacles. This set is then processed by an obstacle-avoidance heuristic path optimization algorithm, which incrementally extends the path towards the target by minimizing a cost function. In the post-processing stage, this paper introduces a multi-pin net repair and wire-shape optimization module. The multi-pin net repair algorithm addresses routing failures in multi-pin nets, thereby improving routing completion and integrity. The wire-shape optimization algorithm refines the geometry of routed paths, enhancing their smoothness and adaptability.

Fig. 1.

Flowchart of the 3D line-exploration-based geometric routing algorithm for PCBs.

3D LineExplore follows a heuristic one-pass routing paradigm. It performs a single pass of exploration to identify a set of candidate routable points that satisfy design rules and avoid obstacles, and then applies a cost-driven heuristic to connect these points into a path that progresses toward the destination. Unlike iterative routing frameworks, 3D LineExplore does not employ rip-up-and-reroute or multi-pass refinement, and thus does not guarantee global optimality. This one-pass design is intentional to achieve high efficiency, while solution quality is improved through multi-pin net repair and geometry refinement in post-processing.

“Radar”-inspired scanning algorithm

The generation of exploration points is a critical factor influencing routing efficiency and success rate, especially in gridless multi-layer PCB routing, where identifying effective exploration points is crucial. If exploration points are too sparse, the solution space becomes insufficient; if too dense, the method may turn into a grid-based approach. Therefore, the selection of exploration points directly determines routing performance. To address this, this paper proposes a ‘radar’-inspired scanning algorithm. This algorithm efficiently generates a set of effective exploration points by dynamically detecting local obstacles and applying a geometric filtering mechanism.This approach avoids redundancy and significantly enhances routing accuracy and efficiency. Figure 2 illustrates the principle of the proposed algorithm. The method consists of the following three modules:

Fig. 2.

“Radar”-inspired scanning algorithm (pins appear on either top or bottom layer, while a via pin is punched through).

Local neighborhood construction and obstacle extraction

As shown in Fig. 2, the “radar”-inspired scanning algorithm first constructs a local region based on the start point s and the goal point d. Within this region, the algorithm effectively detects obstacles and extracts their vertices. For obstacles lacking distinct vertices (e.g., circular or elliptical shapes), it approximates them by quadrilaterals to enable uniform treatment. Using these extracted vertices, the algorithm generates an initial candidate set of exploration points A. This step ensures that critical areas within the target region are adequately covered and lays a solid foundation for subsequent path planning and obstacle avoidance.

If no feasible solution is found within a local region, the neighborhood scope is dynamically expanded, with the entire PCB board serving as the upper bound of the local neighborhood. This expansion is triggered only upon failure to locate a solution in the current local region; consequently, the search space is not enlarged in all cases, thereby significantly reducing computational cost.

Cross-layer exploration point generation

As shown in Fig. 3, the “radar”-inspired scanning algorithm further generates cross-layer exploration points according to the layer to which the start point s belongs, and includes them in the explorable set T.When the start point s and the destination point d reside on the same layer, the algorithm directly adds d to the pre-exploration point set A. If s and d are located on different layers, the algorithm generates a corresponding inter-layer exploration point , where the term “inter-layer relationship” refers to the relative positional relationship between s and d. Specifically, is the projection of the destination point d onto the layer containing the start point s. This inter-layer exploration point is then added to the pre-exploration point set A.The procedure for generating such cross-layer points is illustrated in Fig. 3.

Fig. 3.

Schematic of cross-layer exploration point generation.

Exploration point filtering and optimization

In the exploration point filtering process, the algorithm constructs pre-exploration lines from the start point to each candidate and checks whether these lines intersect with any obstacle in the obstacle set. For each obstacle, it iterates over all its edges (i.e., line segments) to determine whether any edge intersects the current pre-exploration line. Intersection detection is based on computational geometry, where the presence of an intersection point between two line segments serves as the criterion. The procedure is as follows:

First, for any two line segments and , as shown in Fig. 4, we construct the equations of their supporting lines using the coordinates of their endpoints: , and , . For the first line segment , the equation of its supporting line can be expressed as:

10

where: , , ,

Fig. 4.

Line segment intersection.

Similarly, for the second line segment , its line equation is:

11

where: , , ,

Next, we compute the determinant of the two lines:

12

When , the two lines are either parallel or identical. When , the lines intersect at a unique point. The coordinates of this intersection can be obtained by solving the corresponding system of linear equations.

However, the existence of an intersection point between two lines is not sufficient to establish that the corresponding line segments intersect. Even if the two lines intersect, it is necessary to verify whether the intersection point lies within the finite bounds of both segments (as illustrated in Fig. 4). To this end, the intersection point (x, y) is further examined.

• The x-coordinate of the intersection point must lie within the x-coordinate range of the first-line segment :

  13
• The y-coordinate of the intersection point must lie within the y-coordinate range of the first-line segment :

  14
• Similarly, the x-coordinate of the intersection point must lie within the x-coordinate range of the second-line segment :

  15
• The y-coordinate of the intersection point must lie within the y-coordinate range of the second-line segment :

  16

If the intersection point satisfies the above conditions, the two line segments are considered to intersect, and the coordinates of the intersection point are returned. Otherwise, the line segments are regarded as non-intersecting.

If the pre-exploration line does not intersect any obstacle edges, the corresponding pre-exploration point is regarded as valid and included in the final exploration set T. The output set T thereby satisfies the obstacle-free constraint. By integrating the spatial distribution of obstacles, inter-layer feasibility, and reachability conditions, the algorithm efficiently performs local space detection. This enables the generated exploration points to incorporate both directional guidance and obstacle avoidance, thereby preventing unnecessary expansions and providing reliable support for subsequent path planning. Through precise selection and optimization of exploration points, the algorithm significantly enhances the accuracy and efficiency of path planning, allowing feasible and high-quality paths to be generated rapidly even in complex environments.

The pseudocode of the “radar” scanning algorithm is shown in Algorithms 1 and 2.

Algorithm 1.

Method to check if two line segments intersect

Algorithm 2.

“Radar” scan exploration algorithm

Obstacle-avoidance heuristic path optimization algorithm

We propose the obstacle-avoidance heuristic path optimization algorithm that couples a heuristic cost function with a priority queue to support dynamic cost evaluation and incremental expansion. Considering path length, inter-layer (via) transition cost, and a heuristic estimate to the goal, the method incrementally builds a goal-directed search graph and jointly optimizes path length, layer switching, and obstacle-avoidance efficiency for multi-layer PCB routing. It allows flexible inter-layer transitions and significantly improves both path-planning efficiency and solution quality. The approach comprises four modules:

Heuristic cost function

The algorithm employs a multi-factor comprehensive heuristic cost function that accurately integrates the actual cost and estimated cost of paths to guide route selection. Specifically, the cost function accounts for the actual cost from the start node to the current node, the edge cost from the current node to a neighbor, the inter-layer (via) transition cost, and the heuristic estimate from the neighbor node to the goal. By considering these factors, the method can dynamically optimize path selection during the planning process, avoiding the pitfall of traditional methods which often rely excessively on local information at the expense of global optimality.

The definition of the cost function is as follows:

17

f(neighbor): It represents the total cost of the neighboring node, which is used to prioritize path selection.

g(current): The actual path cost from the start node to the current node, which accumulates the path length and inter-layer cost.

d(current, neighbor): The Euclidean distance from the current node to the neighboring node.

: The inter-layer cost term, where:

• v: the weight of the inter-layer cost,

• : an indicator function of whether an inter-layer switch occurs (it takes the value 1 when a switch occurs, otherwise 0).

h(neighbor, goal): The heuristic estimate, typically the Euclidean distance from the current node to the goal node, used to predict the remaining path cost.

Search space generation

During the path expansion phase, a “radar”-inspired scanning algorithm is employed to generate the set of explorable points from the current node, serving as the candidate neighbor nodes for expansion. This method enables the rapid identification of potential explorable points at each expansion step, thereby providing directional guidance for the path search. For each neighbor node in the explorable set, the algorithm computes its total cost and evaluates the following condition: if the node has not yet been visited, or if the total cost to reach this node via the current path is lower than that of any previously known path, the predecessor information of the node is updated, and the node is added to the candidate node set for subsequent expansion. The algorithm maintains a priority queue as the candidate node set, from which the node with the minimum total cost is selected for expansion at each step, ensuring the exploration is directed toward the optimal path.

Graph structure generation

During the path search process, the algorithm incrementally constructs an implicit directed search graph, with the start node as the root. The graph expands by iteratively adding neighbor nodes along the path of minimum total cost. Each time a new neighbor node is expanded, a directed edge from the current node to the neighbor node is established in the logical structure, and the predecessor relationship between nodes is recorded to support subsequent path backtracking and reconstruction. This implicit graph structure does not require explicit storage of a complete adjacency matrix. Instead, it maintains the search trajectory in a sparse and dynamically updated manner, effectively reducing memory overhead while preserving the completeness of path information.

Path backtracking and generation

Upon successfully reaching the target node, the algorithm proceeds to the path generation phase. By utilizing the predecessor relationships recorded during the search, the algorithm traces back from the target node to the start node using the predecessor chain, reconstructing the complete path and ensuring connectivity from the start to the target.

The pseudocode of the obstacle-avoidance heuristic path optimization algorithm is presented in Algorithms 3:

Algorithm 3.

Obstacle-avoidance heuristic path optimization algorithm

Multi-pin net repair and wire-shape optimization module

Multi-pin net repair algorithm

During the PCB routing process, for multi-pin nets containing three or more pins, our method decomposes the net into pin pairs for sequential routing. The algorithm first selects an initial pin and identifies the nearest unconnected pin among the remaining pins to establish a connection. All connected pins are stored, and in each subsequent step, the algorithm connects the unconnected pin that is closest—measured by routing path distance—to any pin already in the connected set.This incremental process repeats until all pins in the net are interconnected. However, routing failures may occur during this procedure. To address such failures, we propose a multi-pin net repair algorithm.

It is worth noting that although topology-based approaches—such as Steiner trees—are theoretically optimal for minimizing total wire length, the pairwise routing strategy adopted here is particularly well-suited for high-speed and high-frequency rigid PCB designs where signal integrity is the primary constraint. In such industrial contexts, signal integrity is critical. Industry feedback indicates a strong preference for direct pin-to-pin connections over shared trunks, as the former reduce risks associated with impedance discontinuities and signal reflections.

In the event of a routing failure, the algorithm first evaluates the relative position of the failed pin against the already connected pins in the multi-pin net. A repair path is then identified to restore connectivity. The repair strategy prioritizes connecting the failed pin to the nearest candidate within the connected set, subject to the stability of the existing routing. The repair decision follows a shortest-distance criterion, where distances are computed using the Euclidean metric:

18

where and are the center coordinates of two pins.

This mechanism restores the connectivity of the original net by flexibly adjusting connection order and routing paths, thereby efficiently repairing breaks. It guarantees that the optimization is completed within minimum time and yields improved total wirelength. Figure 5 shows the process.

Fig. 5.

Schematic of multi-endline network repair process.

Wire-shape optimization algorithm

To enhance the geometric properties of rectilinear paths, a wire-shape optimization algorithm is presented. This algorithm dynamically adjusts the geometric layout of wire segments to enhance path smoothness and adaptability, while satisfying design rules and constraints in PCB routing. By incorporating geometric analysis and obstacle avoidance mechanisms, the approach effectively mitigates acute-angle bends and optimizes overall routing quality and efficiency.

This algorithm is founded on a parallelogram-based technique for optimizing routing paths, thereby ensuring obstacle avoidance and improving wire geometry. Segments aligned with the coordinate axes remain unchanged, while all other rectilinear segments are processed iteratively. For each segment, a parallelogram is constructed and evaluated for intersections with obstacles. If no intersection is detected, the segment is directly replaced. In cases of intersection, the intersection points serve as references for reconstructing a new parallelogram, followed by further refinement. Iterative optimization of these intersection positions ultimately yields a routing path that adheres to the constraint. Figure 6 depicts the wire-shape optimization algorithm procedure.

Fig. 6.

Process of line shape optimization.

Experiments and analysis

Experimental setup

Experimental environment

The experiments were conducted in C++ within Visual Studio Code (version 1.101). The experimental platform was a MacBook Pro equipped with an Apple M1 Pro chip and 16 GB of RAM.

Dataset

The experiment employs the open-source PCBBenchmarks²⁶, a widely used benchmark for PCB routing tasks. The dataset covers multi-layer routing scenarios ranging from simple to complex. Each case includes different numbers of nets, components, pins, and layers. With gradually increasing complexity, it is well-suited for evaluating algorithm performance across diverse scenarios. The detailed configuration is shown in Table 1.

Table 1.

Open-source dataset used in the experiment.

Design	Nets	Components	Pins	Layers
bm1	99	60	319	2
bm2	34	19	77	2
bm3	80	58	229	2
bm4	54	48	163	2
bm5	38	34	138	2
bm6	52	28	140	2
bm7	15	8	40	1
bm8	70	36	188	2
bm9	63	61	314	4
bm10	35	58	233	4
bm11	69	46	207	2

Evaluation metrics

To comprehensively evaluate the performance of the routing method, the following metrics are used in this experiment.

Routability (RT): Routability is defined as the ratio of successfully routed connections to the total number of connections. This metric reflects the algorithm’s capability of addressing routing problems and is a key indicator of its feasibility and effectiveness. A higher routability demonstrates greater capability of completing connections under given constraints, thereby indicating stronger reliability in practical applications.

Wirelength (WL): Wirelength (WL) is defined as the total length of all routed nets. Shorter wirelength reduces signal propagation delay as well as power consumption and electromagnetic interference. It is a key indicator of routing quality.

Via count (#Via): The via count is defined as the number of vias used in routing, reflecting the complexity of inter-layer connectivity. Vias are conductive pathways that interconnect routing segments across different layers. An excessive via count increases routing complexity and manufacturing cost while potentially introducing additional signal delay and electromagnetic interference. Hence, a lower via count generally indicates simpler inter-layer connectivity and higher routing quality.

Runtime (T): Runtime is defined as the total time required for the algorithm to complete the routing process. A shorter runtime indicates higher computational efficiency and faster routing solution generation. Thus, runtime is a critical indicator for evaluating the practicality and scalability of a routing algorithm.

Comparison methods

The four methods compared in the experiment are as follows:

Freerouting²²: An open-source automated routing tool based on the A algorithm and the “rip-up and reroute” strategy. It supports basic path optimization and design rule checking (DRC), and is suitable for small and medium-scale PCB routing tasks. Freerouting achieves high routability but has limited performance in high-density routing scenarios.

ELECTRA²⁷: A commercially optimized PCB autorouting tool that integrates enhanced traditional pathfinding algorithms with global optimization strategies. It supports multi-layer board routing and complex rule checking, making it suitable for medium- to high-complexity designs. ELECTRA excels in both routing efficiency and compliance with design rules.

DeepPCB²⁸: An AI-driven PCB autorouting tool leveraging deep learning and reinforcement learning. It handles complex layouts and irregular designs and includes built-in path optimization and design-rule checking (DRC). Designed for multi-layer, high-density boards, DeepPCB demonstrates significant advantages in improving routability and optimizing wirelength.

Optimized-3D-A*¹⁷: An enhanced 3D-A* algorithm incorporating optimizations for path regularity, via costs, and manufacturing constraints. Tailored for multi-layer PCB routing tasks, it effectively improves routability and minimizes the number of vias.

Experimental results and analysis

Performance comparison analysis

Table 2 presents the detailed experimental results, reporting key metrics such as RT, #Via, WL, and T. Analysis of the data leads to the following conclusions:

Table 2.

Comparison of the overall PCB routing results for ELECTRA (EL), FreeRouting (FR), DeepPCB (DEEP), and our method (“n/a”: not completed within 24 h).

Metric	Method	Average	bm1	bm2	bm3	bm4	bm5	bm6	bm7	bm8	bm9	bm10	bm11
WL (mm)	EL	1595	5583	327	1474	1123	569	926	118	1191	3527	1728	983
	FR	1425	4517	354	1366	1055	588	850	93	1127	3154	1543	1033
	DeepPCB	1499	5038	303	1221	944	535	893	87	1128	3684	1721	937
	Optimized-3D-A*	1351	4244	286	1155	776	445	657	98	1233	3506	1709	753
	3D LineExplore	1404	3960	284	1094	913	575	784	86	1342	3699	1782	933
RT (%)	EL	99	100	100	98	100	100	100	100	100	100	100	92
	FR	99	100	100	93	99	100	100	100	100	100	100	94
	DeepPCB	99	100	100	100	100	100	100	100	100	100	100	97
	Optimized-3D-A*	96	96	94	96	94	100	98	100	100	95	94	93
	3D LineExplore	98	90	100	97	100	100	100	100	100	100	100	94
#Via	EL	50	170	6	57	37	19	28	5	1	111	55	63
	FR	25	45	2	30	22	10	4	0	1	76	27	53
	DeepPCB	27	89	4	19	22	12	3	0	0	80	18	46
	Optimized-3D-A*	30	130	0	20	14	2	18	0	2	82	16	44
	3D LineExplore	87	133	13	104	90	40	46	0	17	269	139	105
T (s)	EL	4	11	1	2	2	1	1	1	1	9	5	7
	FR	n/a	1740	23	n/a	n/a	133	53	2	12	1800	285	n/a
	DeepPCB	3289	3900	1380	4020	4020	3660	4080	240	2340	4320	4020	4200
	Optimized-3D-A*	33	58	10	39	30	19	25	2	36	55	46	40
	3D LineExplore	23	119	2	23	11	4	4	2	6	26	28	24

First, in terms of routing completion rate, our proposed method is overall comparable to FreeRouting and ELECTRA. All three achieve a high routing completion rate and significantly outperform DeepPCB and Optimized-3D-A. Specifically, our method attains a routing completion rate close to 100% on most test cases, which shows its good feasibility and effectiveness for complex routing problems.On the benchmark bm1, the routing completion rate is slightly lower because it contains a large number of nets within only two layers and thus has limited routing resources. Unlike FreeRouting, which relies on multiple rounds of iterative optimization (e.g., rip-up and reroute) and trades longer runtime for a higher routing completion rate, 3D LineExplore uses a one-shot constructive strategy. This result confirms the advantage of our algorithm in ensuring routing success.

Second, regarding wirelength, our algorithm shows particularly strong performance. Experimental results indicate that, compared to ELECTRA, our method reduces wirelength by 15% on average. This improvement boosts signal efficiency, reduces delay. Shorter wirelengths imply more compact routing paths, minimizing signal attenuation and interference during transmission, thereby enhancing overall circuit performance.

With respect to via count, our algorithm exhibits slightly higher values in some cases compared to other methods. However, this trade-off maximizes routing space utilization and reduces wire congestion. The moderate increase in via count facilitates better distribution of routing paths, thereby reducing the risk of inter-wire interference and crosstalk.

Finally, in terms of runtime, our method performs similarly to ELECTRA, with most test cases completing within seconds, demonstrating high computational efficiency. In contrast, DeepPCB and Optimized-3D-A* exhibit significantly longer runtimes, making them less comparable. This indicates that our algorithm can rapidly generate high-quality routing solutions and possesses strong scalability, making it suitable for large-scale and complex routing scenarios.

In summary, the proposed method demonstrates superior performance in routability, wirelength, and runtime, while striking an optimal balance between via count and congestion control.

Via cost parameter analysis

To further investigate the impact of via cost on routing performance in the proposed method, this study evaluates five parameter settings for via cost: 0, 2, 5, 10, and 50. The experiments assess performance across four metrics: routing success rate, path length, number of vias, and runtime. The results are presented in Fig. 7, which respectively illustrate the experimental outcomes on the test set under different via cost values.

Fig. 7.

Metrics variation under different via costs.

As shown in the Fig. 7, when the via cost is set to 0, the number of #vias is highest, the routing success rate is relatively low for certain test cases (e.g., bm1), and the runtime is prolonged. As the via cost increases, the number of vias decreases significantly, the routing success rate improves, and the runtime shortens markedly. When the via cost exceeds 10, the reduction in via count begins to plateau; however, path length increases in some cases, indicating that an excessively high via cost forces the algorithm to select longer single-layer routes to avoid vias, thereby degrading overall routing quality.

In selecting the optimal parameter, we prioritize objectives hierarchically: first ensuring high routing success rate, then minimizing the number of vias, and finally balancing path length and runtime. A comprehensive comparison across all evaluated via costs reveals that a via cost of 2 yields the best overall trade-off. Specifically, it maintains a high routing success rate across all benchmarks while substantially reducing the number of vias (e.g., for bm9, the via count drops from 379 to 202) and achieving shorter path lengths and improved runtimes in most test cases. This balance arises because a very low via cost encourages excessive and unnecessary layer transitions, inflating via usage, whereas a very high via cost overly suppresses layer changes, compelling the router to take detours that increase wirelength and may even compromise routability. In contrast, a via cost of 2 effectively balances the suppression of redundant vias with the three-dimensional routing flexibility needed to achieve high routability. Consequently, all subsequent experiments in this work adopt a uniform via cost of 2.

Wire-shape optimization post-processing analysis

To further validate the impact of routing on routing quality and usability metrics, this paper introduces a wire-shape optimization algorithm. After the initial routing, all segments are converted to comply with geometric constraints.

Table 3 shows the changes in four key metrics before and after post-processing. The experimental results indicate that the post-processing slightly increases wire length (WL) and runtime (T), while other critical metrics, such as routability (RT) and number of vias (#Via), remain unchanged. For instance, across samples bm1 to bm11, the total wire length increases marginally after post-processing, but the change is limited. Meanwhile, routability (RT), via count (#Via), and runtime (T) show no significant differences between pre- and post-processing stages, maintaining the same levels. This suggests that post-processing has minimal impact on routing quality and efficiency.

Table 3.

Changes in metrics before and after post-processing.

Metric		bm1	bm2	bm3	bm4	bm5	bm6	bm7	bm8	bm9	bm10	bm11
RT (%)	Arbitrary angle routing	90	100	97	100	100	100	100	100	100	100	94
	Constrained routing	90	100	97	100	100	100	100	100	100	100	94
#Via	Arbitrary angle routing	133	13	104	90	40	46	0	17	269	139	105
	Constrained routing	133	13	104	90	40	46	0	17	269	139	105
WL (mm)	Arbitrary angle routing	3764	271	1046	938	551	734	82	1294	3518	1701	912
	Constrained routing	3960	284	1094	987	575	784	86	1342	3699	1782	933
T (s)	Arbitrary angle routing	117	1	21	10	3	3	1	5	24	26	23
	Constrained routing	119	2	23	11	4	4	2	6	26	28	24

This phenomenon results from the fact that the post-processing step only adjusts segment geometry without introducing new topological changes or rerouting. Accordingly, the post-processing is regarded as an optional geometric normalization step, excluded from the algorithm’s primary evaluation metrics. Its main role is to improve visual consistency and ensure compatibility with subsequent processes.

Case study

Two-layer case

Figure 8, illustrates the initial routing topology generated by the routing algorithm for test case bm1. No angular constraints are applied, and routing paths extend in arbitrary directions. As a result, the layout contains sharp angles and backtracking segments, resulting in a disorganized wire structure that fails to meet the geometric constraints of high-quality physical implementation.

Fig. 8.

Topology result of case bm1 (Yellow lines represent the first layer, green lines represent the second layer).

Figure 9 presents the routing result after applying the wire-shape optimization algorithm to the same topology. While maintaining connectivity and topology, the post-processing module reconstructs the angles of the segments so that all turning angles conform to , achieving angular regularization. The optimized routing paths exhibit smoother transitions and more natural angle changes, with the overall structure better aligned with industrial requirements for electromagnetic compatibility, manufacturability, and visual aesthetics.

Fig. 9.

Linear post-processing result of case bm1 (Yellow lines represent the first layer, green lines represent the second layer).

A comparison between Figs. 8 and 9 indicates that, while the post-processing step does not affect key metrics such as routability or via count, it markedly improves the geometric quality of the routing layout. This demonstrates that the post-processing method serves as an effective strategy for geometric standardization in PCB routing.

Four-layer case

To further evaluate the performance of the proposed 3D routing framework on multilayer printed circuit boards, we consider three 4-layer PCB benchmarks, denoted as case1, case2, and case3. These designs cover different scales of nets, components, and pins, and are intended to reflect practical multilayer routing scenarios. The configurations and routing results of the three benchmarks are summarized in Table 4. All designs are implemented on 4-layer PCBs, and the proposed method achieves a 100% routing completion rate on all of them, while maintaining reasonable total wirelength, via count, and runtime.

Table 4.

Configuration and routing results of the four-layer PCB benchmarks.

Design	Nets	Components	Pins	Layers	WL (mm)	RT (%)	#Via	T (s)
Case1	25	31	151	4	789	100%	45	3
Case2	53	27	171	4	1238	100%	92	8
Case3	48	31	189	4	920	100%	115	5

In addition, Fig. 10 presents the overall routing result of case2, while Fig. 11 shows the routing patterns of case2 on each individual layer. These results further demonstrate the effectiveness and scalability of the proposed approach for multilayer PCB designs.

Fig. 10.

Overall routing result of Case2.

Fig. 11.

Four layer routing results for Case 2.

Impact of search scope on efficiency and solution quality

To rigorously quantify the balance between routing efficiency and solution quality, we performed a trade-off analysis on five representative test cases (bm4, bm5, bm6, bm8, and case2). We evaluated the performance of the 3D LineExplore algorithm under three different exploration scope settings:

1. Adaptive neighborhood (proposed), where the algorithm adaptively determines the local neighborhood scope based on the positions of the start point s and the destination point d;

2. Half-board scope, where the exploration region is fixed to half the size of the PCB;

3. Full-board scope, where the exploration region covers the entire PCB.

Figure 12 illustrates the normalized trend of routing time, wire length, and via count across these settings. As the search scope expands from the adaptive local region to the full board, the routing time increases exponentially due to the rapid growth of the search graph and obstacle detection overhead. The proposed Adaptive method reduces the total routing time by over 90% compared to the Full-Board setting. This significant reduction demonstrates the algorithm’s high heuristic efficiency and suitability for time-critical industrial applications.

Fig. 12.

Normalized trade-off analysis between search efficiency (routing time) and path optimality (wire length/via count). Results are normalized against the “Full-Board” baseline (1.0).

Regarding path optimality, the reduction in the initial search space incurs only a minimal penalty on solution quality. The total wire length of the Adaptive method is only approximately 4.4% longer than that of the Full-Board global search. However, the via count shows a moderate increase ( 15%). This reflects a trade-off in routing flexibility: the restricted local scope limits the algorithm’s ability to explore extensive planar detours around large obstacles, leading it to prioritize vertical layer transitions (vias) to resolve congestion locally. Despite this, the increase is considered acceptable given the order-of-magnitude reduction in routing time.

Conclusion

This paper presents a 3D line-exploration-based geometric routing method for multi-layer PCBs, overcoming the resolution limitations of grid-based approaches and the constraints of 2D gridless methods in multi-layer routing. A radar-inspired scanning algorithm, combined with an obstacle-avoidance heuristic path optimization algorithm, enables efficient and high-precision routing in continuous space. In addition, a line-shape optimization post-processing step further improves path smoothness and compliance with design rules, ensuring industrial-grade routing quality.

Experimental results show that the proposed algorithm achieves an average routing completion rate of 98% across 11 public PCB datasets, outperforming state-of-the-art methods such as Freerouting, DeepPCB, and Optimized-3D-A* in both runtime and routed path length. These results validate the efficiency and reliability of the method for multi-layer PCB routing.

In the future, we will integrate intelligent algorithms to support larger-scale and higher-density PCB designs. Drawing inspiration from the methodology presented in LithoPW²⁹, we plan to incorporate visual memory encoding to capture global routing congestion features. Specifically, we aim to design a cooperative framework where a deep reinforcement learning (DRL) agent utilizes these encoded features to determine optimal scanning directions or priority regions. This global guidance will assist the Radar-scanning algorithm in generating higher-quality exploration points more efficiently, effectively bridging global planning with local precise detection.

Author contributions

N.S. proposed the main idea, designed the 3D LineExplore algorithm, conducted the experiments, and drafted and revised the manuscript, serving as the primary contributor to this study. J.Z. supervised the research, guided the methodological development, and critically revised the manuscript. N.X. contributed to the additional experiments and case studies in the revised version, and participated in addressing reviewers’ comments. C.Z. assisted in algorithm implementation, experimental setup, and data analysis. H.L. provided technical guidance, contributed to the experimental evaluation, and assisted in interpreting the results. Z.Y. provided academic guidance and contributed to conceptual refinement and manuscript review. J.H. provided high-level academic supervision, contributed to the refinement of the study’s scope and presentation during revision, and reviewed and edited the manuscript. All authors discussed the results and approved the final manuscript.

Funding

This work was supported in part by the National Natural Science Foundation of China under Grant 62441233, in part by the Science and Technology Planning Project of Guangdong Province under Grant 2024B1212020007, and in part by the Shenzhen Science and Technology Program under Grant JCYJ20220818102002005.

Data availability

The datasets used in this study are publicly available from open-source PCB benchmarks, including DeepPCB and FreeRouting. The data generated and analyzed during this study are available from the corresponding author upon reasonable request.

Declarations

Competing interests

The authors declare no competing interests.