SUBTRACTIVE NANOFLUIDICS IN 65-NM CMOS COPPER BEOL ACHIEVE 100-NM WIDTH

Abstract

This paper presents the first implementation of 100-nm-wide nanofluidics in a 65-nm CMOS chip using a one-step wet-etch to remove the copper routing from the back-end-of-line (BEOL) while maintaining transistor integrity through continuous monitoring of the I_DS-V_GS characteristics. Vertical fluidics are also successfully demonstrated by etching through 360 nm × 360 nm-sized vias. A non-destructive laser microscopy technique for imaging fluidic channels at a dimension below the visible-light wavelength is developed.

INTRODUCTION

Heterogeneous integration of CMOS electronics with microfluidics has emerged as a promising approach for future point-of-care (POC) devices by miniaturizing the device form factor and closing the gap between sensor and analyte [1], [2]. CMOS microfluidics enable rapid, low-cost, minimal-sample-volume diagnostics for real-time monitoring and eliminate the need for bulky benchtop equipment for sample analysis. However, conventional integration approaches, in which microfluidics and CMOS are prepared separately and assembled, suffer from limited alignment accuracy, low-throughput assembly, and size-constrained microfluidics [3], [4]. In contrast, “subtractive” microfluidics embed fluidic channels directly within a CMOS chip by selectively removing back-end metal routing (Fig. 1(a)), offering superior dimensional control and alignment precision, and is achieved with a single-step post-CMOS wet-etch [4], [5], [6]. The process is simple, requires no complex post-processing [7], [8], and can realize 3D fluidic networks by leveraging multilayer metallization. Moreover, the wet etch preserves CMOS functionality, enables tight integration of microfluidics with sensing circuits, and reduces routing parasitics that might otherwise dominate the signal chain. We have previously demonstrated subtractive microfluidics with several-μm-wide channels integrated with sensing circuits in a TSMC 180-nm process with an aluminum-based BEOL [5]. This paper achieves, for the first time, the creation of 100-nm-wide, 220-nm-tall nanofluidic channels as well as vertical channels using 360-nm × 360-nm-sized vias, without altering transistor I–V characteristics after 4 days of etchant immersion. This capability is demonstrated in a TSMC 65-nm process with a copper-based BEOL and opens new opportunities for highly sensitive nanofluidic-based biosensing.

Figure 1:

(a) Subtractive microfluidics in CMOS. (b) The die photo of a CMOS die with fluidic devices. Two 1:64 splitters are highlighted, one with (right) and one without (left) distributed pad openings.

SYSTEM ASSEMBLY AND WET ETCH PROCEDURE

Fig. 2 illustrates the device assembly and etching flow. The millimeter-sized CMOS chip is embedded within a printed circuit board (PCB) using a water-resistant epoxy (Epo-Tek 301) to level the PCB surface. Wirebonds, which provide electrical access between the chip and PCB, are also protected with the epoxy. Kapton tape is manually aligned and placed on the CMOS chip to define the etch area. The etchant (ammonium persulfate) is delivered through an elastic microfluidic (PDMS) and heated to 90° C with a 1-Ω resistor mounted to the backside of the CMOS die. Hydraulic pressure is applied at the inlets to promote etchant diffusion through the embedded fluidics. This process removes the metallization from 27 different-designed fluidics structures at varying metal layers in four days, except for the 1:64 fluidic splitter, which has excessively long, complex routing. To address the limited etchant diffusion, we included a second 1:64 fluidic splitter with distributed small pad openings at a size of 6 μm × 6 μm throughout the fluidic structure to increase the number of etchant access ports. These pad-openings are then sealed by PDMS fluidics that interface with the subtractive fluidic inlets and outlets. Due to the longer etching time compared to [4], [5], we characterize the transistor I-V properties throughout the etching process. A trans-impedance amplifier (TIA) using Texas Instruments’ OPA4354 is utilized to continuously monitor transistor drain currents.

Figure 2:

(a) Cross-sectional view of the wet etch procedure. (b) Bird’s-eye view of the system setup for the wet etch process.

EXPERIMENTAL RESULTS

Transistor characteristics

We monitor the transistor I-V characteristics throughout the four-day etching process as the circuit integrity is crucial to the validity of our prolonged wet etching procedure. Fig. 3 reports the measured I_DS-V_GS characteristics of thin-oxide NMOS and PMOS, and thick-oxide PMOS (five each). The changes in I-V results across four days are 0.3%, 1.9%, and 0.5%, respectively, which are within the measurement precision. Therefore, we conclude that prolonged etching does not impact the transistor performance. In other words, we believe that the four-day etching process will have a negligible effect on the sensing circuits that are co-integrated with the subtractive nanofluidics.

Figure 3:

The I_DS-V_GS characteristics of thin-oxide NMOS (4 μm / 240 nm), thin-oxide PMOS (4 μm / 240 nm), and thick-oxide PMOS (4 μm / 500 nm). Here we present one device from the measured five transistors from each group.

Creating 100-nm-width nanochannels

We use the 220-nm thick Metal-7 layer as our sacrificial layer to create the 100-nm width nanofluidic channels, whose width is constrained by the design rule requirements of the CMOS node. Two approaches are taken to determine the complete removal of the 100-nm-width fluidics. First, we utilize a 3D scanning laser microscope (Olympus LEXT OLS4000 3D) and integrate the reflected laser (λ = 405 nm) intensity at 1 μm above and below the target metal layer (Fig. 4(b)). Residue metal in the fluidics reflects brightly in the image in contrast to hollow fluidic channels (Fig. 4(c)) and can achieve spatial resolution equal or less than the laser wavelength. Crucially, there is no dummy metal below the fluidics or in the surrounding area, which allows an accurate comparison of the fluidic reflections in comparison to the CMOS passivation. Next, we verify the fluidic passage by monitoring green dye flowing through the channel, as shown in Fig. 4(d). Note that a well filled with green dye is created at the outlet, formed by removing the exposed “pad layer” consisting of the aluminum AP layer and the copper Metal-9 layers, followed by capping the well with the floor of the PDMS microfluidics for sample delivery.

Figure 4:

(a) The layout (left) and optical image (right) of the 100-nm channel. (b) Laser microscope image of the 100-nm-wide fluidic channel before and after etching. (c) A comparison of the cross-sectional laser intensity profiles from (b). (d) Fluid delivery through the 100-nm channel.

Vertical fluidics with metallization vias

We also implement vertical fluidics by etching away the 360-nm × 360-nm vias connecting Metal-8 and Metal-9. The two vias are required at minimum, constrained by the foundry design rules. We use the above-mentioned microscopy approach to determine the completion of the fluidics. Fig. 5(b) shows the laser microscope images before and after etching. The two via holes are clearly visibility after the etching, verifying the complete removal of the channel sacrificial metal. We further verify the flow with a fluidic passage experiment, as shown in Fig. 5(c).

Figure 5:

(a) The layout (top) and optical image (bottom) of the vertical fluidics using vias. (b) Laser microscope image of the vertical fluidics before and after etching. (c) Fluid delivery through the vertical via channel.

Other subtractive fluidic structures

We demonstrate various fully-etched subtractive fluidics formed using different layers of metallization and geometry (Fig. 6). Notably, the 1:64 splitter without pad openings is not fully etched after four days (Fig. 6(b)). This is due to the excessively long distance between the fluidic inlets/outlets that limits the etchant mass transport. We thus incorporate pad openings across the fluidics to increase the number of etchant access points. An identical 1:64 splitter with pad openings confirms the complete removal of the sacrificial metal (Fig. 6(c)).

Figure 6:

Device photos before and after wet-etching. (a) 1:4, 1:8, 1:16 splitters are fully etched while (b) the 1:64 splitter without distributed pad-openings cannot be fully etched due to etchant diffusion limitation. (c) Metal from 1:64 splitter with distributed pad-openings is fully etched. (d) The device photo of an array of sixteen fully-etched 100-nm channels (e) M8 routing of widths 2, 6, 10 μm, as well as a micromixer, are successfully demonstrated.

CONCLUSION

This work presents the first subtractive nanofluidics in CMOS, achieving fluidic cross-sectional area as small as 100 nm × 220 nm, as well as vertical fluidics with cross-sectional area of 360 nm × 360 nm. We develop a novel microscopy technique to nondestructively image the embedded nanofluidic structures. We also report no transistor performance impact due to the etching process. Table 1 provides a comparison to other prior works.

Table 1:

The comparisons to prior work.

	This work	[5]	[4]	[7]	[8]
Technology	65-nm CMOS	180-nm CMOS	180-nm CMOS	65-nm CMOS	55-nm CMOS
Fluidic cross-sectional area	100 nm × 220 nm (horizontal) 360 nm × 360 nm (vertical)	6 μm × 0.53 pm	8 μm × 0.53 pm	8 μm × 100 nm	1.5 μm width*
Microfluidic process	Copper BEOL Wet etch	Aluminum BEOL Wet etch	Aluminum BEOL Wet etch	Polysilicon gate Reactive ion etch	Polysilicon gate Reactive ion etch
Critical steps	1	1	1	3	3
Transistor survival time in etchant	4 days	20 hours	25 hours	N/A, photodiode	N/A, photodiode

^*Estimated from micrograph, thickness not available from [8].