A First-Principles Study of Monolayer B₄Cl₄: Structural Stability, Anisotropic Electronic Properties, and Ballistic Transport Projections in Sub‑5 nm MOSFETs

Abstract

As traditional semiconductor technologies approach their physical limits, exploring novel two-dimensional materials has become imperative. This study systematically investigates the crystal configuration, structural stability, and electronic properties of chlorinated graphene-like boronene (B₄Cl₄), as well as its potential in metal-oxide-semiconductor field-effect transistor (MOSFET) applications, via first-principles calculations. Incorporating chlorine enhances B₄Cl₄’s structural stability and induces anisotropic electronic properties. N-type and p-type B₄Cl₄-based MOSFET prototypes with different channel lengths are designed to assess the quantum transport limits. Results show that n-type MOSFETs with gate lengths of 5.0 and 4.0 nm meet the International Technology Roadmap for Semiconductors (ITRS) high-performance requirements. Specifically, the 5.0 nm device exhibiting x-directional transport has a subthreshold swing near the theoretical limit of conventional MOSFETs, while the 5.0 nm device exhibiting y-directional transport shows an on-state current 170.63% higher than those of ITRS benchmarks. Optimizing the underlap region extends the compliant gate lengths to 3.0 nm, yielding five devices in which the intrinsic delay and power-delay product are 1 order of magnitude below ITRS standards. This underscores the theoretical potential of B₄Cl₄ as a channel material in next-generation advanced nanoelectronic devices.

1. Introduction

Over the past few decades, the application of semiconductor materials in electronic devices has been a core driver of scientific research and industrial development. However, as Moore’s Law approaches its physical limits, the scope for optimizing traditional silicon-based technologies in terms of performance, power consumption, and dimensional scaling is increasingly constrained. This constraint has accelerated the pursuit of novel materials and device architectures to meet the demanding requirements of post-silicon information technology for higher performance, lower power consumption, and smaller transistor sizes. Two-dimensional (2D) materials, with their atomic-scale thickness, exceptional electrical and mechanical properties, and potential for nanoelectronic applications, have emerged as a frontier research topic in nanoelectronics. , Among these, graphene has garnered global attention since its first successful exfoliation in 2004 due to its exceptionally high carrier mobility and mechanical strength. , However, the absence of an intrinsic bandgap has limited its direct application in field-effect transistors (FETs). To overcome this obstacle, researchers have turned their attention to other 2D materials with suitable bandgaps, , such as transition metal dichalcogenides (TMDs), black phosphorus, and SnSe₂. These materials, with their unique electronic structures and tunability, are considered strong candidates for next-generation electronic devices. Additionally, antimonene has gained attention for next-generation 2D electronics due to its semimetal–semiconductor transition.

As an emerging 2D material, boronene has attracted significant academic interest due to its unique electronic structure, low density, high mechanical strength, and polymorphic phases (including α, β₁₂, δ₆, and χ₃ phases). − In recent years, functionalized boronene derivatives have been further optimized to enhance their structural stability and electronic properties, propelling them to the forefront of research. These derivatives retain the intrinsic superior properties of pristine boronene while demonstrating broad application prospects in nanoelectronic devices. , Despite significant progress in theoretical research and experimental synthesis of 2D materials, numerous challenges remain in their application to metal-oxide-semiconductor field-effect transistors (MOSFETs) at 10 nm and below technology nodes. Moreover, most current research focuses on mature 2D materials (e.g., TMDs and black phosphorus), while exploration of emerging boronene and its derivatives remains relatively underdeveloped, particularly in device-level integration and performance optimization. − Although theoretical studies have demonstrated the potential of boron halide borophene in FETs, their fundamental physical properties and device performance limits remain underexplored. Investigating critical parameters that define device performance limitssuch as on-state current, subthreshold swing (SS), delay time, and power-delay product (PDP)is crucial for advancing post-silicon device technologies. In-depth analysis of these parameters not only reveals device behavior under extreme operating conditions but also provides critical insights and theoretical references for achieving smaller dimensions and higher energy efficiency in next-generation electronic devices. Therefore, systematic investigation of the fundamental physical properties of the 2D boron halide B₄Cl₄ and its performance limits in MOSFETs has become an urgent critical issue in the field of nanoelectronics. Recent experimental demonstrations of 2D CMOS logic and 3D integration with 2D materials provide benchmarks for such theoretical studies.

Using first-principles calculations based on density functional theory (DFT), we systematically investigated the structural stability, mechanical properties, and electronic characteristics of 2D monolayer B₄Cl₄. Concurrently, we incorporated quantum transport simulations to explore the performance limits of monolayer B₄Cl₄ in MOSFETs. Through in-depth analysis of its electronic transport characteristics across different channel lengths, we revealed the application potential of 2D B₄Cl₄ in MOSFETs, particularly in sub-5.0 nm technology node MOSFETs. Specifically, we demonstrate that B₄Cl₄-based MOSFETs exhibit an outstanding device performance. Key performance metricsincluding on-state current, total gate capacitance, delay time, and PDPmeet the requirements of the International Technology Roadmap for Semiconductors (ITRS, 2013 edition). These properties render the material suitable for designing high-performance (HP) devices at the 3 nm technology node, indicating its potential as a channel material in advanced electronic devices. This study provides a comprehensive and in-depth theoretical analysis of the application of 2D B₄Cl₄ in ultra-scaled MOSFETs, laying a theoretical foundation for further exploration of this material in nanoelectronics.

2. Methods and Computational Details

The computational work in this study, including structural optimization, electronic property calculations, and quantum transport simulations, was performed using Quantum Atomistix ToolKit software. , This approach combines first-principles calculations based on DFT with nonequilibrium Green’s function methods. The exchange-correlation between electrons was handled using the generalized gradient approximation with the Perdew–Burke–Ernzerhof (PBE) formalism. The electron wave functions were expanded via the linear combination of atomic orbitals method, using the Fritz Haber Institute (FHI) pseudopotential and the double zeta polarized basis set. To balance computational efficiency and accuracy, the density grid cutoff was set to 75 hartree, and Monkhorst–Pack grids were employed for k-point samplingwith resolutions of 27 × 27 × 1 for the unit cell and 27 × 1 × 200 for the device Brillouin zone along the x, y, and z directions, respectively. Self-consistent field iteration and atomic force convergence criteria were set to 10^–5 eV and 10^–2 eV·Å^–1, respectively. To eliminate spurious interactions between the model and its adjacent periodic images, a vacuum layer exceeding 3.0 nm was introduced. For simplicity, the Fermi level was set to zero for all systems. Furthermore, during quantum transport simulations, boundary conditions along the x, y, and z directions were set to Periodic, Neumann, and Dirichlet, respectively, to mimic crystal periodicity and the device’s interaction with the external environment. The electron temperature was set to 300 K, and atomic charge compensation was employed to dope the source and drain electrodesthis approach achieves n-type or p-type doping by adjusting the electron density relative to the neutral state. In practice, electrostatic doping can be used to adjust the Fermi level and thereby simulate doping effects.

The drain–source current (I _ds) under a specified drain bias (V _ds) and gate voltage (V _g) is calculated using the following Landauer–Büttiker formula:

$$I_{\mathrm{d}\mathrm{s}}(V_{\mathrm{d}\mathrm{s}},V_{\mathrm{g}})=\frac{2e}{h}{\int }_{-\infty }^{+\infty }T(E,V_{\mathrm{d}\mathrm{s}},V_{\mathrm{g}})[f_{\mathrm{d}}(E-{\mu }_{\mathrm{d}})-f_{\mathrm{s}}(E-{\mu }_{\mathrm{s}})]\mathrm{d}E$$ 1

Herein, T(E, V _ds, V _g) denotes the transmission probability at a specified bias and gate voltage, while f _s/d and μ_s/d represent the Fermi–Dirac distribution function and electrochemical potential of the source/drain, respectively. The transmission coefficient T(E, k _x ) for electrons at a specific energy E and wave vector k _x is defined as

$$T(E,k_x)=\mathrm{T}\mathrm{r}[G^{\mathrm{r}}(E,k_x)·{\mathrm{\Gamma }}_{\mathrm{s}}(E,k_x)·G^{\mathrm{a}}(E,k_x)·{\mathrm{\Gamma }}_{\mathrm{d}}(E,k_x)]$$ 2

In the formula, G ^r/a(E, k _x ) represents the retarded/advanced Green’s function, while ${\mathrm{\Gamma }}_{\mathrm{s}/\mathrm{d}}(E,k_x)=i[\sum _{s/d}^{\mathrm{r}}(E,k_x)-\sum _{\mathrm{s}/\mathrm{d}}^{\mathrm{a}}(E,k_x)]$ denotes the energy-level line width function caused by the source/drain electrodes (expressed as the electrode’s intrinsic energy $\sum _{\mathrm{s}/\mathrm{d}}^{\mathrm{r}/\mathrm{a}}(E,k_x)$ ). This function reflects the coupling effect of the electrodes on the scattering region.

3. Results and Discussion

3.1. Crystal Structure, Structural Stability, Mechanical Properties, and Electronic Properties of Monolayer B₄Cl₄

Graphene-like boronene exhibits a hexagonal lattice analogous to graphene, forming a 2D planar structure composed of sp²-hybridized boron atoms. However, pristine graphene-like boronene is structurally unstable. This instability primarily arises from the fact that boron (B) atomspossessing only three valence electronsform partially occupied in-plane σ bonds and out-of-plane π bonds in the self-supported honeycomb boronene. Unlike carbon atoms in graphene, boron atoms cannot establish stable delocalized π bonds. Fortunately, incorporating functional groups capable of donating additional electrons into the boronene structure can enhance its stability. ,− Experimentally, hydrogenated boronene sheets have been successfully synthesized via ion exchange processes and exfoliation. , As shown in Figure a, halogenation of graphene-like boronene with Cl atoms (forming B₄Cl₄) induces partial cleavage of the B–B bonds. Coplanar B atoms are now sandwiched between two layers of Cl atoms, which form a rectangular lattice. This structural transformation alters the bonding patterns of boron atoms, modifies the space group symmetry (from Cmmm to P6/mmm), changes the atomic structure from isotropic to anisotropic, and adjusts the electronic structure. The lattice constants of monolayer B₄Cl₄ are α = 3.19 Å and b = 6.79 Å, consistent with previous reports. ,,

1.

Crystal structure and fundamental properties of monolayer B₄Cl₄: (a) top and side views of the crystal structure, (b) simplified Brillouin zone, (c) phonon spectrum, (d) phonon density of states, (e) ab initio molecular dynamics (AIMD) simulations at room temperature (300 K), (f) elastic constants, (g) orientation-dependent Young’s modulus, and (h) orientation-dependent Poisson’s ratio.

Following a detailed description of the crystal characteristics of monolayer B₄Cl₄, we first evaluated its thermodynamic stability via cohesive energy (E _coh) calculations as the initial verification step. The cohesive energy formula for monolayer B₄Cl₄ is given by

$$E_{\mathrm{c}\mathrm{o}\mathrm{h}}=(E_{\mathrm{t}\mathrm{o}\mathrm{t}}-\sum n_i{E}_i)/\sum n_i$$ 3

where E _tot denotes the total energy of fully relaxed monolayer B₄Cl₄, while E _i and n _i represent the total energy of an isolated atom (B or Cl) and the number of corresponding atoms (B and Cl) in the unit cell, respectively. Calculations yield a cohesive energy of −4.97 eV/atom for monolayer B₄Cl₄, indicating its energetic advantage over the isolated atomic state and thus confirming the thermodynamic stability. Subsequently, we assessed dynamic stability by analyzing the phonon spectrum and phonon density of states. As shown in Figure c, the phonon spectrum of monolayer B₄Cl₄ comprises three acoustic branches and 21 optical branches. Among these, the in-plane longitudinal acoustic and transverse acoustic branches exhibit linear dispersion near the high-symmetry Γ point, while the out-of-plane acoustic (FA) branch shows parabolic dispersion. Notably, the phonon spectrum exhibits no imaginary frequencies across the entire Brillouin zone, and the phonon density of states remains positive throughout (Figure d). This confirms that the structure resides at a local energy minimum and is stable against small atomic displacement perturbations, which verify its dynamic stability. This stability is attributed to the formation of three-center two-electron (3c-2e) B–Cl–B bonds, where two boron atoms share two electrons via a bridging Cl atomenabling electron delocalization among the three atoms and reducing the total system energy. Additionally, monolayer B₄Cl₄ contains the more common two-center two-electron (2c–2e) B–B covalent bonds, where two boron atoms share two electrons (Figure a).

To investigate the thermal stability of monolayer B₄Cl₄, we performed AIMD simulations on a 3 × 4 supercell at room temperature (300 K) under the NVT ensemble with a Nosé–Hoover thermal bath. As shown in Figure e, we observed minimal structural fluctuations throughout the 100 ps simulation with no structural disintegration or bond cleavage. This confirms that monolayer B₄Cl₄ maintains structural integrity under room-temperature thermal agitation, demonstrating excellent thermal stability. Finally, following verification of multi-aspect stability, we evaluated mechanical stability using the Born–Huang criteria (C ₁₁ C ₂₂ – C ₁₂ ² > 0 and C ₆₆ > 0). Elastic constants (C ₁₁, C ₂₂, C ₁₂, and C ₆₆) were obtained by fitting the relationship between strain energy per unit area (E _s) and strain, using the following equations:

$$E_{\mathrm{s}}(\epsilon )=\frac{1}{2}{C}_{11}{\epsilon }_x^2+\frac{1}{2}{C}_{22}{\epsilon }_y^2+C_{12}{\epsilon }_x{\epsilon }_y+2C_{66}{\epsilon }_{xy}^2$$ 4

where ε _x and ε _y denote uniaxial strains along the zigzag and armchair directions, respectively, and ε _xy represents in-plane shear strain. The calculated elastic constants (Figure f) clearly confirm the excellent mechanical stability of monolayer B₄Cl₄.

Based on this, we further investigated the mechanical properties of the monolayer under strain, including in-plane Young’s modulus (Y _2D) and Poisson’s ratio (υ). Young’s modulus, defined as the slope of the stress–strain curve within the elastic deformation range, characterizes material stiffness. The direction-dependent Young’s modulus of monolayer B₄Cl₄ is calculated using

$$Y_{2\mathrm{D}}(\theta )=\frac{C_{11}{C}_{22}-C_{12}^2}{C_{11}{A}^4+(\frac{C_{11}{C}_{22}-C_{12}^2}{C_{66}}-2C_{12})A^2{B}^2+C_{22}{B}^4}$$ 5

where A and B represent sin θ and cos θ, respectively. As shown in Figure g, Young’s modulus of monolayer B₄Cl₄ exhibits significant anisotropy: the maximum value (123.25 N/m) occurs along the zigzag direction, comparable to that of fully hydrogenated 2-Pmmn-phase boronene, while the minimum (61.66 N/m) appears at angles of 56°, 124°, 236°, and 304° relative to the zigzag direction. Poisson’s ratio is a key mechanical parameter describing transverse deformation response: materials with positive Poisson’s ratio contract/expand perpendicularly to the strain direction under uniaxial tension/compression, while those with negative Poisson’s ratio exhibit the opposite behaviorendowing them with unique mechanical properties. The direction-dependent Poisson’s ratio is calculated using

$$\nu (\theta )=\frac{C_{12}(A^4+B^4)-(C_{11}+C_{22}-\frac{C_{11}{C}_{22}-C_{12}^2}{C_{66}})A^2{B}^2}{C_{11}{A}^4+(\frac{C_{11}{C}_{22}-C_{12}^2}{C_{66}}-2C_{12})A^2{B}^2+C_{22}{B}^4}$$ 6

where A and B represent sin θ and cos θ, respectively. As shown in Figure h, all Poisson’s ratios are positive and exhibit distinct anisotropy: the maximum value (0.336) occurs at angles of 40°, 140°, 220°, and 320° relative to the zigzag direction, while the minimum (0.055) appears along the armchair directioncomparable to those of B₄F and B₂F.

To further understand the electronic properties and potential applications of monolayer B₄Cl₄, we calculated its band structure (Figure a). We observe that both the conduction band minimum (CBM) and valence band maximum (VBM) of monolayer B₄Cl₄ are located at the high-symmetry Γ point, confirming it as a direct-bandgap semiconductor with a bandgap of 1.43 eV. To further elaborate on its electronic structure, we calculated the projected density of states (PDOS), as shown in Figure b. The PDOS clearly reveals that the CBM is primarily contributed by B-p_z atomic orbitals, while the VBM is jointly contributed by B-p _x and Cl-p_x atomic orbitals. Near the VBM, the overlapping density of states of Cl and B atoms indicates significant hybridization between their p_x orbitals, along with pronounced p-orbital character in B–Cl bonding. Notably, during analysis of the electronic band structure, we observed pronounced directional anisotropy in band dispersion near both the CBM and VBMthis finding is crucial for elucidating the electronic transport mechanisms of monolayer B₄Cl₄. To intuitively illustrate the directional dependence of carrier mobility, we present a local magnification of the band structure near the CBM and VBM (Figure c). This clearly shows differences in band dispersion along the high-symmetry Γ–X and Γ–Y paths, which directly correlate with the carrier transport behavior across different crystal orientations. Specifically, the CBM exhibits steeper dispersion along the y-direction (armchair) than the x-direction (zigzag), indicating a smaller electron effective mass in the y-direction and thus enhanced electron transport. Conversely, the VBM shows reversed dispersion characteristics: steeper dispersion along the x-direction (zigzag) suggests higher hole mobility in this orientation.

2.

Electronic properties of monolayer B₄Cl₄ and the structure of B₄Cl₄-based MOSFET: (a) band structure, (b) DOS, (c) E–k dispersion near the CBM and VBM, and (d) effective masses of electrons and holes for monolayer B₄Cl₄. (e) Top and (f) side view of the B₄Cl₄-based double-gate MOSFET structure.

To quantify this anisotropic behavior, we calculated the effective masses of electrons and holes in different directions (Figure d). Results show that the electron effective mass is 0.89m ₀ in the x-direction, decreasing to 0.329m ₀ in the y-direction. In contrast, holes exhibit a lower effective mass (0.482m ₀) in the x-direction, which increases to 1.254m ₀ in the y-direction. This distinct anisotropy is closely associated with the atomic arrangement and orbital hybridization in monolayer B₄Cl₄: the introduction of Cl atoms not only modifies the electronic structure of boron atoms but also alters the overall electronic distribution of the monolayer via B–Cl bonds, thereby regulating carrier effective masses. This unique carrier effective mass anisotropy provides novel insights for designing directionally optimized electronic devicesfor example, the high electron mobility in the y-direction could be exploited to develop HP n-type MOSFETs.

3.2. Transport Properties of Monolayer B₄Cl₄-Based MOSFETs

After thoroughly investigating the electronic properties of monolayer B₄Cl₄ and the anisotropy of its carrier effective mass, we employed quantum transport simulations to explore how these physical characteristics translate into practical performance advantages for electronic devicesa crucial step for comprehensively evaluating its application prospects in electronics. As shown in Figure e,f, we designed n-type and p-type double-gated MOSFET prototypes based on monolayer B₄Cl₄. The device model comprises source/drain electrodes, a central scattering region, and an underlap (UL) region (non-gated channel segment between electrodes and the gate) that acts as an extension of the channel to mitigate short-channel effects (SCE), as detailed in Figure e,f. In the potential profile, this UL region exhibits a gradual modulation of the potential barrier under an applied bias, effectively increasing the effective tunneling distance and suppressing source–drain leakage. The source/drain electrodes consist of monolayer B₄Cl₄ doped using the atomic charge compensation method at a concentration of 3 × 10¹³ cm^–2 (corresponding charge density of 0.0081 e/atom), while the central scattering region and UL structure are formed from intrinsic monolayer B₄Cl₄. This doping level corresponds to typical bulk concentrations of 10¹⁹–10²¹ cm^–3, facilitating effective carrier injection in 2D systems. In accordance with ITRS requirements for devices at nodes ≤5.1 nm (Table ), the equivalent oxide thickness (EOT) on both sides of the central scattering region is set to 0.41 nm, and the supply voltage (V _dd) is 0.64 V. HfO₂ (ε_r = 25.0) is used as the dielectric oxide in the MOSFET design. Note that PBE underestimates the bandgap, and simulations are fully ballistic with ideal contacts and ultra-thin EOT, yielding upper bounds on performance by neglecting scattering and contact resistance. However, screening from heavy doping and high-κ dielectrics renormalizes the quasiparticle bandgap to DFT levels, making PBE reliable, as validated by experimental matches in MoSe₂ (1.52 eV) and MoS₂ (1.86 eV) , FETs, and simulations aligning with CNT , and MoS₂ data.

1. ITRS 2013 Key Performance Parameter Requirements for High-Performance (HP) and Low-Power (LP) FETs: Gate Length (L _g), Off-State Current (I _off), On-State Current (I _on), Channel Capacitance (C _g), Intrinsic Delay Time (τ), and Power-Delay Product (PDP).

	L g (nm)	I off (μA/μm)	I on (μA/μm)	C g (fF/μm)	τ (ps)	PDP (fJ/μm)
ITRS HP 2028	≤5.1	0.1	900	0.60	0.423	0.24
ITRS LP 2028	≤5.1	5 × 10–5	295	0.69	1.493	0.28

On-state current (I _on) is a key parameter for evaluating the MOSFET performance, derived from the transfer characteristic curve. It refers to the drain–source current when the device is on, directly impacting operating speed and power consumptionhigher I _on typically corresponds to faster switching speed and stronger drive capability. I _on is determined from the current at the on-state gate voltage (V _g(ON) = V _g(OFF) + |V _dd|), where V _g(OFF) is the off-state gate voltage. Quantum transport simulations reveal that n-type B₄Cl₄-based MOSFETs with x-directional transport meet ITRS HP off-state requirements for gate lengths (L _g) of 2.0–5.0 nm, and low-power (LP) off-state criteria for L _g = 3.0–5.0 nm. At L _g = 4.0 and 5.0 nm, these devices exhibit I _on > 900 μA/μm, satisfying the ITRS 2028 HP standard (Figure a). However, converting to p-type MOSFETs results in failure to turn off for all p-type devices (Figure b), despite lower hole effective mass in the x-direction (0.482m ₀ vs 0.89m ₀ for electrons), likely due to p-doping challenges and unfavorable band alignment causing higher leakage. As shown in Figure c,d, for y-directional transport, n-type MOSFETs still meet HP off-state requirements at L _g = 2.0–5.0 nm, while p-type devices fail, attributable to higher hole effective mass (1.254m ₀ vs 0.329m ₀ for electrons) suppressing mobility. Enabling viable p-FETs may require heterostructures for better hole injection, strain to tune band dispersion, or functionalization for stable doping. At L _g = 4.0 and 5.0 nm, they exceed ITRS HP I _on criteria and meet LP off-state requirements, but all p-type devices still fail to turn off effectivelyindicating that suppressed hole mobility is the key limiting factor for p-type performance. In summary, B₄Cl₄-based MOSFETs exhibit excellent n-type characteristics: when meeting ITRS HP standards, y-directional transport outperforms x-directional transport. This anisotropic advantage enables a higher current density and lower power consumption in the y-direction. Particularly at L _g = 4.0 and 5.0 nm, devices surpass ITRS HP I _on standards for both transport directions, demonstrating great potential as next-generation HP electronic devices.

3.

Transfer characteristic curves of sub-5.0 nm MOSFETs based on monolayer B₄Cl₄: (a) n-type and (b) p-type MOSFETs with x-direction transport; (c) n-type and (d) p-type MOSFETs with y-direction transport (UL = 0.0 nm). The light gray dashed line and light blue dashed line represent the ITRS requirements for off-state current (I _off) in HP devices (0.1 μA/μm) and LP devices (5 × 10^–5 μA/μm), respectively.

To further optimize the device structure, we introduced an UL region to increase effective channel length and suppress leakage current, aiming to scale ITRS-compliant MOSFETs to shorter channel lengths. As shown in Figure , quantum transport simulations systematically investigated the transfer characteristics of n-type MOSFETs under different L _g and UL lengths. Results indicate that all devices except the x-directional n-type MOSFET with L _g = 3.0 nm exhibit significant I _on enhancement under appropriate UL lengths. For example: 1. X-directional n-type MOSFET (L _g = 2.0 nm): 357.75% increase in HP-I _on at UL = 1.0 nm (vs no UL). 2. Y-directional n-type MOSFET (L _g = 2.0 nm): 2016.97% increase in HP-I _on at UL = 2.0 nm (vs no UL). However, further increasing the UL length leads to a decrease in I _on. The underlying physical mechanism stems mainly from the dual effects of the UL region on leakage current and gate controllability: 1. Appropriate UL size effectively suppresses source–drain leakage current by mitigating SCE and reducing non-ideal current leakage, thereby enhancing I _on. 2. Excessively long UL impairs gate controllabilitythe gate electric field cannot effectively regulate the distant channel region, weakening charge modulation and reducing I _on. This is particularly pronounced in ultra-short-channel MOSFETs, where gate controllability becomes critical as channel length decreases; overly long UL may even negate the inherent SCE suppression advantage. Overall, strategic UL length selection can effectively suppress leakage current and enhance I _on without compromising gate controllability, providing a viable optimization strategy for next-generation ultra-short-channel LP devices. UL integration will become a key design approach for performance enhancement in future ultra-large-scale integrated circuits.

4.

Transfer characteristics of monolayer B₄Cl₄-based n-type MOSFETs with x-direction transport at different UL lengths: (a) L _g = 1.0 nm, (b) L _g = 2.0 nm, and (c) L _g = 3.0 nm. Transfer characteristics of n-type MOSFETs with y-direction transport at different UL lengths: (d) L _g = 1.0 nm, (e) L _g = 2.0 nm, and (f) L _g = 3.0 nm.

Previous studies indicate that p-type MOSFET performance degradation primarily stems from material property differences and carrier transport mechanisms. Compared with electron mobility in n-type devices, hole mobility is lower in p-type MOSFETs, resulting in a weaker transport capability under the same bias. Larger hole effective mass also makes leakage current control more challenging in nanoscale devices, leading to higher off-state voltages and lower energy efficiency. Furthermore, UL introduction does not effectively improve hole mobility (Figure ); in some cases, distinct carrier dynamics exacerbate leakage current, further degrading performance. Thus, p-type MOSFETs cannot achieve the same I _on enhancement as n-type devices with UL optimization. The performance bottleneck of p-type devices arises from inherent material properties, rendering them unable to meet the HP device requirements in most scenarios. In summary, while UL optimization delivers substantial gains for n-type MOSFETs, its effectiveness for p-type devices remains limitedindicating that material selection and UL optimization for n-type MOSFETs will be pivotal in future B₄Cl₄-based ultra-short-channel device design, whereas p-type devices require alternative improvement strategies.

5.

Transfer characteristics of monolayer B₄Cl₄-based p-type HP-MOSFETs with x-direction transport at different UL lengths: (a) L _g = 1.0 nm, (b) L _g = 2.0 nm, (c) L _g = 3.0 nm, (d) L _g = 4.0 nm, and (e) L _g = 5.0 nm. Transfer characteristics of monolayer B₄Cl₄-based p-type HP-MOSFETs with y-direction transport at different UL lengths: (f) L _g = 1.0 nm, (g) L _g = 2.0 nm, (h) L _g = 3.0 nm, (i) L _g = 4.0 nm, and (j) L _g = 5.0 nm.

To further investigate ITRS’s influence on HP device switching behavior and the UL region’s performance regulation role, we analyzed y-directional n-type MOSFETs with three configurations: L _g = 4.0 nm, UL = 0.0 nm; L _g = 3.0 nm, UL = 1.0 nm; and L _g = 3.0 nm, UL = 2.0 nm (Figure ). Spectral current reveals an internal current distribution, projected local density of states (PLDOS) reflects channel charge distribution, and transmission spectra characterize electron transmission probability (directly correlating with transport efficiency). In the off-state, spectral current is divided into thermal electron current (I _thermal) and tunneling current (I _tunnel) (Figure a,g,m), with I _tunnel accounting for a significant proportionindicating that interband tunneling effects are difficult to fully suppress. In the on-state, spectral current is entirely contributed by I _thermal, with no tunneling effects (Figure d,j,p). PLDOS shows that all devices exhibit a high effective electron barrier (Φ_B) in the off-state (the maximum energy barrier for electron transport from source to drain; Figure b,h,n), which divides the spectral current into I _thermal and I _tunnel. In the on-state, Φ_B disappears, and electron transport is dominated by I _thermal (Figure e,k,q). Transmission spectra confirm lower transmission probabilities in the off-state than in the on-state, indicating stronger current-blocking capability. Comparing L _g = 3.0 nm devices with different UL values: the UL = 1.0 nm device exhibits superior transport performance (I _on = 988.00 μA/μm, meeting ITRS HP standards), while I _on drops to 522.41 μA/μm at UL = 2.0 nm (failing to meet ITRS HP requirements; Figure f). This decrease stems from additional resistance introduced by the UL. As shown in Figure k,q, the UL region’s regulatory effect arises primarily from altering electron tunneling distance and channel charge distribution: the L _g = 3.0 nm, UL = 1.0 nm device exhibits shorter electron tunneling distance, higher electron density, and broader electron distribution in the channel under on-state conditions, explaining its superior performance.

6.

Spectral currents, PLDOS, and transmission spectra of monolayer B₄Cl₄-based n-type HP-MOSFETs with y-direction transport: (a–c) off-state and (d–f) on-state for L _g = 4.0 nm, UL = 0.0 nm; (g–i) off-state and (j–l) on-state for L _g = 3.0 nm, UL = 1.0 nm; and (m–o) off-state and (p–r) on-state for L _g = 3.0 nm, UL = 2.0 nm.

The difference between I _on and off-state current (I _off) originates from the device’s electron transport mechanism: On-state: The device conducts, electrons possess energy exceeding the channel potential barrier, and I _thermal dominateselectrons traverse the channel with high kinetic energy, generating large current. I _on is closely related to the carrier mobility and gate controllability. Off-state: Electrons must overcome Φ_B for transport, so I _tunnel becomes the main current sourceespecially in ultra-short-channel devices where interband tunneling is hard to suppress, leading to large I _off. Effectively suppressing tunneling current and enhancing gate controllability are key to reducing I _off. The primary purpose of UL introduction is to mitigate SCE and enhance gate controllability by extending electron transport paths. By regulating channel potential distribution, the UL region reduces leakage current, diminishes tunneling-induced I _tunnel, and increases I _on through two mechanisms:

• 1.SCE reduction: Appropriate UL weakens direct source–drain coupling, strengthens gate control over the channel, suppresses SCE, and improves I _on and current-switching ratio.
• 2.Electron potential barrier and tunneling regulation: UL reduces Φ_B, decreasing off-state I _tunnel and improving turn-off performance. Simultaneously, it enhances channel electron transport efficiency by regulating electron state distribution.

To comprehensively elucidate B₄Cl₄-based MOSFET performance, we evaluated key parameters of ITRS HP-compliant devices (all n-type, as noted earlier). For clarity, transport direction is indicated by subscripts in “UL” (e.g., L _g = 5.0 nm, UL _x = 0.0 nm denotes x-directional transport with no UL). As shown in Figure a, all five MOSFETs exhibit I _on values exceeding the ITRS standard. The L _g = 5.0 nm, UL _y = 0.0 nm device performs best, surpassing the ITRS standard by 170.63%a 129.87% improvement over the L _g = 5.0 nm, UL _x = 0.0 nm device. Subthreshold swing (SS = ∂V _g/∂log­(I _ds), where V _g = gate voltage, I _ds = drain–source current) characterizes switching behavior, defined as the gate voltage required to change I _ds by 1 order of magnitude. Smaller SS indicates a better switching performance (effective on/off at lower V _g). As shown in Figure b, the SS ranges from 60.98 to 113.52 mV/dec, reflecting device SS characteristics under different structures. Notably, x-directional devices exhibit lower SS at the same L _g (superior gate controllability), with the L _g = 5.0 nm, UL _x = 0.0 nm device showing SS remarkably close to the conventional semiconductor theoretical limit. This near-limit performance enables high energy efficiency in switching (substantial current modulation with minimal V _g variation), conferring advantages in LP applications while meeting high-speed device switching demands.

7.

Evaluation of key performance metrics for n-type monolayer B₄Cl₄-based MOSFETs meeting ITRS HP 2028: (a) On-state current (I _on), (b) SS, (c) transconductance (g _m), (d) total gate capacitance (C _g), (e) intrinsic delay time (τ), and (f) PDP.

Transconductance (g _m = dI _ds/dV _g) characterizes transistor gain, reflecting the current-driving capability. As shown in Figure c, the L _g = 5.0 nm, UL _y = 0.0 nm device exhibits the highest g _m (2.47 mS/μm), followed by L _g = 5.0 nm, UL _x = 0.0 nm (1.87 mS/μm)indicating stronger current-driving capability in y-directional transport under the same V _g. The L _g = 4.0 nm, UL _y = 0.0 nm and L _g = 3.0 nm, UL _y = 1.0 nm devices yield 1.71 mS/μm and 1.518 mS/μm, respectively. Higher g _m values enable significant current gain with smaller voltage changes, critical for high-speed circuit signal amplification. We further evaluated three key metrics: total gate capacitance (C _g = ∂Q _ch/∂V _ds), intrinsic delay time (τ = C _g·V _ds/I _on), and power-delay product (PDP = C _g·V _ds ²). Here, C _g is the intrinsic gate capacitance (excluding parasitic capacitance), and Q _ch is the Mulliken charge per unit width (accounting for internal charge distribution and junction/edge capacitance effects). These parameters directly influence the MOSFET speed and power consumption, making their evaluation crucial for design optimization.

C _g reflects gate control over channel carriers, impacting the switching speed and dynamic power consumption. As shown in Figure d, all devices exhibit C _g < 0.6 fF/μm (ITRS standard), with the L _g = 5.0 nm, UL _x = 0.0 nm device showing the highest C _g (0.094 fF/μm) and the L _g = 3.0 nm, UL _y = 1.0 nm device the lowest (0.053 fF/μm). τ describes the response speed (lower τ = faster switching). As shown in Figure e, x-directional devices consistently exhibit higher τ than y-directional devices (faster switching in the y-direction). The L _g = 3.0 nm, UL _y = 1.0 nm device shows the lowest τ (0.034 ps), demonstrating that shorter L _g with an appropriate UL significantly enhances speed. PDP combines energy consumption and response speed (lower PDP = higher energy efficiency). Calculations show PDP ranges from 0.022 to 0.039 fJ/μm1 order of magnitude lower than the ITRS standard (0.243 fJ/μm), indicating substantial energy consumption reduction and extended device lifespan. Longer L _g typically correlates with higher PDP, further confirming that structural adjustment can simultaneously enhance the switching efficiency and reduce power consumption.

Systematic analysis of key performance metrics across the five MOSFET types comprehensively evaluates B₄Cl₄-based MOSFET advantages and limitations, providing a scientific basis for practical application optimization. While p-type devices have constraints, n-type devices exhibit significant advantages across multiple metricsmeeting ITRS requirements for future HP nanodevices in I _on, C _g, τ, and PDP and laying a foundation for efficient LP integrated circuits. Their outstanding performance confirms practical application potential in high-efficiency LP devices with significant academic and engineering value. Notably, the L _g = 5.0 nm, UL _y = 0.0 nm device exhibits I _on exceeding the ITRS standard by 170.63%, far surpassing other configurationsdemonstrating exceptional switching and energy efficiency, making it a strong candidate for next-generation nanoelectronics (high-speed computing, LP integrated circuits). Other devices also show excellent performance in SS, C _g, τ, and PDP, providing a robust theoretical basis for the performance optimization and architecture improvement. The exceptional performance of B₄Cl₄-based MOSFETs not only offers a reliable solution for future ultra-scaled integrated circuits but also provides critical implications for extending Moore’s Law. Leveraging these characteristics and referencing ITRS benchmarks, B₄Cl₄-based MOSFETs are expected to find wide application in HP processors, LP sensor networks, and other next-generation computing/communication devices requiring high energy efficiency and compact dimensions.

In order to further contextualize the performance of B₄Cl₄ MOSFETs within the broader research landscape of 2D semiconductor materials, the key performance indicators of B₄Cl₄ MOSFETs were systematically compared with those of other widely studied monolayer 2D semiconductors, including TMDs (e.g., MoS₂ and WS₂ ) and typical 2D materials such as arsenene, germanene, and KMgSb. All comparisons were performed based on ab initio quantum transport simulations of double-gate n-type HP MOSFETs with a channel length of 5.0 nm. As shown in Table , the B₄Cl₄ MOSFET constructed along the x-direction (B₄Cl₄_x) exhibits the lowest SS (60.98 mV/dec), which is close to the thermionic limit of traditional semiconductor devices. This feature endows it with significant advantages in suppressing SCE and improving the device energy efficiency. In terms of I _on, the I _on of B₄Cl₄-based MOSFETs fabricated along the y-direction (B₄Cl₄_y) can reach 1535.68 μA/μm, which is significantly higher than those of MoS₂ (323.49 μA/μm), WS₂ (1009 μA/μm), arsenene (655 μA/μm), and germanene (900.27 μA/μm) and slightly superior to that of KMgSb (1076 μA/μm). This advantage can be attributed to the lower electron effective mass of B₄Cl₄ along the y-direction and the resultant enhanced carrier transport characteristics.

2. Comparison of Key Performance Indicators for n-Type HP MOSFETs with a Channel Length of 5.0 nm.

	I on (μA/μm)	SS (mV/dec)	τ (ps)	PDP (fJ/μm)
B4Cl4_x	1182.45	60.98	0.051	0.039
B4Cl4_y	1535.68	87.97	0.037	0.036
MoS2	323.49	76	2.844	0.285
WS2	1009	117	0.239	0.154
arsenene	655	113	0.059	0.053
germanane	900.27	136	0.504	0.29
KMgSb	1076	68	0.083	0.057

Furthermore, in terms of dynamic performance indicators such as τ and PDP, B₄Cl₄ MOSFETs are generally superior to most of the reference materials. Their τ values range from 0.037 to 0.051 ps, and the PDP ranges from 0.036 to 0.039 fJ/μm. The aforementioned comparisons clearly demonstrate the significant competitive advantages of B₄Cl₄ in terms of anisotropic electron transport, current-driving capability, and energy efficiency. Particularly in 5 nm scale device applications, its performance indicators not only meet the requirements of HP devices but also show great potential to outperform traditional 2D materials. These advantages further confirm the excellent performance of B₄Cl₄ compared with that of the ITRS benchmarks.

4. Conclusions

In conclusion, this study systematically investigates the crystal structure, stability, mechanical properties, and electronic characteristics of chlorinated graphene-like boronene (B₄Cl₄), while further exploring its potential applications in n-type nanoelectronic devices. Results indicate that pristine boronene is structurally unstable and thus unsuitable for direct application; however, chlorination (a halogenation approach) significantly enhances its structural stability via the formation of three-center, two-electron (3c–2e) B–Cl–B bonds. This stability improvement is further confirmed via multidimensional verification, including cohesive energy calculations, phonon spectrum analysis, AIMD simulations, and the Born–Huang mechanical stability criterion. Furthermore, band structure and PDOS analyses reveal pronounced anisotropy in the conduction and valence bands of B₄Cl₄. Notably, its directionally low carrier effective mass indicates distinct advantages in directional electronic transport. Quantum transport simulations demonstrate that HP MOSFETs with L _g = 2.0 nm and UL _y = 2.0 nm exhibit an I _on 2016.97% higher than counterparts without a UL region. Among all configurations, the device with L _g = 5.0 nm and UL _y = 0.0 nm achieves an optimal transport performance, with I _on exceeding the ITRS standard by 170.63%. In contrast, the device with L _g = 5.0 nm and UL _x = 0.0 nm yields an SS approaching the theoretical limit of conventional semiconductors.

Importantly, five B₄Cl₄-based n-type MOSFETs at sub-5.0 nm nodes meet ITRS HP requirements for I _on, C _g, τ, and PDP. Their τ and PDP are 1 order of magnitude lower than ITRS benchmarks, making them strong candidates for next-generation nanoelectronic device design. Collectively, this study not only provides theoretical support for B₄Cl₄’s advantages in structural stability, mechanical properties, and electronic characteristics but also demonstrates its potential in both HP and LP electronics via transport property analysis. Results confirm that monolayer B₄Cl₄ exhibits excellent structural stability alongside unique mechanical and electronic anisotropy. MOSFETs based on this material represent a novel candidate for post-silicon device architectures, with promising prospects for large-scale application in future ultra-large-scale integrated circuits and LP computing platforms. These findings enhance the theoretical understanding of functionalized boronene derivatives and their prospective role in future nanoelectronic applications, thereby complementing ongoing experimental efforts in 2D material-based transistors and monolithic 3D integration.

The authors declare no competing financial interest.