Low-power analog and mixed-signal circuit techniques for next-generation miniature implantable neural interface systems

Abstract

Miniature implantable neural interface devices are increasingly critical for both neuroscience research and clinical neuromodulation applications. However, device miniaturization imposes stringent constraints on power, area, and performance, creating challenges for implementing energy-efficient neuromodulation, high-fidelity neural recording, and wireless data telemetry. This review provides a comprehensive overview of low-power circuit designs enabling next-generation neural interfaces. We discuss energy-efficient stimulation drivers for optogenetic neuromodulation, highlighting advanced switched-capacitor-based techniques that reduce supply voltage requirements while maintaining high-current LED pulses. Low-noise neural recording frontends, including preamplifier-fronted structures, as well as ΔΣ ADC-based and NS-SAR-based direct-digitizing architectures, are reviewed with emphasis on techniques for dynamic range extension, linearity improvement, and artifact tolerance. Finally, state-of-the-art backscatter-based wireless telemetry methods are presented, covering load-shift keying (LSK), frequency-splitting, and push–pull quadrature modulation approaches that decouple power and data transfer to achieve high data rates with minimal energy consumption. This review highlights the critical role of circuit-level innovations in overcoming the power and performance limitations of miniature implants and provides insights for the design of next-generation neural interface systems.

Introduction

In modern healthcare, implantable neural interface devices serve as a critical bridge to the brain. By leveraging their neuromodulation capabilities, these devices can directly influence neural activity, while their neural recording functionality enables the decoding and understanding of brain dynamics. Such technologies play a crucial role in both neuroscience research, where they are used to study brain activity and behavior, as well as in clinical applications, where they enable therapeutic neuromodulation for a wide range of neurological disorders, such as Parkinson’s disease, Alzheimer’s disease, and others [1–5]. Beyond therapy, neural interfaces are also emerging as tools to augment human capabilities, making their potential applications broad and continuously expanding.

Given their invasive nature, significant efforts have been dedicated to advancing implantable neural interface devices toward the next level of performance, safety, and long-term reliability. A primary focus has been on device miniaturization, scaling implant devices down to millimeter or even micrometer level. Miniaturization not only reduces device invasiveness but also extends implantation longevity by mitigating tissue responses and minimizing surgical trauma.

Miniature neural implants for stimulation and recording have been widely reported in recent literature, as shown in Fig. 1 [6–14]. Charthad et al. described an ultrasound-powered implant for deep-tissue electrical stimulation with a device volume of 39 mm³ [6]. Khalifa et al. presented The Microbead, a 0.009 mm³ fully integrated chip-scale neural stimulator [7]. Jia et al. introduced the mm-sized free-floating wirelessly powered implantable optical stimulation device (FF-WIOS) supporting single-channel optical stimulation with a device volume of 9.4 mm³ [8]. For neural recording, Ghanbari et al. demonstrated a free-floating implant featuring ultrasound-based wireless power and data links [9]. In [10], Lee et al. reported the microscale opto-electronically transduced electrodes (MOTE) device for neural recording, achieving a sub-mm³ volume of 0.14 mm³ and using optical links for both wireless power delivery and data transmission. In addition, Lee et al. introduced the Neurograin array, in which each Neurograin device has a volume of 0.1 mm³ and supports either stimulation or recording [11]. Furthermore, Zhao et al. introduced the NeuroFlare device, extending the modality from single-function operation to dual-modality operation with optical stimulation and simultaneous neural recording in a 6.8 mm³ implant [12].

Fig. 1.

Representative miniature neural implants for stimulation and recording

As device dimensions continue to shrink, however, the available power sources, such as batteries, inductive coils, or ultrasonic transducers, become severely constrained, typically providing only tens to hundreds of microwatts. This limited power budget imposes stringent challenges on circuit design, as every functional block must operate under ultra-low-power and area-efficient conditions while still maintaining the high performance required by the application.

Under these power limitations, implementing neuromodulation, particularly optogenetic stimulation, becomes highly challenging due to its high power consumption. Optogenetic stimulation, known for its high temporal precision and cell-type specificity, is a powerful neuromodulation approach. However, effective implementation requires driving LEDs with milliampere-level current pulses, which far exceeds the limited power budget of typical miniature implants.

Similarly, the limited power budget imposes significant challenges on improving neural recording performance. Neural recording circuits, which provide essential feedback for closed-loop neuromodulation, must acquire, amplify, and digitize neural signals with high fidelity while maintaining strong resilience to artifacts and interference. Achieving such high performance inevitably increases power consumption, yet these circuits must still operate within a power budget of only a few microwatts.

The limited power budget also imposes constraints on wireless data transmission. Wireless telemetry is essential for practical usability, eliminating physical tethers and enabling freely moving subjects. However, it remains one of the most power-hungry circuit blocks, particularly when the transmitter needs to deliver high-speed data streams that often reach the megabits-per-second range.

To address these challenges, the integrated circuit (IC) plays a pivotal role. Innovative circuit designs, particularly stimulation drivers, recording front ends, and data telemetry circuits, are proposed to meet stringent power and area constraints, enabling the full integration of functional blocks within a micrometer- to millimeter-scale form factor. These circuit-level innovations collectively drive the development of next-generation neural interface devices that achieve minimal invasiveness, high functional performance, and low power consumption, paving the way for future advances in neuroscience research.

This paper provides a review of innovative low-power circuit designs for miniature neural interface devices, along with an overview of recent representative implementations. Energy-efficient driver designs for optogenetic stimulation are discussed in Sect. 2. Low-power, high-precision recording frontends are presented in Sect. 3. State-of-the-art backscattering-based wireless telemetry techniques are reviewed in Sect. 4. Finally, the review is concluded in Sect. 5.

Energy efficient stimulation driver

In optogenetic stimulation, the stimulation driver is a power-intensive circuit. It needs to deliver large instantaneous current pulses to the LED so that sufficient light intensity, typically exceeding 1 mW/mm² [15], can be generated to effectively activate target neurons. In addition, the driver’s output voltage must exceed the LED’s forward voltage, which is typically around 3 V for blue LEDs commonly used in neural activation [16, 17]. The simultaneous requirements for high current and high voltage make the stimulation driver highly power-demanding. Therefore, achieving high energy efficiency in the stimulation driver is critical to maintaining low overall power consumption in miniature implantable neural interface devices, whose total power budget is typically on the order of microwatts [12, 18]. Moreover, this efficiency requirement becomes even more stringent in neural interface systems that power multiple LEDs simultaneously [19–21].

If the stimulation driver directly drives the LED from a supply voltage, the supply must be high enough, for example, above 3 V for a blue LED, and capable of delivering millisecond-level current pulses in the milliampere range [8, 22]. This imposes a heavy load on the supply and, in the case of wireless power, on the Rx coil, creating challenges for wireless power transmission.

To reduce the loading effect, switched-capacitor-based stimulation (SCS) structures, as shown in Fig. 2a, are commonly used because they isolate the large LED current, I_LED, from the supply, facilitating power transmission [8, 22, 23]. Specifically, the SCS structure continuously charges off-chip capacitor(s) until fully charged. During stimulation, the capacitor disengages from the driver and rapidly discharges, generating a large, exponentially decaying current pulse. The efficiency of SCS is dominated by the capacitor charging efficiency. However, during the charging phase, the supply must replenish the off-chip capacitor in a short time, resulting in a large charging current that still heavily loads the supply. Consequently, an additional off-chip capacitor is often required at the supply for stabilization during large current draws. Furthermore, the uncontrolled charging current degrades charging efficiency due to significant I²R losses in the charging switch. In addition, the SCS structure requires a high supply voltage to drive the LED.

Fig. 2.

A comparison of the conventional SCS structure [8], the VB-SCS structure [18], and the LC-SCS structure [12] with highlighted key features

Extensions of SCS have been proposed to achieve advanced performance. In [18], a voltage-boosting SCS (VB-SCS) structure, as shown in Fig. 2b, leverages the capacitor series-to-parallel conversion scheme to reduce the required supply voltage by half. During the charging phase, the VB-SCS charges two off-chip capacitors connected in parallel to the supply voltage. In the stimulation phase, the two capacitors are disconnected from the VB-SCS driver and are reconfigured in series, providing twice the supply voltage to drive the LED. This capacitor-stacking scheme effectively reduces the required supply voltage by half. However, the VB-SCS driver requires additional off-chip capacitors—at least one at the supply for stabilization due to the large charging current, and two for the VB-SCS itself—which is undesirable for implantable miniaturized devices. Furthermore, since the charging current is uncontrolled, the charging efficiency is limited to 62.9%.

To improve the efficiency of VB-SCS, recent advanced SCS-based stimulation architectures adopt controlled charging/discharging schemes [24, 25]. For example, a stacked-SCS structure reported in [25] achieves a high stimulation efficiency of up to 71.4%, including charging and discharging efficiencies of 72.6% and 99.9%, respectively, by employing an AC-to-capacitor charger and a stacked-capacitor stimulus discharger. Another solution is a linear-charging switched-capacitor stimulation (LC-SCS) structure proposed in [12]. It introduces a self-gate-driven charge pump and a linear capacitor charger, as shown in Fig. 2c. The charge pump boosts the supply voltage by 3 × to charge the off-chip storage capacitor, thereby reducing the required supply voltage by a factor of three. The charge pump, consisting of two identical charge-pump cells with a 3 × voltage conversion ratio (VCR), is designed for high efficiency. These two charge pump cells operate in a time-interleaved manner, alternately generating either 3 × or 1 × the supply voltage. When one cell produces the 3 × supply voltage, the other generates the 1 × supply voltage. The 3 × supply voltage from one cell not only charges the stimulation storage capacitor but also powers the gate driver of the other cell. As a result, the gate driver can operate without bootstrapped circuits, significantly simplifying the design and improving the energy efficiency of the charge pump.

During the charging phase, the linear capacitor charger, implemented with a 4-bit current digital-to-analog converter (IDAC), provides a microampere-level constant current to charge the storage capacitor. The charging current is typically set to the minimum value that allows the storage capacitor to be fully charged to 3 × the supply voltage by the end of the charging period. During the stimulation phase, the storage capacitor is disconnected from the LC-SCS charger and rapidly discharges into the LED with a high driving voltage of 3 × the supply, producing a milliampere-level LED current over a short duration. The linear charging control significantly reduces the loading on the supply, allowing the supply decoupling capacitance to be reduced and implemented on-chip. As a result, the LC-SCS requires only one off-chip capacitor for charge storage, greatly promoting device miniaturization. In addition, the low and constant charging scheme, combined with the high-efficiency charge-pump design, improves the overall charging efficiency, achieving a peak charging efficiency of 86.4%.

Measured transient stimulation waveforms in Fig. 3 show that the required supply voltage, V_SUP, is reduced to just 1.2 V. The charge pump boosts this voltage to 3.6 V to drive the LED. Because the storage capacitor is charged with a small, constant microampere-level current, the capacitor voltage, V_C, increases linearly over time. The stimulator can deliver up to 12 mA of LED current, producing an output light intensity of 10.5 mW/mm², which is sufficient for effective optical stimulation.

Fig. 3.

Transient LC-SCS operation that linearly charges the storage capacitor and drives the LED with high instantaneous current pulses

Low-noise neural recording frontend

Requirements for implantable system

To enable accurate neural recording, the recording frontend needs to meet stringent requirements imposed by neural signal characteristics. Most neural signals, such as electrocorticography (ECoG), local field potentials (LFPs), and action potentials (APs), are weak in amplitude and confined largely to the audio-frequency band. For instance, ECoG signals typically range from 10 to 500 µV within 0.1–200 Hz; LFPs span approximately 50 µV–5 mV within 0.1–300 Hz; and APs exhibit amplitudes of 20–500 µV with a much higher bandwidth of 300 Hz–5 kHz [26–29].

To record specific neural modalities, the frontend must provide bandpass filtering that fully covers the target signal bandwidth and achieve an integrated input-referred noise (IRN) below 10 µV_RMS within the signal band to preserve signal fidelity [30, 31]. In addition, a wide input dynamic range, typically larger than 100 mV and sometimes exceeding 1 V, is required to tolerate large artifacts arising from motion, stimulation, or other interference sources. These artifacts can be orders of magnitude larger than neural signals and may otherwise saturate the frontend, corrupting neural recordings [32, 33]. Furthermore, a high input impedance (Z_in) is necessary to minimize signal attenuation due to voltage division between Z_in and the electrode–tissue impedance (ETI), which can vary widely from kΩ to MΩ depending on electrode type and interface conditions. Consequently, Z_in is typically required to be several tens of times larger than the worst-case ETI (i.e., on the order of tens of MΩ) [34–36]. Finally, state-of-the-art implantable frontends generally consume less than 10 µW per channel [37–39].

Frontend architectures

Frontend with preamplifier

These frontend requirements have motivated the development of various architectures. A conventional approach employs a preamplifier for signal conditioning and bandpass filtering, followed by an analog-to-digital converter (ADC) for digitization. The preamplifier can be implemented using either AC-coupled or DC-coupled configurations [16, 30, 35, 36].

The frontend design in [16, 25] adopts an AC-coupled preamplifier consisting of three stages: a low-noise amplifier (LNA), a variable-gain amplifier (VGA), and a buffer, as shown in Fig. 4a. AC coupling provides immunity to DC offsets through the use of input blocking capacitors. In addition, the preamplifier enables low-pass or bandpass filtering ahead of the ADC, thereby providing anti-aliasing. However, the Z_in of AC-coupled designs is largely determined by the blocking capacitor. As Z_in decreases at higher frequencies, signal attenuation becomes more pronounced. Moreover, the high gain of the preamplifier limits the input dynamic range, making the frontend susceptible to saturation in the presence of artifacts.

Fig. 4.

Preamplifier designs with a AC-coupled [16] and b DC-coupled configuration [40]

The frontend design in [40] also places an LNA and a VGA ahead of the ADC but employs a DC-coupled configuration, as shown in Fig. 4b. The input signal is directly applied to the gate of the first-stage amplifier, providing a high input impedance and thereby significantly reducing signal attenuation. High-pass filtering is realized by subtracting the feedback signal from the input in the LNA, while low-pass filtering is determined by the bandwidth of the LNA/VGA, providing inherent anti-aliasing prior to digitization. However, the absence of DC-blocking capacitors makes the frontend susceptible to DC offsets. Moreover, the high preamplifier gain limits the input dynamic range, increasing the risk of saturation in the presence of artifacts.

Direct-digitizing frontend

To improve tolerance to large artifacts, the input dynamic range of the frontend must be increased. One effective approach is to eliminate the preamplifier and adopt a direct-digitizing frontend, in which the recorded signal is digitized directly by the ADC. To compensate for the absence of analog gain, ADC needs to provide sufficiently high resolution. The dynamic range is typically expected to exceed 80 dB. To achieve an IRN below 10 µV_RMS, the ADC resolution needs to be greater than 80 dB while providing sufficient bandwidth to cover the target neural signals [37, 38, 41].

ΔΣ-ADC-based direct-digitizing frontend

A common solution is to design delta-sigma (ΔΣ) ADCs [12, 37, 38, 42–45]. Continuous-time (CT) ΔΣ ADCs with capacitive inputs are widely used. CT architecture inherently provides anti-aliasing and mitigates kT/C noise [46]. In addition, capacitive inputs are easier to drive compared to resistive-input designs [37]. Chopping is typically employed in the first integrator to reduce flicker noise. However, chopping reduces the input impedance, which can lead to signal attenuation.

In this 2nd-order CT ΔΣ ADC [12], the input signal is capacitively coupled and subtracted by the feedback to generate the residual, as shown in Fig. 5. The 2nd-order noise shaping is realized using a G_m-C integrator followed by a 4-bit NS-SAR quantizer. The G_m-C integrator has an open-loop configuration, which provides the 1st-order of noise shaping and is chosen for its high energy efficiency. However, the G_m-C integrator suffers from poor linearity. Two strategies are implemented to address this. First, the Gm-C integrator is placed in the feedback loop, rendering the input node a virtual ground, which relaxes linearity requirements. Second, G_m-boosting is applied in the OTA, where local feedback suppresses the nonlinearities of the input transistors. The subsequent NS-SAR stage provides an additional order of noise shaping, resulting in overall 2nd-order noise shaping. In this design, only one integrator operates in the CT domain, and the NS-SAR stage implements the extra noise-shaping order. This structure relaxes the excess loop delay (ELD) constraint and eliminates the need for ELD compensation, thereby simplifying the design. With these strategies, the ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.9 dB and a peak dynamic range of 83.7 dB within 10 kHz, demonstrating tolerance to artifacts up to 400 mV.

Fig. 5.

Architecture of the 2nd-order CT ΔΣ ADC used as a direct-digitizing frontend [12]

Another CT ΔΣ ADC employs G_m-C integrators and incorporates two strategies—capacitive feedforward and a duty-cycled G_m cell—to improve the linearity of the G_m-C integrator [47]. Importantly, both techniques are realized without additional OTAs, thereby minimizing power overhead and maintaining high efficiency. As shown in the overall architecture (Fig. 6a), the input signal is capacitively coupled and subtracted by the feedback to generate a residual signal. This residual is then integrated by a G_m-C integrator and an active-RC integrator to achieve 2nd-order noise shaping. The integrator outputs and the input signal are summed through a capacitive summing network, after which a SAR quantizer converts the summed signal into digital codes. A feedback capacitive digital-to-analog converter (CDAC) closes the ΔΣ loop and establishes a virtual ground at the input of the G_m-C integrator, while another CDAC compensates for a fixed half-cycle loop delay. Chopping is also incorporated to suppress in-band flicker noise.

Fig. 6.

Schematic of a the ΔΣ ADC with capacitive feedforward path and duty-cycled G_m cell and b the G_m-C integrator with duty-cycled G_m [47]

The linearity of the first-stage integrator is critical, as it largely determines the overall ADC linearity. Through the capacitive feedforward path, the input signal is directly forwarded to the SAR quantizer input. By appropriately scaling the coefficients of the three signal paths, the capacitive feedforward path, the main integration path, and the local SAR feedback path, to a ratio of 2:1:1 (i.e., C_FF1:C_FF3:CDAC_SAR = 2:1:1, as shown in Fig. 6a), the integrator output swing is significantly reduced to the level of the quantization noise, thereby substantially improving the linearity of the G_m-C integrator. Moreover, the capacitive feedforward path is implemented using a single passive capacitor, inherently providing high linearity without incurring additional power overhead.

Inverter-based amplifiers are commonly used as OTAs in integrators due to their simplicity and high energy efficiency; however, they suffer from poor linearity, particularly during chopping transitions. During these transitions, large glitches can occur, introducing nonlinearity that leads to noise transfer function (NTF) variation and harmonic distortion. To mitigate glitch-induced nonlinearity, an inverter-based OTA with duty-cycled G_m is proposed, as shown in Fig. 6b. The OTA employs two reconfigurable input-pair branches with transconductances of G_m1 and G_m2. The key idea is to use a reduced G_m during glitch-prone intervals and switch to a high G_m during normal low-noise operation, thereby extending the linearity range. Specifically, at chopping transitions, the OTA operates with a cross-coupled input pair, resulting in an effective G_m of G_m1 − G_m2. This low equivalent Gm provides a wider input range to tolerate large glitches. After the transitions, the two input-pair branches are connected in parallel, yielding an effective G_m of G_m1+G_m2, which supports low-noise operation. Notably, the low-G_m phase occupies only about 4% of the sampling period, rendering the associated noise increase negligible. With these techniques, the reported measurements show a peak SNDR of 90.1 dB and a peak dynamic range of 90.1 dB within 10 kHz. A comparison of SNDR with and without duty-cycled G_m demonstrates a 6.4 dB improvement enabled by the proposed approach.

NS-SAR-based direct-digitizing frontend

In addition to using ΔΣ ADCs for direct digitization, another strong option is a high-resolution NS-SAR ADC with Z_in boosting. NS-SAR supports a full input swing, providing a wide dynamic range [41, 48, 49]. With Z_in boosting, the effective Z_in can reach tens of megaohms or higher, which significantly eases the drive requirements and helps reduce signal attenuation [43, 44]. However, because NS-SAR is a discrete-time system, aliasing can be a concern. This issue can be mitigated by operating at a high oversampling ratio.

Figure 7 shows a 2nd-order NS-SAR ADC [49], the input signal is sampled onto the top plate of the input capacitor array, C_SAR. The sampled input is summed with the previous integration results on C₂ by passive summation. A 5-bit SAR quantizer digitizes the summation signal. Its digital outputs are then decoded by the mismatch-shaping dynamic element matching (MS-DEM) calibration block into 32-bit thermometer codes. The bottom plates of C_SAR are switched according to the thermometer codes. This generates the residue voltage on the top plate of C_SAR, which is subsequently integrated by the 2nd-order hybrid integrator. The integration results are stored in C₂ for the next digitization cycle. This design incorporates three key innovations: (1) an energy-efficient hybrid 2nd-order integrator to achieve sharp noise shaping while maintaining low power, (2) dynamic Z_in boosting to ease driving requirements and reduce signal attenuation, and (3) prediction-assisted MS-DEM calibration to reduce mismatch in C_SAR.

Fig. 7.

Block diagram of the NS-SAR used as a direct-digitizing frontend [49]

The hybrid integrator distributes the overall compensation gain required for charge sharing between its 1st and 2nd stages. Specifically, a 6 × passive gain is applied to the 2nd-stage integrator, which relaxes the gain requirement of the 1st stage to approximately 3.3 × and eases its linearity demands. With this reduced gain, the first integrator can accommodate larger residue voltages, making it compatible with low-bit quantizers.

The tree-structured MS-DEM calibration is widely used because it scales well to higher-order MS. However, the conventional tree-structured MS-DEM is not compatible with SAR conversion logic. In the traditional approach, the quantizer outputs, D_out, are decoded into thermometer codes layer by layer, starting from Layer 0 with D_out[0], the least significant bit (LSB), and propagating to Layer n-1 using D_out[n-1], the most significant bit (MSB). These thermometer codes are then used to switch the bottom plates of C_SAR to perform MS. The problem is that conventional MS-DEM decoding starts from the LSB, while the quantizer generates bits sequentially from the MSB. As a result, Layer 1 of the tree lacks the required inputs, preventing the decoding process from progressing.

To make the MS-DEM compatible with SAR conversion logic, a prediction-assisted 5-bit MS-DEM is proposed in [49]. The key idea is to predict the unknown inputs for each layer of the tree. For every layer, the assumption is that the inputs have the opposite digital polarity from the quantizer outputs. For example, if D_out [4] (i.e., MSB) = 1, the inputs for Layer 4 are predicted to be 0, as shown in Fig. 8a. In this case, 16 outputs from Layer 4 are confirmed because they are directly based on D_out [4], while the other 16 outputs remain unconfirmed and are put on hold. These 16 confirmed outputs are sufficient to switch the C_SAR bottom plates and generate D_out [3]. Once D_out [3] is available, the same approach is applied to Layer 3: the inputs for Layer 3 are predicted, yielding 8 confirmed and 8 unconfirmed outputs from Layer 3, as shown in Fig. 8b. The 8 confirmed outputs allow verification of the predictions made for Layer 4, resulting in 8 additional confirmed outputs at Layer 4. This is enough to switch C_SAR’s bottom plates to generate D_out [2]. As each D_out bit is generated, more output information becomes available. The number of unconfirmed outputs in each layer is halved, while confirmed outputs are propagated to verify predictions in higher layers and allow the SAR conversion process to proceed. By the time all D_out bits are ready, all 32 thermometer codes outputs are generated.

Fig. 8.

Operation of the tree-structure prediction-assisted MS-DEM when a D_out[4] and b D_out[3] are generated

To realize Z_in boosting, the proposed method stores the input voltage sampled in the current cycle on a capacitor array (C_V) scaled down relative to C_SAR. Due to the high sampling rate and oversampling, the sampled voltage in the current cycle is approximately the same as in the next cycle. C_SAR is pre-charged to this voltage before the next sampling cycle, compensating for charge loss in C_SAR during both chopping and the first integration. Since C_SAR is always pre-charged to a voltage close to the upcoming sampled value, the additional charge required to fully charge C_SAR is small, effectively boosting Z_in.

This work demonstrates that the NS-SAR ADC’s SNDR increases by nearly 20 dB thanks to the prediction-assisted MS-DEM. As a result, the peak SNDR reaches 98.6 dB, with a dynamic range of 101.1 dB within 1 kHz. Furthermore, the Z_in boosting technique shows a significant improvement, achieving over 80 MΩ at DC and more than 70 MΩ at 1 kHz. In vivo experiments were also conducted to verify that the design can tolerate large artifacts during recording.

Backscatter-based data transmission

Given the limited power budget of implantable devices, both downlink and uplink communication must be energy efficient. The downlink typically delivers low-data-rate user commands to the implantable device. In contrast, the uplink, which transmits physiological data from the implantable device, usually requires high throughput, leading to significant power consumption [16, 50–55]. Ultra-wideband (UWB) transmission is commonly adopted in neural interface systems that demand high data throughput (e.g., several Mbps or higher) and can accommodate a relatively high power budget (e.g., on the order of milliwatts) [56, 57]. In contrast, backscatter data telemetry, which eliminates the need for the implantable device to generate an active carrier, provides a highly energy-efficient solution for the uplink [58, 59]. When an inductive link is employed for wireless power delivery from a primary coil driven by a power amplifier to a secondary coil connected to the implantable device, the same inductive link is often reused for data transmission. In this configuration, the implantable device transmits physiological data back via backscatter over the shared inductive link.

The simplest form of backscatter telemetry employs load-shift keying (LSK) modulation [60–64]. In this approach, a switch is placed across the secondary coil to intermittently change the load impedance based on the transmitted data [59, 60], as illustrated in Fig. 9a. The resulting load variation induces voltage fluctuations on the primary coil, from which the transmitted data can be recovered. LSK is simple and power-efficient. However, conventional LSK suffers from two fundamental limitations arising from the coupling of data and power transmission over the same inductive link. First, LSK directly affects the amount of power delivered to the implantable device, as it relies on periodically shorting the secondary coil. Second, the achievable data rate is limited because it is inversely proportional to the quality factor (Q) of the coils. A high Q is preferred to maximize the power transfer efficiency (PTE) of the inductive link, leading to an inherent tradeoff between data rate and PTE.

Fig. 9.

Back data telemetry over a single inductive link using a conventional LSK modulation, b frequency-splitting method [69], and c push–pull-based quadrature modulation scheme [67]

Despite efforts to develop advanced LSK schemes [60–63, 65, 66], these extensions cannot fully address the limitations of conventional LSK, as they do not decouple data and power transmission. For example, in [62], an energy-recycling LSK modulation reduces energy loss, achieving up to 41% energy savings. However, the inherent tradeoff between data rate and PTE still limits its uplink transmission speed to less than 1 Mbps. In [60], cyclic on–off keying (COOK) modulation partially alleviates the tradeoff between data rate and PTE, achieving 6.78 Mbps at a 13.56 MHz inductive link carrier, but still suffers from substantial energy loss due to periodic coil shorting. Recent studies have proposed new approaches to overcome the two limitations in conventional LSK and its extensions by decoupling data and power transfer, even though both still operate over the same inductive link [67].

One approach [68, 69] leverages the frequency-splitting characteristics of the inductive link to carry power and data over the same link at different frequencies, thereby separating the power and data channels, as shown in Fig. 9b. This method can break the tradeoff between data rate and PTE, enabling the simultaneous achievement of high data rate and high PTE. The work in [69] demonstrated a very high data rate of 200 Mbps using a 390 MHz carrier by combining frequency splitting with quadrature phase-shift keying (QPSK). However, frequency splitting requires the coupling coefficient (k) of the coils to exceed a certain threshold. Maintaining a large k imposes strict constraints on coil alignment and distance. In addition, the two frequencies resulting from frequency splitting are strongly dependent on k, making data transmission highly sensitive to k variations caused by coil misalignment, which can easily occur.

Another approach utilizes the push–pull-based quadrature modulation scheme [67], as shown in Fig. 9c. The push–pull operation separates power and data transmissions into two orthogonal paths without requiring a specific k between the coils: the in-phase (I-phase) path carries power, while the quadrature-phase (Q-phase) path carries data, reducing the coupling between data and power transmission. In addition, push–pull quadrature modulation employs ternary data encoding by combining phase shift keying (PSK) and amplitude shift keying (ASK) modulations, further improving the data rate. This approach achieves a high data rate of 10.17 Mbps over a 13.56 MHz inductive link carrier.

Specifically, to generate the Q-phase data carrier from the inductive link, the push–pull operation is inspired by the impulse response of an LC tank. When an impulse is applied to an LC tank, it induces oscillation with the capacitor voltage immediately reaching a positive peak, as shown in Fig. 10a. Similarly, in the inductive link setup, every time an impulse is injected into the secondary LC tank when the I-phase power carrier is at either 0° or 180° (in this work, 180° is chosen), the capacitor voltage of the secondary LC tank immediately jumps to a positive peak, as shown in Fig. 10b. This induces a 90° phase shift relative to the I-phase, thereby generating the Q-phase data path.

Fig. 10.

a The impulse response of an LC tank. b The generation of the Q-phase path from the power carrier via applying impulses. c The generation of data symbols via the push–pull-based quadrature modulation scheme [67]

In addition, the push–pull modulation employs ternary data encoding, as shown in Fig. 10c. To transmit data ‘+1’, energy is injected into the secondary LC tank by discharging a pre-charged capacitor when the I-phase is at 180°, creating a + 90° phase shift between I and Q paths. To transmit data ‘− 1’, energy is withdrawn from the secondary LC tank by dumping its charge into an empty capacitor slightly before the I-phase reaches 180°, producing a − 90° phase shift between I and Q paths. For data ‘0’, no impulse is applied. This push–pull modulation naturally combines PSK and ASK to encode three symbols, further increasing the data rate.

Conclusion

Advances in low-power IC design are essential to the development of miniature implantable neural interface devices that combine minimal invasiveness with high functional performance. Energy-efficient stimulation drivers enable optogenetic neuromodulation within tight power budgets, while low-noise, high-dynamic-range recording frontends ensure reliable neural signal acquisition in the presence of artifacts. Backscatter-based wireless telemetry, particularly techniques that decouple data and power transfer, provides a pathway for high-speed, energy-efficient uplink communication. Collectively, these circuit-level innovations address the challenges imposed by device miniaturization, paving the way for next-generation neural interfaces that support advanced neuroscience research and clinical applications. Future work will likely focus on further integration, multi-modal sensing and stimulation, and adaptive power management to achieve fully autonomous, high-performance neural implants.

Funding

This work was supported by NSF 2239915.

Declarations

Conflict of interest

Linran Zhao declares that he has no conflict of interest. Yaoyao Jia declares that she has no conflict of interest.

Ethical approval

This article does not contain any studies with human participants or animals performed by any of the authors.