Benchmarking of Ultrascaled Monolayer Halogenated Borophene Transistors: A Comprehensive First-Principles Quantum Transport Study

Abstract

Targeting high-performance and high-density application scenarios, this work systematically investigates the performance limits of ultrashort-channel double-gate (DG) MOSFETs based on halogenated borophene within a density functional theory (DFT)–nonequilibrium Green’s function (NEGF) quantum transport simulation framework. Key device metrics such as on-current, subthreshold swing, switching delay, and power consumption are analyzed for both n-type and p-type devices under various gate and underlap lengths. The optimal channel material selection and underlap length configuration are explored. Using B₄Cl₄ and B₄Br₄ as channel materials for nMOSFET and pMOSFET, respectively, significantly improves the subthreshold performance, ON-OFF ratio, and energy-delay product. Furthermore, selecting appropriate underlap lengths for different gate lengths enables further device performance optimization. These findings provide a crucial theoretical foundation for the material and structural design and optimization of ultrascaled two-dimensional semiconductor transistors in the post-Moore era.

1. Introduction

Due to the stronger quantum tunneling effect and weaker gate electrostatic control, shrinking the gate length of silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) below 10 nm faces significant challenges. Compared to traditional silicon (Si), germanium (Ge), and III–V group bulk materials, two-dimensional (2D) semiconductor channel materials such as monolayer (1L) transition metal dichalcogenides (TMDs) offer numerous advantages, including inherent atomic-scale thickness, absence of out-of-plane dangling bonds, and sufficient bandgap, , which provide pure interfaces, high mobility, , and excellent gate electrostatic control. These properties help address the conducting bottleneck encountered by ultrascaled transistors and effectively suppress the short-channel effect commonly observed in traditional bulk materials, which makes 2D materials promising candidates for extending Moore’s Law and even achieving subnanometer transistor technology.

In recent years, MOSFETs based on 2D-TMDs, indium selenide (InSe), bismuth oxyselenide (Bi₂O₂Se), black phosphorene, , group VA-VA monolayers, , and niobium oxyhalides − have been extensively studied. The aforementioned 2D semiconductor channels significantly enhance the ON-state current (I _ON). − Even when the channel length is reduced below 10 nm, these 2D semiconductor-based MOSFETs can still demonstrate unique advantages in the post-Moore era, achieving a high ON-OFF ratio of ∼10⁶ and a low switching delay (τ_d) of ∼0.2 ps. , There is a class of 2D semiconductors represented by black phosphorene that exhibit anisotropic electronic properties, showing significant differences in band structure along different crystal orientations near the valence band maximum (VBM) and conduction band minimum (CBM). They provide greater design flexibility for n-type and p-type short-channel MOSFETs, allowing for proper selection of channel directions to freely switch between high-speed and low-leakage requirements. However, the tendency of black phosphorene to oxidize and degrade in air severely restricts its practical applications, rendering the search for new 2D semiconductors that are stable at room temperature and exhibit anisotropic properties a current research hotspot.

In particular, graphene-like 2D borophene has attracted widespread attention, − and has been successfully synthesized via exfoliation and ion exchange processes. This type of monolayer material is primarily composed of boron (B) atoms and exhibits a rich allotropic system. Pure boron atom monolayers can be stabilized by placing them on the electron-donating metal surface, where aluminum atom serves as the electron donor and compensates the electron deficiency of B atom. However, studies have shown that double-sided surface passivation with functional groups, such as hydrogen, − fluorine, and oxygen, can also effectively enhance the stability of boron atoms at room temperature by saturating the dangling bonds (p _z orbitals) and forming the multicenter 3c–2e B–X–B bonds, analogous to diborane-type bonding. This stabilization strategy allows the absence of an electron-donating substrate, but the 2D material monolayer is no longer a pure boron atom sheet. Notably, 1L halogenated borophene (B₄X₄, X = F, Cl, and Br) have achieved suitable bandgaps through surface halogenation modification, , rendering them highly suitable for transistor channel materials. Existing studies have shown that in ultrashort (<5 nm) channel 2D semiconductor MOSFETs, introducing an underlap region between source (S)/drain (D) and gate can effectively regulate the shape and width of the S-to-D potential barrier. Therefore, the underlap region is considered as an effective way to suppress drain-induced barrier lowering (DIBL), reduce leakage current, improve subthreshold characteristics, and enhance the energy-delay product. However, in-depth research on optimizing the underlap length (UL) in ultrashort-channel 2D-B₄X₄ MOSFETs is currently lacking, and the influence of the UL on device performance at different channel lengths remains unclear.

Therefore, it holds great scientific and technological significance to systematically explore the performance limits of ultrascaled 2D-B₄X₄ MOSFETs with different gate lengths. It is also crucial to elucidate the correlation mechanism between the material anisotropic properties and device characteristics and determine the optimal channel material and UL for both n-type and p-type devices.

In this work, for both high-performance (HP) and high-density (HD) application objectives, we extracted key performance metrics such as I _ON, subthreshold swing (SS), τ_d, and energy consumption (E _con), and we investigated the impact of UL on device performance at sub5 nm gate lengths in both n- and p-type MOSFETs. By comparing the performance of B₄F₄, B₄Cl₄, and B₄Br₄-based devices, we explored the optimization of channel material selection and UL. This paper is organized as follows. Section introduces the materials and device structures, and Section describes the computational methods. Section presents the results with discussion and analysis, while Section concludes this work.

2. Material and Device Structures

2.1. Material Structure

A 1L-B₄X₄ is generally generated by surface halogenation of a graphene-like boron atom layer, and the partial breakage of the B–B bond results in the transformation of the isotropic atomic structure into an anisotropic one. Figure (a) presents the top and side views of a 1L-B₄X₄ atomic structure, where the B atoms are in the same plane but are sandwiched between the two layers of X atoms, forming a 2D hexagonal honeycomb lattice arrangement. The “armchair” and “zigzag” directions are along the x and y axes, respectively, and the green rectangle shows the primitive unit cell of the lattice (orthorhombic system). Table summarizes the values of the lattice geometrical parameters in Figure for different 1L-B₄X₄ materials.

1.

(a) Schematic atomic structure and (b) first Brillouin zone of 1L-B₄X₄ (X = F, Cl, Br). Halogen (F/Cl/Br) atoms are in red, and boron atoms are in pink. The green rectangular region is the primitive cell, where a and b are the lattice constants, h is the X atom layer spacing (thickness of B₄X₄ monolayer). L ₁ and L ₂ are neighboring B atom distances along two different directions.

1. Lattice Structural Parameters of 1L-B₄X₄ .

	a(Å)	b(Å)	h(Å)	L 1(Å)	L 2(Å)
B4F4	6.13	3.09	2.22	2.32	1.72
B4Cl4	6.77	3.19	3.02	2.67	1.75
B4Br4	7.04	3.28	3.30	2.87	1.76

2.2. Device Structure

Figure shows the schematic structure of a double-gate (DG) inversion-mode MOSFET constructed for the DFT-NEGF simulation, where different B₄X₄ (X = F, Cl, Br) monolayers are used as the channel materials and the transport direction is parallel to the x-axis shown in Figure (a). Considering the scaling extreme of device sizes for technology nodes below 1 nm, we set the gate length (L _g) to 1, 3, and 5 nm in the simulation, which are much smaller than the value of 10 nm in 2023 International Roadmap for Device and System Development (IRDS). The gate dielectric is a bilayer hexagonal boron nitride (h-BN) with a thickness of 6.6 Å, and its dielectric constant is 4.5. For inversion-mode nMOSFETs and pMOSFETs, the source-channel-drain are with n–p–n and p–n–p doping regimes, respectively. The doping concentration of channel region is 0.0002 e/atom (∼6.85 × 10¹¹ cm^–2), and the S/D doping concentration is 0.02 e/atom (∼6.85 × 10¹³ cm^–2). The S/D electrostatics can be adjusted by varying the lateral UL between the gate electrode and the S/D doping regions. Therefore, UL is set to 0, 2, and 4 nm to explore its effect in carrier transport, for different gate lengths. The total lengths of the S/D electrodes and their extensions are 36.78, 33.85, and 35.2 Å for B₄F₄, B₄Cl₄, and B₄Br₄ channels, respectively.

2.

Schematic of a DG-MOSFET structure consisting of a 1L-B₄X₄ channel, where UL denotes length of underlap region between gate electrode and source/drain doping region.

3. Computational Methods

Based on the first-principles DFT-NEGF method, which is performed using Synopsys quantum atomistic toolkits (Quantum ATK), this section conducts an in-depth study on the band structures and quantum carrier transport properties of 1L-B₄X₄. The band structure and density of states (DOS) of the material system are calculated via DFT, and then the device structure is constructed and optimized. NEGF method is further utilized to compute the optimized device transport properties, including the transmission spectrum and current–voltage characteristics. In all DFT calculations, the Perdew–Burke–Ernzerhof (PBE) exchange-correlation functional is employed under the generalized gradient approximation (GGA) to describe electron exchange-correlation interactions, and the PseudoDojo pseudopotential is used to enhance computational accuracy.

3.1. Band Structure and DOS Calculations

To investigate the intrinsic electronic structure of B₄X₄, geometric optimization was first performed, followed by calculations of the band structure, DOS, and partial density of states (PaDOS) for the optimized structure. During structural optimization, the conjugate gradient method was applied to optimize atomic positions until the forces on all atoms were less than 0.05 eV/Å, ensuring the structural stability. A Monkhorst–Pack k-point sampling of 15 × 15 × 1 was used in the Brillouin zone to ensure the convergence and accuracy of the results. The plane-wave cutoff energy was set to 500 eV to guarantee the accuracy of the electronic DOS and charge density calculations.

3.2. Device Modeling and Transport Calculations

The DG-MOSFET structure with the 1L-B₄X₄ channel was constructed at the device level according to Figure as an example. Figure S1a,b in the Supporting Information presents the constructed device structure with 1L-B₄Cl₄ as the channel material for UL = 0 and 2 nm, respectively, where the details of geometric size are marked. To balance the computational accuracy and efficiency in the NEGF quantum transport simulations, a nonuniform k-grid sampling of 9 × 1 × 154 was adopted, and the density mesh cutoff was set to 80 hartree. The transmission spectrum for carrier transport was calculated via the NEGF method under different gate voltage (V _GS) as well as drain voltage (V _DS) conditions, and the drain current (I _D) was further computed using the Landauer-Büttiker formula below

$$I_{\mathrm{D}}(V_{\mathrm{DS}},V_{\mathrm{GS}})=\frac{2e}{h}{\int }_{-\infty }^{+\infty }T(E,V_{\mathrm{DS}},V_{\mathrm{GS}})[f_{\mathrm{S}}(E-{\mu }_{\mathrm{S}})-f_{\mathrm{D}}(E-{\mu }_{\mathrm{D}})]\mathrm{d}E$$ 1

The number of k-point sampling grids and plane-wave cutoff energies were optimized to balance computational accuracy and efficiency with rigorous convergence tests conducted. The Hartree difference potential was monitored and modulated to ensure a flat profile at both electrodes, indicating the realization of rigorous convergence in the device electrostatic potential (see Figure S2 in the Supporting Information for details).

4. Results and Discussion

4.1. Band Structure and Effective Mass

Figure shows the band structures and PaDOS of the three 1L-B₄X₄ (X = F, Cl, or Br) materials considered in this work. The wave vector k follows the path of high-symmetry points Γ–X–S–Y−Γ in the first Brillouin zone of the orthogonal crystal system, as illustrated by the red dashed line in Figure (b). It can be observed that all three 1L-B₄X₄ materials are semiconductors with direct bandgaps (E _g), where both the CBM and VBM are located at the Γ point. Here, B₄F₄ has the smallest E _g (0.56 eV), while B₄Cl₄ has the largest one (1.47 eV). The E _g value of B₄Br₄ is very close to that of Si (1.18 eV).

3.

Energy band structures and PaDOS projected onto different electron orbitals for 1L (a) B₄F₄, (b) B₄Cl₄, and (c) B₄Br₄.

The PaDOS in Figure shows that the valence band states are primarily contributed by the p _x orbitals of B and X atoms, indicating strong hybridization between B and X atoms. In 1L-B₄F₄, the contribution of the B-p _x orbitals to the valence band is significantly larger than that of the F-p _x orbitals. On the other hand, the conduction band states of 1L-B₄F₄ are mainly dominated by the p _z orbitals of B atoms. In the other two materials, the p _z orbitals of B atoms only dominate the states near the CBM, while at higher energy levels of the conduction band, the states include contributions from both B-p _z and X-p _z orbitals, as well as sp hybridization of B-s and X-p _z orbitals.

Furthermore, the zoomed-in views of the energy (E)-k dispersion near the CBM and VBM are presented in Figure (a,b) respectively, for the three considered 1L-B₄X₄ materials. The E–k dispersion relations exhibit significant anisotropy along the Γ–X and Γ–Y directions, corresponding to the “zigzag” (y) and “armchair” (x) directions of the material, respectively. The conduction band has a larger curvature radius along the Γ–X (y) direction, resulting in a heavier electron effective mass, while in the Γ–Y (x) direction, the curvature radius is smaller, corresponding to a lighter electron effective mass. Conversely, the valence band exhibits light-hole curvature along the Γ–X (y) direction and heavy-hole curvature along the Γ–Y (x) direction. The E–k relations and their anisotropy near the CBM and VBM will dominate the carrier transport property in the channel of the n-type and p-type MOSFET, respectively.

4.

E–k dispersion relations near the (a) CBM and (b) VBM. Effective masses of CBM electrons and VBM holes along the (c) “armchair” (x) and (d) “zigzag” (y) directions. (e) DOS effective mass of CBM electrons and VBM holes. Results are compared among different 1L-B₄X₄ materials.

The electron and hole effective masses along the x and y directions are further calculated and summarized in Figure (c,d), where the exact values are explicitly listed in Table S5 in the Supporting Information. For carrier transport along the x direction, the hole effective mass (m _h ) is larger than the electron effective mass (m _e ) in all B₄X₄ materials, with the former being approximately three times as large as the latter. However, when carrier transport is along the y direction, the electron effective mass (m _e ) is larger than the hole effective mass (m _h ), though the difference is less obvious compared to the x direction.

We further calculated the density-of-states effective mass (m _DOS) for electrons at the CBM and holes at the VBM, based on $m_{\mathrm{DOS}}=\sqrt{m_x{m}_y}$ , and the results are shown in Figure (e). The hole m _DOS values are generally higher than the electron m _DOS values for all three 1L-B₄X₄ materials. Their difference is the smallest in 1L-B₄F₄ but the largest in B₄Br₄. Since the transport direction in the simulated devices of this work is along the x direction, Figure (c,e) can be used to interpret the device transport properties. B₄F₄ has the highest m _e and electron m _DOS among all three materials, while B₄Br₄ has the lowest m _e and electron m _DOS. On the other hand, B₄Cl₄ exhibits the lowest m _h but the highest hole m _DOS.

4.2. Device Performance Benchmarking

According to the performance targets for 1.5 nm and below technology nodes in the 2023 IRDS, the supply voltage (V _DD) is set at 0.64 V, and the OFF-state current (I _OFF) target is selected as 0.01 and 2 × 10^–4 μA/μm, respectively, for the HP and HD application scenarios. In all simulation runs, V _DS was maintained at 0.64 V. The I _D–V _GS curves (Figures S3–S8 in the Supporting Information) indicate that pMOSFETs exhibit better subthreshold performance in comparison with nMOSFETs, and UL significantly modifies the current magnitude at different V _GS. Due to the smaller effective mass of electrons compared to holes, nMOSFETs show more significant tunneling effects in the subthreshold region, resulting in a degradation of SS as the subthreshold current decreases. Compared to longer L _g cases, the increase in UL at L _g = 1 nm can effectively reduce the current in both the subthreshold region and the OFF-state. Furthermore, compared to the p-type device, the subthreshold performance of the n-type device is more significantly influenced by the increase in UL. In the 1L B₄Cl₄ and B₄Br₄ pMOSFETs, UL shows barely any impact on their subthreshold performance but has a much greater effect in the saturation region.

The SS and I _ON of n-type and p-type MOSFETs with 1L-B₄Cl₄ channel under different L _g and UL values are listed in Table for the HP application scenario (I _OFF = 0.01 μA/μm), while Table provides the corresponding performance metrics for the HD application scenario (I _OFF = 2 × 10^–4 μA/μm). Tables S1–S4 present the corresponding results for devices with 1L B₄F₄ and B₄Br₄ as channel materials. For the two I _OFF targets specified in Tables and , as well as Tables S1–S4 in the Supporting Information, I _ON can be extracted at V _GS = V _OFF + V _DD, and SS can be extracted at V _OFF, where V _OFF is the V _GS corresponding to I _OFF.

2. Performance Benchmarking of 1L-B₄Cl₄-Channel DG-MOSFETs for HP Application Requirements According to 2023 IRDS.

	L g (nm)	UL (nm)	SS (mV/dec)	I ON (μA/μm)	I OFF (μA/μm)	C t (fF/μm)	τ (ps)	E con (fJ/μm)
n-type	5	4	60.6	415.29	0.01	0.138	0.199	0.025
		2	60.4	2487.31	0.01	0.332	0.08	0.06
		0	96.4	5402.15	0.01	0.658	0.073	0.118
	3	4	64.9	434.19	0.01	0.138	0.191	0.025
		2	92.3	2022.45	0.01	0.264	0.078	0.048
		0	241.8	23.83	0.01	0.542	13.657	0.098
	1	4	91.1	282.66	0.01	0.101	0.215	0.018
		2	224.2	23.72	0.01	0.14	3.543	0.025
		0	-	-	-	-	-	-
p-type	5	4	72.8	71.63	0.01	0.084	0.704	0.015
		2	60	403.15	0.01	0.155	0.23	0.028
		0	61.8	4777.55	0.01	0.589	0.074	0.106
	3	4	74.7	30.68	0.01	0.073	1.428	0.013
		2	62.1	191.74	0.01	0.141	0.443	0.025
		0	68.2	2173.54	0.01	0.559	0.154	0.101
	1	4	76.1	30.7	0.01	0.069	2.197	0.012
		2	80.3	178.78	0.01	0.132	0.444	0.024
		0	-	-	-	-	-	-

3. Performance Benchmarking of 1L-B₄Cl₄-Channel DG-MOSFETs for HD Application Requirements According to 2023 IRDS.

	L g (nm)	UL (nm)	SS (mV/dec)	I ON (μA/μm)	I OFF (μA/μm)	C t (fF/μm)	τ (ps)	E con (fJ/μm)
n-type	5	4	60	212.84	0.0002	0.12	0.339	0.022
		2	60.6	1304.67	0.0002	0.288	0.132	0.052
		0	122	1258.47	0.0002	0.516	0.246	0.093
	3	4	64.6	215.44	0.0002	0.214	0.596	0.039
		2	114.6	715.59	0.0002	0.205	0.172	0.037
		0	-	-	-	-	-	-
	1	4	99.4	99.8	0.0002	0.083	0.498	0.015
		2	404.8	0.1	0.0002	0.188	1130.966	0.034
		0	-	-	-	-	-	-
p-type	5	4	72.8	28.99	0.0002	0.071	1.459	0.013
		2	60.2	156.94	0.0002	0.131	0.502	0.024
		0	60.18	1723.05	0.0002	0.422	0.147	0.076
	3	4	74.7	18.51	0.0002	0.07	2.278	0.013
		2	62.5	131.54	0.0002	0.127	0.581	0.023
		0	69	900.83	0.0002	0.47	0.313	0.085
	1	4	68.9	18.87	0.0002	0.072	1.409	0.013
		2	73.6	65.32	0.0002	0.122	1.124	0.022
		0	-	-	-	-	-	-

Data in Tables , , and S1–S4 show that when UL is insufficient, devices with L _g = 1 and 3 nm exhibit significant tunneling currents in some cases, making it hard to achieve the target I _OFF. Moreover, pMOSFETs generally demonstrate lower SS values compared to their n-type counterparts. In most cases, increasing the UL can improve SS, particularly for devices with L _g = 1 nm.

In the HP application scenario, the optimal UL is 2 nm for both nMOSFETs and pMOSFETs with L _g = 5 nm, which means that for all of the three channel materials, devices achieve the best SS at UL = 2 nm at L _g = 5 nm. Notably, SS even approaches the room-temperature limit of 60 mV/dec for the B₄Cl₄ channel. At L _g = 1 and 3 nm in the HP scenario, the SS of different devices generally shows a monotonically improving trend with increasing UL, except for the cases of the B₄Cl₄-pMOSFET with L _g = 3 nm (achieving optimal SS at UL = 2 nm) and the B₄F₄-pMOSFET with L _g = 1 nm (whose SS degrades with increasing UL). In the HD application scenario, increasing UL can significantly improve the SS of devices with the B₄Br₄ channel. However, for devices with B₄F₄ and B₄Cl₄ channels, an excessively long UL (e.g., UL = 4 nm) will result in degradation in SS.

For both HP and HD I _OFF targets and all three B₄X₄ channel materials, the I _ON of pMOSFETs is reduced by the increasing UL. In contrast, an increase in UL provides a certain degree of enhancement in I _ON of nMOSFETs under short-channel conditions. In the HP scenario, the I _ON of nMOSFETs with 1L B₄Cl₄ and B₄Br₄ channels is significantly improved by increasing the UL at L _g = 1 nm. At L _g = 3 nm, I _ON rises and then falls with increasing UL, peaking at UL = 2 nm. In the HD scenario, the I _ON of B₄F₄-nMOSFET with L _g = 3 nm and B₄Cl₄-nMOSFET with L _g = 1 nm is obviously enhanced by the increase in UL. Under this I _OFF target, the B₄Cl₄ and B₄Br₄ nMOSFETs with L _g = 5 nm also exhibit an optimal UL, achieving the highest I _ON at UL = 2 nm.

Figure presents the optimal I _ON obtained by optimizing UL in n-type and p-type MOSFETs with different channel materials and gate lengths for both HP and HD I _OFF targets. In nMOSFETs with L _g = 1 and 3 nm, the I _ON resulted from 1L B₄Cl₄ and B₄Br₄ channels is much higher than that obtained in the 1L-B₄F₄ channel. Among all of the three channel materials, B₄Cl₄ is proved to be the optimal channel material for nMOSFETs, and it delivers I _ON of 2022.45 μA/μm and 715.59 μA/μm at L _g = 3 nm, corresponding to ON-OFF ratios up to 2 × 10⁵ and 3.6 × 10⁶, respectively, for the HP and HD scenarios. The 1L-B₄F₄ short-channel nMOSFETs exhibit relatively poor I _ON and ON-OFF ratios. Even after UL optimization, it only achieves an I _ON of 0.01 μA/μm and an ON-OFF ratio of 50, at L _g = 1 nm for the HD application. However, as L _g is increased to 5 nm, the 1L-B₄F₄ nMOSFET surpasses 1L-B₄Cl₄ nMOSFET, achieving an I _ON of 1554.93 μA/μm and an ON-OFF ratio of 7.8 × 10⁶ for the HD application target. For the HP application target and L _g = 5 nm case, the B₄Cl₄-nMOSFET still delivers the best performance, with an impressive I _ON of 5402.15 μA/μm and an ON-OFF ratio of 5.4 × 10⁵.

5.

I _ON obtained at the optimal UL for 1L-B₄X₄ DG-MOSFETs with different L _g values in (a) HP and (b) HD application scenarios.

Yielding the lowest I _ON in most cases, B₄F₄ is a nonideal channel material for pMOSFETs either. An exception is the case of L _g = 1 nm and HD application, where UL optimization enables it to achieve an I _ON of 128.09 μA/μm and an ON-OFF ratio of 6.4 × 10⁵. B₄Br₄ consistently emerges as the optimal channel material for short-channel pMOSFETs with L _g = 1 and 3 nm, achieving I _ON values of 3127.61 μA/μm and 1308.33 μA/μm with corresponding ON-OFF ratios of 3.1 × 10⁵ and 6.5 × 10⁶, for HP and HD applications, respectively. However, at L _g = 5 nm, B₄Cl₄ outperforms B₄Br₄ as the channel material of pMOSFET, and the I _ON and ON-OFF ratio of is improved by approximately 0.5 times in both application scenarios when the channel material is changed from B₄Br₄ to B₄Cl₄.

Figure summarizes the optimal SS for n-type and p-type devices with different B₄X₄ channel materials and gate lengths under both application scenarios. In general, pMOSFETs exhibit superior SS with respect to nMOSFETs, and SS is improved as L _g increases. Among all channel materials, B₄F₄ results in the worst SS. B₄Cl₄ channel results in the lowest SS across all gate lengths in a nMOSFET. The SS values for pMOSFETs with 1L B₄Cl₄ and B₄Br₄ channels are quite similar. The former performs slightly better at L _g = 5 nm, whereas the latter excels at a shorter L _g.

6.

SS obtained at the optimal UL for 1L-B₄X₄ DG-MOSFETs with different L _g values in (a) HP and (b) HD application scenarios.

To clarify the impact of UL on device performance, a DG-nMOSFET with 1L-B₄Br₄ channel at L _g = 3 nm was analyzed by examining its projected local density of states (PLDOS) and the corresponding energy-resolved current spectrum shown in Figure , for both ON and OFF states at different UL.

7.

Spatial distributions of PLDOS and current energy spectra in a 1L-B₄Br₄ channel DG-nMOSFET with L _g = 3 nm and different UL values for both OFF-state and ON-state: (a) UL = 0, OFF-state; (b) UL= 2 nm, OFF-state; (c) UL= 4 nm, OFF-state; (d) UL= 0, ON-state; (e) UL= 2 nm, ON-state; (f) UL = 4 nm, ON-state. μ_S and μ_D denote the electrochemical potentials (Fermi levels) of the source and drain, respectively. Φ represents the channel energy barrier faced by the electrons from the CBM during transport from S to D. I _tunnel and I _therm are the tunneling and thermionic current components, respectively. The ratio of I _tunnel to the total current is given in the OFF-state.

At the OFF-state shown in Figure (a–c), since the underlap region is not controlled by gate electrostatics, the introduction of UL creates energy barriers at both ends of the gate-controlled channel. As UL increases, the channel barrier becomes higher and wider, thereby suppressing source-to-drain direct tunneling and improving the subthreshold performance of the device. In the current spectra, I _tunnel represents the tunneling current component due to the wave nature of electrons below the barrier, while I _therm is the current component contributed by thermal excitation above the barrier. The I _OFF spectrum reveals that with increasing UL, the proportion of I _tunnel decreases significantly from 99.3% at UL = 0 to 63.2% at UL = 4 nm.

A shorter L _g results in narrower channel barriers and correspondingly higher tunneling currents. Therefore, devices with L _g = 1 nm experience a more significant improvement in subthreshold performance as a result of UL optimization, compared to the case of L _g = 5 nm. Moreover, the tunneling probability is negatively correlated with the carrier effective mass. Since m _h is generally larger than m _e in all three 1L-B₄X₄ materials, pMOSFETs exhibit weaker subthreshold tunneling with respect to nMOSFETs, leading to better SS and less sensitivity to UL variations.

When V _GS is continuously applied to alter the electrostatic potential of the channel, the conduction band edge in the gated region shifts downward due to electrostatic doping. After V _GS is increased by 0.64 V, the device is switched ON. The corresponding PLDOS and energy-resolved current spectra at ON-state are shown in Figure (d–f), where the barrier height in the gated region nearly vanishes, while it still exists in the region out of the gate control. At UL = 2 and 4 nm, the barrier heights in this region are 0.114 and 0.267 eV, respectively, with barrier widths also proportional to UL. The current spectra indicate that I _ON is dominated by the thermionic component, without any tunneling effects. Therefore, the barrier in the gate-uncovered region impedes the increase of I _therm. This explains why I _ON monotonically decreases with increasing UL in both types of MOSFETs at L _g = 5 nm.

UL can suppress tunneling and improve device subthreshold performance, but an excessively long UL restricts the thermionic current at the ON-state, which is detrimental to the saturation performance. The trade-off between these two effects leads to an optimal UL for certain short-channel devicesfor instance, the B₄Br₄-pMOSFET with L _g = 1 nm achieves the lowest SS and highest ON-OFF ratio at UL = 2 nm.

The switching delay (τ_d = C _t V _DD/I _ON) and the energy consumption per switching event (E _con = C _t V _DD ) were also calculated, where C _t is the total gate capacitance including the intrinsic gate capacitance C _in and the fringing capacitance C _f. C _f originates from the fringing electric fields on both sides of the gate metal toward the S and D regions, which is assumed to be twice C _in according to 2023 IRDS. Here, C _in = ∂Q _ch/∂V _g, where Q _ch is the total integrated channel charge. Figure further illustrates the relation between τ_d and E _con for n-type and p-type MOSFETs with different B₄X₄ channel materials and gate lengths. Data points closer to the bottom-left corner are desired, indicating a lower energy-delay product (EDP). With respect to the HD application target, the HP target renders the devices to exhibit overall lower τ_d and E _con.

8.

τ_d versus E _con relation in DG-MOSFETs with different 1L-B₄X₄ channel materials and gate lengths in (a) HP and (b) HD application scenarios, where different energy-delay product (EDP) levels are indicated by dashed lines.

For both application targets, B₄Br₄ is more suitable for the channel material of pMOSFETs, and the corresponding performance metrics are located closer to the desired corner, effectively reducing EDP. On the other hand, B₄Cl₄ as channel material is more appropriate for minimizing τ_d and EDP in nMOSFETs. Although 1L-B₄F₄ achieves lower E _con (∼0.023 fJ/μm) with respect to the other two B₄X₄ materials in nMOSFETs with L _g = 3 nm under the HP target, devices with B₄F₄ as the channel material demonstrate metrics far from the desired corner in all of the other cases, failing to simultaneously reduce both τ_d and E _con (see Figures S9 and S10 in the Supporting Information for details).

B₄Cl₄-nMOSFETs with L _g = 1 nm achieve an EDP as low as 3.9 fJ·fs/μm in the HP application scenario, while B₄Br₄-pMOSFETs with L _g = 5 nm demonstrate an EDP as low as 4 fJ·fs/μm for both application targets. Additionally, the EDP values of B₄Cl₄-nMOSFETs and B₄Br₄-pMOSFETs with L _g = 3 nm are very close to each other (around 6 fJ·fs/μm) for both HP and HD application targets.

4.3. Comparison with the Cluster-P1 Borophene Transistor

It is noted that the performance evaluation of a pure boron (Cluster-P1 borophene)-based transistor has also been carried out by ballistic DFT-NEGF simulation, and it shows excellent stability and high performance for an I _OFF-target of 0.01 μA/μm and a V _DD of 0.65 V, at a L _g of 3 and 5 nm without any underlap region. Considering the similar device configuration and operational conditions, a valid numerical result comparison is carried out between our 1L-B₄X₄ based transistor with UL = 0 and the Cluster-P1 borophene transistor at L _g = 3 and 5 nm, as summarized in Table below.

4. Performance Comparison between Our 1L-B₄X₄-Based Transistors with Cluster-P1 Borophene-Based Transistor.

	materials	L g (nm)	I ON (mA/μm)	E con (aJ/μm)	τ (fs)	SS (mV/dec)
n-type	B4F4	5	3.97469	135	113	85
		3	0.81588	77	315	198
	B4Cl4	5	5.40215	118	73	96.4
		3	0.02383	98	13,657	241.8
	B4Br4	5	2.93146	90	103	119.6
		3	0.00226	79	115,936	433.6
	Clustered-P1 borophene	5	1.05	97	140	88
		3	0.47	75	243	93
p-type	B4F4	5	1.94407	243	357	111.9
		3	1.3243	84	211	69.8
	B4Cl4	5	4.77755	106	74	63.6
		3	2.17354	101	154	69.3
	B4Br4	5	3.06552	149	162	61.8
		3	3.12761	101	257	68.2
	Clustered-P1 Borophene	5	1.23	95	121	87
		3	0.52	74	222	92

It is found that for the n-type device, the Cluster-P1 borophene transistor almost outperforms all of the three 1L-B₄X₄-based transistors at L _g = 3 nm, although 1L-B₄F₄ shows a little advantage in I _ON and E _con. However, for nMOSFET with L _g = 5 nm, 1L-B₄X₄ as channel material outperform Cluster-P1 borophene leading to significant I _ON improvement, and slight reduction of switching delay. Cluster-P1 borophene transistors still keep their advantages in E _con and SS. On the other hand, when it comes to p-type devices, almost all of the three 1L-B₄X₄-based transistors overwhelmingly outperform the Cluster-P1 borophene transistor in terms of I _ON and SS regardless of L _g. However, our transistors do not show any advantages in the aspect of switching delay and yield a higher E _con in comparison with the Cluster-P1 borophene transistor.

4.4. Discussion on Simulation Limitations

The numerical results of this work are limited to the ballistic transport regime, where the electron–phonon (e-ph) interaction is absent from the DFT-NEGF simulation. However, carrier mobility is severely limited by the e-ph interaction in most 2D semiconductors, which necessitates the discussion on the dissipative transport simulation and ballisticity evaluation in our device. In general, the impact of e-ph interaction on the device performance of short-channel MOSFET depends on the channel length, and it strongly diminishes as the channel length shrink, − where the electron transit time becomes comparable to or even shorter than the phonon-induced relaxation time. Carrier transport in an ultrashort channel that is much shorter than the carrier mean-free-path (λ_ph) under e-ph interaction can be quasi-ballistic. While some 2D semiconductor-based MOSFETs with L _g longer than 20 nm demonstrate ballisticity less than 65% under the effects of phonon, , it was also indicated that as gate length is scaled below 10 nm, the ballisticity can be significantly improved, even exceeding 90% when the L _g goes into the sub-5 nm range. , Considering the sub-5 nm channel length of our device, a quasi-ballistic carrier transport with comparable ballisticity is expected. In order to verify this, we have also taken 1L-B₄Cl₄ as an example to calculate the phonon-limited mobility, using the Boltzmann transport equation (BTE) with the dynamical matrix, e-ph coupling matrix elements and the derivatives of the Hamiltonian calculated by density functional theory (DFT) in quantumATK (see the Supporting Information for computational details). It should be noted that in the DFT-NEGF simulation of the transistor characteristics, carriers are treated quantum mechanically as coherent waves, while the BTE provides a semiclassical description of carrier scattering from the material perspective. Such a multiscale framework is widely adopted in nanoscale device studies, where the BTE-based mobility calculation serves as a physically meaningful approach to quantify the strength of electron–phonon scattering and evaluate ballisticity. − Based on the phonon-limited mobility μ_ph and carrier areal density n _2D (degenerate doping, ON-state), λ_ph can be evaluated by ${\lambda }_{\mathrm{ph}}={\mu }_{\mathrm{ph}}\frac{\hslash }{e}\sqrt{2\pi n_{2\mathrm{D}}}$ , and the ballisticity can be further estimated by $B=\frac{{\lambda }_{\mathrm{ph}}/L_{\mathrm{g}}}{1+{\lambda }_{\mathrm{ph}}/L_{\mathrm{g}}}$ .

Figure presents the electron μ_ph along the x (μ _xx ) and y (μ _yy ) directions as a function of temperature in a monolayer B₄Cl₄. (see Figures S11 to S13 for the details of phonon dispersion, phonon density of states (pDOS), scattering rates, and e-ph coupling matrix elements etc.). It clearly indicates that the effect of e-ph interaction in electron mobility becomes weaker with the decrease of temperature. Specifically, the phonon-limited mobility tensor of 1L-B₄Cl₄ yields μ _xx = 106.3 cm²/(V·s) and μ _yy = 42.6 cm²/(V·s) at room temperature, corresponding to an in-plane trace value of 148.9 cm²/(V·s). Therefore, with the mobility (148.9 cm²/(V·s)) and n _2D (6.85 × 10¹³ cm^–2), λ_ph at room temperature is estimated to be 20.3 nm, and the ballisticity is approximately calculated to be 95.3, 87.1, 80.2% for 1, 3, and 5 nm gate length, respectively. Even when considering the full simulated device length (including extension regions), the ballisticity remains above 50%, suggesting that the ballistic approximation provides the upper bound for intrinsic device performance. It is worth noting that while absolute current values may be moderately overestimated, the extent of overestimation in the I _ON can be evaluated by the ballisticity value representing the ratio of current between dissipative and ballistic transport regimes. Overall, it is expected to be less than 20% in most of the simulation cases.

9.

Phonon-limited electron mobility as a function of temperature in monolayer B₄Cl₄.

A more rigorous quantitative analysis of the e-ph interaction effect should be carried out with the help of dissipative DFT-NEGF simulations; however, that is another systematic ongoing work of ours. Here, the ballistic NEGF simulation results in this work can still appropriately represent the intrinsic upper performance bound for our 1L-B₄X₄ MOSFET with sub-5 nm channel length. Most importantly, the inclusion of e-ph interaction should not qualitatively change the comparative conclusions of this work, such as the relative comparison between device configurations or the influence of underlap engineering.

It should be noted that the contact resistance (R _c) between a 2D semiconductor and a contact metal often becomes a major performance bottleneck due to the interfacial Schottky barrier severely degrading the device current, where metal-induced gap states (MIGS) and Fermi-level pinning inevitably show significant effects. Experimental results in various 2D materials have shown that R _c may span orders of magnitude highlighting its strong dependence on the interfacial electronic structure. − Materials or electrode configurations with intrinsically low MIGS, weak Fermi-level pinning, and good band matching, such as semimetal contacts or band-aligned systems, are therefore highly desirable for achieving Ohmic or near-Ohmic contacts with 1L-B₄X₄. In this work, however, we assume ideal Ohmic contacts to isolate the intrinsic transport characteristics of 1L-B₄X₄, while a detailed evaluation of metal-B₄X₄ interfacial carrier transport and contact resistance will be carried out in our subsequent studies.

5. Conclusions

By constructing and optimizing 1L-B₄X₄ DG-MOSFET structures with different gate and underlap lengths, this work conducted comprehensive DFT-NEGF quantum transport simulations for both n-type and p-type devices, aiming at both HP and HD application targets. The I–V transfer characteristics were simulated to extract I _ON and SS, from which the device performance limits and the role of UL in performance optimization are explored under different gate lengths. Combined with calculations of material band structures, effective masses, device current spectra, and LDOS, the physical mechanisms behind carrier quantum transport properties and device performance were revealed. In addition, optimization strategies of material and UL configuration were provided for n- and p-type devices at sub-5 nm gate lengths. It is found that with the channel parallel to the armchair direction, the subthreshold performance of B₄X₄ pMOSFETs is generally superior to its n-type counterpart. Compared to HP applications, devices under HD targets exhibit degraded I _ON, switching delay, and energy consumption, while the corresponding ON-OFF ratio can be improved by around 1 order of magnitude. By suppression of tunneling current, increasing UL can significantly enhance the subthreshold performance of short-channel and n-type devices. However, due to its limitation on thermionic current, the increased UL also degrades the ON-state performance. In most cases, a UL of 2 nm can make a compromise between the above aspects, effectively reducing the SS (even approaching the room-temperature limit of 60 mV/dec) while improving the I _ON. Furthermore, B₄Cl₄ is identified as the optimal channel material for nMOSFETs, while B₄Br₄ is more suitable for pMOSFETs. For HP applications, the former achieves an I _ON of 2487.31 μA/μm (ON-OFF ratio of 2.5 × 10⁵), a minimum SS of 60.4 mV/dec, and an EDP of 4.8 fJ·fs/μm at L _g = 5 nm, while the latter achieves an I _ON of 1073.69 μA/μm (ON-OFF ratio of 1.1 × 10⁵), a minimum SS of 62.2 mV/dec, and an EDP of 5.5 fJ·fs/μm at L _g = 5 nm.

The data that support the findings of this study are available from the corresponding authors upon reasonable request.

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsomega.5c09965.

• The constructed device structures with geometric details in the DFT-NEGF simulation (Figure S1); convergent Hartree difference potentials of the B₄Cl₄-channel DG-MOSFET (Figure S2); I–V transfer characteristics (Figures S3–S8); switching delay (Figure S9); energy consumption (Figure S10); phonon dispersion and DOS in a monolayer B₄Cl₄ (Figure S11); scattering rates versus energy under the phonon–electron interaction in the B₄Cl₄ monolayer (Figure S12); electron–phonon coupling matrix elements; phase diagrams of energy and momentum conservation near conduction band minimum in the B₄Cl₄ monolayer (Figure S13); performance benchmarking result tables (Tables S1–S4) for DG-MOSFETs based on B₄F₄ and B₄Br₄ channels and the carrier effective masses (Table S5) (PDF)

∥.

S.Z. and Z.G. contributed equally to this work. The manuscript was written through contributions of all authors. S.Z. and H.X. conceptualized the work; Z.G. and Q.S. conducted the simulations and validated the results; S.Z. and Z.G. prepared the original manuscript; S.D. analyzed the data and edited the manuscript; Z.G. and Q.S. revised the manuscript; W.-Y.Y. and S.Z. supervised the work. All authors have given approval to the final version of the manuscript.

The authors declare no competing financial interest.