Generic logic block based on bias-gated 2D MoS₂ transistors

Abstract

Integrating two-dimensional (2D) semiconductors and CMOS technology is a promising pathway for next-generation integrated circuits. However, the implementation of this strategy is hindered by the limited polarity modulation of 2D semiconductors and the inherent characteristics of CMOS architectures. Here, we report a generic logic block (GLB) that uses bias-gated molybdenum disulfide transistors (BG-FET). The BG-FETs exhibit threshold-adaptive field-effect characteristics through simple bias manipulation, enabling good rail-to-rail operation in the inverter circuits. The GLB composed of four BG-FETs can perform reconfigurable logic operations in a single circuit, including basic gate circuits, half-adder, multiplexer, encoder and static-random-access-memory. In contrast, conventional CMOS circuits require at least 100 transistors to perform the same set of operations. We further integrate flip-flop circuits and arithmetic logic units by cascading as-fabricated GLBs, featuring a transistor count saving of over 60% compared to CMOS design. Collectively, BG-FET-based GLB emerges as a post-CMOS integration technology with compelling potential.

2D semiconductors are considered a promising platform to complement silicon in next-generation electronics. Here, the authors report the fabrication of generic logic blocks based on bias-gated 2D MoS₂ transistors, showing the design of logic circuits with transistor count saving of over 60% compared to conventional Si electronics.

Introduction

Two-dimensional (2D) semiconductors still maintain excellent electrical characteristics even at sub-nanometer scales and offer the potential for further extending the logic device scaling^1–6. But its potential is severely hampered by the lack of a proper logic architecture. The current silicon-based CMOS (complementary metal-oxide-semiconductor) architecture realized by high-energy doping technology is not suitable for atomically thin 2D semiconductors. So far, various doping methods have been developed to tune the polarity of 2D transistors^7–9. But effective techniques towards practical circuit-level manufacture still lack because there is little physical space for impurity dopants in such an atomically thin lattice¹⁰. Therefore, most large-scale logic circuits based on 2D semiconductors developed to date primarily follow the non-complementary NMOS architecture^11–14, which inherently exhibit higher power consumption than CMOS technology. More importantly, an inherent problem is that logic functions implemented in CMOS or NMOS architecture require a large number of transistors, which hinders the processes of chip area scaling down and function integration. Consequently, a necessity has been awakened to develop integrated device architectures based on the intrinsic advantages of 2D materials.

The emerging reconfigurable technology¹⁵, in which a transistor can be dynamically programmed to function as either an n- or p-FET during run-time by applying an external control voltage, presents a promising approach beyond CMOS. Reconfigurable circuits can achieve higher logic function density compared to CMOS architecture, thereby improving transistor utilization and reducing circuit redundancy. However, the reconfigurable field-effect transistor (RFET) relies on the modulation of device polarity, transitioning from ambipolar type to either n- or p- type, which necessitates additional hardware resources to implement^16–19. This will result in additional power consumption and problems with circuit complexity. Moreover, the implementation of Boolean functions in the RFET-based circuits with full-swing output still follows a CMOS-like configuration²⁰, utilizing p-FETs and n-FETs for pull-up and pull-down networks, respectively. This approach does not contribute to reducing the overall transistor count. Alternatively, reconfigurable circuit elements based on 2D homo- or heterostructure device^21–23 and 2D single-transistor-based logic elements using a vertical- or split-dual-gate design^24–27 are widely recognized as effective strategies to simplify circuits. However, these reconfigurable circuits are limited to small set of few fundamental logic operations and are further constrained by the intrinsic polarity or thickness of 2D semiconductors.

In this article, we report a bias-gated FET (BG-FET, Fig. 1a) designed to integrate generic logic blocks (GLBs). The asymmetric bias-gated device architecture enables BG-FETs to possess threshold-adaptive field-effect characteristics through different bias modes (source-gated or drain-gated, Fig. 1b). Leveraging these unique structural and electrical features, firstly, a cascaded logic inverter consisting of two BG-FETs with identical process parameters is fabricated to achieve good rail-to-rail operation. Subsequently, within a circuit composed of four BG-FETs, we design and fabricate a GLB with full-equivalent input/output (I/O) ports for performing dynamic reconfigurable logic computing by programming different combinations of input signals (Fig. 1c), including basic gate circuits, half-adder, multiplexer (MUX), encoder and static random-access memory (SRAM). As a benchmark comparison, implementing these functions in CMOS design typically requires more than 100 transistors (Fig. 1d). The as-fabricated GLBs are further used to integrate multiple arithmetic logic units and sequential circuit units with a transistor count reduction of over 60% compared to CMOS design, such as 2-bit multipliers and edge-triggered flip-flops.

Fig. 1. Design of generic logic block (GLB) based on 2D bias-gated FETs (BG-FETs).

a Schematic view of the proposed BG-FET with an asymmetric bias-gated electrode. b Schematic transfer characteristics curves of the BG-FET under different bias modes. Where ΔV_th represents the difference in threshold voltage of transistor. c Three-dimensional schematic of the GLB based on four BG-FETs for dynamic reconfigurable logic computing. d Comparison of the transistor requirements for logic function implementation in CMOS (complementary metal-oxide-semiconductor) design versus GLB design.

Results

Characterization of the unipolar MoS₂ BG-FET

A schematic of the BG-FET device concept is shown in Fig. 2a. The basic structure consists of a unipolar CVD-grown monolayer MoS₂ channel sandwiched between hafnium oxide and antimony oxide (HfO₂/MoS₂/Sb₂O₃/HfO₂), as well as a fully back-gated bottom electrode and a locally unilateral bias-gated top electrode. To confirm the signature device structure of our BG-FET, a representative sample and a traditional MOSFET for reference (Ref. FET) are simultaneously fabricated based on the same MoS₂ film (Fig. 2b). The fabrication processes (see “Methods”) of the two devices are completely identical, except that an asymmetrically extended bias-gated electrode is added to the BG-FET. Notably, we choose a van der Waals crystal Sb₂O₃, as a buffer layer to form a high-quality oxide-to-semiconductor interface^28–30, enabling the integration of high-κ dielectrics via atomic layer deposition. Moreover, a van der Waals gate dielectric interface can better maintain the intrinsic properties of the underlying 2D materials, which is also helpful for improving the uniformity and stability of 2D electronics.

Fig. 2. Structure and device characteristics of the BG-FET.

a Schematic view of the proposed MoS₂ BG-FET with an asymmetric bias-gated electrode. L_BG and L_ch represent the length of the bias-gated electrode and the channel, respectively. b Optical image of the BG-FET and the Ref. FET based on the same monolayer MoS₂ film. D, S, and G represent the drain, source and gate, respectively. Scale bar, 20 μm. c Schematic illustration of energy band diagrams for BG-FET in D-Gated mode and in S-Gated mode compared to Ref. FET. E_C and E_V represent the conduction-band minimum and valence-band maximum, respectively. d Output characteristics of Ref. FET (upper) and BG-FET (lower) under a given V_GS from 0.6 to 1 V with a step of 0.1 V. I_DS, V_DS, V_GS, and V_SAT represent the drain-source current, the drain-source voltage, the gate voltage, and the saturation voltage, respectively. e Comparison of pinch-off mechanism of BG-FET and Ref. FET. Red and blue areas represent the electron accumulation region and depletion region, respectively. f Transfer curves of BG-FET and Ref. FET under the same testing conditions. Set V_REF voltages equal to the V_GS when I_DS is 10⁻⁹A. ΔV_REF represents the difference of V_REF. g Transfer curves of 64 BG-FETs in D-Gated mode and S-Gated mode at V_DS = 2 V. The inset is a statistical histogram of ΔV_REF for BG-FETs under two operation modes. h Transfer curves of the BG-FET placed in the vacuum atmosphere for 1 week, 4 weeks, 7 weeks, and less than 1 day. The inset corresponds to the variation of ΔV_REF. i Transfer curves of the BG-FET under different temperatures. The inset corresponds to the variation of ΔV_REF at 293, 320, 360, and 400 K.

The asymmetrical nature of this as-fabricated BG-FET is defined as two different bias schemes: extended bias-gated electrode as source (named source-gated, S-Gated) and as drain (named drain-gated, D-Gated). In principle, the energy band diagrams under two operating modes are shown in Fig. 2c. In the S-Gated mode, the channel electrons around the source contact are depleted due to the bias-gated electrostatic (negative potential relative to the drain), resulting in the extension of the electron injection barrier compared to the Ref. FET. The widened barrier can block the injection of electrons from the source, thus requiring a larger V_th. In D-Gated mode, the accumulated electrons can improve the channel conductivity around the drain contact due to the bias-gated electrostatic (positive potential relative to the source), but not affect the electron injection barrier at the source.

In a detailed comparison, the electrical properties of two devices are investigated under the same testing conditions. As shown in Fig. 2d, the saturation voltage (V_SAT) of BG-FET is smaller under the same gate voltage (V_GS) compared with the Ref. FET. By definition, the V_SAT corresponds to the drain-source voltage (V_DS) at which the drain-source current (I_DS) reaches saturation, equivalent to the V_DS required for transistor pinch-off. Figure 2e illustrates the pinch-off mechanism of BG-FET and Ref. FET. As V_DS increases, the depletion region of Ref. FET occurs at the drain until the channel is pinched off and V_SAT is defined. In S-Gated mode, however, the depletion of BG-FET occurs both in drain and source due to the extended bias-gated electrode^31,32. The source-side depletion region progressively expands towards the drain with the increasing V_DS due to the bias-gated electrostatic (maintained at a negative potential relative to the drain), enabling the BG-FET to be pinched off prematurely, and a smaller V_SAT is defined. Figure 2f exhibits the transfer characteristics of two devices, both with a high on-off ratio of >10⁹ and a low off-state current of less than 0.1 pA. Noticeably, the V_REF (reference voltage, defined as the V_GS required when the I_DS is equal to 1 nA) in S-Gated mode is offset by around 0.7 V in the forward (right) direction compared to Ref. FET. A larger V_GS for BG-FET is required to achieve the same current due to the bias-gated device structure. The maximum difference of I_DS under the same V_GS exceeds three orders of magnitude in the sub-threshold region. As the V_GS increases, this difference gradually decreases and tends to be consistent, because the electron density in the channel is gradually dominated by V_GS. The V_GS-dependent V_SAT, R_OUT, and more experimental data of two devices are demonstrated in Supplementary Fig. 1. These obvious differences between the two devices indicate the effectiveness of the bias-gated structure design.

More valuable is that the asymmetric bias-gated device architecture enables BG-FETs to possess threshold-adaptive field-effect characteristics, which is crucial for subsequent GLB circuit design. To verify the inherent robustness of this characteristic and assess its scalability for large-scale integration, we fabricate an array of 256 BG-FETs distributed across 16 dies, with each die integrating 16 individual devices (Supplementary Fig. 2). All devices were fabricated on a continuous single-crystal MoS₂ thin film³³ under identical process parameters. Subsequently, four BG-FETs were randomly selected from four units in each die for electrical characterization, yielding a total of 64 devices spread out to study uniformity over a large area. The transfer characteristics of BG-FETs under D-Gated and S-Gated modes are tested, as shown in Fig. 2g. The transistors exhibit a desired uniformity and threshold-adaptive field-effect characteristics. Besides, the statistical histogram of V_REF difference in two modes is concentrated between 0.54 and 0.6 V (see the inset of Fig. 2g), indicating a low device-to-device variability.

To further explore the stability of BG-FETs, we electrically characterized the as-fabricated devices placed in the vacuum atmosphere for 1 week, 4 weeks, and 7 weeks. As shown in Fig. 2h, the BG-FET maintains excellent threshold-adaptive field-effect characteristics after seven weeks, and the ΔV_REF of approximately 0.57 V between the two operating modes shows negligible variation throughout this period. And the BG-FET exhibits impressive threshold-adaptive field-effect characteristics even at high temperature of 400 K, as shown in Fig. 2i. Note that the threshold voltage of the BG-FET exhibits a negative shift with increasing temperature. This phenomenon can be attributed to the enhanced thermal activation of free carriers at elevated temperatures^34,35. Furthermore, a larger shift amplitude is observed in S-Gated mode, leading to a progressive decrease in ΔV_REF. This may be due to the release of more free carriers bound by the widened barrier induced by bias-gated electrostatics at high temperatures. The desired uniformity and stability of BG-FETs can be attributed to the bias-gated structure design with a built-in packaging function for maintaining the integrity of the channel materials, except for the high stability of the grown MoS₂.

Logic inverter based on unipolar MoS₂ BG-FET

The inverter (NOT gate) that performs the Boolean function Y = $\overline{\mathrm{A}}$ is a basic logic element in digital circuits, in which $\overline{\mathrm{A}}$ is defined as an opposite voltage level to input A. Figure 3a shows the schematic of an adaptive-switching logic inverter composed of two as-fabricated unipolar MoS₂ BG-FETs in series. In reported MoS₂-based inverter circuits^11,12,36,37, specific designs are required for the driver and load devices to achieve rail-to-rail operation, such as different width/length (W/L) ratios, metal gates, or channel materials between two transistors. In our demonstration, the as-fabricated SG-FET as driver (BG-FET in S-Gated mode) and DG-FET as load (BG-FET in D-Gated mode) can be dynamically switched through simple voltage manipulation.

Fig. 3. Static and dynamic characteristics of the BG-inverter.

a Cross-sectional schematic of the BG-inverter with a DG-FET (BG-FET in D-Gated mode) as load and a SG-FET (BG-FET in S-Gated) as the driver in series. The V_DD, V_OUT, V_IN, and GND represent the supply voltage, output voltage, input voltage, and ground for the inverter, respectively. b Optical image of two inverters made from BG-FETs and Ref. FETs, respectively, based on the same monolayer MoS₂ film. Scale bar, 20 μm. c Typical voltage transfer curves and voltage gain curves of two inverters at V_DD = 2 V. The switching threshold voltage (V_M) of the BG-inverter and the Ref.-inverter are approximately 0.59 V and −0.15 V, respectively. The corresponding peak voltage gain are approximately 57 and 53, respectively. d The variation trend of V_DD-dependent peak voltage gain (upper) and V_M (lower) for the BG-inverter. e The variation trend of V_DD-dependent static power (upper) and noise margin (lower) for the BG-inverter. f Cyclic reliability of the BG-inverter at a 2 V full-scale square input signal of 100 Hz for more than 1000 switching cycles. g Dynamic output voltage response at a square wave input signal with a frequency of 1 kHz (top) and the corresponding rise time and fall time of the output voltage (bottom).

To further clarify the role of a bias-gated device structure in digital circuits, two inverters made of BG-FETs and Ref. FETs are fabricated, respectively (Fig. 3b). The four devices used to fabricate two inverters have the same size and are based on a same single-layer MoS₂. Figure 3c shows the typical voltage transfer curves (VTCs) of two inverters with different switching threshold voltage (V_M) at V_DD = 2 V. The V_M of the BG-FET-based inverter (BG-inverter) shifts from approximately −0.15 V to 0.59 V compared with Ref. FET-based inverter (Ref.-inverter), which indicates that the BG-inverter can realize good rail-to-rail operation due to the threshold-adaptive field-effect characteristics of BG-FET. Noticeably, an inverter that loses the cascaded function due to input and output not in the same range is strictly referred to as an invalid circuit. As mentioned above, the reported inverters require a specific design to achieve rail-to-rail operation, however, this cannot change the function of the constituent components (load or driver) once built.

More detailed static characteristics of the BG-inverter and Ref. inverter under different V_DD are shown in Supplementary Fig. 3. Two inverters show similar performance for the parameters of gain and I_DD across all V_DD values. Where a peak gain of 157 for BG-inverter and of 159 for Ref. inverter, a peak I_DD of less than 2 nA for BG-inverter and of less than 5 nA for Ref. inverter are achieved at V_DD = 5 V. And the key parameters of BG-inverter, such as peak gain, V_M, noise margin (N_M/V_DD) and peak static power are intuitively shown in Fig. 3d, e. A total noise margin (NM_H + NM_L)/V_DD over 85% and a low static power (P_static) of less than 10 nW across all V_DD values are calculated. And the V_M shift of 0.06 V for BG-inverter under different V_DD is observed, which may be attributed to the ΔV_REF variation of BG-FET under different V_DD. In theory, the competition relationship between bias-gated and back-gated modulation can be controlled by optimizing the L_BG/L_ch ratios, in which L_BG and L_ch are defined as the length of the bias-gated electrode and the channel in Fig. 2a, respectively. As this ratio increases, the control region of the bias-gated electrode expands relatively. The controllable modulation of this competition relationship allows for the on-demand design of application-oriented devices.

Additionally, the BG-inverter can maintain a full-swing output response at a 2 V full-scale square input signal of 100 Hz, even after 1000 switching cycles (Fig. 3f). The dynamic switching speed mainly determined by the RC delay (τ), is also a very significant evaluation indicator in logic circuits. To further characterize this performance, the dynamic switching behavior of the BG-inverter by using an AC input signal is studied at higher frequencies (Supplementary Fig. 4). As demonstrated by the dynamic analysis, the inverter can immediately invert the input signal, and the output signal can maintain a high-quality waveform response that is opposite to the input signal at a relatively low frequency (<500 Hz). However, the output waveform gradually deformed with the frequency of the input signal increases, and full-swing output cannot be achieved at a higher frequency (>5 kHz) mainly due to a RC delay in dynamic switching. A rising time delay (τ_r) of 285 µs and falling time delay (τ_f) of 35 µs are extracted at 1 kHz, where the delay τ is defined as the time intervals between 10% and 90% of V_DD, as shown in Fig. 3g. These performance metrics of the BG-inverters demonstrate competitive results at the current device scale compared with state-of-the-art 2D materials-based CMOS inverters (Supplementary Table 1). There remains significant potential for further optimization through continued device engineering and process refinement.

Generic logic block based on unipolar MoS₂ BG-FET

Figure 4a schematically depicts the circuit design diagram of a GLB with a specific cascade mode based on four BG-FETs. This GLB can perform logic functions with six input terminals (V_IN-P1, V_IN-P2, V_IN-P3, V_IN-P4, V_IN-C and $\overline{{\mathrm{V}}_{\mathrm{IN}-\mathrm{C}}}$) and two output terminals (V_OUT-1 and V_OUT-2). The bias-gated source-drain is set as the pass-input terminal (V_IN-P), the non-bias-gated source-drain is set as the output terminal (V_OUT), and the gate is set as the control-input terminal (V_IN-C). Note that the manufacturing process parameters of four BG-FETs used to fabricate the GLB are almost identical (as shown in Fig. 4b), and they can all dynamically switch between D-Gated mode and S-Gated mode through simple voltage manipulation (Fig. 4c). These features mean that four V_IN-P ports of the as-fabricated GLB are fully equivalent, which is crucial for GLB to perform arbitrary logic operations in the same circuit. For example, the Boolean function for basic gate circuits (AND/NAND, OR/NOR, and XOR/XNOR), arithmetic unit (half-adder and 2:1 MUX) and memory cell (SRAM) can be achieved in a single GLB circuit by programming the combinations of input signals (as shown in Fig. 4d). The measured output waveforms driven by programming schemes and input combinations are shown in Fig. 4e, achieving a dynamic reconfigurable computing paradigm. Here, the high voltage level (2 V) is defined as logic “1” and the low voltage level (0 V) is defined as logic “0”. The implementation of more details is shown in Supplementary Figs. 5–7.

Fig. 4. Generic logic block based on four MoS₂ BG-FETs.

a Schematic diagram of circuit design for GLB with six input signals (V_IN-P1, V_IN-P2, V_IN-P3, V_IN-P4, V_IN-C and $\overline{{\mathrm{V}}_{\mathrm{IN}-\mathrm{C}}}$) and two output signals (V_OUT-1 and V_OUT-2). b Optical image of a MoS₂-based GLB consists of four BG-FETs. Scale bar, 20 μm. c Transfer curves of four BG-FETs in D-Gated mode and S-Gated mode at V_DS = 2 V. d Schemes for performing dynamically reconfigurable logic computing with ten functions in total. e Measured voltage waveforms of this GLB circuit with a full-swing output for all input combinations, including AND/NAND, OR/NOR, XOR/XNOR, Half-Adder and 2-1 MUX. f The measured encoding function of the GLB-reconstructed 4-2 Encoder.

In addition, the GLB can be reconstructed to a 4-2 encoder (a circuit that encodes 2ⁿ input signals using n-bit binary code) according the programming scheme shown in Fig. 4d. When V_IN-P1 is set to A₁, V_IN-P3 is set to A₂, V_IN-P2 and V_IN-P4 is set to A₃, V_IN-C is set to $\overline{\mathrm{A}3}$, V_OUT-1 is set to Y₁, and V_OUT-2 is set to Y₂, the GLB can perform the function of encoding 4-bit binary code (A₃, A₂, A₁, A₀) with 2-bit binary code (Y₁, Y₀). The measured result at a constraint condition (only one of the four signals A₀, A₁, A₂ and A₃ is set as logic “1” at the same time) and a hidden condition (when A₁, A₂ and A₃ are all set as logic “0”, it means A₀ is set as logic “1”) is shown in Fig. 4f. In this circuit, the 4-bit input signals: (0001), (0010), (0100), and (1000) are encoded as 2-bit binary codes: (00), (01), (10), and (11), respectively, which are consistent with the function truth table of the 4-2 encoder (Supplementary Fig. 8). Similarly, GLB can also be reconstructed as a 2-4 decoder (a circuit that decodes n-bit binary code into 2ⁿ-bit signals) that function exactly opposites to the encoder (Supplementary Fig. 9). Noteworthy, the GLB circuit can fully implement all logic functions with a full-swing output voltage due to the threshold-adaptive field-effect characteristics of BG-FET. The principle is analogous to the complementary structure in CMOS technology. More detailed explanation seen in Supplementary Fig. 10.

GLB-based digital circuits

To further verify the feasibility of GLB using BG-FET device architecture for digital circuit optimization, various arithmetic logic units (ALU) and sequential circuit units are integrated on the monolayer MoS₂ film. Figure 5a shows the schematics and optical image of a 2-bit carry-save-adder (CSA) multiplier that consists of four GLBs and four BG-inverters with 24 BG-FETs in total. By analyzing the principle of multiplication (depicted in Supplementary Fig. 11a), it is found that the partial products can be achieved through logic AND gates (Y = AB). While the sum of partial products can be achieved through adder circuits. Based on this principle, two GLBs are reconstructed as four AND gates to implement four partial products, two GLBs are reconstructed as two half-adders for partial product summation and four embedded BG-inverters are used to provide necessary complementary signals. The measured output voltage signals (P₀, P₁, P₂, P₃) are shown in Fig. 5b, indicating that GLB-based 2-bit CSA-multiplier can fully implement multiplication operations according to the truth table (shown in Supplementary Fig. 11b) for all the input combinations (A₁, A₀, B₁, B₀). CSA multiplier circuits that can improve the speed of data processing and enable more complex data analysis with efficient computing play an important part in digital ICs. Furthermore, the circuit design, optical image and measured results for 1-bit digital comparator, controllable left/right shifter and 1-bit full-adder based on BG-FETs are also plotted as examples in Supplementary Fig. 12. The output voltage signals can correctly respond to all possible input combinations according to the truth table.

Fig. 5. GLB-based digital circuits.

a Circuit design and optical image of a GLB-based 2-bit carry-save-adder (CSA) multiplier with 24 BG-FETs in total. Scale bar, 50 μm. b Functional measurements of the CSA multiplier using a series of input combinations (A₁, A₀, B₁, B₀) in the following order: (00 × 00, 00 × 01, 00 × 10, 00 × 11, 01 × 00, 01 × 01, 01 × 10, 01 × 11, 10 × 00, 10 × 01, 10 × 10, 10 × 11, 11× 00, 11×01, 11×10, 11×11). c Status table for the flip-flop circuits. Optical image, circuit design and experimental voltage waveforms for a low-level triggered D latch (d), a falling-edge triggered D flip-flop (DFF) (e) and a falling-edge triggered TFF (T flip-flop) (f) based on GLBs using monolayer MoS₂ film. Scale bar, 50 μm.

The sequential logic elements are critical components in memory and data manipulation circuits for digital ICs. Figure 5c shows the status table of D latch, D flip-flop (DFF), and T flip-flop (TFF), in which signal CLK, as the global clock control input, signal D, as the data input and signal Q, as the output. The circuit design, optical image, and measured waveforms of the D latch based on two BG-FETs and a SRAM reconstructed by GLB are plotted in Fig. 5d. In this sequential circuit, the output Qⁿ⁺¹ is seen to follow the input D when the input CLK is in logic “0”, which is consistent with the characteristic equation (Qⁿ⁺¹ = D). Conversely, the circuit operates as a memory mode when CLK is in logic “1”, meaning that the output Qⁿ⁺¹ remains in its current state Qⁿ. Compared with D latch, an edge-triggered DFF with better anti-interference feature can be fabricated through two D latch elements cascaded. Figure 5e shows the circuit schematic, optical image, and measured waveforms of a falling edge-triggered DFF, which consists of 12 BG-FETs in total. This circuit can immediately follow the data input D to output the correct logic signal (Qⁿ⁺¹ = D) at the falling edge of the control input CLK and hold the signal state (Qⁿ⁺¹ = Qⁿ) until the next falling edge.

Additionally, combining flip-flop circuits and composite basic gate circuits can also implement other sequential logic functions for different applications. For example, a falling edge triggered TFF based on a characteristic equation (Qⁿ⁺¹ = T⊕Qⁿ) can be fabricated by cascading an XOR gate at the D input terminal of DFF (that is, setting D = T⊕Qⁿ), as shown in Fig. 5f. The output signal Qⁿ⁺¹ from the measured waveforms flip once every time at the falling edge of control input CLK when data input T is logic “1”. Conversely, this TFF works in a memory mode when data input T is logic “0”. The TFF circuits can ensure the correct transmission of timing signals and also add a flipping function. Similarly, a flip-flop applied to the frequency-halving circuit is also shown as an example in Supplementary Fig. 13.

Discussion

We present a GLB logic architecture based on BG-FETs that utilize a single-polarity MoS₂ channel. The BG-FETs free of polarity modulation demonstrate promising potential as logic switches that can dynamically switch between D-Gated mode and S-Gated mode through a simple bias manipulation. As shown in Table 1, the as-created GLB, consisting of four BG-FETs, successfully implements over 10 Boolean functions (such as half-adder, 2:1 MUX, 4-2 encoder … SRAM) within a single circuit. In contrast, over 100 transistors are typically required to implement all of these functions in conventional CMOS design. Additionally, more complex digital circuits, such as 2-bit CSA-multipliers and flip-flops, were also designed based on the GLB configuration, yielding a transistor count reduction of over 60% compared to CMOS design. Furthermore, all the BG-FETs utilized in the fabrication of these digital circuits share identical process parameters, which is highly beneficial for the rapid establishment of a standard unit library. Our GLB architecture with built-in BG-FETs offers a promising logic prototype that transcends traditional CMOS design for future integrated circuit manufacturing.

Table 1.

Comparison of transistor number between CMOS and GLB logic design

Logic functions	Number of transistors
	CMOS design38	GLB design
AND	6	4
NAND	4
OR	6
NOR	4
XOR	≥11
XNOR	≥13
Half-adder	≥16
2-1 MUX	≥8
4-2 Encoder	≥16
2-4 Decoder	≥16
Comparator	≥16	6
Shifter	≥16	6
1-bit full-adder	≥28	8
2-bit CSA multiplier	≥58	24
D-latch	≥16	6
D-FF	≥32	12
T’-FF	≥32	12
T-FF	≥43	14

Methods

Device fabrication

The BG-FETs and BG-FET-based logic circuits are built using the fabrication process compatible with silicon-based technology. First, the pad electrodes and bottom electrodes are mapped in advance on the SiO₂/Si substrate using laser direct writing (Micro-Writer ML3) technology and proximity UV lithography (MA/BA6 Gen4) technology. Then, 10/50 nm Cr/Au is deposited using thermal evaporation (PRO-Line PVD 200), followed by atomic-layer deposition (TALD-200) of a 20-nm-thickness HfO₂ dielectric layer. The CVD-grown monolayer MoS₂ films are accurately stacked on the HfO₂ using wet-transfer technology with polymethyl methacrylate film as a sacrificial layer. It is necessary to pattern the MoS₂ film using the plasma etching (RLE-100R) technique with a mixture of O₂ and SF₆ to define the channel region. Subsequently, the designed drain and source electrodes are deposited based on e-beam lithography (EBL, FEI Quanta 3D) and thermal evaporation technology, and the ALD-grown HfO₂ with a buffer layer of Sb₂O₃ is deposited as the top gate dielectric. Where Sb₂O₃ powder was evaporated by heating in the PVD system with a high vacuum (10⁻⁷ torr). The deposition rate is controlled to be 0.05 Å/s for the flat film with a thickness of 2–3 nm. Finally, the top bias-gated electrodes are deposited onto the designated position.

Electrical measurement

The electrical characteristics of the single BG-RFET devices and simple circuits are measured using a semiconductor parameter analyzer (Agilent B1500 coupled with six SMUs and two PMUs) in a vacuum probe station (Lake Shore). The measurements of complex digital circuits are performed by a semi-automatic probe station (SUMMIT200) connecting to a modular PXle SMU testing system (M9019A) equipped with six 5-channel source/measure units with 30 SMUs in total. All measurements for BG-FET, GLB, and GLB-based logic circuits are conducted at room temperature.

Author contributions

X.W., X.Z., Z.Z., and Y.Z. initiated and supervised the project. X.W., X.Z., and Z.Z. designed the experiments. X.W., Z.C., and K.C. performed device fabrication, data collection, and analysis. H.J. and J.S. assisted in the preparation and characterization of monolayer MoS₂ by CVD. L.G. and Z.C. assisted in performing in situ characterization experiments. M.H., L.G, and H.Y. assisted in the device performance measurement and data analysis. X.W., X.Z., and Z.Z. co-wrote the manuscript. All authors discussed the results and commented on the manuscript.

Peer review

Peer review information

Nature Communications thanks Chen Pan and the other anonymous reviewers for their contribution to the peer review of this work. A peer review file is available.

Data availability

Relevant data supporting the key findings of this study are available within the article and the Supplementary Information file. All raw data generated during the current study are available from the corresponding authors upon request.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-70712-9.