Region-segmented gate driver for mitigating RC delay in large-area automotive OLED displays

Abstract

Large-area active-matrix panels suffer from timing distortion caused by resistive–capacitive (RC) accumulation along extended signal lines. To minimize signal propagation length and reduce accumulated RC loading, a distributed gate-driving architecture is proposed. The design embeds multiple gate driver units within a region-segmented pixel array, utilizing a clustered and shielded layout to suppress parasitic coupling. Simulations for a 27-inch AMOLED panel demonstrated a 57% reduction in signal delay, consistent with the Elmore delay approximation. The gate signal delay variation across the panel, which was approximately 4.0 µs in the conventional gate driver, became negligible with the proposed architecture, ensuring sufficient threshold voltage compensation time. A prototype fabricated using low-temperature polycrystalline silicon thin-film transistors exhibited uniform signal timing, 91.4% luminance uniformity, and a black luminance of 0.009 cd/m². These results validate that the proposed gate driver architecture ensures stable signal delivery, substantially reduces timing non-uniformity, and enhances overall electro-optical performance for large, high-resolution display systems.

Supplementary Information

The online version contains supplementary material available at 10.1038/s41598-026-48039-8.

Introduction

The rapid growth of electric and autonomous vehicles has increased demand for advanced automotive displays, which have evolved from basic information panels to integrated systems that provide convenience, enhance safety, and deliver infotainment. As vehicles transform into mobile offices or personal relaxation spaces, this trend has driven the development of larger, pillar-to-pillar and free-form display panels^1–5.

Recently, low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based active-matrix organic light-emitting diode (AMOLED) technology has enabled high performance and flexible designs on polyimide substrates, accelerating its adoption in automotive applications^6–10. However, LTPS TFTs exhibit threshold voltage (V_TH) variations caused by non-uniform grain structures, trap states at grain boundaries, and process-dependent mobility fluctuations^11,12.

An internal V_TH compensation circuit is indispensable for suppressing device-level non-uniformity and stabilizing pixel currents within the limited gate signal timing^13–15. The effective compensation time (T_COMP) is defined as the allocated sampling duration within one horizontal period (1 H) minus the resistive–capacitive (RC) delay. Insufficient effective T_COMP leads to incomplete detection and image degradation^16–19. Since the gate signal is generated by the gate driver in panel (GIP), its output capability and transmission characteristics directly determine the effective T_COMP and the overall panel performance.

The GIP eliminates external driver integrated circuits (ICs) and packaging, thereby reducing costs. Various GIP circuit techniques have been studied to enhance performance^20–25. However, the conventional gate driver (CGD) is typically located in the bezel region. As the panel size increases, the extended gate lines accumulate resistance and capacitance, resulting in signal delay, particularly in the center region, which reduces the effective T_COMP. Although advanced circuit techniques such as bootstrapping^23,24 and pulse shaping²⁵ have enhanced drivability, the structural delay inherent to bezel-based architectures remains a limitation in large-area panels.

Figure 1 illustrates these limitations of the CGD structure. As shown in Fig. 1a, small panels maintain uniform gate signals and stable image quality. In contrast, Fig. 1b shows that large panels, whose gate line length and horizontal resolution are approximately three times larger than those of a small panel, exhibit an RC-induced delay and timing imbalance at the panel center. These effects reduce the effective T_COMP and degrade image quality. As shown in Fig. 1c, a pixel composed of p-type LTPS TFTs performs V_TH compensation within the 1 H period. The reduced effective compensation time causes spatial luminance non-uniformity. To address the issue of extended gate line paths in a landscape-oriented panel, a portrait-oriented panel could be considered. However, this approach introduces longer data lines, which cause data signal delay and compensation distortion, thereby degrading image quality. At the process level, increasing the metal layer thickness or thickening the insulating layer can mitigate RC delay. However, these methods are limited by manufacturing costs and design rules. Consequently, an architectural solution is required to reduce the gate signal propagation length (L) and ensure panel-wide signal uniformity without process-level scaling.

Fig. 1.

Illustration of luminance uniformity and gate signal distribution in a CGD (a) 10-inch panel, (b) 30-inch panel, and (c) representative pixel circuit with internal V_TH compensation and timing diagram.

To minimize the panel bezel and enable free-form designs, the integration of gate driver circuits directly within the active pixel array has been explored^26–28. However, prior studies have reported that large voltage swings of embedded gate-driver signals may induce parasitic capacitive coupling to adjacent pixel nodes^27,28. This issue becomes particularly critical in OLED displays employing internal V_TH compensation, where multiple in-pixel TFTs and dynamic nodes increase the sensitivity of the driving current to electrical disturbances.

We propose a region-segmented gate driver (RSGD) architecture that embeds multiple gate drivers within the segmented regions of the active array. To mitigate the signal interference typical of embedded architectures, a clustered and shielded layout is employed to suppress parasitic coupling between high-voltage gate signals and sensitive pixel nodes. This distributed configuration effectively reduces the signal propagation length and ensures uniform gate signal delivery across large OLED panels while maintaining compatibility with standard manufacturing processes. The output characteristics of the proposed RSGD were analyzed through simulations and compared with those of CGD. The practical effectiveness of the proposed architecture was verified through prototype fabrication, demonstrating uniform gate signal timing and luminance distribution.

Proposed structure

Figure 2a illustrates the CGD-based panel structure, along with the circuit schematic and driving timing of the gate driver that outputs the scan signal. In the CGD, each gate line is driven by two driver outputs located at the panel edges. As the panel size and resolution increase, the signal propagation length increases, leading to severe RC accumulation and significant signal delay. This delay cannot be accurately described by a simple linear transmission model but can be quantified using the Elmore delay approximation by modeling the gate line as a distributed RC network^29,30. The gate signal delay can be expressed as:

Fig. 2.

Gate driver configurations with circuit and driving timing about one horizontal gate line (a) CGD located at both bezels and (b) proposed RSGD with distributed drivers embedded in the active array.

1

where R_S is the output resistance of the gate driver circuit, R_L and C_L are the line resistance (Ω/m) and capacitance (F/m) per unit length, respectively, and L denotes the signal propagation length along the gate line. Consequently, the delay increases proportionally with L², which becomes a critical factor for large-area panels.

To overcome this limitation, we propose an RSGD structure, in which the active array is divided into N regions, each containing one embedded gate driver unit, as illustrated in Fig. 2b. The proposed RSGD preserves the same gate driver timing sequence as the CGD, thereby maintaining compatibility with the existing pixel circuit and timing scheme. Unlike conventional edge-driven architectures where delay scales quadratically with panel length (L²), this segmented architecture reduces the delay proportionality to (L/N)² while preserving the continuous gate line structure. In this configuration, N uniformly arranged drivers provide N output points for each gate line. Consequently, the signal propagation length is reduced to L/N, substantially lowering the accumulated RC load. This configuration achieves uniform signal timing across the panel and improves image quality. As a result, the spatial delay variation across the panel is significantly reduced compared with conventional edge-driven architectures.

To address the increasing RC load at the Q node (gate of the pull-up TFT) and QB node (gate of the pull-down TFT) caused by long interconnect lengths, the proposed RSGD adopts a clustered transistor layout instead of dispersing devices throughout the array. This layout shortens interconnects between driver devices, thereby reducing parasitic resistance and capacitance and stabilizing gate signal timing. Furthermore, to mitigate the signal interference, electrical shielding is implemented to suppress capacitive coupling to pixel nodes, ensuring stable operation of the gate driver units.

Overall, the proposed RSGD reduces accumulated RC delay and improves timing uniformity across the panel. Together with the shielded layout that suppresses capacitive coupling to pixel nodes, the proposed architecture enables stable operation of internally compensated LTPS OLED panels under large RC loading conditions. In addition, the modular architecture ensures scalability, as the RC delay can be managed by adjusting the distribution density (N) of the driver blocks according to the panel size. Consequently, the proposed architecture provides a robust and scalable solution for large-area automotive OLED panels.

Results and discussion

Simulation results

To validate the effectiveness of the proposed RSGD structure, SmartSpice simulations were performed for a 27-inch panel with a resolution of 5500 (H) × 900 (V). The total resistance and capacitance of a single gate line were extracted as approximately 74 kΩ and 165 pF, respectively. In the CGD, each gate line is driven by two edge drivers, which require large pull-up and pull-down TFTs (hundreds of micrometers wide) to charge and discharge the entire line. To verify the architectural benefit of embedding distributed drivers, the RSGD incorporates N = 72 modules uniformly arranged along each gate line, each using smaller TFTs. In this study, the signal delay is defined as the transition time measured between 10% and 90% of the full voltage swing. The segmentation level (N = 72) was determined through a parametric sweep analysis to minimize the gate output delay. As summarized in Supplementary Fig. S1, increasing the number of RSGD modules per driver IC effectively reduces the gate line RC loading. However, beyond the optimal point, the gate output delay begins to increase because the additional control signal (CLK) routing parasitics dominate the signal transition time. Consequently, the minimum delay was achieved at 8 modules per driver IC, resulting in a total of N = 72 modules for the 27-inch prototype panel.

Figure 3 summarizes the simulated gate line delay as a function of the pull-up TFT width, as the falling (T_F) and rising (T_R) transitions depend on the pull-up TFT size, and compares the CGD and RSGD under optimized device dimensions. As shown in Fig. 3a, increasing the pull-up TFT width in the CGD does not sufficiently reduce the delay at the panel center owing to the accumulated RC load. The resulting center-to-edge delay variation (Δ ≈ 4.0 µs) produces a substantial difference in the effective T_COMP, degrading compensation accuracy and causing luminance non-uniformity, consistent with previous reports that insufficient T_COMP increases pixel-current errors^16,18.

Fig. 3.

Simulated signal delay as a function of pull-up TFT width at panel center (maximum RC load) and edge (minimum RC load) for the (a) CGD and (b) proposed RSGD (N = 72). Corresponding simulated gate output waveforms at optimized parameters for the (c) CGD and (d) proposed RSGD. (Input pulse width = 10 µs, V_H/V_L = ± 9 V) (e) simulated pixel current error (I_OLED) at the panel center and edge for CGD and RSGD architectures as a function of the driving TFT threshold voltage variation (from − 0.5 V to + 0.5 V, step 0.1 V).

In contrast, Fig. 3b shows that the RSGD maintains consistently short T_F and T_R across the panel, even with small pull-up TFT widths. The segmented architecture effectively reduces the RC load by reducing the signal propagation length, thereby suppressing the center delay observed in the CGD. Consequently, the variation in delay across the panel becomes negligible. This uniform timing ensures a consistent T_COMP, eliminating the spatial variation present in the CGD. Although the distributed architecture inherently involves signal propagation delays for the input control signals, the simulations presented in Fig. 3 include the delays associated with these pre-driver routing paths. The results demonstrate that the RSGD effectively minimizes the total gate signal delay, outweighing the impact of the increased input routing path. Furthermore, the segmented architecture distributes the total capacitive load across multiple driver units, reducing the peak current demand on individual pull-up and pull-down transistors. This dispersion of electrical stress mitigates current concentration, which is expected to enhance the long-term reliability of the driver components.

To further analyze the signal quality, Fig. 3c compares the center and edge waveforms under the optimized CGD device dimensions (W/L = 500.0/10.0, 500.0/10.0, and 7.0/10.0 μm for pull-up, pull-down, and switch TFTs, respectively, with 200 fF capacitors). At the panel center, the gate signal showed T_F and T_R of approximately 6.3 µs and settled only to − 8.4 V, failing to reach the preset (V_L = − 9.0 V), indicating incomplete discharge and insufficient settling time.

Figure 3d compares the center and edge waveforms under the optimized RSGD (W/L = 6.0/5.0, 4.0/5.0, and 3.0/5.0 μm for pull-up, pull-down, and switch TFTs, respectively, and 100 fF capacitors). Both regions exhibited T_F and T_R of approximately 2.7 µs, a 57% reduction relative to the CGD, and reached the preset voltage (V_L = − 9.0 V), confirming complete and uniform discharge. These improvements are consistent with the Elmore delay approximation (τ ∝ L²), as the segmented architecture substantially reduces the effective propagation length. Furthermore, the coupling noise at the pixel node is effectively suppressed by the electrical shielding, confirming that signal interference does not compromise pixel operation. Consequently, the RSGD provides a sufficient and spatially uniform T_COMP for reliable V_TH compensation across the panel.

To establish the causal relationship between timing uniformity and image quality, the pixel current (I_OLED) error was evaluated via SmartSpice simulation as shown in Fig. 3e. By neglecting IR drop and assuming uniform OLED characteristics, the simulation isolated the impact of RC delay. The I_OLED was measured for a 50 nA target while sweeping the driving TFT threshold voltage variation (∆V_TH) from − 0.5 V to + 0.5 V.

As shown in Fig. 3e, the CGD structure exhibits a 16.8% current variation at the panel center even at ∆V_TH = 0. As illustrated in Supplementary Fig. S2, RC delay variation causes a deviation in the sampled gate voltage of the driving TFT, which leads to pixel current error. Under the worst-case ∆V_TH variation, the current error increases to approximately 37%, indicating that large RC delay degrades the intrinsic V_TH compensation capability of the pixel circuit.

In contrast, the proposed RSGD maintains a nearly uniform effective T_COMP across the panel. Consequently, the I_OLED error remains negligible at ∆V_TH = 0 and is constrained within ± 10% even under ± 0.5 V variations. These simulation results confirm that the mitigation of RC delay is a primary factor in suppressing spatial current variation and ensuring high luminance uniformity in large-area displays.

Prototype fabrication and experimental setup

A 27-inch prototype was fabricated to experimentally verify the RSGD. The gate driver circuits were implemented using top-gate p-type LTPS TFTs, as shown in Fig. 4a, and the test panel was manufactured using a standard commercial top-gate LTPS process. Figure 4b shows the measured transfer characteristics of a representative p-type LTPS TFT (W/L = 3.0/5.0 μm). The V_TH and field-effect mobility were approximately − 3.8 V and 91.9 cm²/V·s, respectively, measured using a Tektronix Keithley 4200 parameter analyzer. The gate driver circuits were fabricated using the same TFT and capacitor dimensions as those used in the simulations.

Fig. 4.

(a) Cross-sectional structure of the LTPS-TFT, (b) measured transfer characteristics of the LTPS TFT (W/L = 3.0/5.0 μm), (c) optical micrograph of the fabricated RSGD gate driver circuit, (d) detailed view of the shielding layout in the RSGD, and (e) transient simulation of coupling-induced pixel current variation under worst-case low-grayscale conditions.

An optical micrograph of the fabricated gate driver layout is shown in Fig. 4c. When gate drivers are integrated within the active array, parasitic capacitive coupling can be induced by dynamic switching nodes, such as Q, QB, and CLK. In OLED panels with internal V_TH compensation, the coupling between the RSGD and pixel circuits requires careful consideration. Without electrical shielding, placing dynamic switching nodes near pixels can introduce fluctuations in pixel-related nodes, causing current variations in the pixel circuit. To mitigate this concern, the proposed RSGD layout incorporates electrical shielding of dynamic nodes using constant bias lines (V_L, V_H, V_INIT, and V_DD), as illustrated in Fig. 4d. These layout optimizations suppress parasitic capacitive coupling and support stable gate signal operation of the embedded drivers.

To preserve the aperture ratio while integrating RSGD blocks, the test panel adopts a top-emission OLED structure in which the emission area is vertically separated from the underlying TFT layout (Supplementary Fig. S3). Because all driving circuits, including the embedded RSGD blocks, are located beneath the reflective anode layer, this configuration avoids degradation of the aperture ratio.

However, allocating a portion of the pixel area for the RSGD block introduces additional layout constraints. For the prototype with a physical pitch of 209 PPI (121.5 μm × 121.5 μm), the RSGD block occupies 27 μm of the horizontal pitch, leaving an effective horizontal space of 94.5 μm for the pixel circuit layout. This corresponds to a layout-equivalent density of 269 PPI (a 28% increase), which remains well within the practical process capability of standard LTPS backplane technologies. The relationship between the RSGD placement period and the layout-equivalent pixel density is analyzed in Supplementary Fig. S4. Although increasing the placement period can reduce the layout density burden, it also increases the control signal routing length and parasitic capacitance. Therefore, the placement period was optimized to balance RC delay mitigation, parasitic capacitance, and layout feasibility.

To further verify the electrical stability of the RSGD architecture, layout-based parasitic analysis and transient simulations were performed. While high-swing CLK signals can potentially disturb pixel operation, the constant bias lines (V_L, V_H, V_INIT, and V_DD) act as effective shields, maintaining the coupling capacitance below 0.5 fF for most nodes. However, due to structural constraints, the absence of a shielding layer between the dynamic nodes and the top-emitting blue pixel anode results in a worst-case parasitic capacitance of approximately 3.3 fF.

To evaluate the impact of this worst-case coupling condition, transient simulations were conducted under low-grayscale operating conditions (80-gray level, with a target current of approximately 12 nA). As shown in Fig. 4e, an 18 V peak-to-peak CLK swing induces temporary current peaks. However, the steady-state root-mean-square (RMS) current deviation, calculated over the emission interval after transient settling, remains under 1.0%.

The minimal deviation indicates that the effective driving current variation remains limited at the pixel level and is unlikely to produce a perceptible luminance variation under the evaluated conditions.

After confirming the feasibility of the proposed RSGD through simulations and prototype fabrication, its performance was evaluated using a 27-inch OLED panel. The electrical and optical characteristics, including luminance uniformity, were measured at room temperature using an Agilent DSO-9104 A oscilloscope and Konica Minolta CA-410 color analyzer. The luminance uniformity was evaluated at 27 positions arranged in a 3 × 9 grid across the panel, with white luminance measured at 600 cd/m²³¹.

Experimental results

The measurement results are summarized in Fig. 5. As shown in Fig. 5a, the gate signal waveforms were measured at both the edge and center of the panel. At the panel center, T_F and T_R were 2.3 and 1.2 µs, respectively. These values align well with the simulated trends, accounting for potential discrepancies in parasitic extraction and measurement conditions. In addition to the scan signal, the emission (EM) output waveform was also measured and verified using the proposed RSGD architecture. The complete gate driver schematics, the combined scan/EM timing sequence, and the measured EM output waveform are provided in Supplementary Fig. S5. The measured EM waveforms exhibit high uniformity, with the rise time (T_R) variation between the panel edge and center being negligible. The uniform distribution of RSGD modules effectively minimized the signal propagation delay, resulting in a significant reduction in delay variation compared to conventional edge-driven structures. These results demonstrate that the RSGD provides sufficient driving time for V_TH compensation and ensures uniform gate signal timing across the panel.

Fig. 5.

Measured results of a 27-inch panel with the proposed RSGD (a) gate signal waveforms at the panel edge and center, (b) white luminance uniformity (3 × 9 points, 600 cd/m²) (c) black luminance distribution of four panels (P1–P4), and (d) spatial luminance-variation map (ΔL_avg) based on white luminance measurements.

To quantitatively assess the luminance uniformity, white and black luminance distributions were measured, as summarized in Fig. 5b,c. White luminance uniformity was calculated using (2):

2

where L_min and L_max denote the minimum and maximum luminance values, respectively. The target specifications were greater than 80% for white luminance uniformity and below 0.010 cd/m² for black luminance, corresponding to typical automotive display requirements^32,33. The measured white luminance uniformity was 91.4%, and the black luminance was 0.009 cd/m².

Figure 5d illustrates the spatial distribution of ∆L_avg (x, y), which represents the white luminance variation measured relative to the panel center:

3

where L_Ref,i is the luminance measured at the panel center. The variation map indicates that the luminance deviation across all measured positions remained within ± 10%, demonstrating excellent spatial uniformity over the entire display area. This performance exceeds automotive requirements, confirming that the distributed architecture of the RSGD ensures stable gate signal delivery, resulting in high luminance uniformity across the panel.

Beyond the improved luminance uniformity, the impact of architectural segmentation on control signal routing capacitance and power consumption was also evaluated. Although distributed placement increases control line parasitic capacitance, experimental results under 60 Hz full-white operation indicate that the gate driver power accounts for approximately 4% of the total panel power (< 1 W). Because the emission (EL) current dominates the overall panel power consumption, the high luminance uniformity (91.4%) achieved by the RSGD architecture minimizes the need for pixel over-driving to compensate for localized luminance drops. The resulting reduction in EL driving power effectively offsets the minor increase in power consumed by control signal routing. The overall trade-off between the performance gain (e.g., gate delay and luminance uniformity) and the associated implementation costs is quantitatively analyzed in Supplementary Table S1. Consequently, the RSGD provides a robust and feasible solution for achieving reliable timing performance in large-area OLED panels while maintaining a reasonable power overhead that is well-compensated by the enhanced luminance uniformity.

Figure 6 presents the visual evaluation results of a 27-inch automotive OLED panel implementing the proposed RSGD. As shown in Fig. 6a, no image distortion or noise artifacts were observed at the boundaries between RSGD segments, even under complex patterns containing backgrounds, icons, and text. Figure 6b further verifies that the shielding design effectively suppresses parasitic capacitive coupling, ensuring uniform image quality under monochromatic test patterns. These results confirm that the proposed RSGD enables stable gate signal operation and uniform luminance across large-area OLED panels, demonstrating its feasibility for next-generation automotive display systems.

Fig. 6.

Demonstration results of a 27-inch automotive OLED display with the proposed RSGD (5500 × 900 resolution) (a) dashboard image and (b) enlarged panel-area views showing monochromatic test patterns, used to verify suppressed parasitic-capacitance coupling.

Conclusion

In this study, an RSGD architecture was proposed to address the signal delay limitations inherent in large-area OLED displays. By embedding the gate driver units within the active array, the proposed structure fundamentally reduces the effective propagation length and accumulated RC delay, thereby mitigating the limitations of conventional edge-driven designs. This approach ensures a sufficient and uniform T_COMP across the entire panel. A 27-inch LTPS TFT-based AMOLED prototype was fabricated to experimentally validate the proposed structure. Measurements confirmed uniform gate signal timing at both the edge and center regions, consistent with the simulation trends, and achieved a high white luminance uniformity of 91.4%. This result indicates that the proposed architecture significantly reduces spatial delay variation across the panel compared with conventional edge-driven architectures. Furthermore, this system-level architecture enhances electrical reliability by distributing electrical stress across multiple driver units. It also supports overall power efficiency by ensuring high luminance uniformity, which reduces the necessity for over-driving. A comprehensive quantitative comparison of the proposed RSGD and the conventional edge-driven architecture is summarized in Supplementary Table S1. Consequently, the RSGD combines enhanced electrical performance with high design flexibility, providing a robust and practical solution for next-generation automotive and premium display applications.

Supplementary Information

Below is the link to the electronic supplementary material.

Author contributions

D.S. organized the data, drew figures, and wrote the main manuscript text. S.G.H., Y.-M.J., E.-H.C., C.N., S.J., and J.Y. reviewed the results and implications and commented on the manuscript at all stages. The project was guided by H.J.K. (corresponding author).

Funding

This work was supported by the LG Display Co., Ltd. and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2023-00256917).

Data availability

All data analyzed during this study are included in this published article. The raw data used are available from the corresponding author upon request.

Competing interests

The authors declare no competing interests.