Void-free Cu/dielectric hybrid bonding at low-temperature enabled by ultrathin metal passivation engineering for 3D-IC applications

Abstract

Copper (Cu) surface topography, galvanic corrosion at the Cu-barrier interface and Cu-to-dielectric bonding primarily due to the misalignment are the present critical challenges in achieving void-free hybrid bonding. Additionally, Cu surface oxidation and dishing remain key bottlenecks in enabling reliable Cu interconnections at low temperatures in Cu/dielectric (SiO₂) hybrid bonding. To overcome these limitations, here we introduced a fabrication strategy that integrates an ultrathin metal (titanium (Ti)) passivation layer selectively engineered for Cu bond pads while maintaining compatibility with the damascene process. Despite the presence of the passivation layer, the observed Cu diffusion across the bonding interface and improved electrical contact resistance provides direct evidence of enhanced interfacial interdiffusion and oxidation resistance. This approach offers a scalable and effective solution for mitigating fundamental challenges in Cu/SiO₂ hybrid bonding and holds strong potential for integration into three-dimensional heterogeneous packaging technologies, enabling low thermal budget processing at ≤ 250 °C for ≤ 1-2 hour.

Hemanth Kumar Cheemalamarri and colleagues report that Ultrathin Cu selective metal passivation enables void-free Cu/dielectric hybrid bonding by suppressing oxidation and topography nonuniformity, enhancing interfacial diffusion and electrical performance at ≤250 ˚C for next-generation 3D stacked high bandwidth memory.

Introduction

Advanced packaging continues to drive semiconductor Performance, Power, Area, and Cost (PPAC) advancements, defying the constraints imposed by the perceived end of Moore’s Law. Among emerging technologies, hybrid bonding has becoming essential in demonstrating remarkable potential in applications such as high-end image sensors¹, high-bandwidth memory², and high-performance computing for Artificial Intelligence (AI)³. This technology enables the vertical/three-dimensional integration (3D IC) of wafers or chips fabricated using different process nodes, achieving sub-10 μm pitch scaled interconnects by utilizing the hybrid bonding^4,5. Hybrid bonding involves the direct bonding of a dielectric material and an embedded metal, typically dielectric (SiO₂, SiCN, etc.) and copper (Cu). The Cu bonding pads, formed through the damascene process as shown in the Fig. 1a: i–viii, maintain compatibility with conventional complementary metal–oxide–semiconductor (CMOS) manufacturing, making hybrid bonding a scalable and promising solution for next-generation 3D integration^4,5. In the damascene process, galvanic corrosion at the Cu and barrier metal interface during chemical mechanical polishing (CMP) presents a critical challenge. This occurs when these dissimilar metals come into contact with an electrolyte, such as the CMP slurry, leading to accelerated corrosion of the less noble metal due to the electrochemical potential difference between them^6,7. Specifically, Cu acts as the cathode, while the barrier metal serves as the anode, resulting in localized degradation at their interface, which can compromise the integrity and reliability of Cu interconnects, particularly at smaller feature sizes. A similar phenomenon has been observed at the Cu/Ti barrier layer interface of 3 µm Cu pads with 6 µm pitch, as shown in high-resolution transmission electron microscopy (HR-TEM) Fig. 1b. i, ii. In addition, Cu surface has been observed with an ultrathin copper oxide (CuO_x), as Cu is very prone to get oxidized and it acts as a diffusion barrier for Cu to diffuse. Furthermore, the atomic force microscopy (AFM) inspection shown in Fig. 1b. iii, depicts a localized variations on the Cu pad roughness, resulted due to the CMP removal subjected to grain size⁶, make the surface roughness higher than dielectric with dielectric surface root-mean-square (RMS) roughness of <0.2 nm and Cu surface is ~0.67 nm measured across 2 µm × 2 µm area, along with galvanic corrosion. The observed Cu dishing of 7 nm ± 3.4 nm, and a hallow trench of ~45 nm between Cu pad and the barrier layer resulted due to the galvanic corrosion.

Fig. 1. Conventional Cu/dielectric hybrid bonding and associated challenges.

a Schematic representation of wafer fabrication via the damascene process and subsequent wafer bonding. i–viii Stepwise damascene process for embedding Cu within the dielectric: i Deposition of dielectric layers—silicon nitride followed by silicon oxide, ii Photoresist coating, patterning using stepper lithography, and resist development, iii Dielectric etching using the resist mask, stopping at the nitride layer with endpoint detection, iv Photoresist removal and wafer cleaning, v–vi Deposition of a Ti barrier and Cu seed layer via PVD, vi Cu electroplating, vii CMP to remove excess Cu and achieve controlled Cu dishing and barrier exposure. ix Room-temperature wafer bonding of dielectric layers following plasma activation. x post-bond annealing to enhance dielectric bond strength and enable Cu–Cu interconnections. b Surface Topography and Hybrid Bond Inspection. i, ii TEM inspection of Cu/barrier interface topography, highlighting increased Cu dishing due to galvanic corrosion and Cu surface oxide of few nm. iii AFM analysis of the hybrid bond surface (20 µm × 20 µm) along with a corresponding line scan profile, capturing post-CMP surface characteristics. c Post-Bonding Interface Defects and Void Analysis. i Schematic representation of potential voids at the bonded interface: 1. Barrier-dielectric layer voids. 2. Cu voids induced by galvanic corrosion. 3. Cu–Cu voids due to surface non-uniformity. 4. Cu-dielectric voids. 5. Dielectric-dielectric voids resulting from thermal stress due to the mismatch in the coefficient of thermal expansion (CTE) during high-temperature annealing. ii FIB-SEM analysis of the bonded interface, correlating observed voids with the schematic representation.

Additionally, in hybrid bonding, achieving the appropriate Cu dishing is crucial to ensure initial dielectric surface contact during the bonding process, as illustrated in Fig. 1a. viii^8,9. These wafers with Cu dishing undergo bonding through hydrophilic interactions formed at room temperature after plasma activation (N₂ plasma used), followed by high-temperature annealing (~350 °C) for 2 h, as depicted in Fig. 1a. ix, x, respectively. This annealing step enhances dielectric bond strength while leveraging thermal coefficient of expansion (TCE) mismatch among dielectric and Cu to facilitate Cu–Cu interconnect formation. The post-bond interface is shown in the schematic and its respective cross section using focused ion beam with scanning electron microscopy (FIB-SEM) shown in Fig. 1c. The bonding interface defects, classified as types 1–5 as marked in the figure, remain unresolved challenges to date. These bonding voids primarily originate from surface roughness introduced during the CMP process. Notably, previous studies have reported a strong correlation between the copper (Cu) grain size and its removal rate during CMP^10,11, which contributes to increased surface roughness of the Cu pad as shown in Fig. 1b. iii, thereby exacerbating bonding defects even at high temperature annealing¹². In addition, inherent fabrication tool misalignments included with bonding tool make the regions where the bonding of Cu or barrier layer to dielectric bonding interface is still a challenge to make the void free interface.

To tackle these challenges, this study presents an innovative approach for achieving a void-free bonding interface through damascene-compatible ultrathin Cu selective surface passivation engineering. While various researchers have explored low-temperature Cu–Cu direct bonding utilizing Cu microstructure^13,14, and surface passivation techniques¹⁵, employing metal passivation layers such as platinum and chromium¹⁶, gold¹⁷, gold and Palladium¹⁵, titanium^18,19, cobalt²⁰, silver²¹, surface-assembled monolayers (SAM)²² and Cu grain and orientation^13,14,23. However, SAM-based methods face limitations in standard CMOS integration due to additional equipment requirements and complex desorption steps prior to bonding. Similarly, while metal-based passivation strategies have shown promise, most demonstrations rely on thermocompression bonding, and their compatibility with damascene process-compatible integration remains largely unexplored. For example, Liu et al.²⁴ proposed Cu-selective Au passivation using photoresist masking, but the scalability of this approach is challenged by lithographic misalignment, step-coverage limitations, and the potential for Cu pad contamination and interfacial void formation, and which is not a damascene-compatible process. Furthermore, Grain-modified Cu bonding has also emerged as a promising route for low-temperature hybrid bonding, particularly through optimization of electroplating bath chemistry and CMP processes, which can minimize added process complexity.

Nevertheless, in fine-pitch hybrid bonding interconnects, grain engineering alone may not sufficiently mitigate interfacial voiding due to CMP-induced localized pad topography non-uniformity, galvanic corrosion at Cu/barrier interfaces, surface oxidation, and bond-pad misalignment. Indeed, studies by Mirkarimi et al.²⁵ comparing standard BEOL Cu, nano-twinned Cu, and fine-grain Cu consistently observed void formation at Cu/barrier interfaces, attributed to galvanic corrosion and pad misaligned metal/dielectric interfaces. These observations underscore the need for an alternative solution that can effectively suppress such interface-driven degradation while enabling high-quality bonding at a reduced thermal budget.

Results and discussion

In this study, a systematic framework was employed to identify an optimal passivation metal, with key selection criteria including electrical conductivity on par with copper (Cu), compatibility with CMOS and damascene process flows, and the capacity to enable Cu diffusion or form a conductive intermetallic interface. Titanium (Ti) was identified as a particularly promising candidate due to its intrinsic CMOS compatibility and favorable surface kinetics. Notably, Ti exhibits a lower surface activation energy, which facilitates the diffusion of Cu toward the Ti interface. In contrast, for ultrathin Ti/titanium oxide (TiOx) films, a reverse diffusion of Ti species toward the Cu substrate was observed, as previously reported²⁶. Although Ti-passivated Cu–Cu bonding has been previously demonstrated, this work extends this concept to Cu/dielectric hybrid bonding in fine- and ultrafine-pitch CMP-patterned structures, where bonding integrity is strongly affected by planarization non-uniformity and reduced Cu feature dimensions. An innovative passivation strategy was developed to selectively form an ultrathin Ti layer on Cu surfaces using CMP process engineering, as schematically illustrated in Fig. 2a (panels vi–x). This tailored passivation architecture effectively mitigates Cu dishing and surface non-uniformities, particularly in regions with complex topography on the Cu pad surface resulted upon Cu bulk polishing and galvanic corrosion-induced trench at Cu/barrier interface, by filling with an optimized Ti passivation thickness. This protective layer also inhibits the formation of copper oxides (CuOx), as the passivation layer deposited immediately after Cu CMP polishing, clear evidence as shown in HR-TEM images in Fig. 2b (panels i–iii). AFM analysis revealed significant improvements in surface planarity, with Cu dishing depths reduced to ~1.4 ± 0.5 nm and RMS surface roughness values below 0.3 nm for both Cu and surrounding dielectric surfaces, measured over a 2 µm × 2 µm scan area, as shown in Fig. 2b (panel iv). Moreover, no hallow trench at Cu/barrier interface due to the galvanic corrosion and no non-uniform surface topography on Cu pad due to grain-dependent polishing induced in CMP defects, is evidence of successful suppression of these challenges by Ti passivation layer and well align with HR-TEM observations. While the exact Ti thickness and removal details remain proprietary, the passivation layer is optimized to ensure effective Cu surface protection while allowing selective removal of Ti overburden from dielectric regions during CMP. We observed and confirm that, this process reproducibly produces planarized surface. To ensure an unbiased comparison, identical CMP parameters and the same slurry chemistry were used for both passivated and non-passivated Cu samples for both Cu overburden, barrier/passivation layer removal. The CMP slurry can act as an electrolyte, enabling galvanic corrosion at interfaces between dissimilar metals with different electrochemical potentials. In the non-passivated case, direct exposure of the Cu/Ti interface to the slurry promotes localized galvanic corrosion and Cu degradation. In contrast, the Ti passivation layer provides a uniform surface during CMP, effectively isolating dissimilar metal interfaces from the electrolyte and suppressing galvanic coupling. This interfacial isolation accounts for the reduced/supressing the corrosion observed in the passivated structures under otherwise identical CMP conditions. Following CMP, subsequent bonding of these passivated wafers was performed following argon plasma surface activation to minimize TiOx formation, enabling direct wafer bonding at room temperature. This was followed by a low-temperature post-bond annealing step at 250 °C for 2 h, as outlined in schematic Fig. 2a (panels xi–xii). The resulting bonding interface demonstrated complete gap closure without any voids as observed in conventional bonding, the cross-sectional transmission electron microscopy (X-TEM) confirming the absence of voids specified 5 critical voiding regions, even bonded under low thermal budget conditions, as depicted in Fig. 2c.

Fig. 2. Engineering Cu selective passivation compatible with the Damascene process and its effect on forming a void-free bonding interface.

a Schematic illustration of Cu-selective passivation engineering, compatible with the damascene process, followed by wafer bonding. The process steps include: (i) Fabrication of embedded Cu within the dielectric using the damascene process. (ii) Deposition of a blanket passivation layer. (iii) CMP optimization to render the passivation layer selective to Cu pads. (iv) Room-temperature wafer bonding with passivation layer facilitated by plasma activation, ensuring dielectric-to-dielectric adhesion. (v) Post-bond annealing to enhance dielectric bond strength and promote Cu interconnection formation. b (i, iii) The Cu/barrier interface exhibits uniform surface topography, with very minimal or no dishing among the contact pad to dielectric and even at the galvanic corrosion barrier/Cu interface, is mitigated by the engineered passivation layer. (ii) Variations in the passivation layer morphology on Cu pad resulted due to the CMP-induced grain-dependent surface non-uniformity. (iv) AFM characterization of the hybrid bond surface (20 µm × 20 µm) with passivation layer, along with a corresponding line scan of the topographic profile. c (i) Schematic representation of the void-free bonded interface achieved through the passivation layer after post-bond annealing, which addresses interfacial bonding challenges discussed in Fig. 1. The key mechanisms include: 1. Reaction bonding between the barrier layer and dielectric. 2. Interdiffusion at the Cu-passivation layer interface. 3. Formation of Cu–Cu interconnections via interdiffusion. 4. Reaction bonding between the passivation layer and dielectric. 5. Absence of stress-induced voids within the dielectric. (ii) TEM image confirming a void-free bonded interface.

To clarify the rationale for using different post-bond annealing conditions for passivated and un-passivated Cu/dielectric interfaces, additional experiments were performed on un-passivated samples annealed at 250 °C, 2 h and 350 °C for 2 h, a FIB cross section bonded interface is as shown in the Fig. 3a, b. The results show that lower-temperature annealing (250 °C) leads to higher interfacial void density and discontinuous Cu–Cu bonding, indicating that Cu diffusion is strongly temperature-dependent and critical for void suppression in the absence of surface passivation. Consequently, un-passivated interfaces were processed at a higher thermal budget (350 °C for 2 h) to overcome CMP-induced surface non-uniformities, and residual surface contamination, thereby achieving mechanically robust bonding. In contrast, passivated interfaces exhibit enhanced interfacial stability and form continuous, void-free bonds even at 250 °C, demonstrating that the observed improvements are primarily due to the passivation mechanism rather than temperature-driven Cu diffusion alone. These findings highlight the pivotal role of surface engineering in enabling reliable Cu hybrid bonding at reduced annealing temperatures and justify the distinct annealing conditions employed for comparative analyses in this study.

Fig. 3. Comparison of un-passivated Cu surface with varying post-bond annealing temperatures.

a Post bond annealing temperatures of 250 °C, 2 h. b Post bond annealing temperatures of 350 °C, 2 h highlighting the void 5 with yellow color arrows. Void-5 root-cause analysis and formation mechanism. c AFM line-scan comparison of dielectric pad topography for un-passivated and passivated Cu surfaces, highlighting the extent of dielectric role-off and associated height variations. d Schematic illustration of the Void-5 formation mechanism in un-passivated hybrid bonding, showing the pre-bond oxide pad with dielectric roll-off, the resulting post hybrid bond interface, and a magnified view of the dielectric region where Void-5 originates.

Furthermore, root cause analysis reveals that Dielectric–Dielectric voids (Void 5) mainly arise from CMP-induced dielectric roll-off present before bonding, rather than from Cu–dielectric thermal expansion mismatch. AFM line-scan measurements (Fig. 3c) show a pronounced dielectric roll-off of ~5–6 nm in un-passivated structures, compared to only ~0.5 nm for passivated surfaces. This local topographical non-uniformity prevents intimate dielectric–dielectric contact during bonding, producing interfacial gaps that persist after annealing. These voids appear in un-passivated samples annealed at both 250 °C and 350 °C (Fig. 3a, b), indicating that their formation is independent of annealing temperature and not caused by thermomechanical effects from Cu expansion. A schematic of the Void 5 formation mechanism is presented in Fig. 3d, showing the pre-bond dielectric surface and the resulting post-bond void with an enlarged view of the dielectric region. In contrast, surface passivation suppresses dielectric roll-off, ensures uniform contact, and eliminates dielectric–dielectric voids in the passivated interfaces.

To gain a deeper understanding of interfacial phenomena associated with optimized passivation engineering, a series of advanced interfacial characterizations were conducted. First, the interface investigation using Energy-dispersive X-ray spectroscopy (EDS) elemental mapping across the Cu/Dielectric hybrid bonded interface (Fig. 4b), including elements only Cu (Fig. 4c) and only Ti (in Fig. 4d) areal maps, reveals a non-uniform distribution of the thin Ti passivation layer. This non-uniformity indicates effective conformal coverage over surface topographical variations, with regions exhibiting locally thinner, thicker, or absent passivation across the bonded interface. To further investigate interfacial reaction kinetics, High-Angle Annular Dark-Field (HAADF) imaging (Fig. 4a) was used to identify representative line-scan locations across aligned bond-pad regions and misaligned bond-pad-to-oxide interfaces. EDS line scan 1 (Fig. 4e), acquired across a misaligned bond-pad-to-oxide region, shows Ti diffusion into Si with the formation of titanium silicide (TiSix), along with Ti–Cu intermixing at the passivation/Cu interface. Line scan 2 (Fig. 4f), across regions with thinner passivation, confirms the presence of Ti/TiOx at the bonding interface and Ti–Cu intermixing at the passivation–Cu boundary. In contrast, line scan 3 (Fig. 4g), obtained from thicker passivation regions, reveals a Ti/TiOx bonding interface, a thicker unreacted Ti passivation layer, and subsequent Cu–Ti intermixing at the passivation–Cu interface.

Fig. 4. Investigation of the passivated bonding interface using TEM.

a HAADF (High-Angle Annular Dark-Field) image of the hybrid bond-pad highlighting with regions with HR-TEM and line scans. Energy-Dispersive X-ray Spectroscopy (EDS) of entire hybrid bond-pad with elemental mapping of b Si, Ti, Cu. c Only Cu, and d Only Ti. EDS line scans at the bonding interfaces. e Across the misaligned oxide and bond pad region. f Across the tinner passivation layers. g Across the thicker passivation layers.

To investigate bonding kinetics and interfacial structure in regions containing thick and ultrathin passivation layers, as well as passivation–oxide interfaces, bright-field high-resolution transmission electron microscopy (HR-TEM) combined with Fast Fourier Transform (FFT) analysis was employed at the locations identified in Fig. 4a. This methodology enables nanoscale evaluation of crystallographic continuity and elemental intermixing across the bonded interfaces. FFT patterns extracted from selected regions within the HR-TEM images provide quantitative lattice spacings and crystallographic orientations, offering direct insight into interfacial structural coherence and phase evolution. Figure 5h shows HR-TEM imaging of region 1, encompassing both ultrathin and thick passivation zones. In the ultrathin passivation region (Fig. 5h-A), three localized areas (regions 1–3) were analyzed. Regions 1 and 2, corresponding to the bottom and top Cu pads, exhibit diffraction patterns characteristic of Cu with a (002) orientation and a measured d-spacing of 0.180 nm²⁷. In contrast, region 3 at the bonding interface shows reduced lattice spacings, consistent with the formation of a Cu–Ti intermix phase²⁸. This observation indicates that an ultrathin passivation layer permits effective Cu diffusion, facilitating the formation of a continuous Cu–Cu joint.

Fig. 5. HR-TEM interface investigation of bonded interface with passivation interlayer with various interface regions and its interface bonding mechanism.

HR-TEM investigation of bonded interface with various regions specified in Fig. 4a (h) Region 1: the Cu–Cu bonding interface with (A). Ultrathin passivation layer, along with FFT diffraction patterns at regions of 1,2. Cu bulk, and 3. At the bonding interface (B). Thicker/Thin passivation interlayer regions, along with FFT diffraction patterns at regions of 1. Bottom pad of Cu bulk. 2. Bottom Cu pad/Ti passivation layer interface. 3. Passivation layer of bottom Cu pad. 4. Passivation layer on top Cu pad. 5. Top Cu pad. 6,7. Top Cu pad/Ti passivation interface. 8. Bonding interface. i Region 2: Cu/Passivation layer – SiO₂ Bonding interface with FFT diffraction patterns at regions of 1. Bonding interface region among the passivation layer to the oxide, 2. Passivation layer filled galvanic corroded Barrier and Cu trench region. j Schematic of bonding mechanism at the bonding interface with passivation layer after bonding and after annealing.

In the thick passivation region (Fig. 5h-B), eight localized areas (regions 1–8) were selected for FFT analysis. Regions 1 and 5, located within the bulk of the bottom and top Cu pads, respectively, confirm Cu (002) diffraction with a d-spacing of 0.180 nm. Region 2, corresponding to the Cu/passivation interface at the bottom bond pad, exhibits diffraction features of a Cu–Ti alloy with reduced d-spacings of 0.185 nm and 0.214 nm, along with Ti phases indexed to (0002) and (01̅10) orientations with d-spacings of 0.214 nm and 0.236 nm, respectively²⁹. Similarly, regions 6 and 7 at the Cu/passivation interface of the top bond pad reveal Cu–Ti alloy diffraction with d-spacings of 0.187 nm, 0.229 nm, and 0.246 nm, as well as Ti phases indexed to the (1̅101) orientation with d-spacings of 0.219 nm and 0.222 nm. At the passivation–passivation bonding interface, a mixed Ti/TiOx interfacial layer is observed, with Ti indexed to the (1̅102) and (0002) planes (d-spacings of 0.173 nm and 0.232 nm) and TiOx exhibiting a characteristic d-spacing of 0.354 nm³⁰. These observations are consistent with the corresponding EDS line-scan results across thin and thick passivation interfaces, indicating the formation of Ti/TiOx layers resulting from rapid Ti oxidation following plasma activation and subsequent DI water rinsing prior to bonding. Such interfacial layers are believed to play a critical role in regulating interdiffusion during post-bond annealing, and further investigation is ongoing to achieve a more comprehensive understanding of these mechanisms.

Following, the bonding interface between the oxide dielectric and the passivation layer was examined via HR-TEM and FFT as shown in Fig. 5i. In Region 1, a well-bonded interface is observed at a misaligned metal-to-dielectric region, with the formation of a TiSi₂ interfacial layer, confirmed by the presence of the (220) diffraction plane and a d-spacing of 0.289 nm³¹. Region 2 exhibits further evidence of Cu–Ti interdiffusion, confirmed by reduced d-spacing values, suggesting interfacial gap closure through the formation of titanium silicide at the passivation–dielectric interface.

These observations collectively highlight the role of selective passivation and interfacial diffusion in achieving robust, void-free bonding under low thermal budget conditions. The interfacial gap-closing mechanism in the presence of a passivation layer can be summarized as, a relatively thick/thin passivation layer promotes bonding primarily between passivation surfaces, while an ultra-thin passivation layer facilitates interdiffusion between Cu and the passivation material, resulting in localized Cu–Cu joint formation. In misaligned bonding pad regions, the interaction between Cu and the passivation layer leads to silicide compound formation, which contributes to gap closure at the interface, as shown in the schematic Fig. 5j.

Beyond the 6 µm pitch structures with 3 µm Cu pads discussed in the manuscript, we assessed the scalability of the proposed passivation-assisted process for fine-pitch interconnects with pitches down to ~700 nm and ~400 nm (Cu pad diameters ~220 nm), as shown in Fig. 6a, b. Despite the smaller feature sizes, similar electrochemical behavior was observed, and Cu EDS mapping (Fig. 6d) confirmed that localized galvanic interactions persist at submicron dimensions. At these pitches, bonding tool misalignments can reduce the effective interconnect area and exacerbate galvanic corrosion at the bonding interface can be observed^31–34, limiting further interconnect scaling. While previous studies suggested that galvanic corrosion diminishes with decreasing via size, but not completely eliminated, our results show that passivation engineering remains effective in mitigating corrosion even at these advanced pitches. A conformal, Cu-selective ultrathin passivation layer was successfully achieved at these finer scales (Fig. 6e), demonstrating the robustness of the approach. These observations indicate that the underlying electrochemical mechanisms of galvanic corrosion are relevant across a wide range of feature sizes, consistent with recent literature, while systematic studies of pitch scaling, barrier thickness, and material properties are left for future work.

Fig. 6. TEM inspection of effect of galvanic corrosion at fine pitches with pad dimensions.

a 700 nm pitch with 220 nm pad diameter. b 400 nm pitch with 220 nm pad diameter. Respective EDS areal map of Cu pads. c All elemental map. d Only Cu map with highlighted galvanic corroded barrier/Cu interface. e Passivation layer selective to Cu at fine pitches.

To evaluate the mechanical reliability and interfacial bonding mechanisms, electrical characterization was carried out using a dedicated test vehicle comprising a µm thick 5 µm diameter bond pads with a 10 µm pitch and incorporating eight thousand daisy-chain interconnects per die. In the fabrication process, both top and bottom wafers were fabricated with damascene-patterned a µm thick redistribution layers (RDLs) with 5.5 µm diameter with 10 µm pitch and connected with 2um line widths. Additionally, the top wafer additionally included 3.2 µm-diameter, 30 µm-deep through-silicon vias (TSVs). After bonding and post-bond annealing, the top wafer back side was thinned to 35 µm, followed by isotropic etching for via reveal, followed by dielectric isolation, and test pad RDL fabrication using a single damascene process, as outlined in Fig. 7a. After fabricating the test vehicle, an electrical testing was conducted using the TSV connected test pads on the top wafer, with daisy chains distributed across both wafers as shown in the 3D schematic Fig. 7b. Cross-sectional FIB-SEM analysis of the bonded interfaces revealed that samples with an ultrathin passivation layer exhibited void-free, well-adhered Cu–Cu interfaces, as shown in Fig. 7c. Whereas those without passivation showed clear interfacial voids and dielectric delamination at the bonding interface, as shown in Fig. 7d. Electrical yield analysis over 1067 dies across multiple wafers demonstrated ~97% yield for passivated samples and ~95% for un-passivated ones. Corresponding wafer-level resistance maps are shown in Fig. 7e, f. A simplified schematic of the daisy-chain network (Fig. 7g) models the interconnects as series-connected resistors between two probe ports, with a calculated theoretical resistance of 763 Ω. The cumulative distribution function (CDF) of the measured resistance reveals that passivated samples exhibit values closer to the theoretical prediction, albeit with some spread attributed to variation in passivation thickness. In contrast, un-passivated structures show elevated resistance, consistent with degraded interface quality. These findings underscore the critical role of interfacial passivation in enhancing electrical performance. However, to further optimize Cu–Cu bonding performance, alternative passivation materials with higher Cu diffusivity and compatibility with damascene processes at low temperatures, beyond conventional Ti should be explored due to its lower conductive and less Cu diffusivity into it at lower thermal budgets.

Fig. 7. Electrical characterization of bonded interconnects using a dedicated test vehicle.

a Schematic overview of the test vehicle fabrication. The bottom wafer comprises redistribution layers (RDL) and bond pads, while the top wafer includes through-silicon vias (TSVs), followed by RDL and bond pads, all formed using single damascene processes. Both wafers, with or without ultrathin passivation layers, undergo room-temperature nitrogen plasma surface activation and bonding, followed by thermal annealing. Subsequently, TSVs on the top wafer are revealed via backside thinning, electrically isolated, and fabricating test pads connected to TSVs through an additional RDL layer using Single damascene process. b Schematic illustration of the daisy chain test structure incorporating an eight-thousand daisy chain links measurements per die. c Cross-sectional SEM image of the bonded interface with an ultrathin passivation layer, showing no evidence of interfacial voids or dielectric delamination. d In contrast, the absence of a passivation layer results in distinct interfacial voids at the Cu–Cu bonding interface (indicated by arrows) and clear signs of dielectric delamination. Wafer maps of electrical resistance measurements for structures with (e) and with (f) without passivation interlayer. g Cumulative distribution frequency (CDF) plots comparing the measured electrical resistance distributions of samples with and without passivation engineering with theoretical resistance.

Conclusions

This work demonstrates the successful fabrication of an ultrathin, Cu-selective Titanium passivation layer with damascene compatable fine-pitch Cu/Dieelctric hybrid bonding. The passivation provides a smooth (lower roughness and surface non uniformities), oxidation-resistant surface, while effectively compensating for CMP-induced topography. This results in a void-free, uniform bonding interface. Moreover, it enables the formation of a reactive/diffusive silicide interfacial compound at the Cu-dielectric interface, addressing a key unsolved challenge till today in Cu-to-dielectric bonding. In addition, superior electrical performance over the convential bonding methods, passivation mechanism a promising method for low thermal budget hybrid bonding. The proposed mechanism underscores the potential of ultrathin passivation for low-temperature (≤250 °C), microstructure-independent bonding and making it a compelling solution for next-generation, temperature-sensitive high bandwidth memory (HBM) integration.

Methods

All experiments were conducted using a 300 mm semiconductor process platform. Double-side polished, 300 mm diameter p-type Si (100) wafers served as the starting substrates.

Experimental protocol for fabricating passivation layer selective to Cu bond-pads

The conventional single-damascene process sequence was employed to fabricate wafer surfaces for Cu/dielectric hybrid bonding prior to selective passivation of the Cu pads, as illustrated in Fig. 1a, i–viii. The process began with a Si wafer deposited with a 200 nm SiN layer serving as an etch-stop layer, followed by the deposition of 1.2 µm tetraethyl orthosilicate (TEOS) oxide. A chemical mechanical polishing (CMP) step was subsequently performed to remove ~200 nm of TEOS to achieve a planar surface. A 3.5 µm conventional ZR8800 an i-line positive photoresist (PR) layer was then spin-coated onto the oxide surface and patterned using a stepper lithography system (Ultratech AP300). After exposure and development using a standard PR developer, the oxide was etched by a dry etching process to form the bonding pad structures. The remaining PR was removed by oxygen plasma stripping, followed by a standard Radio Corporation of America (RCA-1) cleaning process to eliminate organic contaminants. Subsequently, a 100 nm Ti barrier layer and a 200 nm Cu seed layer were deposited using physical vapor deposition (PVD) sputtering. Copper electrochemical plating (ECP) was then performed to fill the trenches with Cu, forming an overburden of ~1 µm. The wafers were annealed at 150 °C for 30 min to stabilize the Cu grain structure. A subsequent CMP process was used to remove the Cu overburden and barrier layers, resulting in controlled Cu dishing.

Following this step, a thin passivation layer was selectively deposited on the wafer surface, as illustrated in Fig. 2a, ix–x, and subsequently planarized using an optimized CMP process. The surface characteristics of the fabricated bond pads, with and without the passivation layer, were evaluated in terms of Cu dishing and surface topography using atomic force microscopy (AFM; Bruker InSight CAP). The processed wafers were then bonded using precision alignment with a SmartView Alignment (SVA) module integrated in an EVG Gemini FB-XT bonding system. After bonding, the wafers were annealed in a vertical furnace (SPTS RVP-300plus) at temperatures of 250 °C and 350 °C for 1–2 h with a ramp rate of 5 °C min⁻¹.

For interfacial characterization, the bonded wafers were diced and analyzed using transmission electron microscopy (TEM; Thermo Fisher Scientific). High-resolution TEM (HRTEM) imaging was performed on a Titan platform equipped with a OneView camera, while energy-dispersive X-ray spectroscopy (EDS) analysis was conducted using a Talos system. Fast Fourier transform (FFT) and HRTEM image analyses were carried out using Gatan Microscopy Suite software.

Experimental protocol for fabricating electrical test vehicle

The effectiveness of the passivation technology was evaluated through working-die yield analysis using electrical testing across more than 1000 dies per wafer, as shown in Fig. 7. To fabricate the test vehicle, the process began with a top Si wafer on which a 200 nm TEOS oxide layer was deposited. The through-silicon via (TSV) structures were then patterned using standard lithography as described previously. Following patterning, TSVs were etched using a pulsed deep reactive-ion etching (DRIE) process (Bosch process) to a depth of ~35 µm. After TSV formation, a conformal 200 nm chemical vapor deposition (CVD) oxide liner was deposited on the wafer surface and within the TSV sidewalls to electrically isolate the vias and minimize signal cross-talk. Subsequently, a Ti barrier layer and Cu seed layer of 200 nm and 600 nm thickness, respectively, were deposited using a high-aspect-ratio compatible physical vapor deposition (PVD) system. An optimized electrochemical plating (ECP) process was then employed to completely fill the TSVs with Cu, forming an overburden of ~2 µm. To stabilize the Cu grain structure, the wafers were annealed at 200 °C for 30 min in an N₂ atmosphere using a furnace annealing system with a ramp rate of 5 °C min⁻¹. A CMP process was subsequently performed to remove the Cu overburden and barrier layers. Following TSV formation, a conventional single-damascene process sequence was used to fabricate the redistribution layer (RDL) on the TSV top wafer with alignment to the TSV layer, while simultaneously preparing the corresponding bottom wafers. An additional single-damascene process was then used to fabricate the bonding pad layer aligned to the RDL layer. After formation of the bond pads, two wafer batches were prepared: one with selective Cu passivation layers on both the top and bottom wafers, and another without passivation layers. The wafers were then bonded using precision alignment. The passivated wafers were annealed at 250 °C for 2 h, while the non-passivated samples were annealed at 350 °C for 2 h.

Following annealing, the wafer edges were trimmed by ~2 mm, and the top wafer was thinned by grinding to a thickness of ~50 µm. The TSV structures were then revealed using a dry etching process that avoided Cu exposure or Cu re-sputtering onto the Si surface to prevent leakage paths. After TSV reveal, an oxide layer was deposited, and a single-damascene process was used to fabricate test pads for electrical characterization. Electrical measurements were performed using an automated wafer probing system (TEL WDF-12DP+) integrated with a National Instruments PXIe-2529 test platform.

Author contributions

Hemanth Kumar Cheemalamarri: Conceptualization, Methodology, Process fabrication, Passivation technology development, Funding acquisition (UIBR), Writing—original draft. Masahisa Fujino: Methodology, Process development, Writing—review & editing. Tanmay Ghosh: Transmission electron microscopy (TEM), Interfacial analysis, Data interpretation. Ratan Bhimrao Umralkar: Electrical characterization, Test setup, Data acquisition. Chandra Rao Bhesetti: Methodology, Process development. Navab Singh: Supervision, Resources, Writing—review & editing. Vempati Srinivasa Rao: Supervision, Project administration, Resources, Funding acquisition, Writing—review & editing. All authors discussed the results, contributed to manuscript revisions, and approved the final version. Correspondence should be addressed to Hemanth Kumar Cheemalamarri (ee16resch010066@gmail.com).

Peer review

Peer review information

Communications Engineering thanks Vikas Dubey, Yun-Hao Shao and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. Primary Handling Editors: [Saptarshi Das] and [Wenjie Wang].

Data availability

All data that support the findings of this study are available from the corresponding author upon reasonable request.

Competing interests

The authors declare no competing interests.