Minimizing interface defects and enhancing optical brightness of µLEDs through polymeric encapsulants

Abstract

The need for high resolution microLED arrays, for applications in chip-level optical interconnects and augmented/virtual reality displays, requires the continuing miniaturization of the LED to reduce the pixel size and enable high pixel density. Miniaturization typically degrades brightness because of surface-related non-radiative recombination. Here we demonstrate a combined dry/wet etching process with polymeric encapsulation to construct InGaN-based microLEDs that show negligible degradation due to sidewall effects for devices having diameters as small as 6 µm. The microLEDs exhibit low surface recombination velocities ( <10 cm s⁻¹) and high wall plug efficiencies of 20.3% at a current density of $2.5\mathrm{A\; c}{\mathrm{m}}^{-2}$. A simple numerical model is developed to explain the dependence of the microLED performance as a function of the microLED geometry. The model determines the critical microLED diameter at which surface recombination becomes comparable to bulk recombination, marking the onset of surface-limited behaviour.

Pranav Gavirneni and William Wong have miniaturized microLED size having enhanced device efficiency using a simple polymeric passivation method. The approach supports high-resolution displays and emerging non-display microLED applications

Introduction

GaN-based micro-light-emitting diodes (µLEDs) offer a compelling platform for next-generation displays, including large-area televisions and augmented or virtual-reality headsets. They also support a growing range of non-display applications such as high-resolution imaging, optical interconnects, ultraviolet disinfection, and many more emerging applications. To succeed in these roles the devices must combine small lateral size with high optical/electrical efficiency¹. However, it has been widely reported that reducing the LED size leads to degraded device performance^2–10. Decreasing the size of the LED requires dry etching processes and increases the surface-to-volume ratio of the device. The resulting surface defects along the sidewall raise the Shockley–Read–Hall (SRH) recombination rate that increases non-radiative recombination losses and lowers the external quantum efficiency (${\mathrm{\eta }}_{\mathrm{EQE}}$) of the diode. These effects reduce the µLED light output due to an increase of the surface recombination velocity (${\mathrm{v}}_{\mathrm{S}}$) from the exposed sidewalls. The degradation may be minimized by using a low damage etching technique, such as neutral beam etching, and/or by applying a surface coating to passivate remaining sidewall defects¹¹.

In this work, we investigate how side-wall quality influences the optical and electrical performance of InGaN blue µLEDs by comparing two contrasting sidewall coating/repair approaches. The two schemes yielded unexpected and dissimilar results, raising questions on the relationship between the diode efficiency and its geometry. The results prompted further investigation that revealed two distinct operating regimes of the LED that was identified as competing loss mechanisms that coexist in typical µLED structures. As a result, we identify a practical critical diameter (${\mathrm{d}}_{\mathrm{crit}}$) to better describe the recombination process. LED diameters larger than this geometric threshold are limited primarily by bulk SRH recombination, whereas diodes smaller than ${\mathrm{d}}_{\mathrm{crit}}$ are governed by perimeter-dependent surface recombination. The methodology provides a rapid, quantitative route to benchmark the fabrication flow consisting of the sidewall coating chemistry, plasma etch, or side-wall treatment, and helps predict the critical pixel size at where surface defects will dominate for a given µLED fabrication technology. By optimizing the µLED fabrication process, smaller ${\mathrm{d}}_{\mathrm{crit}}$ values can be achieved. With the surface pathway effectively suppressed, geometric effects that emerge at small dimensions, including size-dependent improvements in light-extraction efficiency, can now be exploited to realize further performance gains. As a result, simple microfabrication techniques and low-cost materials may be used to achieve high brightness and high resolution μLED arrays for AR/VR display applications.

Results & Discussion

Impact of Sidewall Coating Schemes on the Optical and Electrical Performance of InGaN µLEDs

To evaluate the impact of sidewall etching and coating layers on the performance of InGaN μLEDs, a dry etch process with two different sidewall coating schemes were implemented. Lateral InGaN µLEDs were patterned via chlorine-based plasma etching using a SiO₂ hard mask, followed by deposition of ohmic contacts and the two sidewall coating schemes (full fabrication details are outlined in µLED Fabrication in the Methods section). The first sidewall coating scheme utilized a commonly used bilayer SiO₂ structure composed of a 10 nm film formed using atomic layer deposition (ALD) followed by a 150 nm layer deposited using plasma-enhanced chemical vapor deposition (PECVD)¹². In a second approach, sidewalls were encapsulated using SU-8 3010, a polymeric encapsulant material known to be effective for enhancing the efficiency and production yields of high-voltage and nano-scale LED structures while reducing leakage currents of other III–V optoelectronic devices^13–15.

The μLEDs with both sidewall coating schemes were tested for optical and electrical performance using a semiconductor parameter analyzer on a probe station enclosed in a light-tight Faraday cage, while a photodiode captured the emitted light (see Device Characterization in the Methods section). The $\mathrm{\mu }$LED current-voltage (I–V) and photodiode current were used to extract the ${\mathrm{\eta }}_{\mathrm{EQE}}$, where ${\mathrm{\eta }}_{\mathrm{EQE}}$ is expressed as:

$${\mathrm{\eta }}_{\mathrm{EQE}}={\mathrm{\eta }}_{\mathrm{LEE}}\cdot {\mathrm{\eta }}_{\mathrm{IQE}}=\frac{\mathrm{P}}{\mathrm{h}v}\left./\right)\frac{\mathrm{I}}{\mathrm{q}}$$ 1

The light extraction efficiency $\left({\mathrm{\eta }}_{\mathrm{LEE}}\right)$ is the fraction of photons generated in the active region that escape to free space. The internal quantum efficiency (${\mathrm{\eta }}_{\mathrm{IQE}}$) is the fraction of electrons injected into the LED that generate photons in the active region. P is the optical output power, and I is the applied current. $\mathrm{h}\mathrm{\nu }$ is the photon energy, and $\mathrm{q}$ is the elementary charge. The power supply sources voltage and the current, I, is then measured. The photodiode collects a portion of the light and provides the optical output power, $\mathrm{P},$ collected at a particular current-voltage bias. Although ${\mathrm{\eta }}_{\mathrm{EQE}}$ is a practical performance parameter, it does not convey the power efficiency information of the device. The wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$), accounts for diode optical characteristics and provides insight into the power efficiency of the $\mathrm{\mu }$LED. The $\mathrm{\mu }$LED ${\mathrm{\eta }}_{\mathrm{WPE}}$ is the fraction of the input power converted to optical output power and is expressed as:

$$\begin{array}{c}\hfill {\mathrm{\eta }}_{\mathrm{WPE}}={\mathrm{\eta }}_{\mathrm{EQE}}\times \frac{{\mathrm{V}}_{\mathrm{p}}}{{\mathrm{V}}_{\mathrm{app}}}\hfill \end{array}$$ 2

where ${\mathrm{V}}_{\mathrm{app}}$ is the applied voltage and ${\mathrm{V}}_{\mathrm{p}}=\frac{\mathrm{h}\mathrm{\nu }}{\mathrm{q}}$ is the photon voltage. The voltage ratio $\frac{{\mathrm{V}}_{\mathrm{p}}}{{\mathrm{V}}_{\mathrm{app}}}$ accounts for ohmic losses due to series resistance that scales with ${\mathrm{V}}_{\mathrm{app}}$. Figure 1 illustrates the peak-${\mathrm{\eta }}_{\mathrm{WPE}}$ as a function of µLED diameter for three $\mathrm{\mu }$LED sizes (6, 12, and 17 µm), coated with either SiO₂ or SU-8. Notably, the relationship between device size and efficiency differs between the two sidewall coating schemes: exhibiting opposite trends. SiO₂-coated devices exhibit a decreasing peak-${\mathrm{\eta }}_{\mathrm{WPE}}$ trend with decreasing device size, consistent with widely reported trends from other research groups^6–10. Conversely, SU-8 encapsulation was observed to have an unexpected increase in peak-${\mathrm{\eta }}_{\mathrm{WPE}}$ as the $\mathrm{\mu }$LED size decreases, contradicting the trend observed with SiO₂ coating.

Fig. 1. Size- and sidewall-coating-dependent efficiency of μLEDs.

Peak wall‑plug efficiency (peak-${\mathrm{\eta }}_{\mathrm{WPE}}$, %) plotted as a function of μLED diameter (µm) for devices with SiO₂ (red diamonds) and SU‑8 (blue rectangles) sidewall coatings. Symbols represent mean values; error bars indicate the standard deviation. Semi‑transparent circles denote individual device measurements used to calculate the mean, with colors matching the corresponding coating condition. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models. Sample sizes were n = 3 devices for SiO₂ and n = 4 devices for SU‑8.

To better understand the differences observed between the two sidewall coating schemes, the electrical characteristics of the μLEDs were analyzed. Given that the largest optical performance discrepancy occurred in the 6 µm devices, this electrical analysis specifically focused on these devices. Electrical characterization involved extracting the ideality factor (IF) from the diode’s I–V characteristics within a voltage range of 2–3 V. The IF provides valuable insights into the underlying recombination mechanisms that may be difficult to interpret from standard linear or semi-logarithmic I–V plots alone. The extraction is based on the non-ideal diode equation:

$$\mathrm{I}={\mathrm{I}}_{\mathrm{o}}{\mathrm{e}}^{\frac{\mathrm{q}{\mathrm{V}}_{\mathrm{app}}}{\mathrm{nkT}}}$$ 3

given ${\mathrm{I}}_0$ is the dark saturation current, $\mathrm{I}$ is the measured diode current, and $\frac{\mathrm{kT}}{\mathrm{q}}\approx 25.6\mathrm{meV}$ at room temperature.

The IF is particularly useful in assessing SRH recombination within the device. An ideal diode, exhibiting no SRH recombination, corresponds to an IF of $\mathrm{n}=1$. Conversely, an IF of $\mathrm{n}=2$ indicates maximal SRH recombination, typically associated with defect states located precisely at mid-gap. However, practical GaN-based devices commonly exhibit IFs greater than 2, due to parasitic effects such as series resistance (${\mathrm{R}}_{\mathrm{s}}$), shunt resistance (${\mathrm{R}}_{\mathrm{shunt}}$), or additional parasitic diodes that originate from surface states or defects within the MQW active region plane^16,17. By examining the IF as a function of voltage, the device operation can be analyzed within distinct regimes where parasitic effects dominate performance.

Figure 2a displays the mean semi-logarithmic I–V characteristics for 6 µm µLEDs coated with SiO₂ and SU-8. The reverse-bias currents and low forward bias currents (-3V to +1.5 V) measured remained within the noise level of the measurement system, indicating no observable differences between the two sidewall coating schemes under reverse-bias conditions. For forward-bias conditions, measurable currents begin increasing around 1.5 V, with no differences evident between the SiO₂ and SU-8 sidewall coating schemes. Additionally, the slopes of the linear regions in the semi-log plots are quite similar considering the differences observed in the ${\mathrm{\eta }}_{\mathrm{WPE}}$ plots (Fig. 1). Further investigation of the underlying electrical characteristics is shown in Fig. 2b. The extracted IF as a function of voltage (between 2 and 3 V) is plotted for currents ranging from approximately 1 pA to 10 µA for the 6 µm µLEDs. Both sidewall coating schemes exhibit a minimum IF of about n = 1.6 at approximately 2.5 V, corresponding to a current level of roughly 30–40 nA. The minimum ideality factor reflects the regime where carrier transport is least influenced by parasitic effects. At low forward bias, elevated values can result from leakage through parallel conduction paths (e.g., shunt or parasitic diodes), while at high bias, series resistance dominates. Accurate extraction is therefore confined to the sub-turn-on regime, provided that the contact resistance is low and the effective shunt resistance is sufficiently high¹⁶. In devices with substantial parasitics, no well-defined ideality region may be observable. Typically, a minimum IF greater than 2 suggests considerable parasitic influences such as ${\mathrm{R}}_{\mathrm{s}}$, ${\mathrm{R}}_{\mathrm{shunt}}$, or other parasitic diode components dominating device performance^16,17.

Fig. 2. Sidewall coating-dependent electrical characteristics of 6 µm μLEDs.

a Current–voltage (I–V) characteristics for μLEDs with SiO₂ (red diamonds) and SU-8 (blue rectangles) sidewall coatings. b Corresponding ideality factor extracted as a function of voltage for the same devices, with the voltage range indicated in a shown by the dashed box. Symbols represent mean values; error bars indicate the standard deviation. Semi-transparent circles denote individual device measurements used to calculate the mean, with colors matching the corresponding coating condition. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models. Sample sizes were n = 3 devices for SiO₂ and n = 4 devices for SU‑8.

Examining voltages above 2.5 V, the IF rises steeply, coinciding with the slope of the semi-log I-V plot decreasing with increasing V_app, due to series resistance originating primarily from the p- and n-type ohmic contacts. Given the greater difficulty in achieving high doping concentrations for p-GaN compared to n-GaN, the p-contact dominates the resistance at higher current densities¹⁸. The higher mean forward current observed for the SiO₂ devices at voltages above 2.5 V is believed to be attributed to lithographic variations in p-contact geometry. For the 6 μm-diameter mesas, size deviations of up to ±0.32 µm relative to the mesa were observed, contributing to the measured variations.

Conversely, at voltages below 2.5 V, an increase in the IF above n = 2 was observed, surpassing the minimum IF values, indicating parasitic pathways for current flow. The complete I−V curve spanning from -3 V to 5 V (Fig. 2a) further confirms that this sub-threshold parasitic current appears only under forward-bias conditions. Two possibilities may explain this behavior, carrier transport via surface trap states located along the diode perimeter or through defect regions within the diode structure¹⁶.

The SiO₂-coated 6 µm µLEDs exhibit a slightly higher IF compared to the diodes having SU-8 encapsulation layers within the voltage range corresponding to voltages and currents between approximately 2.0−2.4 V and 1pA−10nA, respectively. The elevated ideality factor indicates stronger sub-threshold parasitic currents in SiO₂-coated devices, likely originating from carrier transport through surface trap states along the diode perimeter or defect-assisted leakage pathways¹⁶. These electrical findings align well with the ${\mathrm{\eta }}_{\mathrm{WPE}}$ results, where the peak-${\mathrm{\eta }}_{\mathrm{WPE}}$ for 6 μm SU-8-encapsulated devices was approximately 1.6 times higher than for the SiO₂-coated devices. Although electrical measurements confirm that SU-8 encapsulation is more effective, that alone does not fully explain the origin for the improvement observed in Fig. 1. Analysis of the ${\mathrm{\eta }}_{\mathrm{WPE}}$ versus current density (J) curves, incorporating microLED diameters of 6, 12, and 17 µm and the different sidewall-coating schemes (SiO₂ and SU-8), was used to further analyze the observed efficiency trends (Fig. 3). The µLED J was consistently calculated using the mesa area for all sizes and sidewall coating schemes.

Fig. 3. Opto-electrical efficiency of μLEDs with different sidewall coatings.

a Wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$,%) as a function of current density (J, A cm⁻²) for SiO₂-coated μLEDs. b Wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$,%) as a function of current density (J, A cm⁻²) for SU-8-coated μLEDs. μLED diameters are represented by 6 μm (yellow diamonds), 12 μm (blue squares), and 17 μm (red triangles). Symbols represent mean values; error bars indicate the standard deviation. Semi-transparent symbols denote individual device measurements used to calculate the mean, with colors matching the corresponding diameter. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models. Green arrows indicate the qualitative variation in ${\mathrm{\eta }}_{\mathrm{WPE}}$ with decreasing μLED diameter. Sample sizes were n = 3, 3, and 4 devices for SiO₂-coated μLEDs with diameters of 6, 12, and 17 μm, respectively, and n = 4 devices for each SU-8-coated diameter.

SU-8–encapsulated μLEDs were found to consistently outperform the SiO₂-coated counterparts of identical dimensions. For 6 μm diameter devices, SU-8 encapsulation achieves a mean peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ of ~17.4% at ~6 A cm⁻², compared to ~8% at ~16 A cm⁻² for SiO₂-coated devices. Although the J at the peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ point (${\mathrm{J}}_{\mathrm{peak}-\mathrm{WPE}}$) increases with decreasing device diameter for both SU-8 and SiO₂ samples, the increase was smaller for SU-8. Given the sidewall coating was the only variable changed in these experiments, the reduced sensitivity with decreasing diameter suggests SRH recombination at the sidewalls decreased in SU-8-coated devices^7,19,20. The SU-8–encapsulated μLEDs also exhibit increasing peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ with decreasing diameter and the SiO₂-coated devices show the opposite behavior. The peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ decreases with decreasing diameter, which is consistent with higher sidewall SRH recombination and correlated to the higher ideality factors (Fig. 2).

The optical contributions should also be considered alongside the electrical characteristics. Prior studies have shown that geometric scaling enhances ${\mathrm{\eta }}_{\mathrm{LEE}}$ in smaller mesas by reducing total internal reflection (TIR) and shortening optical path lengths, lowering the reabsorption probability^21–24. This size-dependent ${\mathrm{\eta }}_{\mathrm{LEE}}$ improvement directly affects ${\mathrm{\eta }}_{\mathrm{WPE}}$ when v_s is sufficiently low, otherwise non-radiative losses dominate and mask the benefit. To quantify the interplay between v_s and ${\mathrm{\eta }}_{\mathrm{LEE}}$, the efficiency curves were fitted using the ABCCD recombination model and described in the next section.

Recombination Coefficient Extraction

Starting with the ${\mathrm{\eta }}_{\mathrm{EQE}}$, defined as:

$${\mathrm{\eta }}_{\mathrm{EQE}}={\mathrm{\eta }}_{\mathrm{LEE}}\cdot {\mathrm{\eta }}_{\mathrm{IQE}}$$ 4

where ${\mathrm{\eta }}_{\mathrm{LEE}}$ is defined above and the ${\mathrm{\eta }}_{\mathrm{IQE}}$ may be modeled using the ABCCD approach:

$${\mathrm{\eta }}_{\mathrm{IQE}}={\mathrm{\eta }}_{\mathrm{inj}}\cdot \frac{\mathrm{B}{\mathrm{n}}^2}{\mathrm{An}+\mathrm{B}{\mathrm{n}}^2+{\mathrm{C}}_{\mathrm{aug}}{\mathrm{n}}^3+{\mathrm{C}}_{\mathrm{dl}}{\mathrm{n}}^3+{\mathrm{D}}_{\mathrm{dl}}{\mathrm{n}}^4}$$ 5

The carrier injection efficiency (${\mathrm{\eta }}_{\mathrm{inj}}$) is the fraction of all injected carriers that successfully reach the LED’s active region, where they can contribute to radiative recombination and is assumed to be equal to unity. In this model, the coefficient $\mathrm{A}$ with units of $\left[{\mathrm{s}}^{-1}\right]$ represents the total SRH recombination coefficient dependent on geometry and recombination parameters, generically defined for a µLED as,

$$\mathrm{A}={\mathrm{A}}_0+{\mathrm{A}}_{\mathrm{s}}$$ 6

Where, ${\mathrm{A}}_0$ is defined as the bulk SRH recombination coefficient with units of $\left[{\mathrm{s}}^{-1}\right]$ and ${\mathrm{A}}_{\mathrm{s}}$ is defined as the surface SRH recombination coefficient with units of $\left[{\mathrm{s}}^{-1}\right]$. ${\mathrm{A}}_{\mathrm{s}}$ can be generally expressed as,

$${\mathrm{A}}_{\mathrm{s}}={\mathrm{v}}_{\mathrm{s}}\frac{{\mathrm{S}}_{\mathrm{active}}}{{\mathrm{V}}_{\mathrm{active}}}$$ 7

Where, ${\mathrm{S}}_{\mathrm{active}}$ [$\mathrm{c}{\mathrm{m}}^2$] and ${\mathrm{V}}_{\mathrm{active}}\left[\mathrm{c}{\mathrm{m}}^3\right]$ represents the sidewall surface area and volume of the µLED multiple quantum well (MQW) active region, respectively. The surface recombination velocity, v_s [cm s⁻¹], is an intrinsic property of the sidewall interface for a given surface chemistry and processing and is independent of device size. The ratio ${\mathrm{S}}_{\mathrm{active}}/{\mathrm{V}}_{\mathrm{active}}$ is an equivalent geometric scaling of the sidewall recombination, such as the perimeter-to-area ratio ($\frac{\mathrm{l}}{\mathrm{w}}$ or $\frac{\mathrm{P}}{\mathrm{A}}$), which are frequently employed in µLED models^25,26. Given the analysis focuses on diodes having circular geometries, the following definitions describe μLEDs with a diameter, d:

$$\mathrm{A}{=\mathrm{A}}_0+{\mathrm{v}}_{\mathrm{s}}\frac{4}{\mathrm{d}}$$ 8

where ${\mathrm{v}}_{\mathrm{s}}$ is dependent on the interface trap density ${\mathrm{N}}_{\mathrm{it}}$ $\left[\mathrm{c}{\mathrm{m}}^{-2}\right]$ through the equation,

$${\mathrm{v}}_{\mathrm{s}}={\mathrm{\sigma }}_{\mathrm{it}}{\mathrm{v}}_{\mathrm{th}}{\mathrm{N}}_{\mathrm{it}}$$ 9

where ${\mathrm{\sigma }}_{\mathrm{it}}$ $\left[\mathrm{c}{\mathrm{m}}^2\right]$ is the capture cross-section of interface traps and ${\mathrm{v}}_{\mathrm{th}}$ $\left[\mathrm{cm}{\mathrm{s}}^{-1}\right]$ is the thermal velocity of the carriers²⁷. Similarly, ${\mathrm{A}}_0$ is given by,

$${\mathrm{A}}_0={\mathrm{\sigma }}_{\mathrm{bulk}}{\mathrm{v}}_{\mathrm{th}}{\mathrm{N}}_{\mathrm{t}}$$ 10

where ${\mathrm{\sigma }}_{\mathrm{bulk}}$ is the capture cross-section of bulk traps $\left[\mathrm{c}{\mathrm{m}}^2\right]$ and ${\mathrm{N}}_{\mathrm{t}}$ is the bulk trap density $\left[\mathrm{c}{\mathrm{m}}^{-3}\right]$.

For the remaining parameters from Eqn. ($5$), $\mathrm{B}$ is the bimolecular radiative recombination coefficient which is on the order of ${10}^{-10}\mathrm{c}{\mathrm{m}}^3{\mathrm{s}}^{-1}$ for GaN based LEDs, while ${\mathrm{C}}_{\mathrm{aug}}$ denotes the Auger recombination coefficient which is typically $\le {10}^{-31}\mathrm{c}{\mathrm{m}}^6{\mathrm{s}}^{-1}$¹⁶. Additionally, higher-order recombination coefficients ${\mathrm{C}}_{\mathrm{dl}}$ and ${\mathrm{D}}_{\mathrm{DL}}$ account for drift-induced carrier leakage, becoming substantial at elevated carrier concentrations. The carrier concentration, $\mathrm{n}$, varies as a function of the $\mathrm{\mu }$LED drive current. Typically, for InGaN LEDs, ${\mathrm{C}}_{\mathrm{cdl}}\gg {\mathrm{C}}_{\mathrm{aug}}$, and are in the range of ${10}^{-29}-{10}^{-28}\mathrm{c}{\mathrm{m}}^6{\mathrm{s}}^{-1}$¹⁶.

To accurately extract the SRH recombination coefficients, particularly ${\mathrm{v}}_{\mathrm{S}}$, the ${\mathrm{\eta }}_{\mathrm{EQE}}$ vs J plots are fitted using the ABCCD recombination model^20,28. However, correctly fitting ${\mathrm{\eta }}_{\mathrm{EQE}}$ data requires consideration of the ${\mathrm{\eta }}_{\mathrm{LEE}}$, which has been reported by various groups to exhibit a size dependence^21–24,29. Since the current study investigates both device size and sidewall coating variations, a size-dependent ${\mathrm{\eta }}_{\mathrm{LEE}}$ has been included to increase the accuracy of the fit. To account for the size-dependent relationship of ${\mathrm{\eta }}_{\mathrm{LEE}}$, an empirical first-order model is proposed, expressed as:

$${\mathrm{\eta }}_{\mathrm{LEE}}\left(\mathrm{d}\right)={\mathrm{\eta }}_{\mathrm{LE}{\mathrm{E}}_{\infty }}+\mathrm{\alpha }{\mathrm{d}}^{-\mathrm{\beta }}$$ 11

Here, ${\mathrm{\eta }}_{\mathrm{LE}{\mathrm{E}}_{\infty }}$ is a constant representing the ${\mathrm{\eta }}_{\mathrm{LEE}}$ for an infinitely large LED, which accounts for the baseline TIR and absorption occurring in a very large device with identical epitaxial layers and metal contacts. The diameter of the circular $\mathrm{\mu }$LED is given by $\mathrm{d}$. The parameters $\mathrm{\alpha }$ and $\mathrm{\beta }$ represent how strongly the ${\mathrm{\eta }}_{\mathrm{LEE}}$ is influenced by device geometry: $\mathrm{\alpha }$ is a proportionality constant, and $\mathrm{\beta }$ is a power constant. Both parameters depend on the $\mathrm{\mu }$LED epitaxial and device structure, specific techniques used for enhancing light extraction (such as surface roughening, microlenses, photonic crystals, and metasurfaces), and photon absorbers including defects, metals, and MQW reabsorption.

This model is supported by previous results from Ryu et al., who demonstrated an increase in ${\mathrm{\eta }}_{\mathrm{LEE}}$ with decreasing circular µLED diameter using 3D finite-difference time-domain simulations²⁹. They attributed the size-dependent ${\mathrm{\eta }}_{\mathrm{LEE}}$ primarily to the interplay between the TIR and absorption in the GaN/InGaN layers and the metallic contacts. As the device dimension grows, a larger fraction of emitted light becomes trapped by TIR, increasing the photon path length. This prolonged optical path increases the likelihood of reabsorption within the GaN/InGaN active region, defect sites, or metal layers, which in turn compounds the net optical loss. In contrast, smaller μLEDs experience less TIR-induced trapping, leading to fewer absorption events and therefore higher ${\mathrm{\eta }}_{\mathrm{LEE}}$. Excellent agreement between this empirical equation (Eqn. ($11$)) to the data reported by Ryu et al. further validated the suitability of this relationship for extracting the size-dependent ${\mathrm{\eta }}_{\mathrm{LEE}}$ in circular µLEDs, in this case for diameters between 2 and 25 µm.

To fit the measured ${\mathrm{\eta }}_{\mathrm{EQE}}$ vs J data to the ${\mathrm{\eta }}_{\mathrm{EQE}}$ model, a standard MATLAB built-in nonlinear optimization loop was run to minimize the sum of squared errors between measured and modeled ${\mathrm{\eta }}_{\mathrm{EQE}}$ (see Supplementary Note 1 for fitting procedure). The values extracted from the numerical fitting resulted in the global recombination coefficients shown in Table 1. The validity of the present fitting is confined to the experimentally tested size range, extending down to 6 µm.

Table 1.

Extracted sidewall coating dependent recombination coefficients and calculated ${\mathrm{N}}_{\mathrm{it}}$ and ${\mathrm{d}}_{\mathrm{crit}}$

Extracted Recombination Coefficient	Sidewall Coating
	SiO2	SU-8	SU-8 with KOH
${\mathrm{A}}_0\left({\mathrm{s}}^{-1}\right)$	$2.8\times {10}^6$
$\mathrm{B}\left(\mathrm{c}{\mathrm{m}}^3{\mathrm{s}}^{-1}\right)$	$1.1\times {10}^{-10}$
${\mathrm{C}}_{\mathrm{dl}}\left(\mathrm{c}{\mathrm{m}}^{-6}{\mathrm{s}}^{-1}\right)$	$1.1\times {10}^{-29}$
${\mathrm{D}}_{\mathrm{dl}}\left(\mathrm{c}{\mathrm{m}}^9{\mathrm{s}}^{-1}\right)$	$2.8\times {10}^{-47}$
${\mathrm{v}}_{\mathrm{s}}\left(\mathrm{cm}{\mathrm{s}}^{-1}\right)$	$2.97\times {10}^3$	$404$	$<1$0
${\mathrm{N}}_{\mathrm{it}}\left(\mathrm{c}{\mathrm{m}}^{-2}\right)$	$3\times {10}^{11}$	4$\times {10}^{10}$	<1 $\times {10}^8$
${\mathrm{d}}_{\mathrm{crit}}$ $\left(\mathrm{\mu }\mathrm{m}\right)$	43	6	<0.1

These coefficients, which primarily depend on the epitaxial wafer quality, align well with values reported in other studies^16,28. Using the bulk- and surface-recombination formulations introduced above, ${\mathrm{N}}_{\mathrm{t}}$ and ${\mathrm{N}}_{\mathrm{it}}$ can be estimated once representative carrier-capture cross-sections are chosen. Published $\mathrm{\sigma }$ values span several orders of magnitude between ${10}^{-17}$ to ${10}^{-14}\mathrm{c}{\mathrm{m}}^2$, the exact number depending on the trap energy, charge state, and surface preparation^30–32. For a first-order numerical estimate we adopt a ${\mathrm{\sigma }}_{\mathrm{bulk}}=5\times {10}^{-16}\mathrm{c}{\mathrm{m}}^2$ and a ${\mathrm{v}}_{\mathrm{th}}=2\times {10}^7\mathrm{cm}{\mathrm{s}}^{-1}$ which lies near the geometric mean of the experimentally reported range and reflects typical carrier thermal velocities at room temperature. ${\mathrm{N}}_{\mathrm{t}}$ can be calculated to be approximately $2.7\times {10}^{14}\mathrm{c}{\mathrm{m}}^{-3}$. Similarly, ${\mathrm{N}}_{\mathrm{it}}$ can be calculated assuming the same values for ${\mathrm{v}}_{\mathrm{th}}$ and ${\mathrm{\sigma }}_{\mathrm{bulk}}={\mathrm{\sigma }}_{\mathrm{surface}}$. Extracted ${\mathrm{v}}_{\mathrm{s}}$ and ${\mathrm{N}}_{\mathrm{it}}$ values for each sidewall coating scheme are shown in Table 1. In the ABCCD model, global coefficients (${\mathrm{A}}_0,\mathrm{B},{\mathrm{C}}_{\mathrm{dl}},{\mathrm{D}}_{\mathrm{dl}}$) are fixed across all devices and sidewall coating schemes, while only the SRH-related term ${\mathrm{A}}_{\mathrm{s}}$ varies. Importantly, ${\mathrm{A}}_{\mathrm{s}}$, and therefore ${\mathrm{v}}_{\mathrm{s}}$, is the only parameter in the recombination model that depends on sidewall quality, determined by the specific sidewall coating or treatment applied.

The ${\mathrm{v}}_{\mathrm{s}}$ for the SU-8 encapsulation is nearly an order of magnitude lower than that observed for SiO₂ coating. This finding aligns well with the trends observed in the ${\mathrm{\eta }}_{\mathrm{WPE}}$ versus device size plot (Fig. 1), where SiO₂-coated samples exhibited a shift of ${\mathrm{J}}_{\mathrm{peak}-\mathrm{WPE}}$ to higher current densities as device size decreased, while SU-8-encapsulated samples demonstrated only a slight shift. The notably lower ${\mathrm{v}}_{\mathrm{s}}$ for SU-8 indicates that surface-related effects have less relative contribution to SRH recombination compared to bulk defects.

To quantify the impact of surface SRH recombination on the total SRH recombination, the total SRH recombination can be normalized by the bulk component, yielding the relationship,

$$\frac{\mathrm{A}}{{\mathrm{A}}_0}=\frac{4{\mathrm{v}}_{\mathrm{s}}}{{\mathrm{A}}_0\mathrm{d}}+1$$ 12

Ratios approaching 1 suggest that bulk SRH recombination dominates the total SRH recombination, either due to very large device diameters, or inherently higher bulk SRH recombination compared to surface effects. Conversely, large ratios ($\frac{\mathrm{A}}{{\mathrm{A}}_0}\gg 1$) indicate either dominant surface-related SRH recombination or very small μLED diameters, emphasizing the increased relative contribution of surface recombination in smaller devices. This ratio introduces a useful reference scenario: the condition when bulk and surface SRH recombination rates are equal (${\mathrm{A}}_0={\mathrm{A}}_{\mathrm{s}}$), corresponding precisely to $\frac{\mathrm{A}}{{\mathrm{A}}_0}=2$. Considering this point, a critical diameter (${\mathrm{d}}_{\mathrm{crit}}$) can be defined, representing the µLED diameter at which bulk and surface SRH recombination contributions are exactly balanced. ${\mathrm{d}}_{\mathrm{crit}}$ is given explicitly by,

$${\mathrm{d}}_{\mathrm{crit}}=\frac{4{\mathrm{v}}_{\mathrm{s}}}{{\mathrm{A}}_0}$$ 13

It is important to recognize that ${\mathrm{d}}_{\mathrm{crit}}$ is dependent on both ${\mathrm{v}}_{\mathrm{s}}$ and ${\mathrm{A}}_0$, which in turn are heavily influenced not only by epitaxial growth quality but also by the µLED fabrication process and the resulting sidewall coating/treatment of sidewall defects. This behavior is further illustrated in Fig. 4, which plots the $\frac{\mathrm{A}}{{\mathrm{A}}_0}$ ratio as a function of µLED diameter for the two sidewall coating schemes investigated in this study. The variation shows the impact of the SiO₂ and SU-8 sidewall coating on the surface and bulk SRH recombination across different µLED sizes.

Fig. 4. Normalized Shockley–Read–Hall (SRH) recombination as a function of μLED size.

Normalized total SRH recombination rate, expressed as A/A₀, plotted as a function of μLED diameter (d) for devices with SiO₂ (red solid line) and SU-8 (blue solid line) sidewall coatings. Values of A/A₀ are extracted from fitting the EQE model to the experimental data, as described in the Supplementary Note 1. The inset equation shows the size-dependent SRH recombination model used, where A is the total SRH recombination rate, A₀ is the bulk SRH contribution, ${\mathrm{\nu }}_{\mathrm{s}}$ is the surface recombination velocity, and d is the μLED diameter. The black horizontal line at A/A₀ = 2 indicates the condition where bulk and surface SRH recombination contributions are equal. Vertical dashed lines mark the corresponding critical diameters (${\mathrm{d}}_{\mathrm{crit}}$) for each coating scheme (SiO₂: ${\mathrm{d}}_{\mathrm{crit}}$ ≈ 43 μm; SU-8: ${\mathrm{d}}_{\mathrm{crit}}$ ≈ 6 μm).

Figure 4 shows the strong dependence of ${\mathrm{v}}_{\mathrm{s}}$ on the $\frac{\mathrm{A}}{{\mathrm{A}}_0}$ ratio. The plot is generated using the extracted fitting parameters ${\mathrm{A}}_0$ and the sidewall coating dependent ${\mathrm{v}}_{\mathrm{s}}$ parameters, as summarized in Table 1. These parameters were then used to extrapolate the $\frac{\mathrm{A}}{{\mathrm{A}}_0}$ behavior to both smaller and larger µLED diameters beyond the experimentally tested range. This approach defines the performance boundaries of the µLED, which are governed by the epitaxial quality and by the condition of the sidewall surface, and it enables extraction of a characteristic ${\mathrm{d}}_{\mathrm{crit}}$ for each sidewall‑coating scheme. For standard sidewall coating methods, such as SiO₂, a sharp increase in SRH recombination due to sidewall effects becomes prominent at relatively large $\mathrm{\mu }$LED diameters (e.g., at diameters ≈ 100 µm). In contrast, with SU-8 encapsulation, smaller dimensions may be achieved with less degradation to the diode performance.

The solid black horizontal line in Fig. 4 highlights the condition $\frac{\mathrm{A}}{{\mathrm{A}}_0}=2$, representing the point at which bulk and surface SRH recombination are equal. Examining the SiO₂-coated devices first, a more pronounced efficiency drop at smaller sizes is observed, driven by increased surface recombination. The critical diameter for the SiO₂ sidewall coating was predicted to be approximately 43 µm from the model. Since the $\mathrm{\mu }$LED sizes investigated in this study are substantially below the critical diameter for SiO₂, non-radiative recombination from interface defects dominates for the oxide coated diodes. The degradation is most likely due to the quality of the SiO₂ or the semiconductor/dielectric interface since both diodes were fabricated from the same epilayer heterostructures with mesas patterned using the same etching processes.

The subsequent analysis of the SU-8 encapsulated diodes also suggest non-radiative recombination from the bulk should not be a contributing factor for the oxide coated LED. SU‑8‑encapsulated diodes were found to have a ${\mathrm{d}}_{\mathrm{crit}}$ of approximately 6 µm, which is about seven times smaller than that of the oxide‑coated LEDs. Given the relatively low ${\mathrm{v}}_{\mathrm{s}}$ compared to ${\mathrm{A}}_0$ for the SU-8 encapsulation, size-dependent SRH recombination is not the dominant mechanism for its optical degradation. The SRH recombination remains relatively stable with decreasing µLED size, showing minimal impact until the diameter falls below ${\mathrm{d}}_{\mathrm{crit}}$. For the SU-8 encapsulation, the 6 µm-diameter $\mathrm{\mu }$LED is close to its expected critical diameter. While SU-8 is used as an encapsulant in this work, experimental evidence suggests it exhibits electronic passivation effects, as indicated by the lower ideality factor in the low-current regime (Fig. 2) and the reduced extracted ${\mathrm{v}}_{\mathrm{S}}$ compared to SiO₂. However, additional characterization is required to conclusively verify SU-8 as a passivation layer for InGaN µLEDs.

Although surface recombination effects are minimal for SU-8 encapsulated devices, a size-dependent efficiency is still observed in Fig. 1 for diameters less than 20 µm. This phenomenon can be attributed to variations in ${\mathrm{\eta }}_{\mathrm{LEE}}$, consistent with observations reported in prior studies^21–24,29. While ${\mathrm{\eta }}_{\mathrm{LEE}}$ varies with device size at low current densities, our measurements show no detectable evidence of ${\mathrm{\eta }}_{\mathrm{LEE}}$ changing as a function of J in the high-$\mathrm{J}$ regime. Extracted ${\mathrm{\eta }}_{\mathrm{LEE}}$ values based on the model described in Eqn. ($11$) shows an increase in ${\mathrm{\eta }}_{\mathrm{LEE}}$ with decreasing µLED size for the SU-8 coated devices, as presented in Fig. 5. Combining effective sidewall coating layers to suppress surface recombination while reducing the diode diameter has the beneficial effect of increasing the ${\mathrm{\eta }}_{\mathrm{LEE}}$ due to suppressed TIR. Specifically, Fig. 5 illustrates the calculated ${\mathrm{\eta }}_{\mathrm{LEE}}$ values from the fitted ${\mathrm{\eta }}_{\mathrm{LEE}}$ coefficients, showing the size-dependent improvement of the ${\mathrm{\eta }}_{\mathrm{LEE}}$ as the diode diameter decreases. Both Fig. 5 and the fitting model have been limited to ${\mathrm{\eta }}_{\mathrm{LEE}}$ ≤ 60% to reflect the ~60% reflectivity of 30 nm Pd at 460 nm.

Fig. 5. Extracted light-extraction efficiency of SU-8-encapsulated μLEDs.

Extracted light-extraction efficiency (${\mathrm{\eta }}_{\mathrm{LEE}}$) plotted as a function of μLED diameter for SU-8-encapsulated devices. Values are obtained from fitting the EQE model to the experimental data, as described in Supplementary Note. 1. The plotted range and fitting model are limited to $\mathrm{\eta }\_\mathrm{LEE}$ ≤ 60% to reflect the approximately 60% reflectivity of a 30 nm Pd contact at 460 nm. Inset: Peak wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$, %) plotted as a function of current density (J, A cm⁻²), normalized by the p-contact area, highlighting the high-current regime where lateral current spreading beyond the p-contact is reduced and size-dependent light-extraction differences are apparent. Symbols depicting device diameters of 6 μm (yellow diamonds), 12 μm (blue squares), and 17 μm (red triangles) represent mean values; error bars indicate the standard deviation, and semi-transparent symbols denote individual device measurements. Sample sizes in the inset were n = 4 devices for all μLED diameters. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models.

The inset of Fig. 5 shows the ${\mathrm{\eta }}_{\mathrm{WPE}}$ plotted as a function of J normalized by the p-contact area. This data shows recombination is increasingly localized beneath the p-contact, reducing lateral spreading toward the mesa sidewalls¹⁶. As a consequence, a smaller fraction of injected carriers reaches the sidewalls and sidewall-related non-radiative losses become less dominant, with ${\mathrm{\eta }}_{\mathrm{LEE}}$ increasing. This behavior is consistent with prior experimental and simulation studies of µLEDs with finite p-contact geometries, which show that current spreading beyond the p-contact footprint diminishes at elevated J³³. In this high-$\mathrm{J}$ regime, the ${\mathrm{\eta }}_{\mathrm{WPE}}$ (Fig. 5 inset) increases as the device diameter decreases, consistent with the extracted size-dependent increase in ${\mathrm{\eta }}_{\mathrm{LEE}}$. Similar high-current ${\mathrm{\eta }}_{\mathrm{WPE}}$ enhancements with decreasing µLED size have been reported in previous studies emphasizing light extraction effects, although those reports typically employ full-mesa p-contacts, whereas the present devices utilize a reduced p-contact footprint²¹. Consequently, the improvement in ${\mathrm{\eta }}_{\mathrm{WPE}}$ observed in SU-8 encapsulated devices (Fig. 1) may be driven by enhancement in ${\mathrm{\eta }}_{\mathrm{LEE}}$, rather than changes in ${\mathrm{\eta }}_{\mathrm{IQE}}$.

To examine this hypothesis, a KOH sidewall etch treatment was applied in combination with the polymeric coating. The KOH wet-etch method is commonly utilized to mitigate sidewall defects induced by the dry-etching process of GaN, and µLED devices were fabricated with and without KOH treatment prior to the SU-8 encapsulation³⁰. Fig. 6 presents the ${\mathrm{\eta }}_{\mathrm{WPE}}$ as a function of $\mathrm{J}$ for the different µLED diameters (6, 12, and 17 µm) comparing both treatment scenarios. Figure 3 (SU-8 encapsulated, right) and Fig. 6 (no treatment, left) present the same image/plot. The general trend of increasing efficiency with decreasing device size is consistent between both treatment methods. However, Fig. 6 clearly indicates that KOH-treated devices consistently exhibit higher peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ values across all tested diameters. The largest improvement due to KOH treatment is observed at the smallest device diameter (6 µm), achieving a peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ increase of approximately 15% compared to untreated devices. No observable shift in the ${\mathrm{J}}_{\mathrm{peak}-\mathrm{WPE}}$ was observed, suggesting negligible surface SRH recombination. The KOH treated sidewall devices had an average peak-${\mathrm{\eta }}_{\mathrm{WPE}}$ of 20.3 % at an average J of 2.5 $\frac{\mathrm{A}}{\mathrm{c}{\mathrm{m}}^2}$ for the 6 μm blue InGaN $\mathrm{\mu }$LEDs.

Fig. 6. Opto-electrical efficiency of SU-8 encapsulated μLEDs with different sidewall treatments.

a Wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$,%) as a function of current density (J, A cm⁻²) for untreated μLEDs. b Wall-plug efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$,%) as a function of current density (J, A cm⁻²) for KOH-treated μLEDs. μLED diameters are represented by 6 μm (yellow diamonds), 12 μm (blue squares), and 17 μm (red triangles). Symbols represent mean values; error bars indicate the standard deviation. Semi-transparent symbols denote individual device measurements used to calculate the mean. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models. Green arrows indicate the qualitative variation in ${\mathrm{\eta }}_{\mathrm{WPE}}$ with decreasing μLED diameter. Sample sizes were n = 3, 4, and 4 devices for KOH treated μLEDs with diameters of 6, 12, and 17 μm, respectively, and n = 4 devices for all untreated μLED diameters. The untreated SU-8 data shown in the left panel are identical to the SU-8 dataset presented in Fig. 3 (right panel) and are reproduced here for direct comparison.

To better understand the results, the inset of Fig. 7a presents an SEM micrograph of a 6 µm µLED following KOH treatment but prior to SU-8 encapsulation revealing roughened sidewalls from the KOH etching, exposing the non-polar facets of the (In)GaN⁷. This sidewall roughness can randomize the photon incidence angles within the MQWs and mesa, reducing TIR and consequently enhancing ${\mathrm{\eta }}_{\mathrm{LEE}}$. Figure 7a shows the ${\mathrm{\eta }}_{\mathrm{LEE}}$ improves for µLED sizes below 10 µm, directly correlated to the 15% increase in ${\mathrm{\eta }}_{\mathrm{WPE}}$ observed in Fig. 5. Both Fig. 7a and the fitting model have been limited to ${\mathrm{\eta }}_{\mathrm{LEE}}$ ≤ 60% to reflect the ~60% reflectivity of 30 nm Pd at 460 nm. These observations help explain the improved ${\mathrm{\eta }}_{\mathrm{LEE}}$ values extracted from the fitted model and the corresponding increase in ${\mathrm{\eta }}_{\mathrm{WPE}}$ shown in Fig. 6.

Fig. 7. Model-extracted light extraction efficiency and Shockley–Read–Hall recombination versus μLED size.

a Extracted light-extraction efficiency (${\mathrm{\eta }}_{\mathrm{LEE}}$) plotted as a function of μLED diameter for untreated (red solid line) and KOH-treated (blue solid line) devices. Values are obtained from fitting the EQE model to the experimental data, as described in Supplementary Note 1. The plotted range and fitting model are limited to ${\mathrm{\eta }}_{\mathrm{LEE}}$ ≤ 60% to reflect the approximately 60% reflectivity of a 30 nm Pd contact at 460 nm. Inset: Tilted scanning electron micrograph of a 6 μm μLED following KOH treatment and prior to SU-8 encapsulation. b Extracted normalized Shockley–Read–Hall recombination rate (A/A₀) plotted as a function of μLED diameter for untreated and KOH-treated devices, obtained from fitting to the recombination model. The black horizontal line at A/A₀ = 2 indicates the condition where bulk and surface SRH recombination contributions are equal.

The effect of KOH etching was further evaluated using the critical diameter model by extracting the recombination coefficients from ${\mathrm{\eta }}_{\mathrm{EQE}}$ versus $\mathrm{J}$ data (Table 1). The extracted ${\mathrm{v}}_{\mathrm{s}}$ for the devices treated with the KOH etch was substantially reduced; the KOH-treated samples exhibit a ${\mathrm{v}}_{\mathrm{s}}$ values of <10 cm/s, among the lowest reported for InGaN µLEDs³⁴. Consequently, the extracted ${\mathrm{d}}_{\mathrm{crit}}$ for KOH-treated SU-8 encapsulated µLEDs was predicted to be smaller <0.1 µm (Fig. 7b) compared to the non-KOH treated diodes. At this critical dimension, surface recombination effects were found to no longer dominate SRH recombination for LEDs approaching nanometer length scales. Thus, employing an effective sidewall treatment (KOH etching) combined with a suitable sidewall coating scheme (SU-8) enabled top-down etched InGaN µLEDs to achieve high-performance operation that were independent of the size of the diode.

Further analysis of the electrical characteristics, illustrated by the I-V and IF versus voltage plots in Fig. 8, reveals nearly identical behavior for both treatment conditions, suggesting minimal electrical differences resulting from the KOH sidewall treatment. The minimum mean IF values for untreated and treated devices are n = 1.68 and n = 1.54, respectively. Although there is a slight decrease in minimum IF, the difference is insignificant and within the measurement error.

Fig. 8. Sidewall treatment-dependent electrical characteristics of 6 µm μLEDs.

a Semi-logarithmic current–voltage (I–V) characteristics for SU-8-encapsulated 6 μm μLEDs without sidewall treatment (green rectangles) and with KOH treatment (purple triangles). b Corresponding mean ideality factor plotted as a function of applied voltage for the same devices, extracted over the voltage range highlighted in panel a. Symbols represent mean values; error bars indicate the standard deviation. Semi-transparent symbols denote individual device measurements used to calculate the mean. Sample sizes were n = 4 devices for untreated μLEDs and n = 3 devices for KOH-treated μLEDs. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models.

As shown in Fig. 6, KOH treatment enhances the efficiency of SU-8-encapsulated devices by reducing ${\mathrm{v}}_{\mathrm{S}}$ and improving ${\mathrm{\eta }}_{\mathrm{LEE}}$, particularly at smaller diameters. Devices treated with KOH and coated with SiO₂ exhibit substantially lower peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ compared to KOH-treated SU-8-coated devices, as evident from the size-dependent trends in Fig. 9. While KOH treatment provides optical benefits, it is not sufficient by itself. The results, supported by the presented models, indicate that the impact of KOH is constrained by factors such as bulk epitaxial layer quality, sidewall coating selection, and sidewall etching processes.

Fig. 9. Size- and sidewall-coating-dependent efficiency of μLEDs.

Peak wall-plug efficiency (peak-${\mathrm{\eta }}_{\mathrm{WPE}}$,%) plotted as a function of μLED diameter for devices with SiO₂ (green circles), SiO₂ with KOH treatment (purple stars), SU-8 (blue rectangles), and SU-8 with KOH treatment (red diamonds). Symbols represent mean values; error bars indicate the standard deviation. Semi-transparent symbols denote individual device measurements used to calculate the mean, with colors matching the corresponding coating condition. Dotted lines are included as visual guides to aid interpretation and do not represent fitted models. Sample sizes were n = 4 devices for all conditions. Exceptions were SU-8 with KOH at 6μm, SiO₂ with KOH at 17 μm, and SiO₂ at 6 μm and 12 μm, where n = 3.

These results demonstrate the potential effectiveness of using polymeric materials and simple etching processes for fabricating high-performance light emitters. This approach creates a feasible approach for producing large-area arrays of μLED media for high-resolution displays, creating a pathway for display applications requiring high pixel density, low-cost, and high brightness.

Conclusion

This study investigated the optoelectronic performance of InGaN μLEDs under various sidewall coating and sidewall treatment schemes. Notably, a simple change in sidewall coating material led to two contrasting trends in efficiency as a function of μLED size. Detailed analysis and model fitting of the electrical and optical data enabled the extraction of key recombination parameters, including the ${\mathrm{v}}_{\mathrm{s}}$ and bulk SRH recombination coefficient, ${\mathrm{A}}_0$.

A practical reference diameter, ${\mathrm{d}}_{\mathrm{crit}}$, was defined as the point at which surface and bulk SRH recombination contribute equally to total non-radiative recombination losses. μLEDs with diameters larger than this critical are relatively unaffected by sidewall defects and surface recombination. Minimizing ${\mathrm{d}}_{\mathrm{crit}}$, is therefore a key objective in μLED fabrication, as doing so allows other second-order effects (such as size-dependent ${\mathrm{\eta }}_{\mathrm{LEE}}$) to be leveraged for further performance gains.

Using effective sidewall engineering through optimized sidewall coating (SU-8 encapsulant) and treatment schemes (KOH etchants), 6 μm diameter μLEDs achieved a mean peak ${\mathrm{\eta }}_{\mathrm{WPE}}$ of 20.3% at 2.5 $\mathrm{A\; c}{\mathrm{m}}^{-2}$ and an optical power density of 1.4 $\mathrm{W\; c}{\mathrm{m}}^{-2}$. Moreover, the corresponding fabrication process resulted in a ${\mathrm{d}}_{\mathrm{crit}}$ < 0.1 μm and a ${\mathrm{v}}_{\mathrm{s}}$ <10 $\mathrm{cm}{s}^{-1}$, highlighting its effectiveness in suppressing surface-related losses. Supplementary Table 1 provides performance parameters for the highest performance μLED configuration demonstrated in this study.

Methods

µLED Fabrication

Commercially available blue InGaN-based LED $\left({\mathrm{\lambda }}_{\mathrm{emission}}=445\mathrm{nm}\right)$ epitaxial heterostructures on double-side polished planar (unpatterned) sapphire substrates (from SemiLEDs Corporation) were initially cleaned with a piranha solution. A 600 nm thick PE-CVD deposited $\mathrm{Si}{\mathrm{O}}_2$ is used as an etch mask for the subsequent GaN etch. Ultraviolet photolithography was utilized to define the µLED mesa area. An $\mathrm{Si}{\mathrm{O}}_2$ etch mask was then defined followed by a GaN etch using an Oxford Instruments ICP380 dry etcher employing a Cl₂/BCl₃ plasma to create a mesa etch depth of 1.5 $\mathrm{\mu }\mathrm{m}$.

Following the LED mesa etch, the wafer was diced into smaller chips with a 15 mm × 15 mm dimension. In summary, five 15 mm × 15 mm chips were fabricated with each chip having the device configurations listed below:

• Chip #1: $\mathrm{Si}{\mathrm{O}}_2$ Bilayer w/o Treatment

• Chip #2: $\mathrm{Si}{\mathrm{O}}_2$ Bilayer w/ KOH Treatment

• Chip #3: SU-8 w/o Treatment

• Chip #4: SU-8 w/ KOH Treatment

• Chip #5: SiO₂ (ALD)/SU-8 Bilayer w/o Treatment

Samples containing both SiO₂/SU-8 bilayer encapsulants were made for comparison (Chip #5). These bilayer encapsulants were found to show similar ${\mathrm{\eta }}_{\mathrm{WPE}}$ behavior to SiO₂ only samples and their performance was independent of ${\mathrm{\eta }}_{\mathrm{LEE}}$ (see Supplementary Fig. 2). Following a dicing step, Chip #2 and #4 was subject to KOH treatment at room temperature (RT). All chips were stripped of the $\mathrm{Si}{\mathrm{O}}_2$ etch mask using a 10:1 BOE solution. Supplementary Fig. 3 shows scanning electron microscopy (SEM) images taken after the $\mathrm{Si}{\mathrm{O}}_2$ etch mask strip for both $\mathrm{\mu }$LEDs with and without the KOH treatment showing an observable change in the sidewall surface roughness through exposed GaN facets for the KOH treated devices.

The n-contact was deposited using an Angstrom Engineering electron-beam evaporator. The n-contact consisted of a Cr/Al/Ni/Au (5/100/10/100 nm) layer deposited using a metal lift-off process. The surface of the exposed GaN was treated with a solution of 1:1 hydrochloric acid before the metal deposition. An Pd/Ni/Au (30/10/200 nm) p-contact was deposited using a similar procedure. The p-contact was laid out so that its radius is consistently about 1.7 µm smaller than the µLED mesa radius, giving a fixed radial offset Δr ≈ 1.7 µm. Both contacts were then annealed in one step by rapid thermal annealing at 500${}^{\circ }\mathrm{C}$ for 5 minutes in air. The resulting contact resistivities were measured using the circular Transmission Line Method. The p-contact and n-contact yielded a mean contact resistivity of $4.3\times {10}^{-3}\mathrm{\Omega }\mathrm{c}{\mathrm{m}}^2$ and $9.1\times {10}^{-6}\mathrm{\Omega }\mathrm{c}{\mathrm{m}}^2$, respectively. The p-contact resistivity is within the range commonly reported for effective p-GaN ohmic contacts for similar device dimensions and operating conditions¹⁸. Prior experimental and simulation studies have also shown that lateral current spreading in µLEDs typically extends ~1–2 µm beyond the p-contact edge, suggesting a substantial fraction of injected carriers reaches the mesa sidewalls at low to moderate current densities³³. The p-contact–to-mesa separation in the measured devices (Δr = 1.7 µm) lies within this range, and is not expected to limit charge injection into the p-layer for the geometries used in these measurements. Supplementary Fig. 4 shows an optical micrograph image of a 6$\mathrm{\mu }\mathrm{m}$ diameter LED after p-contact deposition and annealing.

The $\mathrm{Si}{\mathrm{O}}_2$ bilayer (ALD/PECVD 10/150 nm) was deposited on one of the chips (Chip #1, #2, and #5) using an Oxford PlasmaLab 100 PECVD/ALD Cluster Tool. SU-8 3010 was spin-coated and patterned onto Chips #2, #3, and #5. A conformal layer consisting of 500 nm of aluminum was sputtered and patterned on all chips to define the metal traces acting as the probe pads and as a reflector to redirect light downwards for light emission through the sapphire substrate. The step height of the contact vias were ~ 6 µm for the SU-8 encapsulated devices, providing a modest via aspect ratio <2 that provided adequate electrical contact to the p-contact. Supplementary Fig. 5 depicts a schematic of the bi-layer $\mathrm{Si}{\mathrm{O}}_2$ structure (Chips #1 and #2), and the SU-8 encapsulant structure (Chips #3 and #4).

There are a few differences between the two different sidewall coating schemes. The $\mathrm{Si}{\mathrm{O}}_2$ was deposited in a high-vacuum system, whereas the SU-8 encapsulant is simply spin-coated onto the devices in ambient cleanroom conditions. Another difference is the $\mathrm{Si}{\mathrm{O}}_2$ bilayer sidewall coating allows Aluminum metal to cover the µLED conformally. In this structure, the metal coating on the sidewall of the µLED is separated only by the $\mathrm{Si}{\mathrm{O}}_2$ bilayer. The SU-8 encapsulant scheme also planarizes the device, decoupling the aluminum metal from the sidewall of the µLED. Supplementary Fig. 6 shows SEM images taken after µLEDs with both sidewall coating schemes are entirely fabricated.

Device Characterization

Devices were characterized through combined optical and electrical measurement techniques. For characterization, each LED device on a sapphire substrate was positioned atop a silicon photodiode detector (Thorlabs FDS1010) with a known responsivity curve, capturing emitted light through the sapphire substrate. Electrical connections were established by probing the $\mathrm{\mu }$LED within a blackout Faraday cage to eliminate external interference. Both the photodiode and the μLEDs were connected to a Keithley 4200A Semiconductor Characterization System Parameter Analyzer, which is vendor calibrated annually and capable of measuring currents down to femto-ampere levels. The measurement involved performing a current-voltage (I-V) sweep of the diode while simultaneously recording the LED’s optical intensity through the photodiode’s photocurrent. The electrical measurements were performed across a minimum of three devices to extract device parameters; the error bars represent the extracted standard deviation of the measurements. The $\mathrm{\mu }$LED I-V and photodiode current were used to calculate the External Quantum Efficiency $\left({\mathrm{\eta }}_{\mathrm{EQE}}\right)$ and the Wall Plug Efficiency (${\mathrm{\eta }}_{\mathrm{WPE}}$) for optical characterization. For the ${\mathrm{\eta }}_{\mathrm{WPE}}$ measurements, errors for a given J were determined at a fixed applied voltage. The µLED J was consistently calculated using the mesa area for all sizes and sidewall coating schemes.

Structural Characterization

The SEM images were taken using both a JSM-7200F JEOL and a SU5000 Hitachi microscope system. Both systems were equipped with a variable angle stage allowing for measurements at 35° tilt. An accelerating voltage of 5 kV was used for imaging.

Author contributions

P.G. and W.W. jointly devised the experimental plan. P.G. performed all of the device fabrication, characterization, data analysis, and code creation. P.G. and W.W. participated in extensive discussions on the experimental results and jointly prepared the manuscript.

Peer review

Peer review information

Communications Engineering thanks the anonymous reviewers for their contribution to the peer review of this work. Primary Handling Editors: [Chaoran Huang] and [Wenjie Wang]. A peer review file is available.

Data availability

The numerical source data underlying all figures presented in the main manuscript and Supplementary Information, including electrical and optical measurements and derived parameters, are provided as spreadsheet files in the Figshare repository at 10.6084/m9.figshare.31460458.

Code availability

The code used for EQE fitting and analysis is available on Figshare at 10.6084/m9.figshare.31463881, including a reproducible reference implementation and example input data. The analysis was performed using MATLAB (R2021a or later) with the Optimization Toolbox.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s44172-026-00661-0.