Memristive crossbar array-based hardware framework for compressed sensing and event-driven neuromorphic processing

Abstract

Compressed sensing (CS) enables efficient data acquisition and implicit encryption; however, its recovery stage remains a significant computational bottleneck, as it requires solving large-scale optimization problems by running iterative reconstruction algorithms. Here, we propose an event-driven CS recovery framework developed through an algorithm–hardware co-design approach. This framework employs memristor crossbar array (MCA)-based analog matrix computing (AMC) circuits as the hardware platform and incorporates an efficient CS recovery algorithm (named constrained gradient descent (CGD) algorithm) designed to leverage them. Furthermore, the framework supports event-driven selective recovery via MCA-based feature detection. We fabricated the hardware to validate the proposed framework, and the experimental results demonstrate 20.4× to 45.22× improvements in energy efficiency over state-of-the-art methods for image and ECG signal processing. These results underscore the potential of the proposed framework as a competitive hardware solution for real-time sensing signal processing in edge devices.

Real-time sensing generates large volumes of data requiring compression and reconstruction, often leading to computational bottlenecks. By leveraging algorithm–hardware co-design, Deng et al. propose an event-driven data reconstruction framework built on memristor crossbar-based analog matrix computation.

Introduction

With the rapid development of Internet of Things (IoT) technologies in fields such as healthcare, smart cities, autonomous vehicles, and industrial automation, the deployment of ubiquitous sensors has been accelerating. These sensors not only enable real-time data collection but also facilitate intelligent decision-making and adaptive system responses across interconnected sensors and computing systems in dynamically connected environments.

In such a world, due to the vast amounts of real-time data continuously generated by ubiquitous sensors, new and complex challenges arise, such as excessive storage demands, high computational loads, network bandwidth saturation, and increased energy consumption. These issues are particularly pronounced in edge environments, where computational and power resources are inherently limited. Therefore, it is crucial to develop efficient methods that reduce data volume while preserving essential information for effective communication.

Compressed sensing (CS) offers a promising solution to address this data volume-related challenge by exploiting the inherent sparsity in many real-world signals. Instead of following the Nyquist–Shannon sampling theorem, CS acquires signals in a compressed form (i.e., CS sampling) and reconstructs them when needed (i.e., CS recovery). This reduces the burden on data acquisition, transmission, and storage, particularly at the sensor node, offering strong potential for real-time applications in resource-constrained environments.^1,2 In addition, the randomness inherent in CS sampling may provide a built-in encryption function during data transmission. The matrix used in the compression process serves as a unique key, and the receiver cannot recover the received compressed signal without the matrix. While this mechanism does not offer the full security guarantees of dedicated cryptographic hardware, it can still meaningfully enhance security in data transmission.^3,4

Despite these advantages, the computational complexity of the CS recovery process remains a major obstacle to the practical adoption of the CS framework. The CS recovery processes need to solve classical optimization problems that can be approached using various algorithms that require iterative matrix operations, such as matrix-vector multiplication (MVM), Gram matrix computation, least-squares solutions, or index searches.^5–9 All of these calculations incur high computational and energy costs in conventional computing systems, raising the computational complexity challenge. Therefore, for deploying CS in practical edge applications, a dedicated hardware-based solution is essential.

Recently, memristive crossbar arrays (MCAs) have emerged as a powerful matrix computation accelerator due to their inherent analog matrix computing (AMC) capabilities, which leverage Ohm’s law and Kirchhoff’s current law (KCL). MCAs can perform not only matrix–vector multiplication but also matrix inversion by integrating the MCA with operational amplifiers (OAs) in a feedback loop.^10–21 Therefore, if such AMC capabilities of the MCAs can be exploited for the required operations of CS recovery, they could enhance speed and energy efficiency compared to conventional digital hardware, such as FPGAs or ASICs.^22–25 However, no algorithm has been suggested for this purpose so far, and therefore, this requires the development of an efficient CS recovery algorithm with AMC-based architectures.

In addition to signal acquisition, the CS process inherently performs feature extraction by sampling the raw signal and recovering its sparse coefficients. Therefore, if some part of the neuromorphic computation using the feature information can be performed directly within the framework before the CS recovery process, an initial decision can be made based on the feature information, and only feature-selected data is reconstructed. In this way, the burden of CS recovery can be reduced, thereby further enhancing the advantages of CS. This is especially relevant for applications such as cardiac monitoring and video surveillance, where event detection (e.g., arrhythmia or face detection) is possible from the feature information.^26–28 Such neuromorphic computation tasks are largely composed of matrix–vector multiplication operations, which can also be effectively implemented using MCAs. Therefore, by integrating an additional MCA module to perform these tasks, data for recovery can be selectively chosen through a feature-based initial decision. This approach further reduces the overall computational workload on the receiver side, an aspect that, to the best of our knowledge, has not been explicitly considered in previous studies in the context of improving the efficiency of CS recovery.

In this study, we proposed an event-driven CS recovery framework that fully leverages the AMC capabilities of MCAs, aiming not only to reduce the data volume but also to alleviate the computational burden on the receiver side. The core contributions of this study can be summarized in two aspects: (i) the development of a CS recovery algorithm specifically optimized to leverage the AMC capability of the MCA, and (ii) the design of an event-driven CS recovery framework in which event detection is performed during the CS recovery process (Fig. 1). We first introduce a CS recovery algorithm, termed constrained gradient descent (CGD). The CGD algorithm performs the recovery process through two AMC operations: matrix right-inverse (MRI) multiplication to find the initial vector of iterations, and iteratively row space projection (RSP) to find the optimal solution vector. It is worth noting that we do not need to explicitly compute the right-inverse matrix or the projection matrix. Instead, we only require the products of these matrices with the corresponding vectors, and a series of prior works have investigated efficient ways to obtain these products without directly computing the matrices.¹² To execute the CGD algorithm, we design a compact MCA-based AMC circuit based on the previous design of one-step matrix inversion circuits,^12,15 and implement it in hardware using a foundry-integrated MCA. The hardware demonstrates an array-size-independent O(1) time complexity for each MRI and RSP operation, confirming its effectiveness. Second, we present the event-driven CS recovery framework, which incorporates an additional MCA for event detection. This approach significantly reduces the recovery cost by bypassing the majority of uninformative signals and fully reconstructing only the minority of interest. Based on our hardware results, we show large-scale simulation results of event-detection-oriented tasks such as abnormal ECG signal detection and human face recognition within images, and demonstrate their remarkable energy efficiency improvement of 45.22-fold and 20.4-fold, respectively, compared to conventional CS recovery methods.

Fig. 1. Comparison of data sensing and transmission workflow of conventional data sensing, CS, and event-driven CS.

In conventional data sensing, sensors generate a vast amount of data (original signal $\mathbf{x}$), which can cause bandwidth limitations during sampling and transmission. Moreover, the receiver must process the entire sensor dataset, requiring significant computing resources. In the proposed CS framework, only the compressed data $y$ ($\mathbf{y}=\mathit{\Phi }\mathbf{x}$, where $\mathit{\Phi }$ is a compress matrix) is transmitted, thereby reducing the required data bandwidth. However, the receiver still needs to perform complex CS recovery and process the fully recovered data. In the proposed event-driven CS framework, event detection is embedded within the CS recovery process, allowing only selected signals to be recovered. This allows the receiver to process only the most relevant information, minimizing the overall computational burden.

Results

Constrained gradient descent algorithm

In the CS framework, the receiver should be able to recover the N-dimensional sparse coefficient vector $\mathbf{s}$ of the original signal $\mathbf{x}$ from the M-dimensional compressed signal $\mathbf{y}$, where $M<N$. Figure 2a briefly illustrates the dimensional relationships of signals. This CS recovery process can be described as an ${\mathrm{L}}_1$-norm minimization problem^29–31:

$$\min {\mid \mid \mathbf{s}\mid \mid }_1\mathrm{s.t.}\mathbf{As}=\mathbf{y}$$ 1

where $\mathbf{A}=\mathit{\Phi }\mathit{\Psi }$ with $\mathit{\Phi }\in {\mathbb{R}}^{M\times N}$($M$<$N$) represents the compression matrix, and $\mathit{\Psi }\in {\mathbb{R}}^{N\times N}$ denotes the sparse basis in which the signal $\mathbf{x}$ can be sparsely expressed as $\mathbf{x}=\mathit{\Psi }\mathbf{s}$.

Fig. 2. MCA-based AMC circuits for CGD algorithm.

a Mathematical model of CS sampling and recovery. b The structure of the proposed CGD recovery algorithm. c The proposed AMC circuits function as hardware accelerators for the CGD algorithm. The input ports for MRI and RSP are marked as blue and green boxes, respectively. d The PCB implementation of the circuit in (c). e The matrix $\mathbf{A}$ and f its mapping result for the circuits experiment of sparse signal recovery. The real-time outputs (lines) of MRI (g) and RSP (h) operations with the ideal outputs (dashes). The output voltage converges stably to its ideal value over time, demonstrating that both circuits operate successfully.

The CS recovery process is the most computationally intensive part of the overall CS framework. Therefore, developing a hardware-friendly algorithm to perform this task efficiently is of critical importance. To this end, we developed the CGD algorithm, specifically designed to leverage AMC operations and fully exploit the capabilities of the MCA hardware. It operates through the following iterative update equations to progressively improve the solution $\mathbf{s}$.

$${\mathbf{s}}^{\left(t+1\right)}={\mathbf{z}}^{\left(t+1\right)}+\mathbf{q}-\mathbf{P}{\mathbf{z}}^{\left(t+1\right)}$$ 2

$${\mathit{z}}^{\left(t+1\right)}={\mathbf{s}}^{\left(t\right)}-\epsilon \times \mathrm{sgn}\left({\mathbf{s}}^{\left(t\right)}\right)$$ 3

Here, the vector $\mathbf{q}$ represents the MRI operation given by $\mathbf{q}={\mathbf{A}}^{\mathrm{T}}{\left(\mathbf{A}{\mathbf{A}}^{\mathrm{T}}\right)}^{-1}\mathbf{y}$ to find the ${\mathrm{L}}_2$-norm minimization solution of the equation $\mathbf{As}=\mathbf{y}$. The vector $\mathbf{z}$ is the intermediate variable, matrix $\mathbf{P}$ is called the projection matrix, given by $\mathbf{P}={\mathbf{A}}^{\mathrm{T}}{\left(\mathbf{A}{\mathbf{A}}^{\mathrm{T}}\right)}^{-\mathbf{1}}\mathbf{A}$, and the RSP operation $\mathbf{P}{\mathbf{z}}^{\left(t+1\right)}$ projects the vector ${\mathbf{z}}^{\left(t+1\right)}$ into the affine subspace $\mathbf{As}=\mathbf{y}.$ The superscript $t$ denotes the iteration number, $\epsilon$ is a step size, and $\mathrm{sgn}\left(\cdot \right)$ indicates the sign function for each element of a vector, which is also the subgradient of the objective function ${\mathrm{L}}_1$-norm ${∥\cdot ∥}_1$. To preliminarily demonstrate the performance of the proposed CGD algorithm, we conducted CS recovery on various randomly generated sparse signals under different compression ratios (Supplementary Fig. 1). Compared with conventional algorithms, CGD achieved comparable speed on the CPU platform, indicating its low computational complexity. It also attained comparable recovery accuracy across different compression ratios. Notably, the most significant advantage of CGD emerges in MCA-based hardware implementations due to its simple structure, which will be demonstrated in the following experiments.

MRI and RSP are the two primary computational operations in the CGD algorithm. As illustrated in Fig. 2b, the algorithm begins by obtaining an initial estimate ${\mathbf{s}}^{\left(0\right)}$(${\mathbf{s}}^{\left(0\right)}$= $\mathbf{q}$) through ${\mathrm{L}}_2$-norm minimization via the MRI step. Subsequently, the RSP step refines this estimate $\mathbf{q}$ iteratively to derive the recovery result $\mathbf{s}$, which is expected to approach the optimal solution ${\mathbf{s}}^{\mathit{*}}$. A more detailed description of this procedure is provided in Supplementary Note 1, and the theoretical proof of the CGD algorithm is given in Supplementary Note 2.

As MRI and RSP are mainly composed of matrix multiplication and inversion, MCA-based AMC circuits can efficiently perform these operations in one step. To this end, we propose the MCA-based AMC accelerator as illustrated in Fig. 2c. The proposed accelerator consists of two sets of OAs (OA1 and OA2) and three identical MCAs, whose weight matrices are mapped to $\mathbf{G}={\mathbf{A}}^{\mathrm{T}}{g}_0$, where $g_0$ denotes a unit conductance. The input nodes for MRI and RSP are denoted as ${\mathbf{V}}_y$ (blue dashed box) and ${\mathbf{V}}_z$ (green dashed box), and their common output node is denoted as ${\mathbf{V}}_{\mathrm{o}}$ (black dashed box). The lower two MCAs and two sets of OAs constitute the matrix pseudoinverse (MPI) subcircuit, which can efficiently solve various inverse problems of non-square matrices with different input and output topologies in a single operation.¹¹ The OA1 operates as a transimpedance amplifier with the feedback conductance $c{g}_0$, where $c$ is a constant to optimize the dynamic performance. According to the connection topology of OAs, OA1 negatively transfers its input while OA2 positively transfers its input, thus building a stable negative feedback loop for the overall circuit.

For the MRI operation, the input voltages ${\mathbf{V}}_y$ are applied to a unit conductance $g_0$ and feed to the MPI subcircuit. The steady-state node voltages of the MPI subcircuit are determined by the virtual short and virtual open characteristics of OAs. By applying KCL to the input port of OA2 and OA1, the operation result can be expressed by the following equations:

$${\mathbf{G}}^{\mathrm{T}}\mathbf{G}{\mathbf{V}}_r/\left(c{g}_0\right)=-g_0{\mathbf{V}}_y$$ 4

$${\mathbf{V}}_o=\mathbf{G}{\mathbf{V}}_r/\left(c{g}_0\right)$$ 5

where ${\mathbf{G}}^{\mathrm{T}}\mathbf{G}$ is invertible. The resulting relationship between the output and input voltages is given by:

$${\mathbf{V}}_o=-g_0\mathbf{G}{\left({\mathbf{G}}^{\mathrm{T}}\mathbf{G}\right)}^{-1}{\mathbf{V}}_y=-{\mathbf{A}}^{\mathrm{T}}{\left(\mathbf{A}{\mathbf{A}}^{\mathrm{T}}\right)}^{-1}{\mathbf{V}}_y$$ 6

Therefore, the output voltages ${\mathbf{V}}_o$ directly yield the MRI solution of the input voltages ${\mathbf{V}}_y$, without requiring any iterative process or matrix decomposition.

For the RSP operation, the input voltage ${\mathbf{V}}_z$ is applied to the third MCA, and then the output currents, ${\mathbf{G}}^{\mathrm{T}}{\mathbf{V}}_z$, feed to the MPI subcircuit. Accordingly, the topology of the input port of OA2 is changed, and the KCL equation in this configuration is given by:

$${\mathbf{G}}^{\mathrm{T}}\mathbf{G}{\mathbf{V}}_r/\left({cg}_0\right)=-{\mathbf{G}}^{\mathrm{T}}{\mathbf{V}}_z$$ 7

Since the relationship between ${\mathbf{V}}_o$ and ${\mathbf{V}}_r$ remains the same as Eq. (5), the output voltage becomes:

$${\mathbf{V}}_o=-\mathbf{G}{\left({\mathbf{G}}^{\mathrm{T}}\mathbf{G}\right)}^{-1}{\mathbf{G}}^{\mathrm{T}}{\mathbf{V}}_z=-{\mathbf{A}}^{\mathrm{T}}{\left(\mathbf{A}{\mathbf{A}}^{\mathrm{T}}\right)}^{-1}\mathbf{A}{\mathbf{V}}_z$$ 8

Thus, the RSP operation is successfully executed.

Beyond positive-valued matrices, this circuit can be extended to more generalized cases to handle real-valued matrices.¹⁵ This is achieved by leveraging the natural differential properties of the inverting and non-inverting input ports of OAs to construct a differential structure, thereby enabling the representation of negative values (Supplementary Fig. 2 and Note 3).

Memristor crossbar array-based acceleration hardware

Next, we implemented this circuit in hardware on a printed circuit board (PCB), as shown in Fig. 2d. The MCAs were realized using TiN/HfOx/TaOx/TiN structure devices through a commercial foundry process (see details in Methods and Supplementary Fig. 3). They exhibit excellent retention characteristics and high write accuracy, making them suitable for constructing the AMC circuit, as we have thoroughly investigated in previous studies.^32–34

For the demonstration of CS recovery, a 4 × 8 random-valued matrix ${\mathbf{A}}_{4\times 8}$ (Fig. 2e) was mapped onto the three MCAs. To ensure the values fell within the appropriate conductance range, we set $g_0$ = 83.3 μS and employed a write-and-verify method to program the target conductance with a 5$\%$ verification window (Fig. 2f).

To validate the function of AMC circuits, we applied random-valued input voltages of ${\mathbf{V}}_y$ and ${\mathbf{V}}_z$ and obtained the output voltages ${\mathbf{V}}_o$. Then, we compared the ${\mathbf{V}}_o$ with the ideal calculation results. For example, when ${\mathbf{V}}_y$ = [26 mV, −38 mV, 116 mV, -50 mV]^T, the ${\mathbf{V}}_o$ of the MRI operation should be [−18mV, 22 mV, 28 mV, 70 mV, 58 mV, -58mV, -62mV, 32 mV]^T, according to Eq. (6). Figure 2g shows that the ${\mathbf{V}}_o$ successfully converged to the corresponding ideal results indicated by the dashed lines after approximately 3 μs. Similarly, Fig. 2h shows the ${\mathbf{V}}_o$ of the RSP operation when ${\mathbf{V}}_z$ = [122 mV, −34mV, −46 mV, 34 mV, 80 mV, −41 mV, −93 mV, 99 mV]^T. The ${\mathbf{V}}_o$ converges to the ideal values of [−12 mV, −18 mV, 15 mV, 55 mV, 93 mV, −26mV, −30 mV, 56 mV]^T obtained by Eq. (8) after approximately 3 μs of self-iterative stabilization. Additionally, we also mapped a 2 × 4 random matrix to conduct the corresponding MRI and RSP operations, which produced the similarly accurate convergence results as presented in Supplementary Fig. 4. To further investigate the performance of the proposed AMC circuits, 500 randomly generated input voltage vectors were applied to both 2 × 4 and 4 × 8 random matrices for MRI and RSP operations. We then compared the output voltages with target values and computed the distribution of convergence curves (Supplementary Fig. 5). It’s reasonable that the accuracy of RSP is slightly lower than that of MRI, since RSP requires an additional MCA, which may introduce extra errors due to conductance writing errors and parasitics of PCB. Regarding the matrix size, the convergence speeds of 2 × 4 and 4 × 8 matrices are essentially the same (approximately 3 μs). These results preliminarily validate the O(1) time complexity of the proposed AMC circuits, which will be further demonstrated in simulation with larger matrices.

Demonstration of the acceleration hardware

Next, we demonstrated the full CS recovery process using the hardware. While the hardware accelerates the MRI and RSP operations, the CGD algorithm also requires addition, subtraction, and sign functions. Therefore, we constructed a hardware–software hybrid system to run the CGD algorithm. The complete workflow of this system is shown in Fig. 3a (also see Method and Supplementary Fig. 6 for further details). Here, the compressed signals $\mathbf{y}$ fed first to the AMC circuits for the MRI operation, and the output $\mathbf{q}$ was obtained corresponding to the initial vector ${\mathbf{s}}^{\left(0\right)}$ (${\mathbf{s}}^{\left(0\right)}=\mathbf{q}$, ${\mathrm{L}}_2$-norm minimization result). Then, from this ${\mathbf{s}}^{\left(0\right)}$, the RSP operation was iteratively performed for t cycles until the ${\mathbf{s}}^{\left(t\right)}$ was sufficiently close to ${\mathbf{s}}^{*}$ (${\mathrm{L}}_1$-norm minimization result).

Fig. 3. Experimental results of CS recovery using CGD algorithm and proposed circuit.

a Workflow of the proposed CS recovery hardware. b 80 indices represent 10 segments of the 8-point original sparse signal $\mathbf{s}$ (red), compared with the recovery result of the hardware experiment (blue), after 33 iterations. The vertical dashed lines separate each segment. c Compressed signal $\mathbf{y}$ (top) and the corresponding mapped input voltages for the hardware experiment. d The overall CS recovery results ${\mathbf{s}}^{\left(t\right)}$ gradually evolve close to the ideal values (original signal) over the 40 iterations, with a large step size (left) and a small step size (right). e Performance trajectory corresponding to the results in (d). f Hardware recovered record with adaptive annealing-step-size strategy. g Corresponding performance trajectory relative to the ideal value, compared with the numerical simulation result of the CGD algorithm. The optimal performance is marked by the star.

For the CS recovery demonstration, we randomly generated 10 different sparse signals $\mathbf{s}$ of length 8, each containing a single non-zero element. We sequentially assigned indices to them from 1 to 80, which are displayed in Fig. 3b. These signals were then multiplied by a random matrix $\mathit{\Phi }$ ($\mathit{\Phi }={\mathbf{A}}_{4\times 8}$ in this case) to simulate the CS sampling process, resulting in compressed signals $\mathbf{y}$, whose length is 4 for each (Fig. 3c, top panel). Then, the 10 compressed signals $\mathbf{y}$ were linearly converted into voltage inputs ${\mathbf{V}}_y$, with a voltage mapping unit of 0.2 V (Fig. 3c, bottom panel). This voltage range is below the switching threshold of the memristors, thus not causing unintentional conductance changes.

During the iteration, defining an appropriate step size $\epsilon$ (which is a scaling factor that determines how far the parameters move in the update direction during each iteration, see Eq. (3)) is crucial. To investigate the influence of the step size, we first conducted numerical experiments to validate the effectiveness of the proposed CGD algorithm. Figure 3d shows the recovered result ${\mathbf{s}}^{\left(t\right)}$ for all 80 indexes over a total of 40 iterations with a step size of $\epsilon$ = 0.1 (left panel) and $\epsilon$ = 0.03 (right panel). The 10 nonzero elements in ${\mathbf{s}}^{\left(t\right)}$ (blue lines) gradually converged to the original values (red dashed lines) while the other 70 zero elements (gray lines) converged correctly toward zero. Notably, the ${\mathbf{s}}^{\left(0\right)}$ (${\mathrm{L}}_2$-norm minimization result) was already quite close to the optimal solution ${\mathbf{s}}^{*}$ (${\mathrm{L}}_1$-norm minimization result). This stands in contrast to random initializations used in other greedy algorithms, highlighting the effectiveness of the CGD algorithm.

The corresponding performance trajectories for different step sizes are given in Fig. 3e. Here, we employed the normalized mean squared error (NMSE), defined by $\mid \mid {\mathbf{s}}^{\left(t\right)}-{\mathbf{s}}^{*}{\mid \mid }_2^2/\mid \mid {\mathbf{s}}^{*}{\mid \mid }_2$, and recovery signal-to-noise ratio (RSNR), defined as 20 log(1/NMSE), as the performance metrics to evaluate the recovery performance. The results suggest that a larger step size accelerates convergence but yields lower final recovery accuracy, whereas a smaller step size slows convergence but achieves higher final accuracy.

Therefore, optimizing the step size is crucial for striking a balance between convergence speed and final accuracy (further discussion is included in Supplementary Note 2). To this end, we employed an adaptive annealing strategy in the hardware experiment. We started with a large initial step size, ${\epsilon }_0$ = 0.15 to accelerate convergence, then automatically shrunk it based on the ${\mathrm{L}}_1$-norm of ${\mathbf{s}}^{\left(t\right)}$ to precisely approach the optimal solution. Specifically, we calculated the value of the objective function, ${\mathrm{L}}_1$-norm $f\left(t\right)=\mathrm{\mid \mid }{\mathbf{s}}^{\left(\mathrm{t}\right)}{\mathrm{\mid \mid }}_1$, in each iteration. According to the analysis in Supplementary Note 2, it indicates that we need to shrink the current step size if $f\left(t\right)$ is no longer decreasing sufficiently. Here, we used criterion $f\left(t\right)>{\sum }_{i=1}^{5}f\left(t-i\right)/5$ to robustly and automatically determine whether the decline of $f\left(t\right)$ has saturated. If this condition is met, the step size is reduced to half of its original value. In addition, we impose a lower bound ${\epsilon }_{\min }=0.015$ to avoid meaningless updates caused by circuit noise. With the adaptive step size, Fig. 3f shows the evolution of ${\mathbf{s}}^{\left(t\right)}$ over a total of 30 iterations and Fig. 3g shows the corresponding performance trajectory over 30 iterations. During the early iterations with a larger step size, faster convergence accompanied by larger fluctuations are observed. Later, with a smaller step size, accurate convergence is achieved. After 33 iterations, the recovery result reach its final stable performance with an RSNR of approximately 18.23 dB. Beyond this point, slight oscillations appears due to the inherent accuracy limitations of the AMC circuits. Comparing the performance trajectories in Fig. 3g, e, the adaptive annealing case achieved both a high convergence speed and accuracy. Because the signals considered here are ideally sparse, the numerical results of the CGD algorithm can reach very high accuracy, leading to a noticeable gap compared with the circuit results. For real-world signals with non-ideal sparsity and various noise sources, such as ECG signals, this gap is expected to be smaller. The convergence speed of the CGD algorithm may vary with different data types and signal lengths; however, an adaptive stopping criterion can be incorporated by monitoring the ${\mathrm{L}}_1$-norm objective or recovery accuracy. This ensures that the iterations automatically terminate once the performance stops improving.

After this proof-of-concept hardware demonstration, we further investigated the dynamic characteristics and scalability of the proposed AMC circuits to explore their potential in more complex applications. First, we analyzed the dominant poles (derived in Supplementary Note 3) under varying feedback constant $c$, gain bandwidth products (GBWP) of OAs, and matrix sizes, thereby providing a theoretical proof of the convergence speed (Supplementary Fig. 7). Then, we conducted Monte Carlo circuit simulations in Simulation Program with Integrated Circuit Emphasis (SPICE) to validate the analytical conclusion (Supplementary Fig. 8). As detailed in Supplementary Note 4, the GBWP of the OAs plays a crucial role in convergence speed, whereas the matrix size has little impact, this observation is consistent with our small-scale PCB experiments in Supplementary Fig. 5, suggesting that larger matrices are preferable due to their contribution to faster overall computation in CS recovery.

Simulation of the large-scale dataset and benchmarking

To demonstrate the capability of the proposed CS recovery method, we further applied it to various types of signals in SPICE simulation. A larger MCA was assumed to map a larger matrix A_64×128, which is available in the state-of-the-art RRAM technology. A high GBWP OA model was used for fast convergence (Supplementary Fig. 9).

First, we demonstrated the CS framework for ECG signal analysis using the MIT-BIH Arrhythmia Database.³⁵ For this test, the original 2560-point data dataset was divided into 20 segments of 128 points each to match the size of the MCA (Fig. 4a). Each segment was then compressed using a Gaussian-distributed random matrix $\mathit{\Phi }\in {\mathbb{R}}^{64\times 128}$ to obtain the compressed signal $\mathbf{y}$ with a 50% compression ratio (Fig. 4b). Next, a matrix $\mathbf{A}$ = $\mathit{\Phi }\mathit{\Psi }$ was mapped onto three MCAs with a conductance range of 2–30 μS,³⁶ where a discrete wavelet transform (DWT) matrix was used as the sparse basis $\mathit{\Psi }$ (Supplementary Fig. 10). The sparse signal y was converted to input voltages within the range of ±0.2 V with a unit of 33 mV. Note that it is critical to choose an appropriate input voltage unit to keep the output in the safe range. Here, we have confirmed that 33 mV is small enough with the expected amplitude range of ECG signal. For larger matrix size and different signals, we can also connect a clamp diode between ground and the output of OA to prevent unintended conductance change of MCAs, as implemented in our PCB experiments (see Methods). Additionally, to obtain simulation results more consistent with the real situation, we also considered various nonidealities in the hardware, including quantization effects of ADC/DAC, transmission noise of introduced $\mathbf{y}$, and MCAs nonidealities such as wire resistance, parasitic capacitors, conductance mapping errors, which are summarized in the Supplementary Note 5.

Fig. 4. SPICE simulation results of ECG signals and images with large matrix size of 64×128.

a The original 2560-point ECG compared with the hardware recovery result. b 50% compressed signal $\mathbf{y}$. c Evolution of sparse coefficient $s$ of one 128-point segment of ECG signal with algorithm iterations and adaptively variable step size $\epsilon$. d Final recovered results (blue line) of sparse coefficient (top) and time domain signal $\mathbf{x}$ (bottom) compared with ideal value (red dashed line). e Recovery performance of hardware compared with the numerical simulation results in software. f Summarized influence of various nonidealities on recovery accuracy. g CS recovery result of the image after 15 iterations, using the same circuit model as that used for the ECG signal recovery. h The impact of MRI time $T_r$ (top) and RSP time $T_p$ (bottom) on overall recovery performance. i A brief comparison of time consumption of MRI and RSP for one 128-point segment of ECG and image signal recovery.

Figure 4c shows the recovered sparse coefficient $\mathbf{s}$ of one of the segments (128 points, indicated by a square in Fig. 4a) over 20 iterations using the adaptive annealing strategy of step size $\epsilon$: starting from ${\epsilon }_0$= 0.12 and adaptively shrinking to 0.015. The top panel of Fig. 4d shows the reconstructed $\mathbf{s}$ of the final output, i.e., ${\mathbf{s}}^{\left(\mathbf{20}\right)}$, arranged in the order of the initial indices. The bottom panel of Fig. 4d compares the original signal $\mathbf{x}$ (red dashed line) and the recovered signal $\mathbf{x}$ (blue line) ($\mathbf{x}=\mathit{\Psi }\mathbf{s}$), showing good agreement between them. Figure 4e compares the NMSE and RSNR values obtained by the circuit (dashes) and numerical simulation (lines). The circuit recovery achieves an RSNR of 18.79 dB after 20 iterations, which is about 2.9 dB lower than the numerical simulation results. This performance gap arises from various hardware nonidealities. By progressively incorporating these effects, a clear stepwise degradation in RSNR performance is observed (Supplementary Note 5 and Figs. S11–S15), as summarized in Fig. 4f. The dominant sources of performance degradation are identified as quantization effects and transmission noise, which provide guidance for further optimization when applying the proposed hardware system to large-scale chips and practical applications. In addition, we tested the performance using different Gaussian-distributed random matrices (Supplementary Fig. 17) and different sizes of random matrices (Supplementary Fig. 18), which further demonstrate the applicability and robustness of the proposed recovery method.

Additionally, we also tested the CS framework for a sample image of Mona Lisa based on the aforementioned noise and nonidealities model. As illustrated in Supplementary Fig. 19, the original 256 × 256 image was divided into 16 × 32 blocks, each containing 16×8 pixels. Each block was then expanded into a 128 × 1 vector, which was compressed by 50% using a Gaussian-distributed random matrix $\mathit{\Phi }\in {\mathbb{R}}^{64\times 128}$. For image recovery, the discrete cosine transform (DCT) matrix was used as the sparse basis $\mathit{\Psi }$ (Supplementary Fig. 20), and 15 iterations were performed, with the same step size settings as ECG experiments. Figure 4g compares the original and recovered images. The magnified region highlights a single block and shows the amplitudes of the 128-pixel segment within that block. More results for other natural images are also given in Supplementary Fig. 21. The recovered images closely match the original images, and the hardware result demonstrates a 1.83–5.61 dB degradation from the numerical simulation in software.

The example outputs of the MRI and RSP operations demonstrate that they need only tens of nanoseconds to obtain a stable output (Supplementary Fig. 16). To evaluate the time consumption of AMC circuits, we first set the RSP time to a sufficiently large value $T_{\mathrm{p}}$ = 10 μs and swept MRI time $T_{\mathrm{r}}$ and using the RSNR of the overall ECG signals as the evaluation metric for different time lengths. The results in the top panel of Fig. 4h indicate that it’s accurate enough when $T_{\mathrm{r}}$ = 100 ns. Similarly, we then determined the optimal RSP time,$T_{\mathrm{p}}$ = 80 ns, while $T_{\mathrm{r}}$ = 100 ns (Fig. 4h, bottom panel). Considering the about 28.3 ns for peripheral circuits in each iteration, which will be detailed discussed in Supplementary Note 6, the required times for each MRI and RSP are evaluated as 128.3 ns and 108.3 ns, respectively. Here, the MRI is performed only once, whereas the RSP is executed repeatedly over multiple iterations. As a result, the average time consumption per sample for ECG and image signals is presented in Fig. 4i, suggesting that the iterative RSP computations dominate the majority of time and energy consumption. This overhead can be further reduced by incorporating event-driven concepts, which will be discussed in the next section.

Event detection and event-driven recovery

In some detection-oriented applications, the primary goal of data acquisition is to detect specific events, such as arrhythmia detection in long-term cardiac monitoring and human face detection in video surveillance (Fig. 5a). In such cases, sensors generate massive amounts of data over long durations, but only a small fraction of specific signals is of primary interest, while the majority of normal signals are uninformative. Therefore, reconstructing all compressed signals is highly inefficient.

Fig. 5. Example of event-driven recovery for ECG and Image signal.

a Examples of two dataset: ECG signals containing normal and arrhythmic types, and images containing human face and non-face scenes. b Example of event-driven CS recovery for arrhythmia and human face detection. After the MRI operation on all compressed signal segments $y$, an MLP detects segments containing relevant events, and only those segments are fully recovered for further processing. c Detection accuracy of arrhythmia and human face by using the MLP with different inputs from the CS workflow. d Energy efficiency comparison of proposed CS recovery with state-of-the-art ASIC and RRAM designs.

As discussed above, the proposed CGD recovery algorithm first computes the ${\mathrm{L}}_2$-minimization solution $\mathbf{q}$ as the initial point by the MRI operation. Although $\mathbf{q}$ is not identical to ${\mathbf{s}}^{\mathit{*}}$, it still retains the feature information of the raw signal, enabling it to be used for event detection prior to the RSP iterations. This allows us to establish an event-driven recovery framework that follows a brain-inspired strategy to improve time and energy efficiency. Analogous to the thalamus functioning as a central relay, the framework dynamically filters and gates incoming sensory signals, allowing only behaviorally relevant information to reach the cortex.³⁷

The proposed event-driven CS recovery framework within the CGD recovery algorithm is shown in Fig. 5b. Here, event detection processing, i.e., matrix-vector multiplication, can be performed by using additional MCAs, which determine whether q contains the target features. If the target features are detected, the subsequent iterative RSP operation is executed.

For simulation-based demonstration, we divided an ECG dataset into normal and arrhythmic heartbeat signals from the MIT-BIH ECG database, and an image dataset consisting of human face images and non-face images from Labeled Faces in the Wild (LFW) dataset and CIFAR-10 dataset,^38,39 whose examples are shown in Fig. 5a. ECG signals have a length of 128 for each heartbeat, while images are of size 16 × 16 and need to be divided into two segments. As shown in the subfigures of Fig. 5b, $\mathbf{q}$ preserves the basic structure and key features of ${\mathbf{s}}^{\mathit{*}}$, which is sufficient to enable early detection of arrhythmia and human face identification. For the event detection processing, we used a pre-trained 128 × 64 × 2 multi-layer perceptron (MLP), which can be implemented with two additional MCA modules.

Figure 5c compares the event detection accuracy of arrhythmia and human face through the MLP. The training details over 1000 epochs are provided in Supplementary Fig. 22. The compressed signal $\mathbf{y}$ achieved only 86.05% and 88.3% of accuracy, which is insufficient for accurate detection. Whereas, the MRI output $\mathbf{q}$ could achieve high accuracy comparable to the fully recovered signal ${\mathbf{s}}^{\mathit{*}}$, confirming the validity of moving the detection process from after the full recovery to the intermediate stage of recovery. We also tested the MLP in the SPICE simulations, which showed only 0.5% and 0.45% accuracy degradation when detecting arrhythmia in ECG signals and human face in images using $\mathbf{q}$, respectively, compared with the trained-model baseline (Supplementary Note 6). As the RSP iterations consume the majority of time and energy, the proposed event-driven approach significantly reduces the overall recovery cost, since valuable signals typically comprise only a small fraction of the total signal stream over a long duration.

Note that training the MLP for event-detection requires signal data generated from a certain Gaussian-distributed random matrix $\mathit{\Phi }$. This means that it would need to be retrained when the $\mathit{\Phi }$ changes or when the signal type differs. Therefore, once the random matrix $\mathit{\Phi }$ is selected, it should be unchanged for a certain period and update it intermittently, as in many practical CS hardware implementations, $\mathit{\Phi }$ is predefined and fixed to enable efficient circuit realization.^40–43 With the fixed random matrix and accordingly pre-trained MLP, the on-device processing pipeline, including event detection (inference) and reconstruction, can be executed at high speed for real-time signal recovery. We acknowledge that keeping $\mathit{\Phi }$ fixed over an extended duration can reduce the one-shot encryption randomness of CS and thus introduces a potential security issue, highlighting the inherent limits of the embedded security benefit in our framework. To comprehensively benchmark our proposed method, we evaluated the energy consumption of the overall system, which includes the MCA-based AMC circuit, digital peripheral circuit, ADC/DAC modules, and MLP. Further details are provided in Supplementary Note 6. Figure 5d compares the energy efficiency of our proposed method with other state-of-the-art designs. Here, we divide the event-driven recovery process into two modes (see Fig. 5b).

The first is the all-on mode, which follows the conventional CS recovery process and performs recovery after event detection. We summarize the detailed benchmarking results in Table 1. Compared with the digital ASIC implementation and latest RRAM-based solutions, our proposed method has better recovery accuracy and faster speed while maintaining better energy efficiency. Specifically, our method achieved 4.8× and 2.85× higher energy efficiency than the state-of-the-art ASIC design for ECG signals and RRAM design for images,^7,24 respectively. Our method also achieved speed of 73.14 MS/s for image recovery, suggesting that the throughput is compatible with the real-time recovery of 30 Hz 1080 P video (≈62.2 MS/s). The energy breakdown of MRI and RSP is shown in Supplementary Fig. 23a, indicating that iterative RSP accounts for the majority of total energy consumption. The normalized energy breakdown of each RSP iteration is also given in Supplementary Fig. 23b and compared with GPU, ASIC and RRAM implementation of AMP algorithm (Supplementary Fig. 24).²⁵ These results suggest that, in such implementations, even when the MVM is aggressively accelerated and accounts for negligible fraction of the total energy, the overall energy efficiency can be higher than that of GPU and ASIC implementations; however, the total energy consumption may still be largely dominated by non-MVM peripheral operations. In our work, although the AMC circuit for MRI and RSP consumes more energy than an MCA-accelerated MVM alone due to multiple OAs, the overall energy efficiency benefits from substantially simplified peripheral operations enabled by our proposed CGD algorithm (Supplementary Note 6). Another related work following a similar idea is a full analog implementation that eliminates iterative peripheral operations altogether,²⁴ which also yields a significant improvement in energy efficiency.

Table 1.

Benchmark of all-on mode fully recovery

Reference		Hardware	Algorithm	Size(M×N)	Speed	Accuracy	Energy Efficiency
ECG	BioCAS 1647	ASIC	vOMMP	64 $\times$128	232 us(552 kS/s)	—	—
	JSSC 168	ASIC	OMP	58 $\times$128	330 us(388 kS/s)	RSNR = 15 dB	33nJ/S
	JSSC 197	ASIC	SE-SP	64 $\times$128	68 us(1.88MS/s)	RSNR = 15 dB	72.5nJ/S
	ISCAS 2519	RRAM	BPDN	8 $\times$16	1 us(16 MS/s)	PSNR = 20.1 dB	—
	This Work	RRAM	CGD	64 $\times$128	2.29 us(55.89 MS/s)	RSNR = 18.79 dB	6.87nJ/S
Image	JETCAS 1248	Flash	LCA	64 $\times$128	30 us(4.27 MS/s)	NMSE = 0.05	691.6nJ/S
	IEDM 1723	PCM	AMP	192 $\times$256	30.6 us(8.4 MS/s)	NMSE = 0.011 (House)	—
	Nat. Nano. 1722	RRAM	LCA	64 $\times$128	15.03 us(8.52 MS/s)	—	—
	Sci. Adv. 2324	RRAM	LCA	64 $\times$128	6.353 us(20.15 MS/s)	NMSE = 0.008 (Monalisa)	14.88 nJ/S
	Natl. Sci. Rev. 2525	RRAM	AMP	128 $\times$256	14.4 us(17.78 MS/s)	PSNR = 31 dB	1292 nJ/S
	This Work	RRAM	CGD	64 $\times$128	1.75 us(73.14 MS/s)	NMSE = 0.003 (House) NMSE = 0.0098 (Monalisa)	5.23 nJ/S

The second is the detection mode, which performs only event detection without recovery. In this case, the overall system energy consumption achieves an additional 9.42× and 7.16× energy efficiency by eliminating RSP iterations than all-on mode, and a total of 45.22× and 20.4× than state-of-the-art methods for ECG signals and images, respectively. In real-world applications, only a very small fraction of the signal contains the information of interest. Taking ambulatory 24-h ECG recordings as an example, only a small fraction of patients exhibits frequent arrhythmia, and these arrhythmias also only occupy a very small fraction of the 24-h recording.⁴⁴ In such cases, the overall energy efficiency performance will be dominated by detection mode, thus achieving a significant energy-efficiency improvement.

Discussion

We propose an energy-efficient CS recovery framework that can be used in energy-constrained edge environments. These gains are primarily attributed to the co-design of a new recovery algorithm and circuit architecture, as well as the efficient implementation of MRI and RSP operations using the MCA-based AMC hardware. In particular, in hardware, efficiency is further improved by optimizing the circuit parameters and the design of the OA model to balance speed and energy consumption. In addition, by incorporating with the adaptive annealing strategy of step size to balance the accuracy and speed, the performance of the proposed system can be further enhanced. Despite the high speed and energy efficiency, there is still an accuracy gap between hardware and algorithm due to the inherent nonidealities of MCAs and peripheral circuits, necessitating further optimal techniques, such as bit-slicing or multi-stage correction, to achieve comparable accuracy with float-point.^20,45,46 Furthermore, we introduced a new concept of selective recovery enabled by feature detection, which is particularly optimized for sparse signal processing such as ECG, allowing unnecessary data reconstruction to be skipped and thereby further improving energy efficiency and real-time responsiveness in edge applications.

Methods

Memristor crossbar array fabrication

The front-end fabrication of transistors with a feature size of 180 nm is first conducted in a commercial CMOS foundry. Then the bipolar TiN/TaOₓ/HfOₓ/TiN memristor is installed on the drain side of the transistor in-house. The 40-nm-thick bottom electrode TiN is deposited on a polished W plug through reactive sputtering. The 10-nm-thick HfOₓ and 50-nm-thick TaOₓ are deposited by atomic-layer deposition. A 30-nm-thick TiN layer is deposited as the top electrode. After deposition of the sandwich structure, the dry etching method was used to pattern the device with a size of 0.5 × 0.5 μm². Finally, the crossbar array is packaged using Quad Flat Pack technology. The transistor gates in each column are connected together to open or close the column.

Hardware experiments setup

High voltage is supplied only to the gates of the columns mapped to the matrix, while the other unused columns remain off. The unused rows in the active columns are kept in a non-forming state to minimize current leakage. AD823 and OPA2177 are used for OA1 and OA2, respectively. There are two Schottky diodes paralleled in the opposite direction between OA’s output and ground to limit the voltage under the threshold voltage of memristor devices and prevent the resistance change, especially for the vibration during power on. The entire measurement setup is controlled by a host computer. The input signal of AMC circuits is generated by 14-bit DAC AD9767 while the signal acquisition circuit uses 14-bit AD9253, and UNI-T 7204X oscilloscope is used for intermediate signal measurement. Additionally, the addition, subtraction, and sign functions of vector elements are executed within the Python control software of the host computer.

Author contributions

M.D. and Y.W. conceived and designed the research. M.D., K.M.K. and H.X. designed the experiment. M.D., Y.W., L.S., L.L. and A.X. developed and measured the circuits. M.D. and L.S. designed the simulation code. M.D., N.X. and Z.L. wrote the original draft. Y.W., Q.L. and K.M.K. revised the draft and supervised the work. All the authors reviewed and approved the final manuscript.

Peer review

Peer review information

Nature Communications thanks Hong Wang, Suin Yi and the other anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Data availability

The source data generated in this study are provided in the Source Data file with this paper. Additional data related to this paper can be requested from the authors. Source data are provided with this paper.

Code availability

The simulation codes of proposed CGD algorithm are available at https://github.com/taozihu24/CGD.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-72401-z.