Starvation effect enables computing and memory functions in semiconductor-free fibres

Abstract

Fibre-based switchable devices hold great promise for textile-integrated low-power computing and high-density data storage. However, their development has been hindered by the reliance on semiconductor materials, which demand specialised patterning techniques to achieve nanoscale precision on highly curved fibre surfaces, substantially increasing structural complexity and fabrication cost. Here, two semiconductor-free four-terminal switchable ionic fibres (FSIFs) enabled by a nanoscale-level ion starvation mechanism are presented. This design eliminates the scaling constraints associated with semiconductors, maintaining high device functionality even when feature sizes are relaxed to the sub-millimetre scale. Therefore, the FSIFs are compatible with cost-effective, high-throughput commercial textile manufacturing processes and offer two switching capabilities: binary volatile with a 15:1 ON/OFF ratio at 1 mV and continuous non-volatile with a 2.6:1 ratio between 0.6-1.6 V. These characteristics enable low-power computing, multi-level memory, and extended functions including device control, signal modulation, and neural image recognition, broadening the toolbox for next-generation wearable intelligence.

Fibre-based switchable devices are limited by specialised patterning techniques needed for semiconductor materials. Here, the authors two semiconductor-free four-terminal switchable ionic fibres enabled by a nanoscale-level ion starvation mechanism.

Introduction

As wearable technologies progress toward textile-level intelligence, fibre-based switchable devices, particularly ionic systems such as organic electrochemical transistors and electrolyte-gated field-effect transistors, are emerging as key enablers for computation and data memory within textiles^1–3. Beyond their intrinsic low-power characteristics, these ionic devices naturally meet the demands of intelligent textiles, offering breathability, skin conformability, and biocompatibility for seamless integration into daily wear^4–12.

The future prospects of fibre-based ionic switchable devices are expected to mainly focus on two emerging areas for textile-based systems: computing and data storage. For computing applications, particularly logic operations, achieving clear and stable switching characteristics is critical to ensure reliable device response to input signals, accurate signal discrimination, and robust edge data processing^13,14. Additionally, minimising the operating or threshold voltage of devices is key, as it enhances device controllability, reduces energy consumption per switching cycle, and improves system endurance under high-frequency operation¹⁵. Beyond computing performance, the demand for high-density data storage in ionic devices continues to grow. Most reported ionic data storage devices, such as ionic transistors and capacitor-memristor series units, typically support only two stable storage states (charged/discharged states or high/low resistance states), restricting their capacity to binary encoding. Considering the stringent low-power requirements of wearable devices, expanding the number of stable storage states while achieving zero static power consumption has become a major research direction^16,17. Multilevel storage can improve processing efficiency and increase storage density. For instance, a four-level device can store twice as much information as a two-level storage counterpart.

In conventional switchable devices, the incorporation of semiconductor layers is inevitable for achieving switching functionality^18–20. This necessity, however, makes their performance and reliability constrained by semiconductor-related scaling effects, including the interfacial barriers and Debye screening effects unique to ionic switchable devices at the semiconductor-electrolyte interface, as well as the general constraints imposed by semiconductor channel dimensions and semiconductor-dielectric film thickness that commonly limit both ionic and non-ionic switchable devices^21–23. To ensure the effective regulation of carriers in semiconductor layers during computing and data storage operations, the critical feature sizes have to be confined to the micro- to nano-scale range with limited tolerances^13,24–32. Yet, conventional fibre fabrication techniques, including dip coating and electrospinning, lack the precision required for fine-scale patterning. Achieving high-resolution thin-film patterns on fibres thus requires specialised, fibre-compatible equipment, which increases cost, limits design flexibility, and complicates processing. In addition, semiconductor layers are prone to delamination and cracking during fabrication and daily large bending, which can lead to faster device degradation^33–36. An alternative approach is to adopt all-gel or all-droplet-based architectures for all functional components, including the semiconductor layers. Such designs leverage all-fluid domains to mitigate interfacial mismatch, facilitate ion penetration and transport, and enable fabrication without wafer-based patterning. However, challenges remain: semiconductors containing liquid phases typically exhibit inferior intrinsic properties compared to solid thin films, while droplet-based systems suffer from morphological instability due to rapid evaporation, compromising long-term device reliability^37,38.

To address these challenges, we propose a semiconductor-free fibre-based ionic switchable device, namely the four-terminal switchable ionic fibre (FSIF), designed to meet the dual requirements of low-power wearable computing and high-density data storage while simplifying fabrication. The key breakthrough of the FSIF is the complete elimination of the semiconductor layer and its associated multi-layer solid-film structures. By integrating gating and channel functions within a single aqueous electrolyte, it achieves semiconductor-free transistor-like switching and state retention through an electric-field-mediated Faradaic or non-Faradaic bulk ion starvation effect. This design allows rapid, uniform, and long-range ion transport in a homogeneous electrolyte system, effectively overcoming semiconductor-related scaling effects and mismatches at multi-layer interfaces. Thus, the FSIF offers relaxed sub-millimetre feature dimensions, with a simple structure compatible with standard textile manufacturing processes. Two types of FSIFs are demonstrated. The adsorptive switchable ionic fibre (ASIF) exhibits a stable switching ratio of 15:1 and operates at an ultra-low gate voltage (~1 mV), significantly lower than that of various reported planar and fibre-based transistors, making it ideal for low-power logic computing, signal modulation, and device-level control. The redox switchable ionic fibre (RSIF), on the other hand, enables non-volatile multi-level switching within a voltage window of 0.6–1.6 V, achieving a maximum ON/OFF ratio of 2.6:1. This allows long-term data storage with zero static power consumption, while offering the additional advantage of continuously tunable states beyond conventional non-volatile memory such as memristors and phase change memory, supporting neural network architectures for in-memory computing. This study presents a previously unexplored class of semiconductor-free switchable device systems, demonstrating that regulating the bulk ion concentration solely within a single gel enables complex fibre intelligence, thereby enriching the technological toolbox with simple fabrication for next-generation wearable systems.

Results

Design strategies for semiconductor-free ON/OFF switching

We began by establishing a physical model of the ion starvation effect, forming the theoretical foundation for the design of two principal classes of four-terminal switchable ionic fibres (FSIFs): the adsorptive switchable ionic fibre (ASIF) and the redox switchable ionic fibre (RSIF) (Fig. 1a, b and Methods Note: Theoretical model of adsorptive starvation for ASIF modulation; Theoretical model of redox starvation for RSIF modulation). In the ASIF design, the device integrates an external gate capacitor (g-cap) and an internal channel capacitor (c-cap), both immersed in a common hydrogel electrolyte composed of 1 M LiCl in poly(vinyl alcohol) (LiCl-PVA), forming a parallelly coupled internal fibre circuit. The g-cap consists of multi-stranded internal carbon nanotube (CNT) fibres paired with an external CNT film, while the c-cap comprises two parallel single-stranded CNT fibres, selected for their high electrical conductivity, mechanical robustness, and flexibility (Supplementary Figs. 1, 2)^39,40. The RSIF employs an external gate Zn-I₂ battery (g-bat) and an internal channel battery (c-bat), operating in a unified hydrogel electrolyte of 1 M ZnSO₄ carboxymethyl cellulose sodium (ZnSO₄-CMC). The g-bat comprises a single-stranded Zn wire as the internal electrode and an external CNT film loaded with I₂ (CNT-I₂) as the counter electrode. The c-bat is configured as a symmetric battery with two parallel single-stranded CNT fibres serving as electrodes (Supplementary Fig. 3)^41,42. Switching in FSIFs is triggered by applying a bias voltage to the gate, which induces an ion starvation effect in the electrolyte. This effect drives a reversible transition of the channel between high-capacitance/high-capacity and low-capacitance/low-capacity states (Fig. 1c–f). Although FSIFs exhibit transistor-like switching, their underlying mechanism is fundamentally distinct. The operation relies entirely on mobile ions within the electrolyte, which simultaneously act as both the active species initiating the switching process and the principal charge carriers in the channel. In contrast, organic electrochemical and electrolyte-gated transistors use ions only as modulators for electronic carriers within a semiconductor layer. Structurally, the FSIF integrates the gate and channel within a continuous aqueous electrolyte, eliminating the semiconductor layer and its associated solid-liquid and solid-solid interface^4,5. As a result, during ion starvation-regulated switching, ion motion is no longer hindered by interfacial barriers or relaxation delays. The ions maintain spatial uniformity throughout the electrolyte, enabling continuous, field-driven bulk transport. Consequently, the spatial decay of ion migration under gate bias is minimised, allowing the gate’s influence to propagate uniformly over long distances within the electrolyte. This design permits the core structural dimensions of the FSIF, including the gel electrolyte and source-drain distance, to be scaled up to the millimetre range, far exceeding the nanometre-scale constraints of conventional ionic transistors. With this relaxed size requirement, the entire FSIF can be fabricated using conventional textile manufacturing methods such as coating and film wrapping. This scalability provides enhanced flexibility in device design and enables cost-effective, large-scale production compatibility (Supplementary Figs. 4 and 5a, b).

Fig. 1. Design strategies of FSIF architecture.

a Structural design of FSIFs, including ASIF and RSIF architectures integrated into smart textiles. Insets: photo images of the ASIF and RSIF. Scale bar: 10 mm. b Functional applications of FSIF devices. ASIFs enable Boolean logic computation, signal modulation, and device control, whereas RSIFs provide both multi-level data memory and neural network computing. c ON/OFF switching of ASIFs governed by the adsorptive ion starvation effect: (i) no gate bias (V_g = 0 mV) and (ii) applied bias (V_g = 1 mV). d Mechanism of adsorptive ion starvation effect in ASIFs. The process involves non-selective regulation of all ion species, leading to binary, volatile switching of the c-cap. e ON/OFF switching of RSIFs driven by the redox ion starvation effect: (i) discharge during V_g decrease from 1.6 V to 0.6 V, and (ii) charge during V_g increase from 0.6 V to 1.6 V. f Mechanism of redox ion starvation effect in RSIFs. The process selectively regulates the concentration of I⁻ ions, enabling continuous, non-volatile switching of the c-bat. Note: Fig. 1c and e are schematics illustrating the device architecture and operating mechanism, not the actual cross-sectional geometry.

Switching based on adsorptive ion starvation effect

When two electric double-layer capacitors (EDLCs) share a common electrolyte but possess markedly different effective electrode surface areas, a non-Faradaic adsorptive ion starvation effect arises. The defining feature of the ASIF lies in its LiCl-PVA gel-based gate-channel coupling structure, where the gel thickness between the g₁ and g₂ electrodes determines the minimum structural feature of the fibre (Fig. 2a, b). The g-cap, with a much larger effective electrode surface area than the c-cap, intrinsically exhibits higher capacitance and ion conductivity. Together with the electrolyte’s uniform ion migration, these characteristics enable pronounced and stable switching at ultra-low bias. Applying a 1 mV gate voltage induces extensive cation and anion adsorption on the g-cap surface, reducing the concentration of free ions in the electrolyte. Meanwhile, the high ionic conductivity of the g-cap forms a low-impedance ion diffusion pathway between the c-cap electrodes. When a signal is applied to the c-cap, part of the induced current is diverted through this pathway into the g-cap circuit, effectively functioning as an ion bypass analogous to a spillway. With gate bias, the c-cap cyclic voltammetry (CV) capacitance drops to about 6.7% of its initial value (Supplementary Figs. 5c, d and 6–10), corresponding to an ON/OFF ratio of ~15:1 (Fig. 2c, d). In the OFF state, electrochemical impedance spectroscopy (EIS) reveals an order-of-magnitude increase in impedance, confirming that ion starvation suppresses the local ion concentration (Fig. 2e). Upon applying a 1 mV gate voltage, the g-cap exhibits an immediate ion current response with a sub-millisecond delay, followed by rapid saturation (Supplementary Fig. 11). During cyclic gating, ion adsorption at the g-cap under V_g = 1 mV generates a charging current, while removal of the bias triggers ion desorption and a reverse discharge current (Fig. 2f). The rapid and stable cyclic response indicates no parasitic reactions occur and confirms high ion mobility across millimetre-scale distances. Multiple ASIF c-cap units can be interconnected in series or parallel arrays. Each unit is independently addressable by its own gate voltage, enabling selective modulation of the total array capacitance (Fig. 2g). In the series configuration, a single OFF-state unit significantly reduces total capacitance, switching the array OFF; the system remains ON only when all units are in the ON state. In the parallel configuration, the array maintains a measurable signal as long as at least one unit is ON, while full OFF occurs only when all are OFF. Based on these behaviours, Boolean logic operations analogous to transistor circuits can be realised by controlling the switching states of individual c-caps in various circuit architectures (Fig. 2h, i).

Fig. 2. Switching driven by ion starvation effect within the ASIF.

a Schematic illustration of the operating mechanism of ASIFs, showing the g-cap for gate control and the c-cap for status readout. b SEM image of an ASIF. The LiCl-PVA gel between the g₁ and g₂ electrodes forms the gate-channel parallel-coupling medium, with a characteristic electrode spacing of $\lambda$ ≈ 750 μm. Scale bar: 500 μm. c Comparison of CV characteristics between the g-cap and c-cap. d CV curves of the c-cap in the ON state and OFF state, obtained by cyclic scans from −0.3 V to +0.3 V at 100 mV s⁻¹, highlighting the binary switching behaviour. e EIS of the c-cap in both ON and OFF states, revealing the ion starvation effect. f Cyclic charge-discharge behaviour of the g-cap under repeated biasing, demonstrating stable gating functionality. g Schematic diagrams of ASIF-based logic circuits configured in series c-caps for NOR logic and in parallel c-caps for NAND logic. h CV responses of ASIF NOR gates under different input conditions, measured at a scan rate of 100 mV s⁻¹. i CV responses of ASIF NAND gates under corresponding input conditions.

Switching based on Redox Ion Starvation Effect

By introducing redox-active materials from aqueous metal-halogen battery systems into the gate electrodes, the ion starvation effect was extended into a Faradaic-controlled regime. The metal-halogen electrochemical system enables reversible, high-concentration modulation of halide ions via the dynamic equilibrium between free halide anions (I⁻, Br⁻, Cl⁻) and their molecular or polyhalide counterparts. The Zn-I₂ configuration was selected for gating because of its straightforward fabrication, high electrochemical stability, and minimal side reactions during I⁻ to polyiodide conversion (Fig. 3a). When the gate voltage (V_g) of the g-bat decreases from 1.6 V to 0.6 V, reduction of lower-valent iodine species such as I₃⁻ and I₅⁻ releases large quantities of I⁻ ions into the electrolyte, thereby increasing the concentration of electroactive species. The CV peak current, proportional to this concentration, progressively increases and reaches its maximum at 0.6 V, indicating capacity enhancement. Conversely, during charging as V_g rises from 0.6 V to 1.6 V, I⁻ ions are oxidised to polyiodides and withdrawn from the electrolyte, causing gradual ion depletion and a systematic reduction in CV peak current to its minimum at 1.6 V, signifying capacity suppression. This process constitutes the redox ion starvation effect (Supplementary Fig. 5e, f). Because the g-bat and c-bat share a continuous electrolyte, local I⁻ variations induced by the g-bat propagate rapidly via field-driven migration, enabling the c-bat to respond almost instantaneously during CV measurements. Using the peak CV current as reference, the maximum current at V_g = 1.6 V is only 38.7% of that at 0.6 V, corresponding to a switching ratio of ~1:2.6, while impedance changes by less than an order of magnitude (Fig. 3b, c). This confirms that redox regulation in RSIFs primarily targets the I⁻/I₃⁻/I₅⁻ species specific to the Zn-I₂ system, with minimal influence on other ions such as Zn²⁺ and SO₄²⁻. As a result, ion transport pathways in the c-bat remain sufficiently populated to sustain high overall ionic conductivity. Both simulation and experimental results demonstrate that during constant-current charge-discharge of the g-bat, the CV peak current of the c-bat varies linearly with V_g, in agreement with the Randles-Ševčík model (Fig. 3d–f). This establishes a one-to-one correspondence between the c-bat state and gate voltage, confirming controlled and reversible redox-driven modulation.

Fig. 3. Switching driven by the ion starvation effect within the RSIF and performance comparison with the ASIF.

a Schematic diagram illustrating the working mechanism of RSIFs. The cyclic CV from −0.5 V to +0.5 V at a scan rate of 100 mV s⁻¹ is used to evaluate the capacity changes of the c-bat in its ON and OFF states. b CV curves of the c-bat in the fully-ON state (V_g = 0.6 V) and fully-OFF state (V_g = 1.6 V). c EIS of the c-bat in both fully-ON and fully-OFF states. d Schematic diagrams of RSIF-controlled circuits. e Cyclic charge-discharge curves of the g-bat. f Linear switching characteristics of the c-bat are regulated by the g-bat. g Wearable use of FSIF on curved surfaces and finite element analysis. Significant stress and strain are concentrated at the interface between the electrodes and the gel. Scale bar: 10 mm. h In-situ Raman spectroscopy of the gel for (i) ASIF and (ii) RSIF during switching. Results of the ASIF gel show that no reactive groups are generated during the adsorptive ion starvation process, while those of the RSIF gel reveal that the concentrations of polyiodides and I⁻ ions are significantly regulated during the redox ion starvation process. i (i) ON/OFF ratio of ASIF under multiple switching cycles and (ii) during large deformation bending. j (i) ON/OFF ratio of RSIF under multiple switching cycles and (ii) during large deformation bending.

Mechanistic comparison of ion-starvation switching dynamics

The differences in ion-driven kinetics between ASIF and RSIF dictate their divergences in switching mechanisms, response dynamics, and functional behaviours, as well as determining their suitability for distinct application landscapes (Fig. 3g). The ASIF operates through electric-double-layer formation, a non-Faradaic process that enables non-selective ion regulation. Its g-cap indiscriminately adsorbs and shunts all ion species within the electrolyte, leading to significant suppression of overall admittance. This mechanism facilitates millisecond-scale switching with a high ON/OFF ratio. Upon V_g removal, ions rapidly desorb from the electrode surface, allowing the c-cap to promptly recover its highly conductive state. As a result, the c-cap exhibits a normally-ON configuration and volatile binary switching characteristics. In contrast, the RSIF operates via Faradaic charge-transfer reactions, exhibiting high redox-targeting selectivity for I⁻ ions in the Zn-I₂ electrochemical system. Its g-bat employs smooth Zn electrodes with low specific surface area, resulting in inherently weak capacitive characteristics and negligible global ion adsorption or shunting. Even under a full OFF state (V_g = 1.6 V), the c-bat retains a high concentration of mobile ions, leaving the bulk impedance largely unaffected. Thus, the switching behaviour manifests predominantly through modulation of the CV peak current. Owing to its Faradaic mechanism, the RSIF exhibits comparatively slower switching kinetics. A full ON-OFF cycle requires approximately 150 seconds under a constant current operation of 3 mA. Notably, due to the continuous and non-spontaneous nature of the underlying reaction, the I⁻ concentration remains stable after V_g removal, conferring non-volatile behaviour of the c-bat. This feature allows the device to retain its gate-bias-defined capacity with negligible static power consumption, while also supporting analogue-style continuous tuning functionality (Fig. 3h). Both types of devices exhibit excellent switching stability. The ASIF device employs CNTs as current collectors, endowing it with excellent electrochemical stability. Its g-cap and c-cap exhibit robust rate performance across varying scan rates, operating voltage windows, and charge-discharge conditions, while maintaining a stable high ON/OFF ratio during cyclic switching (Supplementary Figs. 12–14). Benefiting from the highly reversible redox chemistry of the Zn-I₂ battery system, the RSIF device similarly sustains a uniform switching ratio throughout multiple cycling tests (Supplementary Figs. 15–19). Finite element analysis reveals that stress and strain occur between the gel and electrodes due to mechanical mismatch during large-deformation bending; nevertheless, experimental tests confirm both types of devices exhibit excellent mechanical and electrical stability, which is attributed to the robust interfacial adhesion between the gel electrolyte and electrodes as well as the gel’s inherent flexibility and ductility, thereby rendering them highly suitable for a wide range of wearable application scenarios (Fig. 3i, j).

Ultra-low-voltage boolean computing

The ASIF exhibits stable and rapid binary capacitance switching characteristics and operates at low gate voltages, making it well-suited for low power-consuming Boolean logic operations (Fig. 4a). A fundamental logical definition framework was first established: at the input, a gate voltage of V_g = 1 mV is defined as a logical “1”, while V_g = 0 mV corresponds to a logical “0”. At the output, the state of the c-cap is defined as logical “1” when it exhibits a high capacitance (ON state), and as logical “0” when it exhibits a low capacitance (OFF state) (Supplementary Figs. 20a, b and  21). Building on the above logical framework, three fundamental types of ASIF-based logic circuits were developed, enabling transistor-like Boolean operations including NOT, NOR, and NAND. In the single NOT configuration, the c-cap remains in the ON state 1 at V_g = 0 mV, whereas it switches to the OFF state 0 at V_g = 1 mV. In the series NOR configuration, the two c-caps are connected in series, so the equivalent capacitance is jointly determined by both elements. When V_g,1 = V_g,2 = 0 mV, both c-caps remain in the ON state, and the equivalent capacitance stays high, which is defined as the logical output 1 (Supplementary Fig. 22a). Once either V_g,1 or V_g,2 is switched to 1 mV, one c-cap turns to the OFF state with low capacitance. In a series connection, the overall equivalent capacitance is dominated by the smaller capacitance; therefore, as soon as one c-cap becomes low, the total capacitance must drop, and the output is accordingly assigned as logic 0 (Supplementary Fig. 22b–d). In the parallel NAND configuration, the two c-caps are connected in parallel, and the total capacitance is approximately the sum of the two. When V_g,1 = V_g,2 = 0 mV, both c-caps are in the ON state, giving the maximum total capacitance and a logical output 1 (Supplementary Fig. 22e). When either V_g,1 or V_g,2 is 1 mV, one c-cap switches to OFF while the other remains ON; the total capacitance is reduced to roughly half of the fully ON case but still clearly higher than the fully OFF case. To preserve the logical completeness of the NAND operation and maintain consistency with its truth table, this half ON capacitance level is predefined and categorised as the logical output 1 (Supplementary Fig. 22f, g). When V_g,1 = V_g,2 = 1 mV, both c-caps are OFF, leading to the minimum total capacitance and a logical output 0 (Supplementary Fig. 22h). Leveraging the principle that the capacitance of a capacitor is proportional to its conductance for AC signals, we established an AC signal-based logic computing framework using ASIFs. For example, when a 5 V, 100 Hz/100 kHz AC signal is applied to the c-cap of the ASIF using a function generator, and a gate voltage of V_g = 1 mV is applied to the g-cap, the c-cap is switched to the OFF state due to the adsorptive ion starvation effect. As a result, its AC conductivity is significantly suppressed, and the output signal amplitude decreases by more than 95.0% compared to the case without gate voltage. Both simulations and experimental results demonstrate that a smaller impedance ratio between g-cap and c-cap (Z_g/Z_c) coupled with a larger intrinsic capacitance of g-cap leads to more effective suppression of AC input signals (Fig. 4b, c; Supplementary Fig. 20c–e). Based on these findings, an ASIF-based AC input/output logic module capable of performing NOT, NOR, and NAND operations was constructed. The corresponding truth tables are summarised in Supplementary Tables 1 and 2. The system maintains rapid dynamic response during logic input updates, exhibiting negligible propagation delay (Fig. 4d). NOT, NOR, and NAND gates form the fundamental building blocks of Boolean logic. More complex logic circuits can be constructed using combinations of these basic modules, providing scalability for ASIF-based logic operations.

Fig. 4. ASIF-based logic computing and circuit control via adsorptive ion starvation effect.

a Circuit schematics of ASIF-based combinational logic controllers implementing NOT, NOR, and NAND operations, in which an ASIF-based logic controller drives external loads through controlled devices. b Transmission of AC signals (5 V, 100 Hz) through a single ASIF under different gate biases, showing distinct modulation of the output waveform. c Simulation of the influence of the g-cap’s designed impedance and capacitance on the switching characteristics of the ASIF, highlighting the transition from ASIF to RSIF regimes. d Time-resolved input/output responses of ASIF-based NOT, NOR, and NAND circuits, demonstrating robust Boolean logic operations through AC signal gating. e Schematic illustration of the thermal drawing process used to fabricate fibre-based photodetectors (FPDs), and corresponding photocurrent responses of an FPD under 532 nm, 40 mW laser illumination (laser ON/OFF). The photocurrent output is dynamically controlled by ASIF devices configured in NAND or NOR logic modes. Logic truth tables and photocurrent responses of the ASIF-controlled FPD under f NAND (left) and g NOR (right) operations, confirming correct logic functionality. h Schematic of the ASIF-controlled rectifier filter module, including the functional generator, diode bridge, resistor, and oscilloscope measurement setup. i Circuit diagram of the ASIF-controlled rectifier filter block, showing integration of a c-cap with the rectifier and load. j Experimental output signals of the rectifier module, comparing the diode-rectified AC.

Circuit modulation and control

Owing to its rapid response and high ON/OFF ratio for AC signal modulation, the ASIF can be further utilised as a logic control switching element in a broader range of analog circuit systems. In an earlier work, we fabricated a high-precision, mechanically robust fibre-based photodetector (FPD) using a thermal drawing process⁴³. The device consists of two electrodes separated by a photoconductive semiconductor core, enabling efficient photoelectric detection. Under constant illumination, the photosensitivity exhibits a strong dependence on the applied voltage, with effective photodetection occurring only when the driving voltage (V_dr) exceeds the threshold voltage (V_th = 2 V) (Fig. 4e). Utilising this characteristic, we developed an FPD logic control circuit based on the ASIF, in which the photo response of the FPD to incident light is indirectly regulated by adjusting the threshold voltage (V_th) during each operation cycle. The FPD was integrated into a circuit comprising parallel voltage-dividing resistors and a series-connected NAND or NOR ASIF module. In the NAND configuration, when both gate voltages (V_g,1 and V_g,2) are set to 0 mV, or when either V_g,1 or V_g,2 is set to 1 mV, the total capacitance of the NAND ASIF c-caps remains in a conductive state. Under these conditions, a sweeping voltage from 0 V to 5 V can generate a sufficient driving voltage (V_dr > V_th) across the electrodes of the FPD, thereby activating the device and inducing a pronounced photocurrent (I_p) in response to incident light. In contrast, when both V_g,1 and V_g,2 are set to 1 mV, the total capacitance of the c-caps switches to a non-conductive state, keeping V_dr below the V_th throughout the sweep. As a result, the FPD remains inactive and does not produce any photocurrent under illumination (Fig. 4f; Supplementary Fig. 23). The NOR configuration operates in a similar manner. The total capacitance of the NOR ASIF c-caps remains conductive only when both V_g,1 and V_g,2 are set to 0 mV, allowing the sweeping voltage to activate the FPD and generate a photocurrent in response to light. If either V_g,1 or V_g,2 is set to 1 mV, or both are set to 1 mV, the total capacitance remains in a non-conductive state, keeping the FPD inactive with no photocurrent response (Fig. 4g and Supplementary Fig. 24). The corresponding logic truth tables for the NAND- and NOR-controlled photodetector modules are provided in Supplementary Tables 3 and 4, respectively. In addition, the ASIF device can be integrated with conventional analog circuit components to enable coordinated control of AC circuits. A diode bridge, commonly used as a rectifying component in power modules, can be connected in series with the capacitance (c-cap) of the ASIF device and a load resistor to construct a switchable rectification circuit, in which the c-cap serves as an independent control element. This configuration allows the circuit to toggle between ON and OFF states. When driven by an AC input signal with a 5 V amplitude and 1 kHz frequency, the diodes perform rectification, converting the signal into unidirectional current. In this setup, the c-cap acts as a switch that regulates the circuit’s filtering capability. At V_g = 0 mV, the c-cap remains conductive (ON), allowing the filtered signal to pass through and be detected at the output. When V_g is set to 1 mV, the c-cap switches to a non-conductive (OFF) state. As a result, the AC pathway is interrupted, and the system can no longer perform effective filtering (Fig. 4h–j and Supplementary Fig. 25). Throughout this process, the ASIF operates as a NOT logic controller, with its corresponding truth table provided in Supplementary Table 5. The above case demonstrates the excellent scalability of ASIFs in serving as internal power components within circuits. As an ionic device, it can seamlessly integrate with various non-ionic components to form hybrid logic control circuits.

Multi-level zero-static-power memory

By exploiting the continuous, non-volatile capacitance modulation of RSIFs, we propose an erasable and programmable data storage scheme in which input signals are directly mapped to the RSIF's intrinsic states. As proof of concept, we demonstrate this approach by storing the photocurrent output of an FPD. Upon increasing the illumination intensity from darkness to maximum exposure (532 nm wavelength, 40 mW), the photocurrent (I_p) generated by the FPD rises from a baseline of 4.6 μA to a peak of 62.9 μA. Correspondingly, when the V_g is tuned from 1.6 V down to 0.6 V, the peak current of the c-bat CV curve (I_cv) increases from 136.38 μA in the fully OFF state to 352.13 μA in the fully ON state. This correlation enables a reference calibration, whereby each value of I_p can be mapped to a corresponding I_cv, thereby allowing the incident light intensity at any power level to be precisely converted into a well-defined state of the c-bat and stored without the need for maintained voltage (Fig. 5a,b). Furthermore, by discretizing the continuously tunable states of the RSIF, we further propose a multi-level digital information storage scheme. For example, the capacity of the c-bat can be quantified into four distinct levels, corresponding to quaternary logic states Q0, Q1, Q2, and Q3. This configuration enables each RSIF unit to store 4 levels of states, thereby enhancing data density compared to conventional binary memory systems^15,16. The logic levels are defined as follows: when V_g = 0.6 V, the c-bat exhibits its maximum capacity, representing logic level “3” (fully ON). As V_g increases to 1.30 V, the capacity decreases, corresponding to logic level “2” (partially ON). At V_g = 1.35 V, the capacity further decreases to represent logic level “1” (partially OFF). Finally, when V_g = 1.60 V, the capacity reaches its minimum, indicating logic level “0” (fully OFF). The measured capacity values at these intermediate states are approximately 77.84%, 60.71%, and 38.73% of the fully ON state, respectively, exhibiting a clear monotonic decrease (Supplementary Fig. 26). As a demonstration of digital encoding, a quaternary memory array composed of four RSIF units (labeled RSIF3, RSIF2, RSIF1, and RSIF0) was utilised to store and update grayscale pixel values. In a grayscale image, each pixel takes a value from D0 to D255 (decimal), which corresponds to a quaternary range from Q0000 to Q3333. For instance, in image 1 (255 × 255 pixels), a pixel located at (x = 199, y = 137) with a grayscale value of D74 is converted to the quaternary representation Q1022. The corresponding logic states are set as RSIF3 = 1 (V_g,3 = 1.35 V), RSIF2 = 0 (V_g,2 = 1.60 V), RSIF1 = 2 (V_g,1 = 1.30 V), and RSIF0 = 2 (V_g,0 = 1.30 V). In image 2, if the same pixel is updated to a grayscale value of D52 (quaternary Q0310), the RSIF logic states are modified to RSIF3 = 0 (V_g,3 = 1.60 V), RSIF2 = 3 (V_g,2 = 0.60 V), RSIF1 = 1 (V_g,1 = 1.35 V), and RSIF0 = 0 (V_g,0 = 1.60 V). To implement this transition from pixel 1 to pixel 2, the corresponding g-bat modules (g-bat3 to g-bat0) execute a sequence of charge, discharge, charge, and charge operations, respectively. Reverting the pixel from image 2 back to image 1 requires applying the inverse set of charging and discharging operations on each RSIF unit to restore the original logic states. For more complex RGB image storage and manipulation, additional RSIF units are required to accommodate the increased data volume and precision needed for colour representation and pixel switching (Fig. 5c,d). Detailed implementation strategies are provided in Supplementary Fig. 27. This demonstration highlights RSIFs’ distinctive data storage traits: multi-level, continuously tunable states analogous to ionic transistors and long-term state retention without static power consumption comparable to memristors. Building on the continuously tunable switching principle, the four-level discretization has the potential to be extended to a larger number of levels. However, RSIF state modulation relies on reversible redox processes, which may introduce drift and state fluctuations during long-term cycling, thereby limiting the density of reliably distinguishable levels. Accordingly, further multilevel discretization should follow a noise-margin criterion, namely that the peak-current uncertainty induced by ageing and external perturbations remains significantly smaller than the peak separation between adjacent levels. In parallel, materials and interface engineering can be pursued to improve the cycling stability of the g-bat and enhance the sensitivity of the c-bat to local variations in iodine-species concentration.

Fig. 5. RSIF-based multi-level erasable programmable data storage and neural network computing via redox ion starvation effect.

a Schematic illustration of the collaborative memory process: a fibre-based photodetector (FPD) converts incident light into photocurrent, which is calibrated and stored in an RSIF c-bat as discrete current states. The FPD generates a photocurrent of 4.6 μA under dark conditions (V_g = 1.6 V) and 62.9 μA under laser illumination (532 nm, 40 mW, V_g = 0.6 V). b Current retention of the RSIF c-bat under (i) dark conditions and (ii) laser illumination, showing stable holding of maximum current over 24 h with retention rates of 82.18% and 79.65%, respectively. c Demonstration of four-level grayscale data memory using RSIF devices. Example transitions show image pixel values transformed from D74 (Q1022) to D52 (Q0310). d Multi-level memory switching of RSIFs. Representative CV current responses show (i) Q₃ 1 → 0 (charge), (ii) Q₂ 0 → 3 (discharge), (iii) Q₁ 2 → 1 (charge), and (iv) Q₀ 2 → 0 (charge), confirming reversible and rewritable storage functionality. e Quantised synaptic weight distribution in RSIF-based single-layer perceptrons (SLPs), with weights confined to four discrete magnitudes {±1.36, ±2.13, ±2.74, ±3.52} × 10² μA. f Heat map and g distribution of neuron weights after 100-epoch training. h, RSIF-based image recognition framework. Input images are binarized, compressed, and mapped to trained RSIF-SLPs for inference. The classification output distinguishes between two template image categories with test accuracy exceeding 95%.

Neural network computing framework

Leveraging the multilevel, non-volatile data storage capability of RSIFs, we further demonstrate neural network computation via the rigorous co-design of device and algorithm. In this framework, the four discrete redox states of each fibre are mapped onto the quantised synaptic weights of a single-layer perceptron (SLP), thereby enabling image recognition (Fig. 5e; Eq. 22). Each RSIF element functions as a programmable synaptic weight associated with an individual input pixel. The input signal is physically encoded: pixels with a value of 1 (white) are driven by a cyclic voltammetry (CV) sweep from –0.5 V to +0.5 V, while pixels with a value of 0 (black) remain at rest without any CV excitation. The synaptic strengths are first optimised during a training phase and subsequently physically mapped onto the RSIF hardware by applying a specific gate bias to modulate the I⁻ concentration, thereby tuning the redox response of the device. Each calibrated weight corresponds to one of four distinct CV peak current levels: 1.36, 2.13, 2.74, or 3.52 (all ×10² µA), achieved at V_g = 1.60 V, 1.35 V, 1.30 V, and 0.60 V, respectively (Fig. 5f, g). This process implements a fixed-point perceptron whose weights are strictly constrained within the physically realisable multi-level states of the device. Once programmed, RSIFs retain these states non-volatilely, thereby preserving network parameters without static power consumption and enabling seamless compute-in-memory integration. As a proof of concept, we used landscape and architectural scenes as template images to construct a dataset comprising 1000 training samples and 400 test samples. The perceptron was trained and then deployed in hardware by programming V_g at each RSIF site. Inference was performed by summing the CV peak currents followed by threshold comparison. Python/Jupyter evaluation pipeline simulated the end-to-end workflow and confirmed a test accuracy exceeding 95%, validating the fidelity of the device-to-model mapping (Fig. 5h; Supplementary Fig. 28). Because each fibre node acts as a programmable synapse, scaling to fabric-level arrays would naturally support richer network topologies and extensive on-fabric parallelism. These results underscore RSIFs as a compelling compute-in-memory platform that tightly integrates sensing, storage, and inference, offering a promising route toward edge-intelligent textile systems.

Results and discussion

Conventional switchable devices rely on semiconductor layers as the core switching structures, which poses challenges for manufacturability and interfacial performance when integrated on fibre substrates. Here, we develop a semiconductor-free, four-terminal, switchable ionic fibre (FSIF) that replaces semiconductor layers with energy-storage components, including supercapacitors and aqueous halide batteries, in which an ion-starvation effect enables low-power computing and data storage functions fully compatible with low-cost textile manufacturing. We demonstrate two FSIF subtypes: an adsorption-type FSIF (ASIF), which operates at an ultralow gate voltage of 1 mV for low-power Boolean logic, device control and AC signal modulation; and a redox-type FSIF (RSIF), which provides nonvolatile, multilevel memory for in-memory neural-network computation. By combining transistor-like gate modulation at ultralow threshold voltages with memristor-like, zero-static-power data storage featuring continuously tunable states, these devices establish a semiconductor-independent ionic computing-storage architecture with excellent scalability and manufacturing adaptability, making them highly suitable for fibre- and textile-level intelligent systems. Future work will integrate ASIF and RSIF into a single compute-storage device, extend the FSIF platform toward neuromorphic computing, and leverage continued advances in fabrication strategies and high-rate material systems to enable device miniaturisation and higher integration density, while achieving faster switching response without compromising switching stability and ratio.

Methods

Fabrication of ASIFs

The multi-stranded CNT fibre was composed of intricately woven CNT fibres, which were fabricated using a ring-spinning and twisting apparatus, with each fibre measuring 100 μm in diameter. This multi-ply fibre served as the inner electrode for the g-cap and the core substrate of the ASIF device. To prepare the 1 M LiCl-PVA hydrogel, 4.24 g of LiCl and 10 g of PVA were dissolved in 100 mL of distilled water and heated to 80 °C for 90 min under vigorous stirring, followed by maintaining the mixture at 50 °C for an additional 30 min to evaporate excess water. The first layer of 1 M LiCl-PVA hydrogel was then applied onto the surface of the multi-stranded CNT fibres using the dip-coating technique. Subsequently, two single-strand CNT fibres (CNT fibre 1 and CNT fibre 2) were positioned parallel to each other on the upper and lower sides of the first hydrogel layer, serving as the electrodes for the c-cap. This completed the structural assembly of the c-cap. After applying the second layer of LiCl-PVA hydrogel via dip-coating, a CNT film was wrapped around the outermost periphery of the device, forming the secondary electrode for the g-cap.

Fabrication of RSIFs

A 300 μm-diameter Zn fibre was used as the negative electrode of the g-bat and as the core substrate for the RSIF device. The first layer of 1 M ZnSO₄-CMC hydrogel was applied onto the Zn fibre by dip-coating. Next, two single-strand CNT fibres (CNT fibre 1 and CNT fibre 2) were positioned parallel to each other on the upper and lower sides of the first hydrogel layer, acting as the electrodes for the c-bat and completing the structural assembly of the c-bat. A second layer of ZnSO₄-CMC hydrogel was then applied via dip-coating. Finally, the CNT film was exposed to I₂ vapour at 80 °C in a vacuum for 1 h, forming a CNT-I₂ film that enveloped the outermost layer and served as the positive electrode of the g-bat.

Theoretical model of adsorptive starvation for ASIF modulation

Both the ASIF and the RSIF are built on a continuous fibre-based gel ionic architecture, in which the electrolyte-filled microchannel serves as the central ionic pathway connecting the gate and channel electrodes along the fibre axis. This internal ionic circuit integrates an external g-cap/g-bat and an internal c-cap/c-bat that are electrochemically coupled through the shared electrolyte domain. For the ASIF, in the ON state, the c-cap functions as the sole electrochemically active component, with its current response under the input voltage V_in described by the following expression:

$$I_{\mathrm{c}-\mathrm{cap},0}=Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)V_{\mathrm{in}}$$ 1

Where $Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)$ is the intrinsic admittance of the c-cap.

In the OFF state, the g-cap is coupled into the c-cap circuit, and free ions within the shared electrolyte are adsorbed via adsorptive starvation. The frequency-dependent capacitance for both capacitors follows a power-law scaling, consistent with constant phase element (CPE)-like behaviour arising from interfacial ion diffusion and dispersion:

$${\mathrm{C}}_{\mathrm{c}-\mathrm{cap}}\left(\omega \right)={\mathrm{C}}_{\mathrm{c}0}{\omega }^{\alpha };{\mathrm{C}}_{\mathrm{g}-\mathrm{cap}}\left(\omega \right)={\mathrm{C}}_{\mathrm{g}0}{\omega }^{\alpha }$$ 2

Where $C_{\mathrm{c}-\mathrm{cap}}\left(\omega \right)$ and $C_{\mathrm{g}-\mathrm{cap}}\left(\omega \right)$ are the effective low-frequency capacitance constants, $C_{\mathrm{c}0}$ and $C_{\mathrm{g}0}$ are pre-exponential factors representing the effective low-frequency capacitance constants, $\alpha$ is the CPE exponent.

The charge adsorbed by the g-cap under bias V_g > 0 can be expressed as $Q_{\mathrm{g}-\mathrm{cap}}=C_{\mathrm{g}-\mathrm{cap}}\left(\omega \right)V_{\mathrm{g}}$. Given a total mobile ion reservoir $Q_{\mathrm{tot}}$ in the LiCl-PVA hydrogel, the effective free-ion fraction is defined as:

$$f_{\mathrm{eq}}\left(Q_{\mathrm{g}-\mathrm{cap}}\right)=\max \left(f_{\min },1-\frac{\mid Q_{\mathrm{g}-\mathrm{cap}}\mid }{Q_{\mathrm{tot}}}\right)$$ 3

Where $f_{\min }$ is the lower bound of the free-ion fraction required to maintain sufficient electrolyte conductivity.

As a direct consequence of ion adsorption, the intrinsic admittance of the c-cap $Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)$ is effectively attenuated to $Y_{\mathrm{c}-\mathrm{cap},1}\left(\omega \right)$. This attenuation originates from the depletion of mobile ions in the shared LiCl-PVA electrolyte, which is consistent with predictions from both the Gouy-Chapman-Stern theory and ion-adsorption theories, and can be linearly approximated by the following expression:

$$Y_{\mathrm{c}-\mathrm{cap},1}\left(\omega \right)\approx f_{\mathrm{eq}}\left(Q_{\mathrm{g}-\mathrm{cap}}\right)Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)$$ 4

Considering the influence of the diverted ion bypass, the equivalent impedance of the coupled c-cap and g-cap configuration within the electrolyte is given by:

$$Z_{\mathrm{\mid \mid }}=\frac{Z_{\mathrm{c}-\mathrm{cap}}{Z}_{\mathrm{g}-\mathrm{cap}}}{Z_{\mathrm{c}-\mathrm{cap}}+Z_{\mathrm{g}-\mathrm{cap}}}$$ 5

Where $Z_{\mathrm{c}-\mathrm{cap}}$ and $Z_{\mathrm{g}-\mathrm{cap}}$ are the intrinsic impedances of the c-cap and g-cap, respectively, each determined solely by its own capacitance. Under gate bias, the effective clamped voltage across the c-cap can be expressed as:

$$V_{\mathrm{c}-\mathrm{cap},1}\begin{array}{c}\hfill =V_{\mathrm{in}*}\frac{Z_{\mathrm{\mid \mid }}}{Z_{\mathrm{t}}+Z_{\mathrm{\mid \mid }}}\hfill \\ \hfill =V_{\mathrm{in}*}\frac{Z_{c-\mathrm{cap}}{Z}_{\mathrm{g}-\mathrm{cap}}}{Z_{\mathrm{t}}\left(Z_{\mathrm{c}-\mathrm{cap}}+Z_{\mathrm{g}-\mathrm{cap}}\right)+Z_{\mathrm{c}-\mathrm{cap}}{Z}_{\mathrm{g}-\mathrm{cap}}}\hfill \end{array}$$ 6

The coupled c‑cap and g‑cap circuit can be modelled as a node composed of parallel capacitors driven by two separate voltage sources. Applying nodal analysis based on charge conservation to parallel capacitors yields the node voltage V_in* as an admittance-weighted average:

$$V_{\mathrm{in}*}=\frac{\frac{V_{\mathrm{in}}}{Z_{\mathrm{c}-\mathrm{cap}}}+\frac{V_{\mathrm{g}}}{Z_{\mathrm{g}-\mathrm{cap}}}}{\frac{1}{Z_{\mathrm{c}-\mathrm{cap}}}+\frac{1}{Z_{\mathrm{g}-\mathrm{cap}}}}$$ 7

Because V_g (on the mV scale) is several orders of magnitude smaller than V_in (on the V scale), its contribution is negligible and is therefore omitted. Accordingly, Eq. 7 simplifies to:

$$V_{\mathrm{in}*}=\frac{\frac{V_{\mathrm{in}}}{Z_{\mathrm{c}-\mathrm{cap}}}}{\frac{1}{Z_{\mathrm{c}-\mathrm{cap}}}+\frac{1}{Z_{\mathrm{g}-\mathrm{cap}}}}=\frac{Z_{\mathrm{g}-\mathrm{cap}}{V}_{\mathrm{in}}}{Z_{\mathrm{c}-\mathrm{cap}}+Z_{\mathrm{g}-\mathrm{cap}}}$$ 8

From Eq. 8, V_in* can be approximated as V_in scaled by a factor determined by $Z_{\mathrm{c}-\mathrm{cap}}$ and $Z_{\mathrm{g}-\mathrm{cap}}$. Since $Z_{\mathrm{c}-\mathrm{cap}}$ and $Z_{\mathrm{g}-\mathrm{cap}}$ differ by no more than one order of magnitude, V_in* is dominated by the V_in branch and remains much closer to V_in than to V_g. To simplify the analysis, $V_{\mathrm{in}*}\approx V_{\mathrm{in}}$ is assumed.

In Eq. 6, Z_t represents the total impedance of all other components within the system that is independent of the capacitances of the c-cap and g-cap, which is associated with the series impedance of the electrodes and the coupled value of the internal circuit impedance. In the g-cap-dominated regime ($Z_{\mathrm{g}-\mathrm{cap}}<<Z_{\mathrm{c}-\mathrm{cap}}$), the Eq. 6 reduces to:

$$V_{\mathrm{c}-\mathrm{cap},1}\to V_{\mathrm{in}}\frac{Z_{\mathrm{g}-\mathrm{cap}}}{Z_{\mathrm{t}}+Z_{\mathrm{g}-\mathrm{cap}}}$$ 9

The combined effect of ion depletion and current bypass suppresses the c-cap’s current. The effective current in the OFF state is:

$$I_{\mathrm{c}-\mathrm{cap},1}=Y_{\mathrm{c}-\mathrm{cap},1}\left(\omega \right)V_{c-\mathrm{cap},1}\approx f_{\mathrm{eq}}\left(Q_{\mathrm{g}-\mathrm{cap}}\right)Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)V_{\mathrm{in}}\frac{Z_{\mathrm{g}-\mathrm{cap}}}{Z_{\mathrm{t}}+Z_{\mathrm{g}-\mathrm{cap}}}$$ 10

Therefore, the current suppression ratio $S$ and the ON/OFF ratio is cast into a compact form:

$$S_{\mathrm{adsorptive}}=\frac{I_{\mathrm{c}-\mathrm{cap},1}}{I_{\mathrm{c}-\mathrm{cap},0}}=\frac{I_{\mathrm{c}-\mathrm{cap},1}}{Y_{\mathrm{c}-\mathrm{cap},0}\left(\omega \right)V_{\mathrm{in}}}\approx f_{\mathrm{eq}}\left(Q_{\mathrm{g}-\mathrm{cap}}\right)\frac{Z_{\mathrm{g}-\mathrm{cap}}}{Z_{\mathrm{t}}+Z_{\mathrm{g}-\mathrm{cap}}}$$ 11

$${\text{ON}/\text{OFF}}_{\text{adsorptive}}=S^{-1}$$ 12

Under applied bias, this attenuation of effective current leads to suppressed responses in the c-cap’s CV curves, chronopotentiometry profiles, and impedance. Due to the coupling through a continuous uniform electrolyte, ion modulation triggered at the g-cap is rapidly transmitted via field-driven migration over submillimeter scales, enabling fast modulation of the c-cap’s ion current. Based on this model, enhancing the switching ratio requires designing the g-cap with a capacitance significantly larger than that of the c-cap. This allows the g‑cap to adsorb more ions from the electrolyte and maximise the ion bypass.

Theoretical model of redox starvation for RSIF modulation

The operation of a standard aqueous Zn//I₂ battery (g-bat) hinges on the reversible redox chemistry of iodine species within the aqueous electrolyte. The limited solubility of I₂ in water promotes its rapid conversion to the highly soluble I₃⁻. The fundamental electrochemical reactions are thus governed by the interplay between I⁻ oxidation and I₃⁻/I₅⁻ reduction:

$$\mathrm{Main}\mathrm{discharge}\mathrm{reaction}:I_3^{-}\left(aq\right)+2e^{-}\to 3I^{-}\left(aq\right)$$ 13a

$$\mathrm{Side}\mathrm{discharge}\mathrm{reaction}:I_5^{-}\left(aq\right)+2e^{-}\to I_3^{-}\left(aq\right)+2I^{-}\left(aq\right)$$ 13b

$$\mathrm{Main}\mathrm{charge}\mathrm{reaction}:3I^{-}\left(aq\right)\to I_3^{-}\left(aq\right)+2e^{-}$$ 13c

$$\mathrm{Side}\mathrm{charge}\mathrm{reaction\; :}{I}_3^{-}\left(aq\right)+2I^{-}\left(aq\right)\to I_5^{-}\left(aq\right)+2e^{-}$$ 13d

To link the Zn-I₂ redox chemistry with the electrochemical state during RSIF modulation, Raman spectroscopy was used to track the characteristic bands of the polyiodide species I₃⁻ and I₅⁻. The evolution of their band intensities serves as a spectral metric for iodine speciation and the corresponding charge-discharge state. According to Eq. 13a–d, discharging reduces and depletes I₃⁻ and I₅⁻ toward I⁻, whereas charging enhances I⁻ oxidation and promotes the formation and accumulation of I₃⁻ and I₅⁻. Consistent with Fig. 3h(ii), the I₃⁻ and I₅⁻ peaks are minimised at V_g = 0.6 V and maximised at V_g = 1.6 V, providing direct spectroscopic support for the proposed reaction pathway and the assigned charge-discharge states.

Under diffusion-controlled conditions, the peak current of the c-bat in cyclic voltammetry follows the Randles-Ševčík equation.

$$i_{\mathrm{p}}=\left(2.69\times {10}^5\right)n^{3/2}{AD}^{1/2}{Cv}^{1/2}$$ 14

Where $n$ is the number of electrons transferred, $A$ is the electrochemically active surface area of the working electrode, $D$ is the diffusion coefficient of the electroactive species, $v$ is the potential scan rate, $C$ is the bulk concentration of the electroactive species. The $C$ primarily corresponds to the concentration of I⁻, which is a critical specification attributed to the substantial fluctuations in concentration that occur throughout the charge-discharge cycle.

In the fully-ON state (V_g = 0.6 V), the ZnSO₄-CMC gel contains the highest concentration of ${\mathrm{I}}^{-}\left(C_0\left(I^{-}\right)\right)$. The peak current obtained from CV scanning of the c-bat is given by:

$$i_{\mathrm{p},0}\propto C_0\left(I^{-}\right)$$ 15

In the fully-OFF state (V_g = 1.6 V), the equilibrium concentration of ${\mathrm{I}}^{-}\left(C_1\left(I^{-}\right)\right)$ in the ZnSO₄-CMC gel reaches the minimum value among all operational states. Under this condition, a trace amount of I⁻ persists in the electrolyte matrix. This non-negligible residual concentration arises from the inherent thermodynamic equilibrium of I⁻/I₂/I₃⁻ in the gel and the kinetic barriers of relevant reactions, which collectively prevent the complete depletion of I⁻. Coupled with the presence of I₃⁻, these factors result in the existence of a small yet detectable CV peak:

$$i_{\mathrm{p},1}\propto C_1\left(I^{-}\right)$$ 16

Therefore, the current suppression ratio $S$ and the ON/OFF ratio are cast into a compact form:

$$S_{redox}\approx \frac{i_{\mathrm{p},1}}{i_{\mathrm{p},0}}=\frac{C_1\left(I^{-}\right)}{C_0\left(I^{-}\right)}$$ 17

$${\mathrm{ON}/\mathrm{OFF}}_{\mathrm{redox}}=S^{-1}$$ 18

ASIF-based AC modulation

According to Eqs. S1 to S10, the c-cap of the ASIF can operate in two distinct modes. In the ON state the c-cap exhibits a high capacitance approximated as C > 0, whereas in the OFF state it exhibits a minimal capacitance approximated as C ≈ 0:

$$C_{\mathrm{c}-\mathrm{cap},\mathrm{i}}=C\left(ONstate,>0\right),C_{\mathrm{c}-\mathrm{cap},\mathrm{i}}\approx 0\left(OFFstate\right)$$ 19

When multiple c-cap units from different ASIF devices are connected in series or parallel, the total capacitance conforms to the standard rule for capacitors in series, as described by the following relation:

$$\mathrm{If}\mathrm{in}\mathrm{series}:\frac{1}{C_{\mathrm{c}-\mathrm{cap},\mathrm{eq}}}={\sum }_{i=1}^n\frac{1}{C_{\mathrm{c}-\mathrm{cap},\mathrm{i}}}$$ 20a

$$\mathrm{If}\mathrm{in}\mathrm{parallel}:C_{\mathrm{c}-\mathrm{cap},\mathrm{eq}}={\sum }_{i=1}^n{C}_{\mathrm{c}-\mathrm{cap},\mathrm{i}}$$ 20b

In a series configuration, the total capacitance is governed by reciprocal summation, such that a single ASIF unit in the low-capacitance (OFF) state substantially reduces the overall capacitance. As a result, the system transitions to the OFF state whenever any constituent ASIF is OFF. This ensures that the system remains ON only when all ASIF units are simultaneously in the high-capacitance (ON) state. In contrast, in a parallel configuration, the total capacitance is determined by direct summation. Here, the presence of at least one ASIF in the ON state is sufficient to maintain a high overall capacitance and yield a measurable output signal. Conversely, when all ASIF units are OFF, the capacitance approaches zero, effectively suppressing the output. The binary switching of the ASIF c-cap can thus be harnessed for AC signal modulation. In ideal electrical circuits, capacitors exhibit frequency-dependent impedance, expressed as:

$$Z=\frac{1}{j2\pi fC}$$ 21

$Z$: impedance, $f$: frequency of the applied AC signal, and $C$: capacitance. Upon applying a gate bias, the c-cap capacitance switches between a high-capacitance (ON) state and a low-capacitance (OFF) state: the ON state yields low impedance and allows AC transmission, whereas the OFF state leads to high impedance and suppresses the signal. In series configurations, a single OFF unit dominates the equivalent capacitance and blocks the pathway, thereby realising AND/NAND logic. In parallel configurations, the presence of any ON unit maintains a sufficiently high capacitance to sustain the output, corresponding to OR/NOR logic. Thus, by translating gate-controlled capacitance switching into tunable AC impedance, ASIFs provide the physical basis for implementing Boolean logic and signal processing in ion-electron hybrid circuits.

RSIF-based single-layer perceptron (SLP) computing framework

The single-layer perceptron (SLP) is one of the most fundamental architectures in artificial neural networks and a canonical model for linear pattern classification. In its simplest form, the SLP consists of three components: an input layer that encodes external features, a weight vector specifying the strength and polarity of each connection, and an output unit that produces the final decision. Mathematically, the perceptron computes a weighted sum of its inputs, expressed as:

$$y=f\left({\sum }_{i=1}^n{\omega }_{\mathrm{i}}{x}_{\mathrm{i}}+b\right)$$ 22

Where $x_{\mathrm{i}}$ is the input features, ${\omega }_{\mathrm{i}}$ is the associated synaptic weights, $b$ is the bias term, and $f\left(\cdot \right)$ is the threshold or activation function. The perceptron learns through an iterative weight update rule, commonly implemented via gradient-based optimisation, which adjusts the weight vector to minimise classification error over the training set. In this study, we experimentally validated three key principles:

1. The state of the RSIF can be maintained, thereby exhibiting intrinsic memory characteristics.

2. The RSIF states can be further discretized, with four distinct states demonstrated in this work.

3. Transitions between these states can be reversibly and cyclically modulated through the control of the gate voltage (V_g).

Building on these findings, we further imposed explicit constraints on both the input representations and weights of the SLP, thereby constructing a computational framework featuring four discrete weight values. The specific methodology is outlined as follows:

Step 1. Physical input mapping

To standardise the input representation, raw images are first converted into binary form by applying a fixed intensity threshold, where pixels with intensity values greater than the threshold are assigned to 1 and the rest to 0. The resulting binary images are then uniformly down-sampled and compressed into an $n\times n$ pixel bitmap. To realise a quaternized SLP, explicit mappings are established between the input features, the perceptron parameters, and the underlying physical device states. Each binary input pixel is associated with a cyclic voltammetry (CV) scanning protocol: for each pixel $x_m=1$ (white), a CV scan between -0.5 V and +0.5 V at 100"mVs^-1 is applied; for $x_m=0$ (black), no CV scan is applied. This one-to-one mapping ensures that software inputs correspond precisely to physical stimulation protocols (Supplementary Table 6).

Step 2. FSIF-based four-level weight quantisation

The RSIF unit serves as the physical realisation of synaptic weights. As demonstrated previously, its states can be discretized into four distinct levels under controlled gating voltages. Specifically, when V_g = 0.60 V,1.30 V,1.35 V,1.60 V, the corresponding mean peak currents measured under a ± 0.5 V CV scan are 352 μA, 274 μA, 213 μA, and 136 μA, respectively. These discrete currents serve as the four quantization levels for the SLP weights.

Step 3. RSIF-based SLP Training

The training framework adopts a discretized weight quantization scheme. Specifically, upon completion of training, the latent weight of each RSIF is discretized to the nearest level within the predefined weight set $\left\{{\omega }^{\left(1\right)},\right)$ ${\omega }^{\left(2\right)},$ ${\omega }^{\left(3\right)},$ $\left({\omega }^{\left(4\right)}\right\}$. During training, the accuracy of both the training and test datasets is monitored at each epoch. As training progresses, the accuracy curves increase and gradually stabilise; once a stable level assignment is established (typically after 20-40 epochs, depending on augmentation strength and dataset size), the test accuracy generally exceeds 95%. After the final epoch, the weights of each neuron are fixed to one of the four discrete values, serving as the final parameters of the single-layer perceptron for image recognition.

Step 4. Image recognition

In the inference stage of image recognition, the binarized 8×8 image is flattened into a 64-dimensional vector $x\in {\left\{0,1\right\}}^{64}$, processed by a single-layer perceptron whose score is passed through a sigmoid to yield the confidence p. Empirically, when Image 1 is input, the perceptron assigns >90% confidence to the Image-1 class, and similarly for Image 2, demonstrating that the four-level (quantised) single-layer perceptron provides strong discrimination between the two images.

Author contributions

Conceptualization: X.H.Z., Q.C.Z., L.W. Methodology: X.H.Z., L.H., Z.X.W. Investigation: L.H., Q.C.Z., L.W. Visualisation: X.H.Z. Funding acquisition: Q.C.Z., L.W. Project administration: L.W. Supervision: Q.C.Z., L.W. Writing - original draft: X.H.Z., L.H., J.J.W., Y.C.X. Writing - review & editing: X.H.Z., Q.C.Z., L.W.

Peer review

Peer review information

Nature Communications thanks Gang Wang, and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 (MOE-T2EP50123-0014 and MOE-T2EP50223-0007), the Singapore Ministry of Education Academic Research Fund Tier 1 (RG72/24 and RG159/25), A*STAR under MTC IRG (M24N7c0079), National Natural Science Foundation of China (52473270 and T2422028), the CAS Project for Young Scientists in Basic Research (YSBR-128), the National Key R&D Program of China (2022YFA1203304), and Nano-Bionics, Chinese Academy of Sciences (start-up grant E1552102).

Data availability

All source data supporting the conclusions of this study are provided in the Source Data file. The data that support the findings of this study are available from the corresponding author upon request. Source data are provided with this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-73274-y.