All-2D vertical metal-semiconductor field-effect transistor with sub-10 nm channel and contact lengths

Abstract

Two-dimensional (2D) materials are promising candidates for next-generation nanoelectronics in the post-Moore era. However, simultaneously scaling the channel length (L_ch) and contact length (L_c) in transition metal dichalcogenide-based field-effect transistors remains a challenge. Here, we introduce an all-2D vertical metal–semiconductor field-effect transistor featuring an MoS₂ channel that contacts the sidewall of a graphene (source)–hBN (insulator)–graphene (drain)–hBN (insulator) heterostructure. A self-aligned TiS₂–MoS₂ Schottky junction ensures full-gate control over the channel. The L_ch and L_c are determined by the thicknesses of the bottom hBN and the graphene electrodes, respectively. Consequently, the L_ch and L_c can be simultaneously scaled to sub-10 nm with a vertical pitch size of sub-30 nm. The typical device exhibits an on/off ratio > 10⁷ at an operating voltage of ~0.5 V, a subthreshold swing of ~62 mV/Dec, a drain-induced barrier lowering of ~33 mV/V, and an on-state current density of ~144 μA/μm at 1 V. Sentaurus technology computer-aided design simulations further verify the good electrostatic control provided by the full-gate configuration and the bottleneck-free transport within the channel. These results highlight the potential of 2D materials for high-density and low-power integrated circuits.

The simultaneous downscaling of the channel length (L_ch) and contact length (L_c) remains an important challenge towards the industrialization of 2D transistors. Here, the authors report the realization of high-performance vertical metal–semiconductor field-effect transistors based on 2D MoS₂ channels with sub-10 nm L_ch and L_c.

Introduction

The field-effect transistor (FET) is a fundamental component of modern integrated circuits. Continuing miniaturization of FET has driven advancements in chip density and energy efficiency. However, as silicon-based FETs are approaching physical and technological limits, further scaling encounters significant challenges, including short-channel effects (SCE), increasing power consumption, and escalating fabrication costs^1–3. Two-dimensional (2D) van der Waals (vdW) materials, such as transition metal dichalcogenides (TMDCs), graphene, and hexagonal boron nitride (hBN), etc., with atomic-scale thicknesses and dangling-bond-free surfaces^4–7, have advantages in mitigating SCE, constituting clean interfaces, and eliminating lattice match requirement, providing a promising pathway for the post-Moore era^2,3,8.

The fundamental metric for transistor density in conventional planar architectures is the contacted poly pitch (CPP), which is the sum of the gate length, contact length, and necessary lateral spacing^9,10 (Supplementary Fig. 1a). Therefore, scaling certain critical parameters (such as the gate, channel, and contact length, L_g/L_ch/L_c) is indispensable. Many efforts focused on scaling these parameters in TMDC-based metal–oxide–semiconductor FETs (MOSFETs) have been reported, in which high-cost and complex lithography processes, such as deep ultraviolet (DUV), extreme ultraviolet (EUV), or electron beam lithography (EBL), are employed^11–13. Although alternative strategies, including nanowire masking^14,15, self-assembly patterning¹⁶, crack formation^17–19, shadow evaporation^20,21, self-oxidation²², and selective etching²³, etc., have been developed to create sub-100 nm channels, the related devices still have large lateral footprints. On the other hand, MoS₂ FETs with 1 and sub-1-nm gate lengths have been realized using carbon nanotube (CNT)²⁴ and the edge of monolayer graphene²⁵ as the gates, respectively. However, in these two works, the physical L_ch remains at the micrometer scale. Meanwhile, scaling contact electrodes also meets challenge: current crowding effect hinders the continuous reduction of the L_c^26,27. The transfer length (L_T) is a criterion for evaluating the scaling limit of the contacts. When the L_c, especially at the source, approaches this value, severe current crowding occurs, leading to a significant reduction in the on-current^26,27.

It is inspiring that vertical FETs (VFETs) have brought forth a new concept, where the device density is governed by the vertical pitch size²⁸ (the cumulative thickness of the functional stack, Supplementary Fig. 1b). In this architecture, L_ch and L_c are determined by film thicknesses, enabling atomic-scale precision without relying on expensive lithography. Recently, VFETs based on an M (source)–TMDC–M (drain) architecture (M represents graphene, CNT, or metal) have been reported^29,30, in which the L_ch is determined by the thickness of the TMDC. However, in these devices, source–drain tunneling frequently occurs, resulting in a low on/off ratio and a large operating voltage. VFETs based on a source–insulator–drain (S–I–D) sidewall architecture have also been reported^31–33, in which the TMDC channel is laid on the sidewall and the L_ch is determined by the thickness of the insulator. These devices inhibit source–drain tunneling, but sacrifice the vertical pitch size.

Apart from the MOSFET, the metal–semiconductor FET (MESFET) is another fundamental transistor architecture, where the metal gate and semiconductor channel form a Schottky junction (SJ). In conventional TMDC-based MESFET fabrication processes, metal deposition typically introduces defects into the interface, causing Fermi-level pinning and deteriorating SJ quality³⁴.

In this work, we design and fabricate an all-2D vertical MESFET based on vdW materials with a source–insulator–drain–insulator (S–I–D–I) configuration. Herein, few-layer graphene (FLG) flakes serve as the source and drain, while hBN flakes serve as the bottom and top insulators. Monolayer MoS₂ serves as the channel, which contacts the sidewall of the S–I–D–I heterostructure. The channel length is determined by the thickness of the bottom hBN flake, and the contact lengths are determined by the thicknesses of the FLGs. We adopt TiS₂, a vdW semimetal material with good conductivity and a high work function (~6.6 eV) to serve as the gate, which can form an SJ with MoS₂³⁵. Our approach simultaneously scales the channel and contact lengths to sub-10 nm with a vertical pitch size of sub-30 nm. The fabrication process does not involve dielectric/metal deposition on the TMDC, thereby preserving a near-ideal SJ³⁴. The typical device exhibits satisfying performance: on/off ratio $>$ 10⁷ at an operating voltage of ~0.5 V, a subthreshold swing (SS) of ~62 mV/Dec, a drain-induced barrier lowering (DIBL) of ~33 mV/V, and an on-state current density (I_on) of ~144 μA/μm at 1 V. Sentaurus technology computer-aided design (TCAD) simulations further verify the good electrostatic control provided by the full-gate configuration and the bottleneck-free transport within the channel. Our work demonstrates a subtle and low-cost paradigm toward the extreme miniaturization of FET in the post-Moore era.

Results

Device fabrication and characterization

The device fabrication procedures are shown in Fig. 1a–d. First, an FLG (source)–hBN (bottom insulator)–FLG (drain)–hBN (top insulator) heterostructure was assembled on a p⁺-Si/SiO₂ substrate by mechanically exfoliating the constituent materials. We chose a thicker FLG to serve as the source²⁷. Subsequently, ultraviolet (UV) lithography and reactive ion etching (RIE) were employed to create a sloped sidewall region of the heterostructure. Chemical-vapor-deposition (CVD)-grown monolayer MoS₂ (detailed characterization is provided in Supplementary Fig. 2) and mechanically exfoliated few-layer TiS₂ were transferred in sequence onto this region. Next, with atop TiS₂ as the mask, the uncovered part of the MoS₂ was removed by a second RIE process. The self-aligned TiS₂–MoS₂ SJ ensures full-gate control over the channel, thereby enhancing the electrostatic modulation³⁶. Detailed processes are provided in Supplementary Fig. 3 and the “Methods” section. The final MESFET device (Fig. 1e) features a vertical S–I–D–I sidewall architecture. The top hBN ensures that the MoS₂ only contacts the sidewall of the top FLG to scale the contact length of the drain and mitigate interlayer tunneling between the gate and drain³⁷. In this device configuration, the channel length and contact lengths are determined by the thicknesses of the bottom hBN and FLGs, respectively (Fig. 1d).

Fig. 1. Schematic diagrams of the fabrication procedures and cross-sectional view of the all-2D vertical metal–semiconductor field-effect transistor (MESFET) and the equivalent circuit.

a A few-layer graphene (FLG, source)–hexagonal boron nitride (hBN, bottom insulator)–FLG (drain)–hBN (top insulator) heterostructure was assembled on a p⁺-Si/SiO₂ substrate by mechanically exfoliating the constituent materials. b A sloped sidewall of the heterostructure was created by ultraviolet (UV) lithography and reactive ion etching (RIE). c Chemical-vapor-deposition (CVD)-grown monolayer MoS₂ and mechanically exfoliated few-layer TiS₂ were transferred in sequence onto the sidewall region. d The uncovered part of the MoS₂ was removed by a second RIE process, with atop TiS₂ as the mask, forming a self-aligned TiS₂–MoS₂ SJ. e and f Cross-sectional view and equivalent circuit of the all-2D vertical MESFET. R_G, R_ch, R_c, R_D, and R_S represent the resistances of the gate, channel, contact, drain, and source, respectively.

The schematic diagram of the device together with the equivalent circuit is shown in Fig. 1f, where R_G, R_ch, R_c, R_D, and R_S represent the resistances of the gate, channel, contact, drain, and source, respectively. The conduction of the MoS₂ channel is controlled by the gate through modulating the barrier height and depletion region width.

Figure 2a presents an optical micrograph of an as-fabricated device. The source FLG (s-FLG), bottom hBN (b-hBN), drain FLG (d-FLG), and top hBN (t-hBN) are demarcated around the sloped sidewall region. We employed high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) and energy-dispersive spectroscopy (EDS) to further characterize the vertical MESFET. The false-colored image in Fig. 2b reveals the distinct S–I–D–I heterostructure featuring a sloped sidewall with a slope angle (θ) of ~43°. The TiS₂–MoS₂ SJ is located across the sidewall. The L_ch and L_c are measured to be ~9.6 and ~6.7/6.2 nm, respectively. During the etching process, the flow rate ratio of O₂ to CHF₃ influences the etching rate, and accordingly the θ (Supplementary Note 1, Supplementary Fig. 4, and Supplementary Table 1). To optimize the trade-off between the miniaturization and interface conformality, we adopted the ratio of O₂/CHF₃ to be 20 sccm/1 sccm, which yields an optimal sidewall angle of θ_opt ~ 45° (ranging from 43° to 48°, Supplementary Fig. 5). Therefore, later we can estimate L_ch and L_c of other devices with identical process condition using the equations: $L_{\mathrm{ch}}=\frac{T_{\mathrm{b}-\mathrm{hBN}}}{{\sin \theta }_{\mathrm{opt}}}$, and $L_{\mathrm{c}}=\frac{T_{\mathrm{FLG}}}{\sin {\theta }_{\mathrm{opt}}}$, where θ_opt = 45°, T_b-hBN and T_FLG are thicknesses of the b-hBN and related FLGs, respectively. It is worth noting that in our case, T_b-hBN must not be less than ~5 nm to prevent source–drain tunneling current (Supplementary Fig. 6). The corresponding L_ch is limited to ~7.1 nm. To mitigate the current crowding effect, T_FLG must not be less than ~4 nm. The corresponding L_c is limited to ~5.7 nm. EDS elemental mappings of Ti, Mo, N, and C (Fig. 2c) further confirm the locations of the constituent 2D layers. Kelvin probe force microscopy characterization (Fig. 2d) reveals a surface potential difference of ~120 mV between TiS₂ and MoS₂, indicating the formation of an SJ at their interface.

Fig. 2. Characterization of a representative all-2D vertical MESFET.

a Optical micrograph of an as-fabricated device. The white, black, and orange dashed lines represent the FLG, hBN, and TiS₂–MoS₂ Schottky junction (SJ), respectively. The TiS₂–MoS₂ SJ is located on the sloped sidewall of the vertically stacked FLG–hBN–FLG–hBN heterostructure. Scale bar: 10 μm. b False-colored cross-sectional high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image of the MESFET with the sloped sidewall (θ ~43°). The channel length (L_ch) and contact length (L_c) are measured to be ~9.6 and ~6.7/6.2 nm, respectively. The blue, gray, gold, and purple regions correspond to the hBN, FLG, TiS₂, and SiO₂, respectively. The white dashed line indicates the location of the MoS₂. Scale bar: 10 nm. c Corresponding energy-dispersive spectroscopy (EDS) elemental mappings of Ti, Mo, N, and C, further confirming the locations of the constituent 2D layers. Scale bar: 5 nm. d Kelvin probe force microscopy image of the TiS₂–MoS₂ SJ and the corresponding surface potential profile extracted along the blue dashed line, respectively. Scale bar: 2 μm.

Electrical properties of the all-2D vertical MESFET

A representative device of ours has an L_ch of ~8.1 nm and L_c of ~14.0 and 12.6 nm. The corresponding vertical pitch size is sub-30 nm, with the thicknesses of the s-FLG, b-hBN, d-FLG, and t-hBN measured before RIE (Supplementary Fig. 7). First, I–V curve of the SJ was measured, as shown in Fig. 3a. The device exhibits clear Schottky characteristics with a rectification ratio exceeding 10⁴. From the I–V curve, we can extract the ideality factor ($\eta$) of ~1.21 by using the equation: $\eta =\frac{q}{m\ln \left(10\right)k_{\mathrm{B}}T}$, where $q$ is the unit charge, m is the slope of the linear region, $k_{\mathrm{B}}$ is the Boltzmann constant, and T is the absolute temperature^34,38. The near-ideal value of $\eta$ is attributed to the metal gate transfer process that preserves a clean interface between the TiS₂ and MoS₂, as well as a pristine MoS₂ channel^38,39. Subsequently, the I_DS–V_DS output curves of the MESFET were measured under various gate voltages (Fig. 3b). The I_on can reach up to ~144 μA/μm at V_DS = 1 V. The distinct linear and saturation regions demonstrate the typical output characteristics of an FET with efficient carrier transport between the source/drain and the channel. Notably, the I_on decreases significantly when the source contact length is reduced below ~14 nm (Supplementary Fig. 8), suggesting that the L_T is expected to be less than 14 nm. Compared to previous reports about short contacts (Supplementary Table 2), our result represents a state-of-the-art L_T value obtained through the direct measurement of physically scaled contacts^{13,26,27,40–44}. We attribute this merit to the sidewall contact of our device.

Fig. 3. Electrical properties of the all-2D vertical MESFET.

a Current–voltage (I–V) characteristic of the TiS₂–MoS₂ SJ. b The source–drain current (I_DS) versus bias (V_DS) output curves of the MESFET under various gate voltages (V_GS) (from −0.5 to 1 V with step of 0.25 V). c Corresponding I_DS–V_GS transfer curves at various V_DS (0.01, 0.1, and 1 V). The left and right axes are presented in logarithmic and linear scales, respectively. HP: high-performance, HD: high-density, I_off: off-state currents. d On/off ratio of the device as a function of operating voltage at V_DS = 0.1 V. The red shaded area marks the sub-1 V operating range where an on/off ratio above 10⁷ is achieved. The vertical blue dashed line denotes the 0.7 V low-power supply voltage specified for complementary metal–oxide–semiconductor (CMOS) logic. e Corresponding threshold voltage (V_th), drain-induced barrier lowering (DIBL), log (on/off ratio), and minimum subthreshold swing (SS_min) at various V_DS (0.01, 0.1, and 1 V). These data are extracted from the transfer curves depicted in (c). f The corresponding SS–I_DS curves at various V_DS (0.01, 0.1, and 1 V).

Figure 3c shows the I_DS–V_GS transfer curves at various V_DS. The off-state currents (I_off) are < 10 ^{– 4} μA/μm, meeting the International Roadmap for Devices and Systems (IRDS) benchmarks for both high-performance (HP, I_off $<$ 10⁻² μA/μm) and high-density (HD, I_off $<$ 10⁻⁴ μA/μm) applications⁹. The gate leakage current of the device (Supplementary Fig. 9) is consistent with SJ characteristics and meets the low-power limit requirement⁹ ($<$ 1.5 × 10 ^{– 2} A/cm²). Figure 3d illustrates the relationship between the on/off ratio and operating voltage, measured at V_DS = 0.1 V. Herein, the operating voltage is defined as the V_GS required for reaching a target on/off ratio^45,46. The device achieves an on/off ratio exceeding 10⁷ within a remarkably narrow operation window of ~1 V (i.e., the device can be turned from off-state to on-state within a small gate voltage range from −0.5 to 0.5 V). Notably, the operating voltage can be as low as 0.5 V, satisfying the 0.7 V limit of the complementary metal–oxide–semiconductor (CMOS) logic standard⁹, which decisively demonstrates its superior switching efficiency and low-power potential.

From Fig. 3c, we extracted the key parameters of the MESFET, including threshold voltage (V_th), on/off ratio, and SS, and summarized them in Fig. 3e. The DIBL, calculated from the shift of the V_th values under V_DS = 0.1 and 1 V by using the equation $\mathrm{DIBL}=-\frac{V_{\mathrm{th}}^{\mathrm{high}}-V_{\mathrm{th}}^{\mathrm{low}}}{V_{\mathrm{DS}}^{\mathrm{high}}-V_{\mathrm{DS}}^{\mathrm{low}}}$, is only ~33 mV/V, indicating strong SCE immunity. The on/off ratio can reach 10⁷ under various V_DS values. Specifically, the minimum SS (calculated by $\mathrm{SS}=\frac{\mathrm{d}{V}_{\mathrm{GS}}}{\mathrm{d}{\log }_{10}\left(I_{\mathrm{DS}}\right)}$) can be as low as ~62 mV/Dec, close to the Boltzmann limit of 60 mV/Dec. Moreover, the SS–I_DS relations under various V_DS (Fig. 3f) demonstrate that the SS remains sub-100 mV/Dec over a current range spanning more than four orders of magnitude, further confirming good switching efficiency.

To quantitatively evaluate the electrostatic control limit of our vertical architecture, we extract the capacitance-equivalent thickness (CET). As a comprehensive metric, CET accounts for the equivalent thickness of the gate, vdW gap, and quantum capacitance effects, making it a critical indicator of the gate-coupling efficiency⁴⁷. Capacitance–voltage (C–V) measurements were performed on the TiS₂–MoS₂ SJ with varying TiS₂ thicknesses. As shown in Supplementary Fig. 10a, clear depletion and accumulation behaviors are observed. The CET is extracted from the accumulation capacitance density (C_accum) using the standard relation⁴⁷: $\mathrm{CET}=\frac{3.9{\epsilon }_0}{C_{\mathrm{accum}}}$, where ${\epsilon }_0$ is the vacuum permittivity, and 3.9 is the relative dielectric constant of SiO₂. Strikingly, the CET decreases with the thickness of TiS₂ (Supplementary Fig. 10b) and can be as low as ~0.85 nm, meeting the IRDS 2037 target for logic applications⁹ ($<$ 0.9 nm). This robust electrostatic coupling capability directly underpins the good switching efficiency and low-power characteristics observed in our MESFETs. More discussion is provided in Supplementary Note 2.

We have also extracted the field-effect mobility of the representative MESFET device based on the equation $\mu =\frac{\partial I_{\mathrm{DS}}}{\partial V_{\mathrm{GS}}}\frac{L}{qnW}$^34,38,48, where $n$ is the carrier density in cm⁻², $q$ is the unit charge, and W and L are the width and length of the channel, respectively. We first extract the n value from C–V measurement^48,49 (Supplementary Fig. 11a, b). Then, from the transfer curves of the MESFET depicted in Fig. 3c and the n value, we derive the V_GS-dependent $\mu$ values, as shown in Supplementary Fig. 11c. Detailed extraction procedures are provided in Supplementary Note 3. When the conductive channel gradually opens, the field-effect mobility increases with the gate voltage. However, the mobility decreases rapidly at higher V_GS due to the gate-contact effect, where contact resistance dominates the total resistance⁵⁰. Besides, the enhanced scattering at the 2D interface and velocity saturation effect under high bias may also cause the degradation of mobility^50–52.

It is worth noting that the hysteresis of the I_DS–V_GS curves of the MESFET device can be as small as ~20 mV (Supplementary Fig. 12). We attribute this merit to our MESFET fabrication, which is free from the gate dielectric and metal deposition processes^34,38.

Physical mechanism and TCAD simulation

To further elucidate the operating principle of the all-2D vertical MESFET, the band diagrams of the TiS₂–MoS₂ SJ and MESFET were analyzed under various gate voltages. As illustrated in Fig. 4a–c, TiS₂ and MoS₂ form a type-I band alignment. Owing to the large difference between the work function of TiS₂ (${\Phi }_{{\mathrm{TiS}}_2}$) and the electron affinity of n-MoS₂ (${\chi }_{{\mathrm{MoS}}_2}$)¹³, the n-MoS₂ bands bend upward, forming an SJ. When the SJ is forward/reverse biased, the Fermi level of n-MoS₂ near the SJ moves toward/backward the conduction band edge, and the built-in potential energy (${\Phi }_{\mathrm{bi}}$) decreases/increases. Accordingly, the depletion region width within the MoS₂ channel of the MESFET narrows/widens, thereby effectively modulating the transport efficiency across the channel. Notably, our full-gate MESFET architecture offers a distinct advantage in electrostatic modulation due to the direct contact between the metal gate and the entire semiconductor channel. We preserve a robust Schottky barrier through pristine vdW integration and appropriate post-assembly thermal treatment. This approach maximizes capacitive coupling, facilitating efficient charge accumulation to support a high I_on and mitigate leakage current^36,38,53. This strong capacitive coupling is reflected in the small CET value of ~0.85 nm as discussed above.

Fig. 4. Energy band diagrams of the all-2D vertical MESFET.

a–c Energy band diagrams of TiS₂–MoS₂ before contact, after contact, and under forward/reverse bias, respectively. d–f Energy band diagrams of the MESFET before channel formation, under positive gate voltage, and under negative gate voltage, respectively. E_vc, E_c, E_f, and E_v represent the vacuum energy level, conduction band minimum, Fermi level, and valence band maximum, respectively. ${\Phi }_{\mathrm{SB}}\left(={\Phi }_{{\mathrm{TiS}}_2}-{\chi }_{{\mathrm{MoS}}_2}\right)$ is the Schottky barrier height and ${\Phi }_{\mathrm{bi}}$ is the built-in potential energy. ${\Phi }_{{\mathrm{TiS}}_2}$, ${\Phi }_{{\mathrm{MoS}}_2}$, and ${\Phi }_{\mathrm{FLG}}$, are the work functions of TiS₂, MoS₂, and FLG, respectively. ${\chi }_{{\mathrm{MoS}}_2}$ is the electron affinity of MoS₂. V_F and V_R are forward and reverse biases, respectively. $q$ is the unit charge.

As illustrated in Fig. 4d–f, the close alignment between the work function of FLG (${\Phi }_{\mathrm{FLG}}$) and ${\chi }_{{\mathrm{MoS}}_2}$ results in a reduced Schottky barrier at the FLG/n-MoS₂ interface, ensuring highly efficient carrier transport. For a fixed V_DS, when the TiS₂–MoS₂ SJ is forward-biased under a positive gate voltage, the MESFET is in the on-state with larger I_DS, and vice versa.

To quantitatively elucidate the underlying device physics, we perform Sentaurus TCAD simulations. The modeled device structure is presented in Fig. 5a. The agreement between the simulated transfer characteristics and our experimental data validates the constructed physical model (Fig. 5b). Based on this model, the electric field and electron density distributions were extracted. As shown in Fig. 5c, the on-state electric field is more concentrated at the source region rather than the drain region. Such an asymmetric electric field distribution facilitates efficient electron injection at the source and electron collection at the drain, enabling bottleneck-free transport⁵⁴. Furthermore, Fig. 5d reveals that, in the on/off-state, the entire channel acts as a highly uniform carrier accumulation/depletion region. This good electrostatic control is attributed to the superior capacitive coupling provided by the full-gate configuration.

Fig. 5. Technology computer-aided design (TCAD) simulation.

a Modeled device structure of the all-2D vertical MESFET. b Comparison between experimental and simulated I_DS−V_GS transfer curves at V_DS = 1/0.1/0.01 V. c Electric field (E) contour plots in the on-state (V_DS = 0.01 V, V_GS = 1 V) and off-state (V_DS = 0.01 V, V_GS = −0.1 V). d Electron density (n) in the MoS₂ channel on the sidewall in the on-state (V_DS = 0.01 V, V_GS = 1 V) and off-state (V_DS = 0.01 V, V_GS = −0.1 V).

Reproducibility and benchmarks

To statistically validate device reproducibility and reliability, an additional batch of 15 devices with a physical channel length of ~8.7 ± 0.7 nm was fabricated under the identical optimized conditions. As illustrated by the cumulative distribution functions in Fig. 6a, the devices exhibit overall uniformity with narrow parameter distributions. Specifically, strong switching characteristics are demonstrated by an on/off ratio reaching ~7.8 × 10⁸ (average ~1.4 × 10⁸) and a steep minimum subthreshold swing (SS_min) down to ~62 mV/Dec (average ~81.5 mV/Dec). Furthermore, good immunity to SCE and low-power capability are evidenced by minimum values of DIBL and operating voltage of ~30 mV/V and ~0.5 V, respectively. More details are provided in Supplementary Figs. 13 and 14.

Fig. 6. Reproducibility and benchmarks.

a Cumulative distribution function plot of key device metrics, including the on/off ratio, SS_min, DIBL, and operating voltage of our all-2D vertical MESFETs. b Comparisons of the L_ch and operating voltage versus on/off ratio of our all-2D vertical MESFETs against previously reported short-channel MoS₂ FETs. c Comparison of the I_on,area versus L_c of our all-2D vertical MESFETs against previously reported short-contact MoS₂ FETs. d Radar chart benchmarking the comprehensive performance of our all-2D vertical MESFETs against representative devices from other categories.

To comprehensively evaluate our all-2D vertical MESFETs, we benchmark several key parameters against the best reported data from state-of-the-art scaled MoS₂ FETs. Previous studies were categorized into four groups based on device architecture and scaling strategy: (1) Planar–EBL: planar source and drain distribution with a nanoscale channel or contact defined by EBL^{11,12,40–43,55–57}; (2) Planar–other methods: planar source and drain distribution with a nanoscale channel defined by alternative strategies^15–23; (3) Vertical–stack: vertically stacked source/channel/drain (M–MoS₂–M, where M represents graphene, CNT, or metal) structures^{28–30,37,58–63}; (4) Vertical–sidewall–stack: vertically stacked S–I–D sidewall structures^31–33. Figure 6b compares the L_ch and operating voltage versus the on/off ratio. Our device stands out by exhibiting a high on/off ratio of ~10⁸ at a scaled L_ch, demonstrating stronger immunity to SCE compared to the previously reported devices. Notably, among these devices, our device is the only one that meets the 0.7 V operating voltage limit of the CMOS logic standard. Figure 6c benchmarks the on-state current density of the reported devices with scaled L_c^{13,26,27,40–44,57}. The on-state current is normalized to the channel area (I_on,area) to rule out geometrical contributions from the L_ch, allowing for a fair intrinsic comparison. It is worth noting that our device can maintain a high I_on,area even at L_c of ~10 nm, demonstrating the robust current transport capability and scalability. Finally, a radar plot is presented in Fig. 6d to compare recent representative works^21,33,37,41 with ours, which demonstrates the advantages of our achievement in scaling, power consumption, and performance. Detailed data are provided in Supplementary Tables 4 and 5.

Discussion

In summary, we have demonstrated an all-2D vertical MESFET architecture with sub-10 nm channel and contact lengths (vertical pitch size of sub-30 nm). The MESFET is constructed from vdW materials, including FLG, hBN, MoS₂, and TiS₂. The fabrication process is independent of lithographic precision and avoids direct dielectric/metal deposition onto the TMDC, thereby preserving a near-ideal SJ and pristine channel. The typical device exhibits favorable electrical performance, such as an on/off ratio > 10⁷ at an operating voltage of ~0.5 V, SS_min ~62 mV/Dec, DIBL ~33 mV/V, and I_on ~144 μA/μm at 1 V. These metrics are attributed to the device configuration and precise nanoscale contact engineering. Our work provides a promising and low-cost paradigm for beyond-silicon and post-Moore nanoelectronics. It is anticipated that with the development of the high-quality wafer-scale growth of graphene, hBN, and their heterostructures^4,5,64,65, alongside the successful synthesis of large-scale TiS₂⁶⁶, our conceptual vertical MESFET devices will transition from the laboratory stage to industrial-scale production in the near future.

Methods

Synthesis of monolayer MoS₂

The monolayer MoS₂ films were grown on a p⁺-Si/SiO₂ (285 nm) substrate using the CVD method in a three-temperature-zone tubular furnace. High-purity molybdenum trioxide (MoO₃, 99.999%, 130 mg) and sulfur powder (S, 99.999%, excess) were used as precursors. Perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt (PTAS) served as the seeding promoter. The S powder was placed in the upstream zone at 150 °C. The MoO₃ powder, PTAS, and substrate were sequentially placed in the downstream zone at 650 °C. The growth was carried out in a high-purity Ar environment under atmospheric pressure. The Ar flow rate was maintained at 15 sccm. The growth duration was 5 min, after which the furnace was cooled naturally to room temperature.

Transfer of monolayer MoS₂ on the sidewall of the heterostructure

Monolayer MoS₂ was transferred to the target substrate with the assistance of polymethyl methacrylate (PMMA) in deionized water. Once detached from the growth substrate, the PMMA/MoS₂ film was subsequently collected onto the target substrate. After natural drying in a vacuum chamber for 12 h, the target substrate was placed on a hot plate and baked at 90 °C for 2 min to further improve the adhesion between the MoS₂ and the sidewall of the heterostructure. The PMMA layer was removed from the target substrate using warm acetone.

Fabrication of the all-2D vertical MESFET

Mechanically exfoliated FLG and hBN flakes were transferred onto a p⁺-Si/SiO₂ substrate by polydimethylsiloxane (PDMS) stamp under the help of a microscope attached with a micro-manipulator, to form the FLG–hBN–FLG–hBN vertical heterostructure. The FLGs were connected to two pre-fabricated metal electrodes for measurement purposes. The substrate was subsequently annealed in a tubular furnace at 200 °C with Ar/H₂ (10 sccm/40 sccm) environment under low chamber pressure (0.45 Torr) for 2 h. Next, UV lithography (Suss MJB4) and RIE (SENTECH EtchLab200) were employed to create the sloped S–I–D–I sidewall region. Prior to RIE, the exposed lithography window region was cleaned with O₂ plasma. The RIE was conducted in O₂/CHF₃ mixed gas (20 sccm/1 sccm) with a chamber pressure of 6 Pa and radio frequency power of 30 W. The etching duration was 3 min (more details are provided in Supplementary Note 1). CVD-grown monolayer MoS₂ was transferred onto the sidewall region using the above-mentioned method. Subsequently, TiS₂ was transferred onto the MoS₂. With TiS₂ as the mask, the uncovered part of MoS₂ was removed by a second RIE process in O₂ (30 sccm) environment for 1 min. The chamber pressure was 7 Pa, and the radio frequency power was 70 W. Finally, an additional FLG was transferred to connect the TiS₂ to the third pre-fabricated metal electrode for measurement purposes. The completed device underwent a final low-pressure annealing treatment (the same condition as above) to remove transfer medium residues, reduce bubble density, and improve overall contact quality.

Characterizations and measurements

The Raman and photoluminescence (PL) spectra were collected by a micro-zone confocal Raman system (WITec alpha 300R) attached with a 532 nm laser. The thicknesses of 2D materials and surface potential of the TiS₂–MoS₂ SJ were measured by an atomic force microscope (Asylum Research, Cypher S). The HAADF-STEM and EDS elemental mapping images were taken by a spherical aberration-corrected transmission electron microscope (FEI Titan Cubed Themis G2 300). The sample for HAADF-STEM observation was prepared in a focused ion beam (FIB) system (ThermoFisher Helios G4 UX). The electrical measurements were conducted in a probe station (EB-6) connected to a semiconductor characterization system (Keithley 4200A-SCS). All the characterizations were conducted in the dark at room temperature.

TCAD Simulation

The electrical properties of the all-2D vertical MESFET were simulated using Sentaurus TCAD. All 2D materials were modeled by adapting the material parameters of bulk semiconductors, including permittivity, electron affinity, work function, and bandgap, to their respective layered 2D structures. A 0.2 nm vdW gap was intentionally introduced between adjacent 2D material interfaces to accurately reflect the physical nature of vdW integration. Carrier transport within the MoS₂ channel was modeled using the drift-diffusion approximation, and field-effect mobility was assumed to be limited by phonon scattering. The Caughey–Thomas phenomenological model was used for velocity saturation in the high-lateral-field limit. Given the nanometer-scale of all the constituent layers in the device, the density-gradient quantum correction model was applied to account for quantum confinement effects on the carrier distribution. The contact between the FLG source/drain electrodes and MoS₂ was modeled as a Schottky barrier with the thermionic emission model. Detailed parameters are provided in Supplementary Table 3.

Author contributions

L.D. and Y.Z. conceived the project, designed the experiments, performed the data analysis, and wrote the manuscript; Y.Z. prepared the related materials, fabricated the devices, and conducted the simulation, characterization, and measurement. X.J. helped in the design of the device and data analysis. J.C., M.L., and Y.L. assisted in the device fabrication. L.D. supervised this research. All authors contributed to the discussion.

Peer review

Peer review information

Nature Communications thanks Hao-Yu Lan and the other, anonymous, reviewers for their contribution to the peer review of this work. A peer review file is available.

Funding

L.D. discloses support for the research of this work from the National Key Research and Development Program of China (No. 2022YFA1604302) and the National Natural Science Foundation of China (No. 62174005).

Data availability

The Source Data underlying the figures of this study are available with the paper. All raw data generated during the current study are available from the corresponding authors upon request.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-74555-2.