Reversibly Stacked Monolithic 3D Integrated Circuits

Abstract

Monolithic three-dimensional integration enables dense vertical stacking of devices with fine-pitch interconnects, offering a promising route toward high-density, energy-efficient logic and memory systems. However, its implementation is constrained by the thermal budget of back-end-of-line processes, which must remain below 400 °C to avoid degrading underlying circuitry. While various low-temperature semiconductors have been explored, current demonstrations remain confined to fixed stacking sequences due to high-temperature growth or transfer requirements. Here, we demonstrate a M3D complementary field-effect transistor architecture using low-temperature-deposited n-type In₂O₃ and p-type Te semiconductors. This platform resolves existing thermal constraints, demonstrating the design freedom to reverse n- and p-type sequences. This capability enables the integration of CMOS inverters, multilayer logic stacks, and a fully functional 3D SRAM storage cell, all fabricated below 300 °C. This scalable platform provides a practical pathway for constructing vertically integrated complementary logic with intrinsic interconnects, paving the way for next-generation 3D system-on-chip technologies.

Monolithic 3D integration employs low-temperature n-type In2O3 and p-type Te semiconductors, enabling reversible stacking of complementary field-effect transistors. This method maintains fabrication below 300 °C, facilitating efficient logic and memory circuit development for advanced applications.

Introduction

Monolithic three-dimensional (M3D) integration offers a transformative scaling pathway by enabling nanoscale vertical stacking of devices with dense interlayer connections^1,2. It provides a versatile platform to realize heterogeneous system-on-chip architectures for both front-end stacked transistors and back-end logic–memory co-integration, expanding architectural flexibility across circuit layers. However, its implementation is constrained by a strict thermal budget below 400 °C, which limits the use of conventional materials and requires alternative low-temperature processes to avoid damaging underlying transistors and interconnects.

To overcome thermal constraints, the industry has explored low-temperature polycrystalline silicon (LTPS) as a viable option^3,4, given its compatibility with CMOS processing. Two-dimensional (2D) semiconductors, such as MoS₂ and WSe₂, offer van der Waals bonded, atomically thin channels that can be transferred onto target substrates without high-temperature growth, enabling strong electrostatic control and vertical stackability^5–8. Amorphous or polycrystalline indium-gallium-zinc-oxide (IGZO) is another promising candidate, with moderate mobility, low-temperature deposition below 300 °C, and optical transparency^9,10. Carbon nanotubes (CNTs) are also candidates for M3D integration due to their potential for assembly via solution-based techniques within the BEOL thermal budget, enabling all-CNT computers with multifunctional M3D systems^1,11–17. However, each material system presents challenges. LTPS typically still requires thermal annealing near 450 °C and suffers from variability due to grain boundaries. For 2D materials, high-quality 2D films typically require growth temperatures exceeding 600 °C, posing a major limitation for integration. Consequently, large-area transfer is necessary but remains a significant challenge. IGZO devices face long-term reliability concerns, including threshold-voltage instability and bias-stress-induced degradation. For CNTs, large-scale CNT integration with high electronic uniformity remains challenging.

Despite their inherent challenges, the feasibility of M3D integration using these emerging semiconductor materials has been demonstrated. M3D CFETs have been demonstrated using 2D materials or hybrid systems combining other material platforms^18–24. For example, n-type monolayer MoS₂ transistors have been integrated atop p-type Si Fin Field-Effect Transistors to form CMOS inverters at thermal budgets below 200 °C²⁵. Similar efforts have used atomic-layer-deposited indium oxide (In₂O₃) n-type FETs (nFETs) stacked over LTPS p-type FETs (pFETs) to achieve high-gain logic inverters below 450 °C²⁶. In these M3D prototypes, 2D materials have to either be transferred or restricted to the bottom layers to circumvent their growth thermal budget. Similarly, Si-based demonstrations are limited to be used as bottom layers due to high-temperature processing requirements, such as >950 °C rapid thermal annealing for dopant activation. As a result, current M3D demonstrations are constrained to fixed n–p or p–n sequences due to strict thermal budget and process limitations. To fully unlock the potential of M3D platforms, n- and p-type transistors have to be co-integrated with flexible stacking capabilities. Arbitrary stacking order enhances interconnect routing efficiency and thermal management by allowing designers to minimize vertical interconnect length and density, which reduces parasitic delay. However, a platform enabling such freely interchangeable stacking of multiple n- and p-type layers has yet to be realized.

In this study, we demonstrate M3D of a reversibly stacked CMOS architecture based on the complementary field-effect transistor (CFET) configuration, utilizing low-temperature-deposited n-type In₂O₃ and p-type tellurium (Te) semiconductors. We developed a fabrication method for 3D-integrated transistors and circuits at near-room temperature, employing established materials and process technologies. This approach enabled the successful realization of both inverters and a vertically integrated multilayer structure composed of alternating In₂O₃ nFET and Te pFETs. A monolithic 3D static random-access memory (SRAM) storage cell was constructed, validating the reliability of the integration scheme. Notably, all process steps were carried out below 300 °C, ensuring full compatibility with back-end-of-line (BEOL) thermal budgets in conventional silicon technology. This low-temperature, scalable approach significantly simplifies the fabrication of 3D-stacked transistors with intrinsic interconnects, highlighting its strong potential for next-generation logic and memory applications.

Results and discussion

The CFET, a fundamental standard cell for logic gates, is first employed to demonstrate the proposed M3D platform. CFETs consist of vertically stacked nFETs and pFETs that are interconnected and simultaneously controlled by a common gate. As illustrated in Fig. 1a, fabrication began with the bottom-tier FET, where the semiconductor layer was deposited, and contacts were formed. A first gate dielectric was then deposited, followed by the construction of the common gate shared by both tiers. A second dielectric layer was added, and vertical interconnects (vias) were etched to connect the two tiers. Finally, the top-tier FET was fabricated and precisely aligned to complete the CFET stack. The key challenge for CFETs in M3D integration is to meet the sub-400 °C thermal budget to preserve underlying interconnects and circuits. Among all fabrication steps, semiconductor deposition is especially challenging because high material quality and electrical performance typically demand high growth temperatures (a comparison of different M3D platforms based on material selection, integration strategy, thermal budget, and stacking reversibility is shown in Supplementary Table 1). To address this constraint, In₂O₃ and Te are selected as the n- and p-type channel materials (Fig. 1b) due to their ability to deliver high performance at low processing temperatures. In₂O₃ has emerged as a promising n-type option for high electron mobilities exceeding 100 cm²V⁻¹ s⁻¹ even at nanometer-scale thicknesses in the amorphous phase^27,28. Its compatibility with atomic layer deposition (ALD), which enables a low-temperature process with conformal coating compatibility for complex 3D geometries, has recently demonstrated drive currents exceeding 20 mA μm⁻¹(refs. ^29,30). On the p-type side, the scarcity of high-mobility semiconductors that meet M3D thermal constraints has limited device options. Here, Te overcomes this limitation by offering high hole mobility (~100 cm²V⁻¹ s⁻¹) based on a cryogenic deposition technique, making it ideal for sequentially stacked M3D pFETs^31–34. Te thin films were deposited by thermal evaporation at low temperature (−80 °C) to enable the fabrication of high-performance p-FETs³⁵. Leveraging these low-temperature processes of In₂O₃ (250 °C) and Te (0 °C), this material combination enables CFETs with a reversible vertical stacking sequence (n/p and p/n stacking), as shown in Fig. 1b.

Fig. 1. Schematic fabrication process, architecture, and BEOL thermal budget for M3D CFET integration.

a Fabrication process flow for 3D monolithic and heterogeneous integration of In₂O₃ and Te CFET inverters. b The schematic diagram of the reversible stacking M3D CFET integration. The insets are the crystal structures of In₂O₃ and Te. c Thermal budget profile for each fabrication step, highlighting that all processing temperatures remain below BEOL failure thresholds, including low-k dielectric degradation (350 °C to 400 °C), interconnect thermal stress (330 °C to 400 °C), and thermal diffusion barrier failure (500 °C to 550 °C).

In addition to low-temperature semiconductor deposition, all steps in the proposed CFET fabrication were maintained below 300 °C, well within the BEOL thermal budget (Fig. 1c). For the formation of gate dielectrics, Al₂O₃ (20 nm) layer was deposited at 150 °C and HfO₂ (10 nm) layer at 250 °C by ALD. The soft-bake and reverse-bake processes for lithography were carried out at 90 °C and 120 °C, respectively. This low-temperature approach is essential since low-k dielectrics degrade at annealing temperatures above 330–400 °C because of porosity loss and reduced mechanical strength³⁶. Furthermore, repeated thermal cycling near 400 °C can induce cracking in low-k layers around TSV sidewalls^37,38 and diffusion barriers, such as Ta or TiN fail around 550 °C, leading to copper diffusion and reliability degradation^39,40. By keeping all processes well below these critical thresholds, our approach ensures full BEOL compatibility while preventing interconnect damage. Such a sub-300 °C scheme is a key enabler for flexible layout optimization in advanced 3D ICs.

To demonstrate the stacking flexibility of the proposed platform, we first present a CFET with a Te pFET stacked on an In₂O₃ nFET (Fig. 2a), while the reverse sequence will be discussed later. A cross-sectional transmission electron microscopy (TEM) image of the fabricated CFET is shown in Fig. 2b, where both transistors are controlled by a common gate with the HfO₂ layer serving as the high-k dielectric. The energy-dispersive X-ray spectroscopy (EDX) mapping images are shown in Supplementary Fig. 1. The design criteria for complementary logic require closely matched V_T of nFET and pFET for symmetric switching with optimal noise margins. However, achieving this symmetry is challenging. Although the V_T of In₂O₃ can be modulated by adjusting the channel thickness^41–43, buried In₂O₃ channels often exhibit significant V_T drift during the gate-stack process due to the oxygen-scavenging effect of HfO₂ (ref. ⁴⁴). To address this issue, we employed a solution-based surface treatment that stabilizes V_T without post-fabrication annealing and passivates oxygen-related defects in In₂O₃ (ref. ⁴⁵). Note that stabilizing V_T without high-temperature annealing can also be achieved via pre-deposition oxygen plasma treatment⁴⁶ or the use of specific dielectric precursors⁴⁷. With the optimized HfO₂ gate stack, the buried In₂O₃ nFET exhibits enhancement-mode behavior with a V_T of 0.6 V, closely matching the V_T of the Te pFET at 0 V, as shown in Fig. 2c (The output characteristics are shown in Supplementary Fig. 2). The device mobility remains unchanged compared to that of planar In₂O₃ transistors (Supplementary Fig. 3) with an on-currents (I_ON) of 2.3 µA µm⁻¹. To balance I_ON between the two transistors, the Te thickness was tuned, with a 10 nm-thick Te channel achieving an I_ON of 2.3 µA µm⁻¹. The In₂O₃ and Te devices exhibit on/off current ratios of 2 × 10⁷ and 2 × 10⁴, respectively, which are sufficient to ensure proper inverter functionality with clear logic transitions. The inverter function was characterized to validate the complementary operation of the stacked CFET. Here, nFET and pFET share a common gate as the input, and their drains are connected to form the output. The pFET source is biased with V_DD, while the nFET source is grounded (equivalent circuit in Fig. 2d). The voltage transfer characteristics (Fig. 2e) exhibit a clear inverter response, with V_OUT switching from high to low as V_IN increases. A narrow transition region and strong output saturation in the In₂O₃ and Te transistors yield high noise margins, with a gain of 13 V/V at the transition midpoint. Noise margins, extracted from mirrored voltage transfer curves (Fig. 2f), show a symmetrical window of extracted NMH = 0.55 V and NML = 0.60 V at V_DD = 1.5 V, and the voltage transfer curves under V_DD ranging from 0.5 V to 3.0 V are shown in Supplementary Fig. 4.

Fig. 2. Monolithic 3D CFET inverter structure and electrical performance.

a Schematic diagram of M3D CFET integration, where the In₂O₃ nFET is located at the bottom and the Te pFET is located at the top. b Cross-sectional transmission electron microscopy image of the 3D-stacked CFET structure, with false-color highlighting the material layers. c I_D–V_G transfer characteristics of the In₂O₃ nFET and Te pFET, with gate lengths and widths of 5/10 μm and 5/15 μm, respectively. The measurements are performed by sweeping the common gate voltage used in the CFET inverter configuration. d Equivalent circuit diagram of the CFET inverter. e The voltage transfer characteristics and gains of the CFET inverter under V_DD = 0.5–3.0 V. f The extraction of noise margin by mirrored coupling of VTC curve.

To further demonstrate the versatility of our platform, we fabricated a reverse CFET structure with an In₂O₃ nFET stacked on a Te pFET, as illustrated in Fig. 3a. A cross-sectional TEM image of the reverse configuration is shown in Fig. 3b, confirming the precise alignment of the vertical channels. The EDX spectroscopy mapping images are provided in Supplementary Fig. 5. To demonstrate integration flexibility in terms of dielectric selection, both Al₂O₃ and HfO₂ are utilized in this study. Interface trap analysis, hysteresis characteristics^48–50, contact resistance and mobility variance for different dielectrics are shown in Supplementary Information (Supplementary Fig. 6).

Fig. 3. Monolithic 3D CFET inverter structure and electrical performance.

a Schematic diagram of M3D CFET integration, where the Te pFET is located at the bottom and the In₂O₃ nFET is located at the top. b Cross-sectional transmission electron microscopy image of the 3D-stacked CFET structure, with false-color highlighting the channel layers. c I_D–V_G transfer characteristics of the In₂O₃ nFET and Te pFET, with gate lengths and widths of 5/10 μm and 5/10 μm, respectively. The measurements are performed by sweeping the common gate voltage used in the CFET inverter configuration. d The corresponding equivalent circuit diagram of the CFET inverter. e The voltage transfer characteristics and gains of the CFET inverter under V_DD = 7–12 V. f, The extraction of noise margin by mirrored coupling of VTC curve.

The device mobility remains unchanged compared to that of planar Te transistors (Supplementary Fig. 7), with an on-currents (I_ON) of 9.3 µA µm⁻¹ and on/off current ratios of 2.7 × 10³. With In₂O₃ placed on the top tier, its V_T can be finely tuned by low-temperature annealing in controlled nitrogen or oxygen environments^51,52, allowing precise matching of the V_T between the In₂O₃ nFET (V_T = −0.9 V) and the underlying Te pFET (V_T = −0.9 V), as shown in Fig. 3c. Note that the V_T of nFET can be further tuned toward enhancement-mode operation through CF₄ plasma doping techniques (Supplementary Fig. 8). The output characteristics of this configuration are shown in Supplementary Fig. 9. The equivalent circuit and inverter function of the reversely stacked CFET are shown in Figs. 3d and 3e. The voltage transfer characteristics of the reverse CFET inverter (Fig. 3e) exhibit a sharp switching transition, with a maximum voltage gain of 7 V/V at the transition midpoint. Note that the switching threshold V_M is ~ 0.5 V_DD for both stacking cases (Supplementary Fig. 10), confirming that the V_T of In₂O₃ nFET and Te pFET is correctly matched, regardless of the stacking order. Noise margins extracted from mirrored voltage transfer curves show a well-balanced window (NMH = 4.1 V, NML = 3.9 V) at V_DD = 11 V. The voltage transfer curves under V_DD ranging from 5 V to 12 V are shown in Supplementary Fig. 11. These results represent the first demonstration of complementary FETs with arbitrary vertical stacking sequences, highlighting the versatility of our CFET-based M3D platform.

To fully exploit the architectural potential of M3D, >3-layer integrations are necessary to enable the full development of true 3D standard cell libraries, which are critical for overcoming the limitation of 2D cell placement and routing. Here, we demonstrate the first four-layer monolithic 3D integration of alternating n- and p-type transistors, forming an n–p–n–p FET stack. Details of the fabrication flow for this multilayer integration are provided in Supplementary Table 2. Figure 4a presents a schematic cross-section of the multilayer M3D structure, comprising four repeated In₂O₃ nFETs and Te pFETs. Figure 4b shows cross-sectional TEM and EDX spectroscopy mapping images of the multilayers. The results confirm conformal deposition and structural integrity across all layers without interlayer diffusion. Figure 4c–f presents transfer characteristics of different stacked FETs, controlled by common gates. For both In₂O₃ nFET and Te pFETs, the devices show consistent performance regardless of their vertical position in the stacking sequence and detailed statistics analyses of performance are shown in Supplementary Fig. 12. The vertical integration process preserves device quality across all layers with consistent mobility and contact resistance regardless of stack orders. Minor V_T shifts occur due to dielectric capping but can be mitigated through subsequent treatments^51,52. Note that the bias-stress reliability and material stability of the proposed platform are robust, as both material growth and device fabrication have been optimized (Supplementary Figs. 13 and 14). Previous works have demonstrated multilayer nFET M3D stacking using metal-oxide semiconductors and organic transistors^53–56. However, our work is the first to achieve alternating n–p–n–p FET integration using BEOL-compatible processes, which demonstrates the potential of the proposed multilayer M3D technology for realizing high-density and fine-grained 3D integrated circuits.

Fig. 4. Monolithic 3D integration of vertically stacked In₂O₃ nFETs and Te pFETs in a multilayer structure, with structural, elemental, and electrical characterization.

a Schematic illustration of the multilayer M3D structure consisting of four repeated In₂O₃ nFETs and Te pFETs. b Cross-sectional TEM image of the multilayer M3D structure, with false-color layers indicating the channel layers. EDX mapping images show the distribution of In, Te, Ni, Al, and O atoms across the multilayer M3D structure. c–f Transfer characteristics of the ten transistors in each layer: c and e, In₂O₃ top gate devices; d and f, Te bottom gate devices. Each transistor features a gate length and width of 10/10 μm. The consistent performance across layers confirms the uniformity and reliability of the 3D integration process.

To demonstrate the memory capability of the proposed low-temperature M3D technology, we constructed a SRAM cell, as schematically shown in Fig. 5a. The SRAM consists of a storage cell comprising two cross-coupled CFET inverters and an access cell comprising two nFETs (an optical image, Fig. 5a, bottom left). The writing cycle began by applying the desired logic value to the bit lines (BL1 and BL2), e.g., setting BL1 = “1” and BL2 = “0”, which stored a logic 0. When the word line (WL) was enabled, the cross-coupled inverters latched the input, storing the value in the memory cell (circuit diagram, Fig. 5a, bottom right). To verify the storage functionality, a voltage of 0 V was applied to the input (V_IN), driving the output (V_OUT) into logic state 1 (Fig. 5b). When the input was opened, the output remained at logic state 1, confirming data retention. When a voltage of 2 V was applied to write logic state 0, and after opening the input at t = 30 s, the output remained in logic state 0. The dynamic switching behavior was further validated under pulsed input operation with a pulse width of approximately 25 s and V_DD = 2 V (Fig. 5c). The operation of the dynamic output of the storage cell exhibits a reliable storage function of the SRAM under numerous cycles. SRAM implementation in monolithic 3D circuits is challenging because of strict requirements on device matching, stability, and thermal budget. The demonstration of a flip-flop SRAM cell using low-temperature M3D CFETs validates the robustness of our approach for scalable, BEOL-compatible memory integration.

Fig. 5. Illustration of a SRAM cell on In₂O₃ and Te.

a Schematics, optical micrograph, and equivalent circuit of the SRAM cell. b Input and output voltages of the SRAM storage cell. A logic state 1 or 0 at the input voltage can set the output voltage to logic state 0 or 1. Once the input switch is opened, the output state remains latched at logic 0 or 1, confirming the data retention capability. c Repeated write/erase cycles under pulsed input demonstrate stable operation and reliable data retention.

In this work, we demonstrated an M3D platform for complementary logic and memory circuits using low-temperature-deposited In₂O₃ nFETs and Te pFETs. By leveraging atomic layer deposition of In₂O₃ and cryogenic thermal evaporation of Te, we achieved CFETs with reversible vertical stacking (n/p and p/n) and extended this approach to a four-layer n–p–n–p FET stack, with all fabrication temperatures kept below 300 °C. The successful implementation of a monolithic 3D SRAM cell further validates this platform's robustness for both logic and memory integration. The channel materials demonstrated here, including In₂O₃ and Te, already exhibit scalability^29,57, making them promising for future M3D integrated circuits, with the dimensions needed to match mature-node SRAM performance (~250 ps read access delay at V_DD < 1 V) detailed in the Supplementary Information. Nonetheless, further scaling is required to fully realize the platform’s potential (scaling discussion in the Supplementary Information). Recent research has shown promising scaling capabilities and enhanced performance, as these materials are inherently well-suited to aggressive gate-length reduction while maintaining high mobility at ultra-thin limits. Additionally, material-specific challenges remain. Te requires improved thermal stability for reliable high-current operation, while In₂O₃ needs enhanced interface engineering to address reliability issues such as bias stress effects. Addressing these challenges will be essential for manufacturable M3D logic–memory architectures. With continued material optimization and further scaling, this technology provides a viable path toward high-density, energy-efficient 3D logic–memory systems, positioning M3D technology as a cornerstone for post-CMOS computing and heterogeneous system integration.

Methods

Synthesis of Te films

Te thin films were deposited using a thermal evaporator system with a base pressure of about 2 × 10⁻⁶ torr. Te pellets (99.999%) were loaded into a tungsten boat positioned beneath the substrate. The substrate, SiO₂ on p⁺⁺-Si was affixed to a sample chuck using Kapton tape. The chuck was cooled using the nitrogen gas flow. A negative photoresist (AZ5214E) was used to define the pattern on the substrate. When the pressure reached 2 × 10⁻⁶ torr, the substrate temperature was lowered to −80 °C by a cooled nitrogen gas flow before the evaporation. The deposition rate (around 0.5 Å s⁻¹) and film thickness were monitored using a quartz crystal microbalance. After deposition, the Te film was crystallized at 0 °C for 30 minutes while remaining on the cooled chuck. For patterned samples, the photoresist was removed by a lift-off process after crystallization.

Synthesis of In₂O₃ films

In₂O₃ thin films were deposited by ALD at 250 °C using (CH₃)₃In and H₂O as the In and O precursors, respectively. N₂ was used as the carrier gas. The base pressure at the N₂ flow rate of 0 s.c.c.m. was 5 × 10⁻² torr.

Fabrication processes of CFETs

The CFET fabrication began with standard cleaning procedures on a p⁺⁺-Si substrate coated with 50 nm of thermally grown SiO₂. In₂O₃ thin films were deposited by ALD at 250 °C using (CH₃)₃In and H₂O as precursors. Photolithography and diluted HCl etching were used to define the In₂O₃ active area. Subsequently, 30 nm of Ni was deposited by electron-beam evaporation following lithography patterning, and the lift-off process was performed to form the S/D contacts. A solution-based treatment using 30% H₂O₂ was applied for 10 minutes before the gate dielectric deposition. Next, 10 nm of HfO₂ was deposited by ALD using [(CH₃)₂N]₄Hf as the precursor and O₂ plasma as the oxygen source. The ALD process was carried out at 250 °C with a plasma power of 300 W. Gate electrodes were formed by depositing 30 nm of Ni via e-beam evaporation. Contact holes were defined using standard photolithography and etched by BCl₃/Ar plasma. A negative photoresist (AZ5214E) was then applied to define the pattern for the Te active area. Te thin films were deposited by thermal evaporation onto the bottom In₂O₃ nFET. After deposition, the photoresist was removed by lift-off, and Ni S/D were formed by e-beam evaporation. The other stacking configuration, in which Te was used as the bottom pFET and In₂O₃ as the top nFET, was fabricated using a similar process. In this case, Al₂O₃ was employed as the gate dielectric and deposited by ALD using Al(CH₃)₃ as the precursor and O₂ plasma as the oxygen source. The ALD process was carried out at 150 °C with a plasma power of 300 W. Contact holes were defined by standard photolithography and opened by wet etching using (CH₃)₄NOH.

Transmission electron microscopy

Cross-sectional TEM and STEM analyses were carried out using a Thermo Fisher Talos F200 operated at an accelerating voltage of 200 keV. The system provided a TEM resolution of 0.25 nm and a STEM resolution of 0.16 nm. Elemental analysis was performed using an integrated Super-X EDX detector with an energy resolution of ≤136 eV. Specimens were prepared using focused ion beam (FIB) milling on a Thermo Fisher Helios G4 dual-beam system. During FIB preparation, the electron beam was operated at accelerating voltages up to 30 keV, and the ion beam was operated at voltages up to 30 kV using a Ga ion source to achieve site-specific lamella thinning and cross-sectional precision.

Electrical measurements

Electrical characterization of the fabricated devices was performed using an Agilent B2902B source meter and a probe station under vacuum conditions. The V_T of the In₂O₃ and Te transistors was extracted using the linear extrapolation method. For MOSFETs operating in the linear regime (V_D < V_G – V_T), the I_D–V_G curve was linearly fitted and extrapolated to I_D = 0. The V_T was then obtained by adding V_D/2 to the intercept voltage.

Author contributions

T.-T.W., S.-T.W. and D.-H.L. conceived the idea. T.-T.W. performed the device fabrication and the measurement. S.-T. W., K.-W. L., Y.-C.C. and R.T. help the thin film growth. C.-C.C. (Chia-Chen Chung) and C.-H. L. carried out the TEM and EDX analysis. T.T.C. designed and developed the ALD tools. S.-C.C. designed and developed the Low-T PVD tools. T.-T.W., S.-T.W. and D.-H.L. analyzed the data. I.R., TYT H., C.-C.C. (Chao-Ching Cheng) provided scientific guidance throughout. Y.-L.C. and D.-H. L. supervised the research. T.-T.W., S.-T.W. and D.-H.L. prepared the paper draft. All the authors contributed to the discussion and manuscript preparation and read the final manuscript.

Peer review

Peer review information

Nature Communications thanks Sanghyeon Kim, Kunjesh Agashiwala, and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

This work was supported by the National Science and Technology Council (NSTC), Taiwan, under Grant No. of NSTC 115-2112-M-A49-009. This work was in part supported by NSTC T-Star Center Project: Future Semiconductor Technology Research Center under NSTC 115-2634-F-A49-009 -. This work was partially supported by the NSTC under Grant No. 114-2634-F-A49-006, 113-2112-M-007 −034 -MY3, 114-2119-M-007 −015 -MBK, and 114-2628-E-007-001. The research was also supported by the Taiwan Semiconductor Manufacturing Company. D.H.L. acknowledges the Yushan Scholar Program by MOE in Taiwan.

Data availability

The source data generated in this study are provided in the Source data file. Source data are provided with this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-75242-y.