A new step-up quadratic DC/DC converter based on coupled-inductor

Abstract

This article introduces a novel ultra-high voltage gain DC-DC converter with a low component count, designed for renewable energy applications. In the presented topology, a three-winding coupled-inductor (TWCI) and a switched-capacitor network are embedded within a classic quadratic boost converter. This arrangement yields high voltage gain, ensures continuous low-ripple input current, and preserves a common ground between the source and the load. Due to its trans-inverse feature, the circuit achieves ultra-high voltage gain even with a very low turns ratio in the TWCI. The topology also features current sharing between the TWCI and the main power switch, which significantly reduces power losses in the main power switch and coupled-inductor device. To limit voltage stresses on the active switches, the circuit integrates two passive regenerative clamp circuits, with the switches themselves operated using simultaneous switching patterns. The paper provides detailed steady-state analysis, power loss calculations, comparative evaluation, and design considerations. Finally, a laboratory prototype rated at 200 W has been implemented to verify the theoretical analysis, achieving a very high voltage conversion from 20 V input to 400 V output.

Introduction

Driven by growing environmental concerns and the depletion of fossil fuels, renewable energy sources (RES) such as wind, solar, and photovoltaic systems have emerged as key sustainable alternatives. The significant voltage gap between renewable energy sources (e.g., PV panels at 20–50 V) and a standard 400 V DC bus requires a high-gain DC-DC converter as an interface circuit¹. The use of high step-up converters extends beyond renewable energy to applications such as solar inverters, lighting systems, industrial systems, automotive and railway technology, portable electronics, telecommunications infrastructure, data centers, and medical devices. An effective high step-up DC-DC converter interface should deliver a high conversion ratio, under low switch voltage stress, and high efficiency, while also being cost-effective¹. Drawing a non-pulsating input current is critical for preserving the performance and longevity of a PV array². The low component count, cost-effectiveness, and compact design of non-isolated structures make them a preferable option for low-power applications¹.

Although the conventional step-up DC-DC converters like the Boost and SEPIC offer topological simplicity and continuous input current with low ripple, their performance at high duty cycles to provide high voltage gain is fundamentally constrained by parasitic effects, which limit both voltage gain and efficiency. Several effective voltage boosting techniques have been developed to overcome the challenges posed by high duty cycles in step-up DC-DC converters. These include voltage-lift circuits, switched-capacitor and switched-inductor networks, specialized gain-extension cells, and cascaded converter stages^1–4. These approaches, however, suffer from a significant limitation: the high conversion ratio is often achieved through excessive component usage, hard switching, and diode reverse recovery issues, each of which degrades performance^3,4. Coupled-inductor (CI) structures with two or three windings provide a significant performance boost in step-up converters. Their inclusion allows the turns ratio to contribute to the gain equation, enabling high voltage gains at moderate duty cycles and thus enhancing overall efficiency^5,6. A major design challenge, however, is managing the leakage inductance energy in the CI, which requires the use of either an active or passive clamp circuit^7,8.

A proven and effective strategy for attaining superior voltage gain is to integrate CI structures with other boosting techniques, such as switched-capacitor networks. Building on this concept, researchers have proposed many hybrid converter topologies. Quadratic DC-DC topologies represent an efficient solution within step-up DC-DC converters, delivering high voltage gain while using fewer components³. These topologies are characterized by a conversion ratio that scales quadratically with the duty cycle, a property that facilitates ultra-high voltage gains.

A wide range of high-performance, coupled-inductor-based quadratic topologies have been introduced in the literature. The literature reports several quadratic DC-DC converter topologies that achieve high voltage gain through the integration of coupled inductors, voltage multiplier (VM) cells, and cascaded conventional quadratic circuit^9–13. A critical evaluation, however, reveals two inherent limitations: considerable power dissipation in the input diodes and elevated current stress on the high-power-side components. To address this issue, novel quadratic two-winding CI-based step-up topologies were introduced in^14–16. These innovative high step-up circuits integrate cascaded boost stages with a current-sharing mechanism involving the input inductor and the coupled inductor. This configuration significantly reduces power losses in the magnetic components. Nevertheless, these structures exhibit a relatively high input current ripple due to the parallel connection between the CI and the input inductor. To solve it, a two-switch step-up topology with coupled inductor have been presented in¹⁶ to achieve higher voltage gain under low input current ripple. Furthermore, a novel single-switch quadratic high step-up DC-DC converter utilizing a coupled inductor (CI) was presented in¹⁷. While it successfully reduces switch voltage stress and input current ripple to achieve a very high conversion ratio, the topology is fundamentally limited by its lack of a common ground along with high power losses in the input diodes. Additionally¹⁸, proposed an ultra-high double-switch step-up quadratic DC–DC converter utilizing a three-winding coupled inductor with low input current ripple.

Recent research has focused on trans-inverse and semi-trans-inverse coupled-inductor topologies for step-up DC-DC converters. These designs enable a high voltage gain using a very low turns ratio, which in turn reduces winding losses and improves the utilization of the magnetic core^19,20.

Recent research has considered trans-inverse or semi-trans-inverse coupled-inductor topologies for step-up DC-DC converters. A key advantage of these structures is that high voltage gain can be realized with a very low turns ratio, thereby minimizing wire consumption and improving magnetic utilization^19–21. New families of single-switch, high step-up soft-switching integrated SEPIC converters with TWCI and low input current ripple were proposed in^22–26. However, despite employing trans-inverse coupled-inductor configurations, these converters fail to achieve ultra-high voltage gain. References^27,28 introduced two new expandable high step-up soft-switching integrated boost-SEPIC converters. These designs incorporate a Y-source coupled inductor with a trans-inverse feature. Additionally, new Y-source trans-inverse high step-up DC-DC structures with continuous input current were introduced in^29,30. However, these circuits lack a common ground between the input and output sides, which restricts their practical applications.

Quadratic step-up DC-DC converters with trans-inverse characteristics have recently emerged as a focus of research interest. These structures enable very high voltage gains using only a small number of turns and low duty cycles. A novel non-isolated single-switch high step-up DC/DC converter was presented in³¹, featuring a three-winding coupled inductor (TWCI) integrated into a conventional quadratic topology. The design achieves low input current ripple and low voltage stress on the switch. A notable drawback, however, is the substantial power dissipation in the input diodes, which are subjected to high average currents. Reference³² introduced a high step-up quadratic DC-DC converter utilizing a Y-source coupled inductor. While the converter offers a high voltage gain, its applicability is limited by the absence of a common ground and the need for three separate magnetic cores. A novel quadratic trans-inverse DC-DC converter with very high voltage gain, enabled by a three-winding coupled inductor (TWCI), was proposed in³³. Despite this advantage, the topology requires large input and magnetizing inductors to maintain low input current ripple.

This paper presents a novel quadratic DC-DC converter designed to overcome the limitations of existing high step-up topologies for RES applications. The proposed solution delivers high voltage gain and low input current ripple, with its main advantages summarized below:

1- Ultra-high voltage gains under low turns ratios of TWCI and duty cycle.

2- Trans-inverse characteristic;

3- Three designing freedom degrees;

4- Low current stress for the power MOSFET;

5- Continuous input current with low ripple;

6- Very low switch voltage stress;

7- Simultaneous operation of two power switches;

8- Shared common ground between input and output;

This work provides a comprehensive account of the proposed converter, covering its operational principles, steady-state analysis, comparative performance evaluation, and practical design considerations. The theoretical analyses are substantiated through experimental validation using a laboratory prototype, which achieves a voltage gain of 20.

Structure and operation principles of the proposed converter

The proposed circuit topology, illustrated in Fig. 1, comprises a three-winding coupled inductor (TWCI), an input inductor (L_in), two simultaneously-operated active switches (S1 and S2), four capacitors (C₁, C₂, C₃, and C_o), and four diodes (D₁, D₂, D₃, and D_o). Two regenerative clamp circuits, formed by C₁-D₁ and C₂-D₂, limit the voltage stress across the active switches S₁ and S₂. Furthermore, the energy stored in the coupled inductor’s leakage inductance (L_k) is recycled to capacitor C₂ and subsequently transferred to capacitor C₃. To enhance the voltage gain, the secondary and tertiary windings of the coupled inductor in this topology are combined with voltage multiplier cells. A resonant tank, comprising the CI windings and capacitors C₁, C₂, and C₃, is incorporated to mitigate conduction and switching losses. Additionally, the leakage inductance (L_k) of the TWCI enables soft commutation of the output diode Dₒ, suppressing its reverse recovery issue. Consequently, switching-frequency noise on the output DC voltage is significantly reduced.

Fig. 1.

Proposed converter schematic.

To simplify the steady-state analysis of the presented topology, the voltages of the capacitors are considered to be a constant value. Also, the coupled-inductor is modeled as an ideal transformer with two turns ratios (n₂₁=N₂/N₁ and n₃₁=N₃/N₁₎, a magnetizing inductor (L_M) and also a merged leakage inductor (L_k). The main theoretical waveforms of the proposed converter operating in Continuous Conduction Mode (CCM) are illustrated in Fig. 2. Furthermore, the equivalent circuits for each operating mode during one switching period are presented in Fig. 3.

Fig. 2.

Steady-state theoretical key waveforms of the proposed converter in CCM operation.

Fig. 3.

Equivalent circuits of the proposed converter; (a) Mode-1, (b) Mode-2, (c) Mode-3, (d) Mode-4 and (c) Mode-5.

Mode-1 [t₀ - t₁

At t = t₀, both active switches S₁ and S₂ begin conducting simultaneously. As shown in the equivalent circuit of Fig. 3(a), the unique topology of the proposed converter ensures that S₂ achieves zero-current switching (ZCS) turn-on. In this short mode, diode Dₒ is still conducting from the previous mode. At the mode’s end, however, the leakage inductance reflected to the TWCI’s tertiary side forces the current in Dₒ to zero, enabling lossless reverse recovery (LRR).

Mode-2 [t₁ – t₂

Figure 2(b) shows that at mode start, diode D₃ turns on with a gentle current slope. In this mode, L_M is charged from the capacitor C₁, while L_in is charged from the input DC source. Concurrently, energy is transferred from clamp capacitor C₂ to capacitor C₃. In this mode, the output capacitor supplies the load resistor. During this interval, with the coupling coefficient defined as k = L_M/(L_M+L_k), the following equations can be derived.

1

2

3

To reduce switching losses, a resonant tank is integrated without adding extra components. As shown in Fig. 3(b), this tank utilizes the middle capacitors (C₁, C₂, C₃) and the leakage inductance of the TWCI. During this mode, the leakage inductance current, switches currents, and the current through diode D₃ all exhibit a sinusoidal waveform. Based on the converter’s topology, the resonant frequency is determined to be:

4

Here, L_k2 represents the reflected leakage inductance of the TWCI on the secondary side. Also, the parameter X₁ is defined as:

5

It is important to note that for optimal performance, the resonant period should be designed to be close to the switching period of the circuit switches, satisfying 0.5T_r≤DT_S. This interval terminates upon the turn-on of diode D₃.

Mode-3 [t₂ – t₃

During this operating mode, the power switches S₁ and S₂ remain ON. As shown in Fig. 3(c), the magnetizing inductor of the TWCI and the input inductor L_in are energized by capacitor C₁ and the input DC source, respectively. Consequently, their currents continue to increase linearly.

Mode-4 [t₃ – t₄

This state, shown in Fig. 3(d), begins at t = t₃ with the turn-Off of switches S₁ and S₂. Concurrently, diodes D₁, D₂, and the output Dₒ start conducting, which clamps the switch voltage stresses. The secondary-side leakage inductance of the coupled inductor ensures that the current in diode D₂ reaches zero during this mode, facilitating zero-current switching turn-off and eliminating reverse recovery loss. For this mode, the following equations apply.

6

7

8

Mode-5 [t₄ – t₅

As shown in Fig. 3(d), only the clamp diode D₁ and the output diode Dₒ conduct during this interval. Similar to the previous mode, the energy stored in the input inductor L_in is delivered to capacitor C₁. Furthermore, the output capacitor C_o receives energy from both the magnetizing inductor and capacitor C₃ via the output diode D_o.

Steady-state analysis

A steady-state analysis of the presented topology is conducted in this section. To facilitate the derivation of key voltage gain and stress relationships, the influence of the leakage inductances and the short-duration modes are ignored.

Voltage gain ratio

Applying the volt-second balance principle to the input inductor L_in and the magnetizing inductor L_M, and utilizing Eqs. (1)–(2) and (6)–(7), the voltages across capacitors C₁ and C₂ are determined.

9

10

Here, D denotes the duty cycle of the switches. Substituting Eqs. (2) and (9) into (3) yields the voltage across capacitor C₃ as:

11

Using (8), the ideal CCM voltage gain of the proposed circuit is obtained as:

12

Because proper design and construction of coupled inductors typically produce a coupling coefficient of approximately 0.98, this value can be reasonably approximated as k = 1. Accordingly, the ideal voltage gain equation is given as follows:

13

From (13), the converter’s voltage gain varies exponentially with n₂₁ and quadratically with D. Thus, the gain can be easily tuned across a wide range via three control parameters: D, n₂₁, and n₃₁. Figure 4 plots the voltage gain of the proposed converter against duty cycle for selected values of the TWCI turns ratios n₂₁ and n₃₁. Also, Fig. 5 presents a three-dimensional (3D) plot of the voltage gain ratio. The figures demonstrate that the circuit can produce ultra-high voltage gains across a broad duty-cycle range without necessitating large duty cycles or high turns ratios, resulting in reduced conduction power losses. According to (13), as the turns ratio n₂₁ approaches unity (n₂₁→1), the converter’s voltage conversion ratio increases markedly, demonstrating a semi-trans-inverse behavior. Thus, by increasing n₂₁ toward unit, high voltage gains can also be obtained under fewer turns of the TWCI, which leads to less ohmic losses.

Fig. 4.

The voltage gain ratio of the proposed converter versus D and several values of n₂₁ and n₃₁.

Fig. 5.

3-D plot of the voltage gain versus D, n₂₁ and n₃₁.

Switching Component Voltage and Current Stresses

The maximum voltage stresses on the switching components, determined by the distinct operating modes of the proposed circuit, are derived as:

14

15

16

17

As indicated by (14)–(17), the voltage stresses across the switching components of the proposed topology are lower than the output voltage. Also, with respect to the performance of the proposed circuit, the average current value of the magnetic component L_M is expressed as follows:

18

Here, M and I_o denote the voltage gain and load current of the topology. The average currents of the converter diodes are also estimated as:

19

20

The instantaneous and the root-mean-square (RMS) current values of the switches are given as follows:

21

22

23

24

Here, X₁ and X₂ are defined as follows:

25

26

Additionally, the switch currents at turn-off are given by:

27

28

Finally, the RMS currents of the capacitors and the TWCI windings are calculated as:

29

which, X₃ is defined as follows:

30

31

32

33

34

35

36

Figure 6 shows the peak and RMS currents of the switching devices for V_o=400 V, n₂₁=0.5, n₃₁=0.5, and R_o=800 Ω. The data indicate that choosing 0.1 < D < 0.6 minimizes current stress on the power components, thereby simplifying component selection and improving overall converter efficiency.

Fig. 6.

Peak and RMS currents of the semiconductor switches versus duty cycle.

Efficiency estimation

This section presents the power loss analysis of the proposed converter. The main parasitic components of the converter are summarized in Table 1. Power losses in switched-mode DC–DC converters mainly occur in four components: switches, magnetic parts, diodes, and capacitors. The estimated power losses of the proposed converter are determined as follows:

Table 1.

The main parasitic parameters of the converter.

Parameter	Description
rDS(ON)	ON-state resistance of the active switch (MOSFET)
ESRi	Equivalent Series Resistance of the converter capacitors
VFDi	Threshold voltage of the converter diodes
rD	Diodes’ Resistance in Forwarding State
rLin, rNi	Parasitic resistances of the magnetic components (Lin, and CI)

Active Switches

The power loss of S₁ and S₂ are given by.

37

Where t_on and t_off are the turn-on and turn-off times of the switches.

Diodes

The diode power losses in the circuit are determined as.

38

Capacitors

The capacitor power losses are given by.

39

Magnetic Devices

The copper and core losses of the magnetic components (L_in and CI) are calculated as.

40

Figure 7 illustrates the estimated theoretical efficiency and non-ideal voltage gain of the proposed structure versus the duty cycle and the key parameter n₂₁. The curves are obtained for, V_in = 20 V, R_L = 800 Ω, f_s = 50 kHz, n₃₁=0. 5, r_DS1 = r_DS2 = 7.6 mΩ, t_off = t_on = 4 ns, ESR_C1 = ESR_C2= ESR_C3=10 mΩ, ESR_Co = 30 mΩ, V_FD1= 0.54 V, V_FD2=V_FD3 = V_FDo= 0.65 V, r_N1 = 12 mΩ, and r_N2 = r_N3 = 7 mΩ. As observed, the proposed converter achieves very high voltage gain while maintaining high power-handling capability.

Fig. 7.

Theoretical efficiency and non-ideal voltage gain of the proposed circuit versus duty cycle and n₃₁.

Performance comparison

In this section, to highlight the merits of the proposed converter, its key performance indicators are compared with those of other similar high-gain converters, as summarized in Table II. To ensure a fair comparison, the turns ratios of the coupled-inductor (CI)–based converters listed in Table II are selected as n₂₁=0.6, n₃₁=0.4 for the three-winding coupled inductor, and n=n₂₁+n₃₁=1 for the two-winding coupled inductor.

Voltage Gain

Figure 8 presents the voltage gain versus duty cycle for the proposed topology and existing converters listed in Table II. The results indicate that the proposed converter, along with the designs in^14,18,32, and³³, achieves superior voltage gain across a wide duty cycle range. Although the converters in^{18] and[32} attain higher voltage gains, they require a greater number of components. Furthermore, the converter in^{14] and [33}, which offers a voltage gain comparable to the proposed design, exhibits significant input current ripple.

Fig. 8.

Voltage gain comparison of the proposed converter and the other similar converters introduced in Table 3.

Normalized Voltage Stress

Figures 9 and 10 present the normalized maximum voltage stresses of the power switches and diodes for the compared converters. As observed, the proposed topology exhibits low switch voltage stress over.

Fig. 9.

Comparison of normalized voltage stress of the main power switch.

Fig. 10.

Comparison of normalized maximum voltage stress of the diodes.

the entire duty cycle range while maintaining acceptable low diode voltage stress. Consequently, lower voltage-rated switches and diodes can be utilized, which reduces switching and conduction losses and improves the overall converter efficiency.

Moreover, Table 2 summarizes the estimated costs and power densities of the converters in the comparison table evaluated at an identical operating point (200 W, 20 V/400 V, n₂₁=0.6, n₃₁=0.4, n=n₂₁+n₃₁=1, ΔI_Lin = ΔI_LM=2 A, and 50 kHz). To ensure a fair comparison, all magnetic components were optimally designed using the same methodology, and component pricing was sourced from major electronics distributors (Mouser, DigiKey, and element14 websites). Semiconductor elements in different current and voltage stresses are selected from the same brand, including the IRF, SUP, and BSC series for MOSFETS, MBR and MUR series for diodes, ECA series from Panasonic industry for capacitors and ferrite cores from EPCOS (TDK) for magnetic components. It should be noted that the Power density values were calculated from the total volume of the magnetic components and capacitors. According to this table, among the converters in the comparison table, the power density of the proposed converter with current sharing property along with the converters in^14,18,21, and³³ are at the highest level. Therefore, due to the unique structure, using three winding CI in the proposed converter does not lead to a decrease in power density. Also, as shown in the table, the proposed converter maintains a highly competitive overall cost. Furthermore, Table 3 also provides a comparison of the reliability of the converters. It is worth noting that the components’ failure rates are estimated based.

Table 2.

Performance comparison of the proposed converter with other counterparts.

Converter Topology	No. of Components	Voltage Gain	I.C.R	Voltage Stress on Main Power Switch	Maximum Voltage Stress on Diodes	C.G
	S/D/C/CI + L/T
5	1/4/5/13w +1/12		Low			Yes
6	1/4/5/13W +1/12		Low			Yes
8	1/4/5/12W +1/12		Low			Yes
13	1/5/6/13w +1/14		Low			Yes
14	2/4/4/12w +1/12		High			Yes
18	2/5/5/13W +1/14		Low			Yes
21	1/5/6/13w +1/14		Low			Yes
22	1/3/4/13w +1/10		Low			Yes
23	1/4/5/13w +1/12		Low			Yes
26	1/4/5/13w +1/12		Low			Yes
29	2/3/5/13w +1/12		Low			No
30	1/4/5/13W +1/12		Low			No
32	2/4/5/13W +2/14		High			No
33	2/4/4/13w +1/12		High			Yes
Proposed Converter	2/4/4/13w +1/12		Low			Yes

S = Switch, D = Diode, C = Capacitor, CI = Coupled-Inductor, L = Inductor, T = Total Device, I.C.R = Input Current Ripple, C.G=Common Ground.

Table 3.

The comparison of the electrical especifications of the converters.

Converter	[5]	[6]	[8]	[13]	[14]	[18]	[21]	[22]	[23]	[26]	[29]	[30]	[32]	[33]	Propo.
fs (kHz)	60	50	50	100	50	50	50	50	100	50	50	50	50	50	50
Pout (W)	250	250	100	300	200	200	200	150	200	200	300	28	24	200	200
Vin (V)	20	25	36	48	26	22	25	25	32	37.5	30	300	400	25	20
Vout (V)	200	400	380	600	400	400	400	200	380	400	300	380	400	400	400
Voltage Gain	10	16	10.5	12.5	15.3	18.2	16	8	11.8	10.6	10	10.7	16.6	16	20
M. Eff. (%)	95.7	96.4	96.5	95.8	94.2	92.8	96.6	94.8	93	95.2	95.5	94.6	96.3	96.5	96.0
P.D. (w/cm3)	1.74	2.2	2.44	2.19	2.7	2.87	2.91	2.23	2.34	2.3	1.7	2.2	2.52	2.75	2.96
Cost $	23.8	22.3	29.5	30	23.8	25	20	19.6	19.9	20.3	25.3	22.7	21.6	23	23
Failure rate ()	7.72	6.29	7.56	7.91	8.2	8.84	6.17	7.79	6.14	7.43	8.8	7.19	8.95	8.19	8.07

M. Eff.=Measured Efficiency, P.D. =Power Density, C.C.= Control Complexity.

on the widely adopted Military Handbook for reliability prediction of electronic equipment, MIL-HDBK-217 F^{34] and [35}. The proposed topology uses two switches, which increases the parameter λ_p. Nevertheless, its failure rate remains at an acceptable level compared to other converters. Consequently, the proposed converter outperforms other related step-up topologies under the same conditions.

Design considerations

The minimum inductances of L_in and the magnetizing inductor L_M in the coupled inductor are determined as follows:

41

42

which, ΔI_Lin and ΔI_Lm are the allowable current ripples. To optimally design the magnetic core for the input inductor and TWCL, the parameter A_P (product of window winding area cross-sectional area) is employed, defined as follows:

43

Here, K_u denotes the window utilization factor, K_t is a constant value 48,200, is the ratio of iron loss to copper loss, B_max is the maximum flux density, L is the inductance value, is the peak current of the magnetizing inductor, K_i is current waveform factor and is the allowable temperature rise. Then, after selecting the core type, the required turns ratio for the input inductor and the primary side of the TWCI are obtained as follows:

44

which, A_L is the inductance per turn, extracted from the relevant datasheet. Also, regarding Figs. 4, 5 and 6, the optimal design parameters for the proposed converter are 0.1 < D < 0.6 and n₂₁<0.75. This region ensures high voltage gain with minimum current stress and serves as the best starting point for the converter’s design. Finally, the turns ratio n₃₁ is selected according to the desired voltage gain. Furthermore, according to the charge balance principle, the required capacitance values in the circuit are given as:

45

46

47

48

Here, denotes the maximum permissible voltage ripple of the capacitors. Furthermore, to realize the desired quasi-resonant operation, where T_R/2D.T_S, the conditions derived from (49) must satisfy the following:

49

In high step-up converters, the recommended output voltage ripple is around 1%. However, the middle capacitors of the proposed converter are not performing any filtering effect. Thus their design can be done at larger allowable voltage ripples.

Experimental verification

A 200-W laboratory prototype with a voltage gain of M = 20 is implemented to verify the performance of the proposed converter. The prototype parameters are summarized in Table 4. The voltage and current waveforms of the experimental prototype are captured using a high-frequency current probe (PA-667) with sensitivities of 500 mV/A and 50 mV/A, and a differential voltage probe (GDP-025) with attenuation factors of ×20, ×50, and ×200.

Table 4.

Key parameters of prototype setup.

Parameter	Description
Output Power (Pout)	200 W
Input Voltage (Vin)	20 V
Output Voltage (Vo)	400 V
Switching Frequency (fs)	50 kHz
Capacitor C1	15 µF / 100 V
Capacitor C2	2.2 µF / 250 V
Capacitor C3	100 µF / 250 V
Capacitor Co	10 µF / 450 V
Power Switches S1 and S2	IPP076N15N5/ RDS(on) = 7.6 mΩ
Inductor Lin / Core	100 µH / T184-52
Magnetizing Inductor of the CL (LM)	350 µH
Turns Ratios of the TWCI / Core	(0.50:0.50) / EE42/21/20
Diodes D3, Do	MUR440
Diode D2	MUR420
Diode D1	MBR10100

The experimental waveforms of the input and leakage inductor currents (i_Lin and i_Lk1) together with the output DC voltage are shown in Fig. 11. It can be observed that the proposed converter achieves a high output DC voltage (V_o=400 V) while maintaining minimal voltage spikes during switching instants. As shown in Fig. 12, the main power switch S₁ experiences low current stress and voltage stresses (I_S1(Peak)=12 A and V_DS1=40 V) during operation.

Fig. 11.

Experimental results of V_o, i_Lin, and i_LK1.

Fig. 12.

Experimental results of the power MOSFET S₁.

Moreover, Fig. 13 shows that switch S₂ turns on under ZCS conditions with low voltage stress about V_DS2=90 V and very low current stress I_S2(Peak)=8 A. The quasi-resonant behavior of the active switches during Mode 2 alleviates the current level at the turn-off instant. The reduced voltage stress allows the use of MOSFETs with very low on-state resistance R_DS(on). The experimental diode waveforms of the converter are shown in Figs. 14, 15, 16 and 17, which closely match the results obtained from the theoretical analysis. The diodes experience the following voltage stresses: V_D1=40 V, V_D2=130 V, and V_Do= V_D3=300 V.

Fig. 13.

Experimental results of the MOSFET S₂.

Fig. 14.

Experimental results of the diode D₁.

Fig. 15.

Experimental results of the diode D₂. (LRR = Low Reverse Recovery.)

Fig. 16.

Experimental results of the diode D₃.

Fig. 17.

Experimental results of the diode D_o.

Figure 18 shows the current waveforms of the TWCI secondary and tertiary windings. Figures 19 and 20 illustrate the measured efficiency versus output power as well as the theoretical loss distribution of the components. Under the load conditions (Table III), the presented converter achieves a measured efficiency of approximately 96.0%. Also, Table 5 details the component loss analysis for the proposed converter at P_o=200 W. The dynamic response to a load step change from 140 W to 200 W is illustrated in Fig. 21, verifying the converter’s capability to regulate the output at 400-V DC. A photograph of the implemented laboratory prototype is shown in Fig. 22.

Fig. 18.

Experimental results of i_Lk2 and i_Lk3.

Fig. 19.

The measured and theoretical efficiencies of the proposed converter versus output power.

Fig. 20.

Estimated loss distribution profile of the introduced converter under the rated power (20 V / 400 V) / 200 W).

Table 5.

Loss distributions of the proposed converter.

Components	Power loss relations	Loss value (w)	Percent (%)
Inductor Lin		0.7	10.2
TWCI		0.53	7.7
MOSFET S1		0.59	8.5
MOSFET S2		0.26	3.7
D1		1.91	27.6
D2		0.32	4.6
D3		0.35	5
Do		0.35	5
C1		0.48	6.9
C2		0.02	0.28
C3		0.03	0.4
Co		0.005	0.07

Fig. 21.

Dynamic response with a PI controller under a step load change.

Fig. 22.

A photograph of the lab-scale of the converter at P_o=200 W.

Conclusion

A novel double-switch ultra-high-voltage-gain quadratic DC–DC converter with low component counts and low input current ripple. In this circuit, by employing the TWCI, ultra-high voltage gain can be achieved without the requirement for high turns ratios or extreme duty cycles. The proposed topology offers several advantages, including high voltage gain, low-ripple continuous input current, low current and voltage stresses, trans-inverse characteristics, and high efficiency. The leakage inductance energy is recycled by two regenerative passive clamp circuits, thereby reducing the maximum voltage stress on the active switches. The merits of the proposed converter are assessed through a comparative study with existing counterparts. To validate the feasibility of the proposed structure, a 200-W prototype with a high voltage gain of M = 20 (V_in=20 V and V_o=400 V) is developed. The experimental results show that the converter achieves 96% efficiency at full load, demonstrating its potential for renewable energy applications.

Author contributions

Sara Hasanpour: conceptualisation, data curation, formal analysis, investigation, methodology, project administration, resources, software, supervision, validation, visualisation, writing- review and editing.

Funding

The author received no specific funding for this work.

Data availability

Data is provided within the manuscript.

Declarations

Competing interests

The authors declare no competing interests.