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. 2026 Apr 9;6(4):537–548. doi: 10.1021/acsnanoscienceau.6c00003

Introduction of Tunneling Oxide and Oxidation Process Effects for Reliable Si-Compatible Resistive-Switching Random-Access Memory

Yeji Lee †,‡, Soomin Kim §, Seongmin Kim ⊥, Sungjun Kim ⊥, Seongjae Cho †,‡,∥,*
PMCID: PMC13495463  PMID: 42631091

Abstract

Resistive-switching random-access memory (RRAM) has gained a great deal of attention as an emerging memory suitable for massive data storage media and synaptic device applications. For low-power operation capability, eliminating the necessity of current compliance, tunneling oxide can be inserted as a tunneling layer in the conventional RRAM devices. In this work, we have systematically investigated the effects of SiO2 tunneling layer and its formation method on the reliability of a Si3N4-based RRAM device. The tunneling oxide layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) and medium-temperature oxidation (MTO) and compared to a single-layer reference device. The devices with tunneling layers demonstrated reduced state current, and the device prepared by MTO exhibited superior endurance and retention. All of the devices demonstrated space-charge-limited current conduction in the high-resistance state. X-ray photoelectron spectroscopy revealed that the MTO oxide layer was chemically more stable, resulting in a difference in endurance characteristics.

Keywords: resistive-switching random-access memory, Si-compatible memory, low-power operation, high on/off ratio, medium-temperature oxidation

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Introduction

Among emerging nonvolatile memories (NVMs), resistive-switching random-access memory (RRAM) has attracted a great deal of interest owing to its virtuous features of high-speed operation, high scalability, and simplicity of process integration. − The technological foundation of RRAM dates back to the 1960s, when an electrically induced resistance switching phenomenon was first observed in the thin films of metals and SiO2. , Subsequent milestones, including the establishment of the memristor theory, accelerated the development of filament-based resistive-switching models and devices, and transition-metal oxides (TMOs) were regarded as candidate materials relatively lately. − Since the 2000s, research on RRAM has advanced beyond material exploration toward innovative device structures, process environments compatible with conventional Si-based fabrication, and low-thermal-budget processes suitable for integration in the back-end-of-line (BEOL) steps. − Recently, the emergence of artificial neural networks (ANNs) implemented with RRAM crossbar arrays for more hardware-oriented low-power artificial intelligence (AI) and processing-in-memory (PIM) architectures has further increased the demand for RRAM technologies that can be integrated within standard Si process platforms. − Although the early Si-compatible RRAMs exhibited the resistive-switching characteristics, there has been much room to resolve issues regarding limited endurance, unstable retention, and pronounced device-to-device (D-to-D) variation, mainly due to the probabilistic nature of filament formation and rupture. − In this work, a closer investigation is made into the performance and reliability of a dual-layer RRAM device having a Si3N4 switching layer with SiO2 tunneling layers prepared by different processing methods. Si3N4 is a most frequently used material in the CMOS integrated circuits and is reported to have relatively high controllability over the filament formation and rupture with the help of nitrogen vacancies and N-deficient conduction pathways. − To maintain compatibility with Si-based process flows, Ni was selected as the top electrode, and p + poly-Si was selected as the bottom electrode. The high-temperature oxidation process, including the MTO process, was performed prior to Ni electrode formation, and no additional high-temperature thermal treatment was applied after Ni deposition. This process sequence limits diffusion in the Ni electrode. Previous studies have reported stable switching behavior and good reproducibility in RRAM devices with Ni electrodes. − In addition, p + poly-Si is widely used in Si-based semiconductor processes and is often employed in vertically stacked memory structures such as 3D NAND Flash. − The use of p + poly-Si enables the device structure to be implemented without deviating from the existing Si memory process flow. Accordingly, we investigate how the presence and formation method of the tunneling oxide influence the electrical performances and conduction behaviors of the Si3N4 RRAM.

Experimental Details

Figures a and b show the schematic representations of the fabricated RRAM cells: a single-layer device without a tunneling oxide and a dual-layer device with insertion of a SiO2 tunneling layer between the Si3N4 switching layer and the p + poly-Si bottom electrode (BE). The tunneling oxides were deposited by two different processing methods, plasma-enhanced chemical vapor deposition (PECVD) and medium-temperature oxidation (MTO). The integrated fabrication flow and optical microscope images obtained over the processes are shown in Figures S1a–e. The process conditions of PECVD and MTO are also provided in detail in the Supporting Information. Cross-sectional transmission electron microscopy (TEM) images are presented in Figures c–e. Figure c indicates that the single-layer device has direct contact between the Si3N4 layer and the BE. Figures d and e clearly show the separated layers in both dual-layer structures, with the tunneling oxide layers formed by PECVD and MTO, proving the distinct multilayer formation. The RRAM cell with an MTO-deposited tunneling oxide exhibits a uniform thickness and sharply defined boundaries, reflecting high structural integrity. To analyze material compositions, energy-dispersive X-ray spectroscopy (EDS) mapping was conducted for the device with tunneling oxide prepared by MTO, as shown in Figure f. The elemental distributions of Ni, N, O, and Si are distinguished within their respective layers, making up the dual-layer structure. Analysis results for the other RRAM devices without tunneling layer and with PECVD oxide tunneling layer are also provided in Figures S2a–c. These structural and compositional features are the foundation on which the subsequent electrical characteristics can be grasped.

1.

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Schematic representation and structural analyses of the fabricated RRAM devices. Device schematics of (a) a single-layer cell without a tunneling oxide and (b) a dual-layer cell with a tunneling oxide layer. Cross-sectional TEM images of (c) the device without a tunneling layer, (d) the PECVD-based device, and (e) the MTO-based device. (f) EDS elemental mapping of the MTO-based device, confirming distinct distributions of Ni, N, N–O, and Si across the stacked layers.

The deposition techniques and key process conditions for the SiO2 tunneling layers and the Si3N4 switching layer are summarized in Table . The comparison includes the deposition temperature, processing gases, chamber pressures, and plasma power conditions for the medium-temperature oxidation (MTO) and plasma-enhanced chemical vapor deposition (PECVD) processes employed in this work. The MTO process was conducted at 800 °C using DCS (SiH2Cl2) and N2O without plasma assistance, whereas the PECVD process was performed at 350 °C using SiH4/N2O with RF plasma. For the Si3N4 switching layer deposited by PECVD, both RF and low-frequency (LF) plasma power were applied. These summarized parameters clarify the distinct reaction environments used for forming each tunneling layer in the fabricated RRAM devices. From a process classification perspective, the MTO process employed in this work should be distinguished from conventional thermal oxidation. Thermal oxidation proceeds through direct reaction between oxygen and the Si substrate, accompanied by oxide growth from the Si/SiO2 interface and substantial consumption of the Si substrate under diffusion-limited kinetics. In contrast, the present MTO process utilizes thermal energy to drive surface reactions between DCS and N2O without plasma assistance. Therefore, the oxide formation does not involve direct substrate oxidation. Because PECVD relies on plasma-assisted decomposition of precursor gases and surface reactions at relatively low temperatures, , whereas the MTO process does not consume the Si substrate as in thermal oxidation, the MTO process used here can be regarded as a thermally activated CVD-type SiO2 growth mechanism.

1. Deposition Techniques and Process Conditions for the SiO2 Tunneling Layers and the Si3N4 Switching Layer.

  Layer Dielectrics
  SiO2
 
      Si3N4
Deposition Technique MTO PECVD PECVD
Temperature (°C) 800 350 350
Gas DCS (SiH2Cl2): 40 sccm 5% SiH4/N2: 170 sccm 5% SiH4/N2: 800 sccm
N2O: 80 sccm N2O: 710 sccm NH3: 34.5 sccm
    N2: 1000 sccm
Pressure   1000 mTorr 1900 mTorr
Power   RF: 20 W RF: 20 W
    LF: 200
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To evaluate thickness uniformity at the wafer level, 49-point ellipsometer measurements were performed. The thickness distributions of the SiO2 tunneling layers formed by PECVD and MTO are shown in Figure a–b. The PECVD-grown SiO2 exhibited a thickness of 8.15 ± 0.10 nm, while the MTO-grown SiO2 showed 8.35 ± 0.13 nm, with standard deviations within 0.13 nm, indicating a uniform thickness across the wafer. Therefore, the observed differences in endurance and current suppression behaviors are difficult to explain solely by thickness differences or thickness variation. Thus, the local morphology observed in the TEM cross sections does not represent structural inhomogeneity at the device level. In filament-based RRAM devices, filament formation and rupture are localized phenomena, and the dispersion observed in the set and reset voltages is associated with the probabilistic nature of filament formation rather than being dominated by interfacial roughness. The degraded cycling performance of the PECVD-based devices is related to process characteristics, as plasma-assisted deposition can introduce interface damage and hydrogen-related defect states. ,

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Measurements of thickness and uniformity over the 6-in. Si wafers for device fabrication. (a) SiO2 tunneling layer deposited by PECVD and (b) SiO2 tunneling layer deposited by MTO.

Results and Discussion

Repeatable DC I–V characteristics measured under CC-free conditions are shown in Figures a–c for the single-layer device and the dual-layer devices with SiO2 tunneling layers formed by PECVD and MTO. Under CC-free conditions, the single-layer device showed a current increase of approximately 1 mA during filament formation, whereas the devices with tunneling layers maintained relatively lower current levels during repeated cycling. The PECVD-based device operated at an average current level of approximately 600 μA, while the MTO-based device maintained a current range of around 200 μA. In particular, the MTO device maintained the lowest current range throughout repeated cycling. The PECVD-based device also maintained a current level lower than that of the single-layer device under CC-free conditions. Intermittent current overshoot is observed in the PECVD-based device; however, no sustained current divergence or device breakdown occurred during 100 cycles of operation. The on/off ratios were extracted at a read voltage of 0.2 V. The single-layer reference device exhibited an average on/off ratio of ∼6.41 × 104, while the PECVD- and MTO-based devices achieved ratios of ∼1.44 × 105 and ∼5.61 × 106, respectively. These results confirm that the tunneling oxide effectively suppresses both HRS and LRS currents with a more pronounced effect on the HRS, thereby increasing the current ratio compared with the device without a tunneling layer. These behaviors, reduced HRS current and enlarged on/off ratio, contribute to low-power consumption and improved state discrimination, which are undoubtedly beneficial for NVM and ANN applications.

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Repeatable I–V characteristics measured under CC-free: (a) for the device without a tunneling layer, (b) for the device with a SiO2 tunneling layer formed via the PECVD process, and (c) for the device with a SiO2 tunneling layer formed via the MTO process.

Figures a–c present the pulse-based operation characteristics of the fabricated RRAM devices. The endurance during cyclic pulse operations strongly depends on both the presence of a tunneling layer and the method used for its formation. All of the fabricated Si3N4-based RRAM devices exhibited clear resistance windows between the HRS and LRS states. Among the devices in comparison, the RRAM cell with a tunneling oxide layer prepared by MTO demonstrated the highest endurance (>106 cycles) without noticeable degradation. The single-layer device maintained stable operation up to approximately ∼5 × 105 cycles, whereas the device with a tunneling layer deposited by PECVD showed the lowest endurance, reaching ∼1 × 104 cycles. The relatively poor endurance observed in the RRAM cell with a PECVD tunneling oxide might be attributed to compositional nonuniformity and interface defects within the tunneling oxide deposited at a relatively lower processing temperature in the plasma. Retention characteristics were measured at room temperature with the devices fixed on a probe station during evaluation, as shown in Figure d. The resistance was periodically monitored by applying a 50 μs read pulse at 0.2 V at 1 s intervals. This read voltage is well below the set/reset voltage range and does not correspond to a switching condition based on the I–V characteristics. Therefore, the retention measurement reflects a read-out of the stored resistance state, and the read operation does not cause a change in the resistance state. Stable HRS and LRS states were maintained for more than 1 × 105 s in all devices. The pulse-based read scheme used for the retention measurement is shown in Figure e. Stable HRS and LRS states were maintained for over 105 s in all devices. Previous studies on nitride-based RRAM devices have reported retention stability exceeding 104 s at 85 °C under accelerated conditions, − indicating that the present results are consistent with the established reliability behavior of SiNx-based resistive switching devices.

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Pulse endurance and retention characteristics of RRAM devices with and without tunneling layers. Pulse endurance of devices: (a) without a tunneling layer, (b) with a PECVD tunneling layer, and (c) with an MTO tunneling layer. (d) Retention performance comparison of the three devices. (e) Pulse-based retention measurement scheme. (e) Pulse-based retention measurement scheme with identifications of pulse magnitude, duration, and interval.

The variation in electrical characteristics with device area was additionally compared under identical conditions for three different areas: 0.49 μm2 (700 nm × 700 nm), 1 μm2 (1 μm × 1 μm), and 25 μm2 (5 μm × 5 μm), as shown in Figure a–c. Fifteen independent devices were measured for each area, and 10 DC switching cycles were performed per device. The I–V curves presented represent the average results from a total of 150 switching events per area. The measurements show that the LRS current increases slightly with an increasing device area; however, it does not exhibit a linear proportional relationship with area. In contrast, the HRS current shows a clear increase with an increasing device area. In devices incorporating a tunneling layer, the increase in leakage current with the device area is more pronounced. Moreover, the MTO-based devices maintain lower HRS currents across the entire area range compared with the PECVD-based and single-layer devices.

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Area dependence of the I–V electrical characteristics for device areas of 0.49, 1, and 25 μm2: (a) without a tunneling layer, (b) with a PECVD-grown SiO2 tunneling layer, and (c) with an MTO-grown SiO2 tunneling layer.

Cumulative probability distributions of HRS and LRS resistances extracted from 50 DC switching cycles for 20 independent devices are presented in Figure a at a read voltage of 0.2 V. The distributions clearly distinguish the resistance levels of the three device structures and maintain separation between the HRS and LRS states. To quantitatively evaluate device-to-device variation, the ratio of standard deviation to average (σ/μ) was extracted from the resistance distributions. For the LRS, the σ/μ values are 0.46 for the single-layer device, 0.60 for the PECVD-based device, and 1.00 for the MTO-based device. For the HRS, the corresponding values are 0.20, 1.12, and 2.49, respectively. These values indicate different degrees of dispersion depending on the device structure. The broader HRS distribution can be explained by the additional role of the tunneling barrier in the conduction process. In the single-layer device, HRS conduction is primarily determined by conduction paths within the switching layer. In contrast, in the bilayer structure, charge injection conditions and local electric-field distribution also influence HRS conduction. As a result, the HRS current becomes more sensitive to the barrier characteristics, leading to differences in the statistical distribution. In addition, box plots of the set and reset voltages measured over 50 DC switching cycles for each of the 20 devices are shown in Figure b–d. Although a measurable dispersion of switching voltages is present in all three structures, the set and reset voltage ranges remain clearly separated.

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Statistical analysis of switching characteristics based on 50 cycles for 20 devices. (a) Cumulative probability distributions of LRS and HRS resistances measured at a read voltage of 0.2 V. Box plots of set and reset voltages for (b) the single-layer device, (c) the PECVD-grown SiO2 device, and (d) the MTO-grown SiO2 device.

Following these reliability evaluations, the conduction mechanisms were analyzed through log–log I–V characteristics, as shown in Figures a–c. These analyses clarify the dominant transport mechanisms governing the resistive-switching behavior of each RRAM cell.

I∝Vm 1

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log–log scale I–V characteristics and conduction mechanism analysis of Ni/Si3N4-based RRAM devices. (a) Device without a tunneling layer. (b) Device with a PECVD SiO2 tunneling layer. (c) Device with an MTO SiO2 tunneling layer.

Equation. is the simplest mathematical form that relates current and voltage. m values are determined by the dominant transport mechanism across the dielectrics and can be extracted as the slope of a curve depicted on the log–log scale. Figure a shows the I–V characteristics of the comparison device without a tunneling layer on the log–log scale. In the low-voltage region, an ohmic conduction was observed (m ≈ 1). When the current conduction is mostly populated by thermally generated carriers, an ohmic conduction can be extracted. , As the voltage increases, the transport mechanism transitioned to the trap-intermediated space-charge-limited conduction (SCLC) (m ≈ 1.67), followed by a sharp increase in slope (m ≈ 9.94) in the high-voltage region, signifying a transition to a conduction mechanism related with high fields. − Figure b presents the characteristics of the Si3N4 RRAM cell with a tunneling oxide layer prepared by PECVD. Quasi-Ohmic behavior (m ≈ 0.87) was observed in the low-voltage region. The slope increased to, which ensures that the transport mechanism has been brought into the SCLC regime, and the slope is larger than that of the single-layer device. The tunneling oxide prepared by plasma modified the trap distribution significantly and suppressed HRS current to a degree. At high voltages, the slope rose sharply to m ≈ 92.75, which reflected that the conduction mechanism turned into Fowler-Nordheim (FN) tunneling. − Compared with the single-layer device, the transition takes place more abruptly, and the PECVD-grown oxide still contributed to improvement in switching stability by moderating electric field distribution. Figure c shows the device with an MTO-deposited oxide layer. The conduction in the low-voltage region was exhibited to be ohmic (m ≈ 1.07), followed by the SCLC region with the smallest slope (m ≈ 1.35) among the three types of devices, indicating the most gradual and uniform trap-filling process, which effectively suppresses the HRS current. At the high-voltage region, the slope was reached, representing the steepest high-field conduction, but with a smoother transition compared with the PECVD-oxide-inserted RRAM device. This implies that the oxide layer prepared at a higher temperature is allowed to have precise control over charge injection and field distribution, minimizing variations and enhancing the reliability in switching operations. Unlike the reference device without a tunneling layer, the experimental devices with tunneling layers demonstrate the very sharp transitions from SCLC to FN tunneling, which is the evidence for differentiation of low- and high-field current components and, eventually, the high LRS/HRS current ratio. As the log–log I–V slope alone may not fully explain the conduction mechanism, FN tunneling analysis was additionally performed in the high-field region using the ln­(I/V2) versus 1/V representation. Linear regression in this region yielded R2 = 0.96 for the PECVD-based device and R2 = 0.95 for the MTO-based device, indicating a clear linear behavior. These results confirm that the high-field conduction is consistent with the FN tunneling model, , as shown in Figures a–c, and provide quantitative verification beyond simple slope analysis. To further clarify the transport behavior, a schematic energy-band diagram was added to illustrate how differences in bonding uniformity and trap distribution between PECVD and MTO oxides are reflected in the electric-field distribution and carrier injection behavior, as presented in Figures a–c. The material analysis results supporting this interpretation are discussed in the following section.

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Fowler–Nordheim (FN) tunneling analysis of the three devices. (a) ln­(I/V2) vs 1/V plots comparing devices without a tunneling layer and with PECVD- and MTO-grown SiO2 tunneling layers. (b) Linear fitting of the FN region for the PECVD-based device. (c) Linear fitting of the FN region for the MTO-based device.

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Schematic energy-band diagrams of the Ni/Si3N4/SiO2/p + poly-Si structure. (a) Band alignment before bias application. (b) Energy band diagram of the PECVD-based device under positive bias. (c) Energy band diagram of the MTO-based device under positive bias.

To elucidate the origin of the differences in the electrical characteristics, XPS analysis was performed across the dielectric stacks of the three types of fabricated RRAM devices. Figures a–c shows the Si 2p spectra for each device. In Figure a, a strong Si–N bonding peak appears at 100.8 and 101.8 eV, accompanied by weaker Si–O peaks. The largest area is occupied by the signals from the Si–N bonds, and the signals from Si–O bonds might have come from the native and interface oxides since the reference device for Figure a does not have a tunneling oxide layer. In Figure b, Si–O signal was detected at 102.8 eV and Si–N bonding peaks associated with N-deficient environments were located at 100.8 and 101.8 eV, respectively. Figure c exhibits a Si–O peak at the same location, 102.8 eV. However, the intensity from the Si–O bonds was stronger, which assures the fact that the atomic matrix in the tunneling oxide layer prepared at a higher temperature by the gaseous precursors via MTO processing has been more densely woven. − Figures d and e compare the O 1s spectra from the dielectric stack with tunneling oxide layers deposited by PECVD and MTO, respectively, providing further insight into the oxygen bonding states. In Figure d, a dominant Si–O peak is observed at 532.8 eV, accompanied by a relatively weaker oxygen-vacancy-related peak at 531.8 eV. In Figure e, the signal intensities are inverted: the signals centered at 531.8 eV have the predominance and those from the peak 532.8 eV are lowered. At the same time, Figure d shows a higher concentration of oxygen vacancies and more homogeneous oxygen configuration. − More specifically, the nominal peak intensity from the MTO oxide layer and the area below the distribution curve are larger than those from the PECVD tunneling oxide. At the same time, full-wave half-maximum (fwhm) values of the total oxygens are 2.793 and 2.494 eV from PECVD and MTO oxide layers, respectively. These results indicate that the MTO process produces chemically more dense stable oxide networks and a narrower distribution of oxygen bonding energies. The narrower total oxygen profile is mainly due to higher homogeneity of oxygen vacancy essential for resistive-switching operation. , The XPS analyses empirically confirm that the chemical composition and bonding configuration in the tunneling layers are significantly affected by the process method for oxide deposition. These material differences are closely related to the endurance characteristics of the devices. The higher contribution of oxygen-related defect states in the PECVD-grown oxide can affect the switching stability during repeated cycling. The defect density of PECVD-grown oxides may be influenced by deposition condition control or postdeposition annealing (PDA), , indicating that further improvement is possible through process optimization. Previously, the Si3N4-switching RRAM device with an MTO tunneling oxide layer exhibited superior endurance, in close relation with higher uniformity and stability in material configuration. The bonding characteristics of the tunneling oxide play a crucial role in determining charge injection and filament formation stability eventually one of the key findings of this study. Additional N 1s spectra for different tunneling oxides are provided in Figure S3. −

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XPS spectra from the dielectric stacks in the three types of RRAM devices. Si 2p spectra for devices (a) without a tunneling oxide layer, (b) with a PECVD tunneling oxide layer, and (c) with an MTO-deposited tunneling oxide layer. O 1s spectra for (d) PECVD- and (e) MTO-prepared tunneling oxide layers beneath the Si3N4 switching layers.

Table has been included in the main text to summarize representative state-of-the-art dual-layer devices, including those based on low-dimensional materials such as MoS2 and graphene oxide. Table lists key device parameters including operating voltage, compliance current, CC-free operation, on/off ratio, retention, and endurance. The comparison shows that many previously reported bilayer devices rely on an external compliance current for stable operation, whereas the devices presented in this work operate without external ICC. In particular, the MTO-based device achieves an on/off ratio of approximately 3.37 × 106 and endurance of about 106 cycles, which are comparable to those of reported bilayer structures. This comparison places the performance of the proposed structure in a clearer context relative to existing studies.

2. Comparison of the Device Structures and Switching Characteristics.

reference Device Structure Set/Reset [V] Compliance current CC-Free operation On/off ratio Retention [s] Endurance [cycles]
Pd/SiO2/p +2-Si 7/–5 60 μA No ∼1.4 × 105 104 102
Ta/TiN/SiN x /Pt 0.7/–0.6 1 mA No ∼8 105 104
Ni/SiN x /a-Si/p +-Si 10/–8 100 μA No ∼104   102
TiN/TiO x /Al2O3/IrO x 7/–3 100 μA No 21.6   106
Ti/TaO x /HfO x /Pt 2/–1.25 100 μA No >103 >105 >108
TaN/Ta/HfO2/TaO x /Pt 6/–2 500 μA No   103 ∼2 × 103
Au/AlO y /HfO x /Au –1/1.2 100 μA No 50–100   ∼102
TiN/TaO/HfO x /TiN 4.5/–2.5 1 μA No 104 >103  
Al/GO/ITO 2.8/–2 10 mA No 120 6 × 103 50
Ag/TiO2/GO/FTO 1.77/–1.88 100 mA No 199 4 × 104 103
Au/MoS2/Au 0.85/–1.05 10 mA No 8 104 240
Ag/MoS2/Pt 0.42/–0.56 10 mA No >104 ∼3 × 103 ∼180
This work Ni/Si3N4/p + poly-Si 6.5/–6 ∼1 mA Yes ∼9.57 × 104 104 ∼5 × 105
This work Ni/Si3N4/SiO2/p + poly-Si (PECVD) 6/–5.5 ∼ 600 μA Yes ∼3.29 × 106 104 ∼1 × 104
This work Ni/Si3N4/SiO2/p + poly-Si (MTO) 8/–6.5 <200 μA Yes ∼3.37 × 106 104 ∼106
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Conclusions

In this work, we systematically examined the effects of introducing a tunneling oxide layer and its formation method on the electrical performance of Si-compatible RRAM devices. Comparative analyses among devices in a single switching layer structure, dual-layer structure with a PECVD tunneling layer, and with an MTO tunneling layer revealed that both the presence and the quality of the tunneling layer strongly influence device performance and reliability metrics. Although all of the devices exhibited similar SCLC behaviors in the low and intermediate voltage regions, the device with an MTO tunneling oxide layer demonstrated superb characteristics, enduring over 106 cycles without observable degradation. Log–log I–V analysis revealed distinct high-field transitions into FN tunneling depending on the existence and the quality of tunneling oxide. The PECVD oxide-tunneling device exhibited an abrupt transition to FN tunneling, indicative of a sudden onset of high-field conduction, whereas the MTO-layer device showed a smoother transition with a steeper high-field slope, reflecting the effective suppression of carrier injection in the low-field regime leading to the larger current ratio. It has been assured by the XPS analysis results that the MTO tunneling oxide has more uniform and stable interface compared with PECVD tunneling oxide layer, which provides another clue for understanding the effectively suppressed HRS current and smaller variation. These results emphasize the critical importance of introduction and engineering of tunneling oxide not only for better electrical device performances aiming low-power applications but also for operation reliability greatly required for advanced computing architectures as well as massive data storage.

Supplementary Material

ng6c00003_si_001.pdf (533.2KB, pdf)

Acknowledgments

We want to express our deepest gratitude to Process Team Leader Yu-Kyung Park at the Interuniversity Semiconductor Research Center (ISRC) at Seoul National University, Seoul, Korea and Dr. Seongwook Yoo at Electronics and Telecommunication Research Institute (ETRI), Daejeon, Korea, for taking care of the critical and challenging unit processes during the device and array fabrications. Prof. Seongjae Cho cherishes the memory of Prof. Byung-Gook Park and expresses deep gratitude for his teaching, inspiration, and steadfast commitment to students and society.

Glossary

Abbreviations

RRAM

resistive-switching random-access memory

HRS

high-resistance state

LRS

low-resistance state

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnanoscienceau.6c00003.

  • Fabrication process flow and optical microscope images of key process steps, cross-sectional TEM image and EDS elemental mapping results, and XPS spectra of the dielectric layers in the single-layer and dual-layer RRAM devices (PDF)

Yeji Lee refined the process integration, carried out device and array fabrication, measured the fabricated devices, and wrote the manuscript. Soomin Kim performed the layout design and participated in the device and array fabrication. Seongmin Kim participated in the device and array fabrication, and set up the pulsed-mode synaptic operation characterization environment. Sungjun Kim provided the environments for the unit fabrication processes and for the measurement of fabricated device and array, and evaluated the device characteristics. Seongjae Cho prepared the funding sources, set the research direction, conceived the cell and array structure and process integration, set performance targets, evaluated the fabrication results, device performances, and system-level simulation results, and wrote the manuscript. CRediT: Yeji Lee data curation, formal analysis, methodology, visualization, writing - original draft; Soomin Kim data curation, methodology, software; Seongmin Kim data curation, methodology, resources; Sungjun Kim methodology, resources, supervision, validation; Seongjae Cho conceptualization, data curation, formal analysis, funding acquisition, investigation, methodology, project administration, resources, software, supervision, validation, visualization, writing - original draft, writing - review & editing.

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Ministry of Science and ICT of Korea (MSIT) under Grant No. RS-2024-00402495, and also supported in part by NRF grant cofunded by MSIT and the Ministry of Education of Korea under Grant No. RS-2025-16063688.

The authors declare no competing financial interest.

References

  1. Park J., Kumar A., Zhou Y., Oh S., Kim J.-H., Shi Y., Jain S., Hota G., Qiu E., Nagle A. L., Schuller I.-K., Schuman C.-D., Cauwenberghs G., Kuzum D.. Multi-Level, Forming and Filament Free, Bulk Switching Trilayer RRAM for Neuromorphic Computing at the Edge. Nat. Commun. 2024;15:3492. doi: 10.1038/s41467-024-46682-1. [DOI] [PMC free article] [PubMed] [Google Scholar]
  2. Ghose S., Boroumand A., Kim J. S., Gomez-Luna J., Mutlu O.. Processing-in-Memory: A Workload-Driven Perspective. IBM J. Res. Dev. 2019;63(6):3:1–3:19. doi: 10.1147/JRD.2019.2934048. [DOI] [Google Scholar]
  3. Burr G. W., Shelby R. M., Sebastian A., Kim S., Kim S., Sidler S.. et al. Neuromorphic Computing Using Non-Volatile Memory. Adv. Phys. X. 2017;2(1):89–124. doi: 10.1080/23746149.2016.1259585. [DOI] [Google Scholar]
  4. Alibart F., Pleutin S., Bichler O., Gamrat C., Serrano-Gotarredona T., Linares-Barranco B., Vuillaume D.. A Memristive Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing. Adv. Funct. Mater. 2012;22(3):609–616. doi: 10.1002/adfm.201101935. [DOI] [Google Scholar]
  5. Pi S., Li C., Jiang H., Xia W., Xin H., Yang J. J., Xia Q.. Memristor Crossbar Arrays with 6-nm Half-Pitch and 2-nm Critical Dimension. Nat. Nanotechnol. 2019;14:35–39. doi: 10.1038/s41565-018-0302-0. [DOI] [PubMed] [Google Scholar]
  6. Hickmott T. W.. Low-Frequency Negative Resistance in Thin Anodic Oxide Films. J. Appl. Phys. 1962;33:2669–2682. doi: 10.1063/1.1702530. [DOI] [Google Scholar]
  7. Simmons J. G., Verderber R. R.. New Conduction and Reversible Memory Phenomena in Thin Insulating Films. Proc. R. Soc. London A. 1967;301:77–102. doi: 10.1098/rspa.1967.0191. [DOI] [Google Scholar]
  8. Chua L.. MemristorThe Missing Circuit Element. IEEE Trans. Circuit Theory. 1971;18:507–519. doi: 10.1109/TCT.1971.1083337. [DOI] [Google Scholar]
  9. Younis A., Chu D., Li S.. Evidence of Filamentary Switching in Oxide-Based Memory Devices via Weak Programming and Retention Failure Analysis. Sci. Rep. 2015;5:13599. doi: 10.1038/srep13599. [DOI] [PMC free article] [PubMed] [Google Scholar]
  10. Lee C., Kim I., Choi W., Shin H., Cho J.. Resistive Switching Memory Devices Composed of Binary Transition Metal Oxides Using Sol-Gel Chemistry. Langmuir. 2009;25:4274–4278. doi: 10.1021/la804267n. [DOI] [PubMed] [Google Scholar]
  11. Yadav D., Dwivedi A. K., Verma S., Avasthi D. K.. Transition Metal Oxide Based Resistive Random-Access Memory: An Overview of Materials and Device Performance Enhancement Techniques. J. Sci.: Adv. Mater. Devices. 2024;9(4):100813. doi: 10.1016/j.jsamd.2024.100813. [DOI] [Google Scholar]
  12. Sandrini J., Thammasack M., Demirci T., Gaillardon P.-E., Sacchetto D., De Micheli G., Leblebici Y.. Heterogeneous Integration of ReRAM Crossbars in 180 nm CMOS BEoL Process. Microelectron. Eng. 2015;145:62–65. doi: 10.1016/j.mee.2015.03.011. [DOI] [Google Scholar]
  13. Zahoor F., Zulkifli T. Z. A., Khanday F. A.. Resistive Random Access Memory (RRAM): An Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (MLC) Storage, Modeling, and Applications. Nanoscale Res. Lett. 2020;15:90. doi: 10.1186/s11671-020-03303-8. [DOI] [PMC free article] [PubMed] [Google Scholar]
  14. Li Y., Tang J., Gao B., Yao J., Fan A., Yan B., Yang Y., Xi Y., Li Y., Li J., Sun W., Du Y., Liu Z., Zhang Q., Qiu S., Li Q., Qian H., Wu H.. Monolithic Three-Dimensional Integration of RRAM-Based Hybrid Memory Architecture for One-Shot Learning. Nat. Commun. 2023;14:7140. doi: 10.1038/s41467-023-42891-1. [DOI] [PMC free article] [PubMed] [Google Scholar]
  15. Lee W. J., Kim B., Koo M., Kim Y.. Three-Dimensional Resistive Random-Access Memory Based on Stacked Double-Tip Silicon Nanowires for Neuromorphic Systems. ACS Appl. Electron. Mater. 2024;6(4):2232–2241. doi: 10.1021/acsaelm.3c01680. [DOI] [Google Scholar]
  16. Ielmini D., Wong H.-S. P.. In-Memory Computing with Resistive Switching Devices. Nat. Electron. 2018;1:333–343. doi: 10.1038/s41928-018-0092-2. [DOI] [Google Scholar]
  17. Finster J., Klinkenberg E.-D., Heeg J., Braun W.. ESCA and SEXAFS investigations of insulating materials for ULSI microelectronics. Vacuum. 1990;41(7):1586–1589. doi: 10.1016/0042-207X(90)94025-L. [DOI] [Google Scholar]
  18. Qin Y., Sheng Q. Z., Falkner N. J. G., Dustdar S., Wang H., Vasilakos A. V.. When Things Matter: A Survey on Data-Centric Internet of Things. Journal of Network and Computer Applications. 2016;64:137–153. doi: 10.1016/j.jnca.2015.12.016. [DOI] [Google Scholar]
  19. Rajendran G., Banerjee W., Chattopadhyay A., Aly M. M. S.. Application of Resistive Random Access Memory in Hardware Security: A Review. Adv. Electron. Mater. 2021;7(12):2100536. doi: 10.1002/aelm.202100536. [DOI] [Google Scholar]
  20. Cho S.. Volatile and Nonvolatile Memory Devices for Neuromorphic and Processing-in-Memory Applications. J. Semicond. Technol. Sci. 2022;22(1):30–46. doi: 10.5573/JSTS.2022.22.1.30. [DOI] [Google Scholar]
  21. Waser R., Aono M.. Nanoionics-Based Resistive Switching Memories. Nat. Mater. 2007;6:833–840. doi: 10.1038/nmat2023. [DOI] [PubMed] [Google Scholar]
  22. Fowler B. W., Chang Y.-F., Zhou F., Wang Y., Chen P.-Y., Xue F., Chen Y.-T., Bringhurst B., Pozder S., Lee J. C.. Electroforming and Resistive Switching in Silicon Dioxide Resistive Memory Devices. RSC Adv. 2015;5:21215–21236. doi: 10.1039/C4RA16078A. [DOI] [Google Scholar]
  23. Mehonic A., Shluger A. L., Gao D., Valov I., Miranda E., Ielmini D., Bricalli A., Ambrosi E., Li C., Yang J. J.. et al. Silicon Oxide (SiOx): A Promising Material for Resistance Switching? Adv. Mater. 2018;30(43):1801187. doi: 10.1002/adma.201801187. [DOI] [PubMed] [Google Scholar]
  24. Pérez E., Zambelli C., Mahadevaiah M. K., Olivo P., Wenger C.. Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention. IEEE J. Electron Devices Soc. 2019;7:740–747. doi: 10.1109/JEDS.2019.2931769. [DOI] [Google Scholar]
  25. Lanza M., Waser R., Ielmini D., Yang J. J., Goux L., Suñe J., Kenyon A. J., Mehonic A., Spiga S., Rana V., Wiefels S., Menzel S., Valov I., Villena M. A., Miranda E., Jing X., Campabadal F., Gonzalez M. B., Aguirre F., Palumbo F., Zhu K., Roldan J. B., Puglisi F. M., Larcher L., Hou T., Prodromakis T., Yang Y., Huang P., Wan T., Chai Y., Pey K. L., Raghavan N., Dueñas S., Wang T., Xia Q., Pazos S.. Standards for the Characterization of Endurance in Resistive Switching Devices. ACS Nano. 2021;15(11):17214–17231. doi: 10.1021/acsnano.1c06980. [DOI] [PubMed] [Google Scholar]
  26. Aldana S., Zhang H.. Unravelling the Data Retention Mechanisms under Thermal Stress on 2D Memristors. ACS Omega. 2023;8(30):27543–27552. doi: 10.1021/acsomega.3c03200. [DOI] [PMC free article] [PubMed] [Google Scholar]
  27. Solanke B. V., Raskar N. D., Dake D. V., Mane V. A., Sonpir R. B., Raylkar G. D., Chavan K. M., Munde S. S., Kayande P. R., Dole B. N.. Low-Variability, High-Endurance Memristive Behavior in Tungsten-Functionalized GO Based Cu-Doped NiO Nanocomposites for Next-Generation Memory Devices. Mater. Chem. Phys. 2025;346:131352. doi: 10.1016/j.matchemphys.2025.131352. [DOI] [Google Scholar]
  28. Kim S., Jung S., Kim M.-H., Cho S., Park B.-G.. Resistive Switching Characteristics of Si3N4-Based Resistive-Switching Random-Access Memory Cell with Tunnel Barrier for High Density Integration and Low-Power Applications. Appl. Phys. Lett. 2015;106:212106. doi: 10.1063/1.4921926. [DOI] [Google Scholar]
  29. Li D., Li C., Wang J., Xu M., Ma J., Gu D., Liu F., Jiang Y., Li W.. Multifunctional Analog Resistance Switching of Si3N4-Based Memristors through Migration of Ag+ Ions and Formation of Si-Dangling Bonds. J. Phys. Chem. Lett. 2022;13(23):5101–5108. doi: 10.1021/acs.jpclett.2c00893. [DOI] [PubMed] [Google Scholar]
  30. Di Valentin C., Palma G., Pacchioni G.. Ab Initio Study of Transition Levels for Intrinsic Defects in Silicon Nitride. J. Phys. Chem. C. 2011;115(2):561–569. doi: 10.1021/jp106756f. [DOI] [Google Scholar]
  31. Khan S. A., Hussain F., Chung D., Rahman M. K., Ismail M., Mahata C., Abbas Y., Abbas H., Choi C., Mikhaylov A. N.. et al. Memristive Switching and Density-Functional Theory Calculations in Double Nitride Insulating Layers. Micromachines. 2022;13(9):1498. doi: 10.3390/mi13091498. [DOI] [PMC free article] [PubMed] [Google Scholar]
  32. Lampert M. A.. Simplified Theory of Space-Charge-Limited Currents in an Insulator with Traps. Phys. Rev. 1956;103:1648–1656. doi: 10.1103/PhysRev.103.1648. [DOI] [Google Scholar]
  33. Chiu F.-C.. A Review on Conduction Mechanisms in Dielectric Films. Adv. Mater. Sci. Eng. 2014;2014:578168. doi: 10.1155/2014/578168. [DOI] [Google Scholar]
  34. Lim E. W., Ismail R.. Conduction Mechanism of Valence Change Resistive Switching Memory: A Survey. Electronics. 2015;4(3):586–613. doi: 10.3390/electronics4030586. [DOI] [Google Scholar]
  35. Zubair M., Ang Y. S., Ang L. K.. Thickness Dependence of Space-Charge-Limited Current in Spatially Disordered Organic Semiconductors. IEEE Trans. Electron Devices. 2018;65(8):3421–3429. doi: 10.1109/TED.2018.2841920. [DOI] [Google Scholar]
  36. Sajedi Alvar M., Blom P. W. M., Wetzelaer G.-J. A. H.. Space-Charge-Limited Electron and Hole Currents in Hybrid Organic-Inorganic Perovskites. Nat. Commun. 2020;11:4023. doi: 10.1038/s41467-020-17868-0. [DOI] [PMC free article] [PubMed] [Google Scholar]
  37. Perera R., Ikeda A., Hattori R., Kuroki Y.. Trap-Assisted Leakage Current Conduction in Thin Silicon Oxynitride Films Grown by Rapid Thermal Oxidation Combined Microwave Excited Plasma Nitridation. Microelectron. Eng. 2003;65(4):357–370. doi: 10.1016/S0167-9317(02)01025-0. [DOI] [Google Scholar]
  38. Simmons J. G.. Electric Tunnel Effect between Dissimilar Electrodes Separated by a Thin Insulating Film. J. Appl. Phys. 1963;34:2581–2590. doi: 10.1063/1.1729774. [DOI] [Google Scholar]
  39. Joshi S. S., Kim S. M., Kim C.-H., Cho S.. Compact Modeling of a HfO2 Memristor Cell with Dependence on Compliance Current for Large-Area Simulations. J. Semicond. Technol. Sci. 2023;23(6):382–388. doi: 10.5573/JSTS.2023.23.6.382. [DOI] [Google Scholar]
  40. Chang T., Jo S.-H., Kim K.-H., Sheridan P., Gaba S., Lu W.. Synaptic Behaviors and Modeling of a Metal Oxide Memristive Device. Appl. Phys. A: Mater. Sci. Process. 2011;102:857–863. doi: 10.1007/s00339-011-6296-1. [DOI] [Google Scholar]
  41. Hector A. L.. Synthesis and Processing of Silicon Nitride and Related Materials Using Preceramic Polymer and Non-Oxide Sol-Gel Approaches. Coord. Chem. Rev. 2016;323:120–137. doi: 10.1016/j.ccr.2016.05.009. [DOI] [Google Scholar]
  42. Alfonsetti R., Lozzi L., Passacantando M., Picozzi P., Santucci S.. XPS Studies on SiOx Thin Films. Appl. Surf. Sci. 1993;70–71:222–225. doi: 10.1016/0169-4332(93)90431-A. [DOI] [Google Scholar]
  43. Ingo G. M., Zacchetti N., Della Sala D., Coluzza C.. XPS Investigation on the Growth Model of a-SiNx and Silicon-Nitrogen Chemical Bonding. Surf. Interface Anal. 1989;14:675–678. [Google Scholar]
  44. Finster J., Klinkenberg E.-D., Heeg J., Braun W.. ESCA and SEXAFS Investigations of Insulating Materials for ULSI Microelectronics. Vacuum. 1990;41(7):1586–1589. doi: 10.1016/0042-207X(90)94025-L. [DOI] [Google Scholar]
  45. Larkins F. P., Lubenfeld A.. The Auger Spectrum of Solid Ammonia. J. Electron Spectrosc. Relat. Phenom. 1979;15(1):137–144. doi: 10.1016/0368-2048(79)87024-3. [DOI] [Google Scholar]
  46. Viard J., Beche E., Perarnau D., Berjoan R., Durand J.. XPS and FTIR Study of Silicon Oxynitride Thin Films. J. Eur. Ceram. Soc. 1997;17(15–16):2025–2028. doi: 10.1016/S0955-2219(97)00051-4. [DOI] [Google Scholar]
  47. Ma K., Zhao S., Dou M., Ma X., Dai C.. Enhancing the Stability of Methanol-to-Olefins Reaction Catalyzed by SAPO-34 Zeolite in the Presence of CO2 and Oxygen-Vacancy-Rich ZnCeZrOx . ACS Catal. 2024;14:594. doi: 10.1021/acscatal.3c04707. [DOI] [Google Scholar]
  48. Padilha A. C. M., McKenna K. P.. Structure and Properties of a Model Conductive Filament/Host Oxide Interface in HfO2-Based ReRAM. Phys. Rev. Mater. 2018;2:045001. doi: 10.1103/PhysRevMaterials.2.045001. [DOI] [Google Scholar]
  49. Rushchanskii K. Z., Blugel S., Lezaic M.. Ordering of Oxygen Vacancies and Related Ferroelectric Properties in HfO2‑δ . Phys. Rev. Lett. 2021;127:087602. doi: 10.1103/PhysRevLett.127.087602. [DOI] [PubMed] [Google Scholar]
  50. Ma L.-Y., Liu S.. Structural Polymorphism Kinetics Promoted by Charged Oxygen Vacancies in HfO2 . Phys. Rev. Lett. 2023;130:096801. doi: 10.1103/PhysRevLett.130.096801. [DOI] [PubMed] [Google Scholar]
  51. Wu X., Mei S., Bosman M., Raghavan N., Zhang X., Cha D., Li K., Leong K. P.. Evolution of Filament Formation in Ni/HfO2/SiO x /Si-Based RRAM Devices. Adv. Electron. Mater. 2015;1:1500130. doi: 10.1002/aelm.201500130. [DOI] [Google Scholar]
  52. Yang Y., Duan Y., Gao H., Qian M., Guo J., Yang M., Ma X.. Improved switching stability in SiNx-based RRAM by introducing nitride insertion layer with high conductivity. Appl. Phys. Lett. 2023;122:113504. doi: 10.1063/5.0142897. [DOI] [Google Scholar]
  53. Lee Y., Kim S., Kim S., Shim W., Kim S., Cho S.. A Fully Si-Compatible Ni/Si3N4/Al2O3/p + Poly-Si RRAM Device for Analog Synapse and Its System-Level Assessment toward Processing-in-Memory Applications. ACS Omega. 2025;10:57476–57486. doi: 10.1021/acsomega.5c08019. [DOI] [PMC free article] [PubMed] [Google Scholar]
  54. Yang T., Xia Z., Fan D., Zhao D., Xie W., Yang Y., Liu L., Zhou W., Huo Z.. Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash. Micromachines. 2023;14:230. doi: 10.3390/mi14010230. [DOI] [PMC free article] [PubMed] [Google Scholar]
  55. Zhang Q., Zhang Y., Luo Y., Yin H.. New Structure Transistors for Advanced Technology Node CMOS ICs. Natl. Sci. Rev. 2024;11:nwae008. doi: 10.1093/nsr/nwae008. [DOI] [PMC free article] [PubMed] [Google Scholar]
  56. An U., Yoon G., Go D., Park J., Kim D., Kim J., Lee J.-S.. Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory. Micromachines. 2023;14:2199. doi: 10.3390/mi14122199. [DOI] [PMC free article] [PubMed] [Google Scholar]
  57. Yen T. J., Chin A., Gritsenko V.. High Performance All Nonmetal SiN x Resistive Random Access Memory with Strong Process Dependence. Sci. Rep. 2020;10:2807. doi: 10.1038/s41598-020-59838-y. [DOI] [PMC free article] [PubMed] [Google Scholar]
  58. Li S., Yang N., Yuan X., Ye X., Wang L., Zheng F., Liu C., Li H.. Plasma-Induced Damage and Annealing Repairing in ALD-Al2O3/PECVD-SiN x Stacks. Mater. Sci. Semicond. Process. 2019;100:214–219. doi: 10.1016/j.mssp.2019.05.010. [DOI] [Google Scholar]
  59. Qin F., Zhang Y., Guo Z., Park T. J., Park H., Kim C. S., Park J., Fu X., No K., Song H. W., Ruan X., Lee S.. High On/Off Ratio SiO2-Based Memristors for Neuromorphic Computing: Understanding the Switching Mechanisms through Theoretical and Electrochemical Aspects. Mater. Adv. 2024;5:4209–4220. doi: 10.1039/D3MA01142A. [DOI] [Google Scholar]
  60. Yan Y., Duan Y., Gao H., Qian M., Guo J., Yang M., Ma X.. Improved Switching Stability in SiN x -Based RRAM by Introducing Nitride Insertion Layer with High Conductivity. Appl. Phys. Lett. 2023;122:113504. doi: 10.1063/5.0142897. [DOI] [Google Scholar]
  61. Kwon H. T., Lee W. J., Choi H.-S., Wee D., Park Y. J., Kim B., Kim M.-H., Kim S., Park B.-G., Kim Y.. Resistive Random-Access Memory with an a-Si/SiN x Double-Layer. Solid-State Electron. 2019;158:64–69. doi: 10.1016/j.sse.2019.05.014. [DOI] [Google Scholar]
  62. Banerjee W., Xu X., Lv H., Liu Q., Long S., Lu M.. Variability Improvement of TiO x /Al2O3 Bilayer Nonvolatile Resistive Switching Devices by Interfacial Band Engineering with an Ultrathin Al2O3 Dielectric Material. ACS Omega. 2017;2:6888–6895. doi: 10.1021/acsomega.7b01211. [DOI] [PMC free article] [PubMed] [Google Scholar]
  63. Hao Y., Zhang Y., Wu Z., Zhang X., Shi T., Wang Y., Zhu J., Wang R., Wang Y., Liu Q.. Uniform, Fast, and Reliable CMOS Compatible Resistive Switching Memory. J. Semicond. 2022;43:054102. doi: 10.1088/1674-4926/43/5/054102. [DOI] [Google Scholar]
  64. Wang T., Brivio S., Cianci E., Wiemer C., Perego M., Spiga S., Lanza M.. Improving HfO2-Based Resistive Switching Devices by Inserting a TaOx Thin Film via Engineered In Situ Oxidation. ACS Appl. Mater. Interfaces. 2022;14:24565–24574. doi: 10.1021/acsami.2c03364. [DOI] [PubMed] [Google Scholar]
  65. Basnet P., Anderson E. C., Athena F., Chakrabarti B., West M. P., Vogel E. M.. Asymmetric Resistive Switching of Bilayer HfO x /AlO y and AlO y /HfO x Memristors: The Oxide Layer Characteristics and Performance Optimization for Digital Set and Analog Reset Switching. ACS Appl. Electron. Mater. 2023;5:1859–1865. doi: 10.1021/acsaelm.3c00079. [DOI] [Google Scholar]
  66. Lin Y.-D., Chen P.-S., Lee H.-Y., Chen Y.-S., Rahaman S. Z., Tsai K.-H., Hsu C.-H., Chen W.-S., Wang P.-H., King Y.-C., Lin C.-J.. Retention Model of TaO/HfOx and TaO/AlOx RRAM with Self-Rectifying Switch Characteristics. Nanoscale Res. Lett. 2017;12:407. doi: 10.1186/s11671-017-2179-5. [DOI] [PMC free article] [PubMed] [Google Scholar]
  67. Moazzeni A., Madvar H. R., Hamedie S., Kordrostami Z.. Fabrication of Graphene Oxide-Based Resistive Switching Memory by the Spray Pyrolysis Technique for Neuromorphic Computing. ACS Appl. Nano Mater. 2023;6:2236–2248. doi: 10.1021/acsanm.2c05497. [DOI] [Google Scholar]
  68. Jia W., Hu L., Gao W., Mu W., Chou Z., Cheng X.. Improvement of Switching Uniformity in TiO2-Based Resistive Random Access Memory with Graphene Oxide Embedded Film. Mater. Sci. Semicond. Process. 2024;182:108688. doi: 10.1016/j.mssp.2024.108688. [DOI] [Google Scholar]
  69. Yadav, S. ; Patel, C. ; Chaudhary, S. ; Paul, A. ; Ghodke, S. ; Mukherjee, S. . Bilayer MoS2 Based Memristive Crossbar Array for Neuromorphic Applications. In 2024 IEEE 24th International Conference on Nanotechnology (NANO); IEEE: Gijón, Spain, 2024. 224–227. 10.1109/NANO61778.2024.10628597. [DOI] [Google Scholar]
  70. Ling Y., Li J., Luo T., Lin Y., Zhang G., Shou M., Liao Q.. MoS2-Based Memristor: Robust Resistive Switching Behavior and Reliable Biological Synapse Emulation. Nanomaterials. 2023;13:3117. doi: 10.3390/nano13243117. [DOI] [PMC free article] [PubMed] [Google Scholar]
  71. Deal B. E., Grove A. S.. General Relationship for the Thermal Oxidation of Silicon. J. Appl. Phys. 1965;36:3770–3778. doi: 10.1063/1.1713945. [DOI] [Google Scholar]
  72. Meeks E., Larson R. S., Ho P., Ablett C., Han S. M., Edelberg E., Aydil E. S.. Modeling of SiO2 Deposition in High Density Plasma Reactors and Comparisons of Model Predictions with Experimental Measurements. J. Vac. Sci. Technol. A. 1998;16:544–563. doi: 10.1116/1.581096. [DOI] [Google Scholar]
  73. Zhang J., Guo J., Zhao Q., Yu L., Ye S., Yin H., Wang Y.. Formation of SiO2 Thin Films through Plasma-Enhanced Chemical Vapor Deposition Using SiH4/Ar/N2O. Thin Solid Films. 2024;797:140348. doi: 10.1016/j.tsf.2024.140348. [DOI] [Google Scholar]
  74. Yang Y., Duan Y., Gao H., Qian M., Guo J., Yang M., Ma X.. Improved Switching Stability in SiNx-Based RRAM by Introducing Nitride Insertion Layer with High Conductivity. Appl. Phys. Lett. 2023;122:113504. doi: 10.1063/5.0142897. [DOI] [Google Scholar]
  75. Puglisi F. M., Qafa A., Pavan P.. Temperature Impact on the Reset Operation in HfO2 RRAM. IEEE Electron Device Lett. 2015;36:244–246. doi: 10.1109/LED.2015.2397192. [DOI] [Google Scholar]
  76. Liu, X. ; Zhou, M. ; Rosing, T. S. ; Zhao, J. . HR3AM: A Heat Resilient Design for RRAM-Based Neuromorphic Computing. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED); IEEE: Lausanne, Switzerland, 2019. 10.1109/TED.2023.3266186. [DOI] [Google Scholar]

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