Array of Cointegrated Transistor‐Based Artificial Neurons and Synapses for Neuromorphic Computing

ABSTRACT

Neuromorphic computing seeks to replicate the computational efficiency and parallelism of the human brain by emulating its neural architecture. In this work, we present the Array of Cointegrated Transistor‐Based Artificial Neurons and Synapses (ACTANS), a simplified hardware architecture that unifies transistors as both artificial neurons and synapses within a fully compatible complementary metal‐oxide‐semiconductor (CMOS) fabrication process. The artificial neurons and synapses are homotypic transistors that are structurally identical but functionally distinct. The proposed ACTANS consists of one neuron and sixteen connected synapses. In contrast to circuit‐based neuromorphic systems that are limited by excessive area requirements and high‐power consumption, and to non‐CMOS systems that struggle to integrate neurons, synapses, and peripheral circuits owing to incompatibility with CMOS processes, the ACTANS architecture provides a compact device footprint and enables seamless neuron‐synapse‐circuit cointegration. The system is capable of performing cognitive tasks such as letter and pattern recognition.

A fully cointegrated neuromorphic hardware array based on CMOS transistors is demonstrated. Artificial neurons and synapses are simultaneously integrated within a single wafer plane, and their performance is verified through real‐time hardware demonstrations and system‐level simulations, achieving reliable pattern recognition and providing a scalable pathway toward energy‐efficient on‐device AI computing.

1. Introduction

Recent advances in artificial intelligence (AI) have significantly improved the ability of AI to perform complex tasks, including pattern recognition, image classification, and speech recognition. In particular, recent progress in conversational AI models, such as ChatGPT, Gemini, and Llama 2, has made AI more accessible in everyday life, expanding its practical applications across various fields [1, 2, 3]. With regard to their structure, these software‐based artificial neural networks (ANNs) operate based on the von Neumann architecture, where the processor and memory are separate. Due to this separation between the memory, storing weights, and the processor, conducting computations, significant energy consumption occurs when shuttling weight data and computed values [4]. Additionally, the conventional von Neumann computing architecture inherently has a critical limitation known as the von Neumann bottleneck, a delay arising from the mismatch between memory speeds and the significantly faster processor operations [5]. Consequently, certain types of high‐performance memory, such as high‐bandwidth memory (HBM), have become widely adopted. However, servers equipped with large quantities of graphics processing units (GPUs) and HBMs consume significant amounts of energy, leading to environmental concerns [6, 7].

Thus, there is an increasing demand for the development of hardware capable of executing AI tasks with lower energy consumption. Neuromorphic hardware, inspired by the efficient information processing mechanisms of the human brain, has increasingly emerged as an attractive alternative to von Neumann computing architectures [8, 9, 10]. Unlike conventional computing systems, neuromorphic hardware employs spiking neural networks (SNNs), which mimic biological neural networks by transmitting information through discrete electrical spikes, as illustrated in Figure 1a. This spike‐based communication approach drastically enhances energy efficiency, making neuromorphic systems highly suitable for power‐sensitive applications such as mobile and Internet of Things devices (IoT) [11, 12, 13, 14].

FIGURE 1.

(a) Schematic of a biological neuron and synapses. A pre‐synaptic neuron transmits spike signals to a post‐synaptic neuron with the weight of the synapse between them. (b) Schematic of three distinct operational characteristics exhibited by a single SONOS‐FET. The fabricated transistor demonstrates the functionalities of a transistor, an artificial neuron, and an artificial synapse, all within the same structure. (c) Schematic of cointegrated SONOS‐FETs forming a 1×16 neuron‐synapse array. (d) Optical photograph of the fabricated 8‐inch wafer with SONOS‐FET‐based neurons and synapses created via 100% standard Si CMOS fabrication technology.

The practical implementation of neuromorphic hardware involves three primary components: neurons, synapses, and peripheral CMOS circuits. There are mainly two approaches to realizing them. The first approach, known as circuit‐based neuromorphic hardware, utilizes standard CMOS transistor technology to construct neurons and synapses [15, 16, 17]. This method capitalizes on mature fabrication techniques and well‐established integration processes, enabling the implementation of highly reliable systems. However, this approach has significant limitations due to the substantial area and power consumption, as each component comprises multiple transistors. Considering that the human brain contains approximately 10¹¹ neurons and 10¹⁵ synapses, area limitations severely constrain circuit‐based implementations of neuromorphic hardware [18].

To address these limitations, as a second approach, emerging device‐based neuromorphic hardware is actively studied at present. Neurons have been realized using devices exhibiting metal‐insulator transitions (MIT), Mott transitions, and ovonic threshold switching (OTS), while synapses have been implemented using devices such as resistive random access memory (RRAM), phase‐change memory (PCM), and ferroelectric random access memory (FeRAM) [19, 20, 21, 22, 23, 24, 25, 26]. Despite these advances, significant challenges remain in realizing fully integrated neuromorphic systems. In addition to simultaneous integration with peripheral CMOS circuits, the cointegration of neurons and synapses on the same plane also remains virtually impossible due to poor CMOS compatibility and mismatched material properties [27, 28]. These challenges lead to increased fabrication complexity and cost, reduced yields, and limited scalability.

This study proposes a neuromorphic type of hardware architecture in which all essential components—neurons, synapses, and transistors—share an identical structure, as shown in Figure 1b, enabling simultaneous integration on a single plane using CMOS microfabrication. As illustrated in Figure S1, when the neuron and synapse consist of different materials or have different structures, additional separation steps or out‐of‐plane fabrication followed by packaging become necessary to ensure process separation. In contrast, our approach enables a unified in‐plane fabrication process. To achieve this, we employed a silicon–oxide–nitride–oxide–silicon (SONOS) transistor, which is analogous to a metal‐oxide‐semiconductor field‐effect transistor (MOSFET), and implemented it on a silicon‐on‐insulator (SOI) substrate, as shown in Figure 1b. A MOSFET consists of a gate stack and a body. The gate stack comprises a gate (G), a blocking oxide, a charge trap nitride (CTN), and a tunneling oxide, collectively referred to as ONO, arranged in the vertical direction. The body contains a source (S), a channel, and a drain (D), aligned in the lateral direction. In the SONOS‐based MOSFET, hereafter referred to as the SONOS‐FET, the body part plays a critical role in neuronal operations, while the gate stack is primarily responsible for synaptic operations. Consequently, this homotypic SONOS‐FET is capable of supporting both functions, analogous to the dual‐faced nature of Janus. Moreover, the SONOS‐FET also operates as a conventional transistor, as it is fundamentally a type of transistor.

In detail, due to the floating body (FB) characteristic arising from the SOI structure, neuronal operation can be achieved by applying a high drain voltage (V _D) [29, 30]. Furthermore, by intentionally embedding a CTN layer between the blocking oxide and the tunneling oxide, which are materials commonly used in commercial NAND flash memory, we enabled analog memory functionality [31, 32]. Owing to the Janus‐like properties of the SONOS‐FET, neurons, synapses, and transistors were simultaneously fabricated on the same wafer plane by means of standard CMOS microfabrication processes.

In this work, we also experimentally realized an Array of Cointegrated Transistor‐Based Artificial Neurons and Synapses (ACTANS), which consists of one neuron and sixteen connected synapses, thereby extending beyond individual device characterization to demonstrate functional interconnection within a neuromorphic system with a fan‐out value of 16. For this purpose, we systematically explored and established an appropriate interconnection scheme between the neuron and synapse that aligns with the system requirements. In addition, we validated the scalability and system‐level functionality of the proposed architecture through both hardware‐level and software‐level simulations. In the hardware‐oriented simulations, the circuit simulator SPICE was used to confirm that the ACTANS configuration could be scaled beyond the experimentally implemented 1 × 16 array by incorporating the measured characteristics of the fabricated SONOS‐FETs. This ACTANS successfully performed letter recognition tasks. In the software‐oriented simulations, recognition testing of handwritten digits from the MNIST dataset was conducted to evaluate the ACTANS configuration, incorporating experimentally measured neuronal and synaptic data. The results demonstrate the feasibility of large‐scale neuromorphic computing using the proposed SONOS‐FET‐based architecture.

2. Results and Discussion

2.1. Neuronal and Synaptic Characteristics of the SONOS‐FET

After fabricating the neurons, synapses, and transistors, all structurally identical homotypic SONOS‐FETs were interconnected through metallization to construct a neuromorphic array with a fan‐out value of 16, where each neuron is connected to 16 synapses, as shown in Figure 1c. These devices were fabricated on p‐type 8‐inch silicon‐on‐insulator (SOI) wafers with a (100) crystal orientation, as shown in Figure 1d. This SOI wafer has top silicon with a thickness (T _si) of 50 nm and buried oxide (BOX) with a thickness (T _box) of 145 nm. The nominal gate length (L) and width (W) of the fabricated SONOS‐FETs are 500 and 300 nm, respectively. Detailed fabrication procedures are described in Figure S2 of the Supporting Information.

Figure 2a shows a scanning electron microscopy (SEM) image and a cross‐sectional transmission electron microscopy (TEM) image of the fabricated SONOS‐FET. The neuron operation is derived from the n ⁺ S–p‐type FB–n ⁺ D structure along the channel direction. Many previous studies have demonstrated that neuron functionality can be realized in this n ⁺‐p‐n ⁺ structure [30, 33]. As shown in Figure 2b, a key operation of the neuron with the n ⁺‐p‐n ⁺ structure is the single‐transistor latch (STL) phenomenon, which drives the firing function as an artificial neuron. Figure S3 illustrates the STL mechanism through energy band diagrams, highlighting carrier generation by impact ionization (I.I.) and subsequent carrier confinement. The SONOS‐FET operates in two distinct modes, the first being voltage input (V _in) and current output (I _out), and the second being current input (I _in) and voltage output (V _out).

FIGURE 2.

Measured characteristics for neuronal and synaptic operations from the same SONOS‐FET: (a) SEM image of the SONOS‐FET in a bird's‐eye view. The TEM image in the inset presents a cross‐sectional view along the a‐a′ line. The gate stack is composed of three layers: a tunneling layer (SiO₂), a charge trap layer (Si₃N₄), and a blocking layer (SiO₂), designed to implement the memory characteristics required for synaptic operation. (b) Single‐transistor latch (STL) characteristic (I _D‐V _D) of the fabricated SONOS‐FET. (c) Neuronal spiking characteristic showing integrate and fire behavior with a wedge‐shaped waveform. (d) Transfer characteristics (I _D‐V _G) of the fabricated SONOS‐FET‐based synapse after potentiation and depression (P/D). The threshold voltage (V _T) was shifted. (e) P/D characteristics showing the change in G _CH as a function of N _pulse. (f) Retention characteristics of the fabricated SONOS‐FET‐based synapse.

First, the voltage input and current output mode is described as follows. There are two potential barriers: the first is the built‐in potential between S and the FB (V _{bi, SFB}), and the second is the built‐in potential between the FB and D (V _{bi, DFB}). V _{bi, SFB} and V _{bi, DFB} are indicated in Figure S3. When the drain voltage (V _D = V _in) increases, V _{bi, DFB} also increase, which corresponds to an increase in the potential energy. This potential energy is converted into kinetic energy for electrons injected from S. These energetic electrons induce I.I. near the FB to D boundary, resulting in the generation of equal numbers of electrons and holes. The generated electrons move toward D, while the holes (Q _{h, FB}) begin to accumulate in the FB. During this process, the holes become latched in the FB of the single SONOS‐FET, a phenomenon corresponding to the aforementioned STL. They are confined laterally by both V _{bi, SFB} and V _{bi, DFB} in the energy band diagram along the channel direction, and vertically by the gate oxide and BOX in the energy diagram perpendicular to the channel. The accumulated holes transiently reduce V _{bi, SFB}, thereby facilitating further electron diffusion into the FB. This sequence of events continues until V _{bi, SFB} is flattened, indicating that the potential barrier which that confined the accumulated holes has disappeared. When V _D approaches the latch‐up voltage (V _LU), the holes are abruptly diffused out from the FB to S. Prior to V _LU, the SONOS‐FET remains in the off‐state, while beyond V _LU, it transitions to the on‐state. The STL thus enables an abrupt transition from the off‐state to the on‐state. These two states result in two bi‐stable states, meaning that a forbidden region exists between the off‐ and the on‐state when I _in is applied to D of the SONOS‐FET.

Second, the current input and voltage output mode is described as follows. When I _in is applied to D of the SONOS‐FET, V _{OUT, N} is generated from the same D and increases linearly, as a charging process. Before V _{OUT, N} reaches V _LU, the SONOS‐FET remains in the off‐state, and the injected carriers are integrated in the parasitic capacitor, as illustrated in Figure S4. The integrated charge raises the drain potential, resulting in an increase in V _{bi, DFB}. The elevated potential energy near D, associated with the increased V _{bi, DFB}, is subsequently converted into kinetic energy for electrons diffusing from S. These energetic electrons also enable I.I. near D, resulting in the generation of equal numbers of electrons and holes. The generated electrons move toward D, while the Q _{h, FB} begin to accumulate in the FB. Once V _{OUT, N} reaches V _LU, the SONOS‐FET transitions from the off‐state to the on‐state, and the accumulated charges at the parasitic capacitor are abruptly discharged toward S, forming the source current (I _S), which is characterized by a narrow and sharp peak. At the moment of this rapid discharging event, V _top abruptly drops to V _bottom. Consequently, V _{OUT, N} exhibits a wedge‐shaped waveform, as shown in Figure 2c. The linear increase of V _{OUT, N} toward V _top, followed by the abrupt decrease to V _bottom, constitutes one cycle that corresponds to a spiking event in neuronal operation. This wedge‐shaped V _{OUT, N} waveform is continuously generated at D as long as I _in is supplied to D. Herein, the linear charging process corresponds to the integrate phase of neuronal operation, while the abrupt discharging corresponds to the fire phase. During the integration phase, the leakage current is determined by the I _D corresponding to V _D under the off‐state in the I _D‐V _D characteristics in Figure 2b. In contrast, during the fire phase, the firing current is determined by the I _D corresponding to V _D under the on‐state, as shown in Figure S4. Through the leaky integrate operation in the off‐state and fire operation in the on‐state, the SONOS‐FET exhibits typical leaky integrate‐and‐fire (LIF) behavior. The leaky characteristic provides the passive, time‐dependent decay needed to reset an excited artificial neuron. In contrast to the abrupt discharge observed during the firing operation, the charges stored in the FB are gradually released through intrinsic leakage currents during the leaky operation. This process autonomously returns the device to its resting state without the need for external reset circuitry, thereby preparing the SONOS‐FET for the next input.

Synaptic operation is also demonstrated using the same homotypic SONOS‐FET. Owing to the SONOS structure, memory characteristics are realized by modulating the density of charge trapped in the CTN, which in turn alters the channel conductance (G _CH), which is quantified as I _D/V _D. Each specific value of G _CH corresponds to a unique synaptic weight. Figure 2d shows the transfer curve (I _D‐V _G) of the fabricated SONOS‐FET. Negative gate voltage induces a leftward shift in the threshold voltage (V _T), representing an erasing operation corresponding to potentiation (an increase in G _CH). Conversely, positive gate voltage induces a rightward shift, which is a programming operation corresponding to depression (a decrease in G _CH).

These V _T shifts become more potentiated or further depressed as the number of applied V _G pulses (N _pulse) increases, enabling the control of synaptic plasticity. Figure 2e presents the potentiation and depression (P/D) characteristics of the fabricated SONOS‐FET, showing the change in G _CH as a function of N _pulse. For potentiation, a V _G pulse of ‐12 V with a pulse width of 5 msec was applied to G. For depression, a V _G pulse of 11.6 V with a pulse width of 10 µs was applied to G. Consequently, a range of values of G _CH with 32 discrete levels (5‐bit) was achieved. For the reading operation, V _G and V _D were set to 2.5 and 1 V, respectively. The nonlinearity parameter that determines the shape of the conductance‐update curve in Figure 2e was calculated as follows: [34]

$$G=\left\{\begin{array}{c}{\left[\left(G_{max}^{\alpha }-G_{min}^{\alpha }\right)\eta +G_{min}^{\alpha }\right]}^{1/\alpha }if\alpha \ne 0\\ G_{min}{\left(G_{max}/G_{min}\right)}^{\eta }if\alpha =0\end{array}\right.$$ (1)

where η is a normalized internal variable ranging from 0 to 1, G _max and G _min are the experimentally measured maximum and minimum conductance values, respectively. The measured P/D branches were fitted separately, yielding α _pot = 4.16 and α _dep = −1.24, respectively.

Meanwhile, with regard to the array configuration, it is important to note that when P/D occur at the selected synapse, the unselected synapses must retain their states. To ensure this, the selected synapse operates under the aforementioned conditions, while voltages of −5.1 V during potentiation and 4.5 V during depression are applied to the drain line of the unselected synapses. This method induces a strong lateral electric field to prevent unintended P/D caused by the high V _G [35]. To evaluate the inhibition behavior of unselected synapses, the measured G _CH characteristics under these inhibition conditions are shown in Figure S5. The detailed conditions for the potentiation, depression, read, and inhibition operations are summarized in Table S1. Figure 2f presents the retention characteristics of the SONOS‐FET. Each distinct G _CH level is maintained for more than 10⁵ sec owing to the inherent non‐volatility provided by the SONOS structure. The SONOS‐FET demonstrates exceptionally low energy consumption during P/D, attributed to its intrinsic three‐terminal configuration. During these operations, there is no significant flow of I _D, as both the source voltage (V _S) and drain voltage (V _D) are grounded, thereby preventing current from passing through the channel. Therefore, energy consumption is determined by the product of the gate voltage (V _G) and gate current (I _G). The energy consumption per event (E _update) is estimated using the following equation:

$$E_{update}=I_G·V_G·t_{pulse}$$ (2)

Based on the measured I _G and V _G characteristics of the SONOS‐FET shown in Figure S6, the energy consumed per event is 1.52 fJ/event for potentiation and 0.58 aJ/event for depression. These values are less than the energy consumption of a biological synapse, which is approximately 10 fJ/event [36].

The fabricated SONOS‐FET demonstrates three modes of operation, working as a conventional transistor, a neuronal transistor, and a synaptic transistor. As shown in Figure S7, the SONOS‐FET exhibits typical I _D‐V _G transfer characteristics and I _D‐V _D output characteristics, in addition to the neuronal and synaptic operations described above. Although all three modes are implemented within the same structure, they remain independent owing to distinct voltage biasing conditions. The synaptic mode demands a high |V _G| (>> V _T) and a low V _D, whereas the neuronal mode requires a low V _G (< V _T) and a high V _D.

2.2. Interconnected Characteristics of a Neuron and a Synapse

A spiking neural network consists of a presynaptic neuron and postsynaptic neurons connected through synapses. When the presynaptic neuron fires, the spike signal is transmitted through the synapse and applied to postsynaptic neurons with different current values depending on the synaptic weight. The interconnection properties between the neuron and synapse are shown in Figure 3. Figure 3a shows the circuit schematic for signal transmission between the presynaptic neuron and the synapse. When input voltage to the neuron (V _IN,N) is applied, current (I _IN,N) flows into the neuron device due to the resistor (R _D) connected in series to the drain of the neuron. Consequently, the neuron generates a spike signal, as depicted by the red curve in Figure 3b. The neuron remains inactive and does not transmit any signal until V _D reaches a threshold level, denoted as V _LU. Once V _D reaches V _LU, the neuron fires and generates a spike.

FIGURE 3.

Measured characteristics of the cointegrated SONOS‐FET for neuron and synapse operations: (a) Circuit diagram illustrating the connection of the proposed SONOS‐FET between neurons and synapses. Resistors are connected in series to the drain and the source of the neuron, while the synapse is connected in parallel to the source load resistor (R _S). (b) When input voltage (V _IN,N) is applied to the neuron, current is fed to the neuron, with wedge‐shaped output voltage then produced from the neuron. When the neuron fires, charge flows at once to R _S, which serves as the input voltage for the synapse (V _IN,S). When the synaptic weight is high (LRS), a pulse‐shaped current is generated, whereas when the synaptic weight is low (HRS), no current is produced. (c) Extracted f _spike as a function of V _IN,N. (d) Extracted f _spike for various R _D (e) Extracted peak value of the input voltage applied to the synapse (V _IN,S) for various R _S. (f) Synaptic output current at five different conductance levels (G ₀ < G ₁ < G ₂ < G ₃ < G ₄).

When the neuron fires, the integrated charges are discharged rapidly through the source terminal. The resulting source current (I _S) as the output current (I _out), exhibiting a narrow peak profile, is subsequently converted into a synapse input voltage (V _IN,S) with a spiking waveform by the source load resistor (R _S). As a result, the spike signal generated by the presynaptic neuron is transmitted to the connected synapse, as indicated by the blue curve in Figure 3b. According to Ohm's law, I _OUT,S is proportional to V _IN,S scaled by the synaptic conductance (weight). Thus, when the synaptic weight is high, corresponding to an LRS, a high level of I _S (green curve in Figure 3b) is delivered to the synapse. In contrast, when the synaptic weight is low, corresponding to an HRS, a lower level of I _OUT,S (orange curve in Figure 3b) is transmitted to the synapse.

When a signal is transmitted from a presynaptic neuron to a postsynaptic neuron through a synapse, its magnitude is governed by the amount of charge delivered. Accordingly, the interconnection configuration of the presynaptic neuron, postsynaptic neuron, and synapse must be carefully designed. A comparison suggests that the configurations in Figure 3a and Figure S8a enable more accurate transmissions of information than the configuration in Figure S8b. When the synaptic input voltage is derived from the source terminal through the series resistance shown in Figure S8a, the voltage across R _S reflects each presynaptic spike, and the corresponding charge per event remains constant regardless of the firing frequency. This implies that the postsynaptic neuron receives an accurate representation of the presynaptic information encoded through the spike frequency. In contrast, if the synaptic input voltage (V _IN,S) is taken not from the source terminal but from the drain terminal of the presynaptic neuron, as shown in Figure S8b, the delivered charge becomes dependent on the operating frequency of the presynaptic neuron. Thus, an increase in presynaptic activity decreases the charge per spike, which in turn degrades the fidelity of information transmission to the postsynaptic neuron.

As shown in Figure 3c, the spiking frequency (f) increases with an increase in V _IN,N. f is determined by both V _IN,N, and R _D, as follows:

$$f=1/\mathrm{\Delta }t=1/\left(R_{\mathrm{D}}·C_{\mathrm{par}}·\ln \left[\left(V_{\mathrm{IN},\mathrm{N}}-V_{\mathrm{bottom}}\right)/\left(V_{\mathrm{IN},\mathrm{N}}-V_{\mathrm{top}}\right)\right]\right)$$ (3)

In this equation, C _par represents the parasitic capacitances arising from the parameter analyzer and the associated cables used to connect the probing tips to the analyzer. If V _bottom and V _top are much smaller than V _IN,N, f is then approximated to 1/(R _D · C _par · [{V _top − V _bottom}/V _IN,N]). Details of this equation are explained in Text S1.

On the other hand, f and V _{IN, S} were controlled by adjusting R _D and R _S, respectively. As shown in Figure 3d,f decreases inversely with an increase in R _D. V _{IN, S} was also modulated by varying R _S, as shown in Figure 3e. As R _S increases, V _{IN, S} increases initially but becomes saturated when R _S exceeds a certain value. This behavior corresponds to the reduction in the firing current with an increase in the resistance, which is also evident from the I _D‐V _D characteristics, as shown in Figure S9. Figure 3f shows the output current of the synapse (I _{out, syn}) at different weights (G _i). The spike‐shaped I _{out, syn} from the synapse, becomes larger as G _i increases.

Meanwhile, energy consumption is an important metric for low‐power neuromorphic computing. Figure S10 shows the measured waveforms used to extract the operation energy of the SONOS‐FET‐based neuron and synapse. First, the energy consumption per neuronal spike (E _neuron/spike) was defined as the energy consumed by the input current during one spiking period and was calculated as $E_{neuron}/\mathrm{spike}=I_{in}·{\int }_0^{1/f}{V}_{OUT,N}(t)dt$. The extracted neuronal energy consumption was 746 pJ/spike. In the neuron‐synapse connection scheme shown in Figure 3a, the synapse is not read by an externally applied DC read voltage. Instead, the firing current generated by the neuron is converted into a spike‐shaped V _IN,S through R _S, and this transient voltage is delivered to the synapse input. Therefore, in the ACTANS configuration, the synapse is not read by applying a separate DC read voltage. Instead, the spike‐shaped V _{IN, S} generated by the presynaptic neuron is applied to the synapse, and the corresponding synaptic current is transmitted to the following neuron. Thus, the synaptic read energy was evaluated as the spike‐driven synaptic read energy consumed in the synapse branch during one presynaptic spike. The synaptic read energy per spike (E _{read, syn}/spike) can be approximated as $E_{\mathrm{read},\mathrm{syn}}/\mathrm{spike}\approx G_{CH}·{\int }_0^{1/f}{V}_{\mathrm{IN},\mathrm{S}}^2(t)dt$. Using the measured V _{IN, S} waveform, and G _CH = 1 µS, the extracted synaptic read energy was 53.4 pJ/spike. A comparison of the device‐level inference energy and CMOS compatibility with previously reported artificial neuron–synapse hardware is summarized in Table S2.

It is worth noting that the extracted neuronal and synaptic energies include the influence of parasitic capacitances associated with the measurement setup, including the measurement instruments, cables, connectors, and probing configuration connected to the V _{OUT, N} and V _{IN, S} nodes. These parasitic capacitances increase the effective capacitive load and can prolong the charging and discharging transients, thereby increasing the energy evaluated from the measured voltage waveforms. Therefore, the reported values do not necessarily represent the intrinsic energy limits of the SONOS‐FET devices. The operating energy is expected to be further reduced through on‐chip integration and shorter interconnections that minimize the parasitic capacitance at these nodes.

2.3. Measurement of the 1 × 16 Neuron‐Synapse Array Configuration

By interconnecting the neurons and synapses through metallization, we implemented a proof‐of‐concept demonstration of a SONOS‐FET‐based ACTANS with a fan‐out value of 16, in which a single presynaptic neuron drives sixteen synapses (S₁, S₂, …, S₁₆), forming a 1 × 16 array. Figure 4a presents the hardware setup with the demonstrated ACTANS, which consists of seventeen homotypic SONOS‐FETs. A probe card connects the ACTANS and the measurement setup, enabling both voltage application and signal measurement from the single neuron and sixteen synapses. Figure 4b illustrates the circuit schematic of the hardware setup used to demonstrate ACTANS operation. V _IN,N is applied to activate the neuron, while each synapse is biased with a gate voltage (V _{SG, i} ; i = 1, 2, 3, …, 16) of 2.5 V during the read operation. The output current of each synapse (I _{S i} ) is measured using a read‐out circuit that includes a charge integrator with a 300 pF feedback capacitor and an 8‐bit analog‐to‐digital converter (ADC). The measured output from the read‐out circuit is transferred to a field‐programmable gate array (FPGA). Additionally, the voltage applied to R _S is simultaneously monitored using an oscilloscope to observe the neuron's spiking operation.

FIGURE 4.

Hardware implementation for a proof‐of‐concept demonstration of SONOS‐FET‐based ACTANS: (a) Photograph of the hardware setup for array measurements, including an FPGA‐based hardware system and an oscilloscope. (b) Circuit diagram of the demonstrated ACTANS with a single presynaptic neuron and 16 synapses. (c) Illustration of the distribution of the five‐level distinguishable updated conductance levels of the 16 synapses. (d) Measured output of each synapse as a function of V _IN,N. The output currents of the synapses are accumulated by a charge integrator and converted to 8‐bit outputs by the ADC. (e) Differential pair configuration for both positive and negative weight representation, with the weights defined as the conductance differences between adjacent synapses, G _2i‐1‐G _2i. (f) Output of each differential pair, calculated by subtracting the ADC outputs of paired synapses. V _IN,N is bidirectionally swept in the range of 4.8 V to 7.9 V in steps of 0.1 V, and this is repeated 16 times.

To evaluate the ACTANS with this hardware setup, we updated the 16 synapses to five distinct conductance levels, as shown in Figure 4c. Then, we measured the output current of each synapse while increasing V _IN,N. The output current was accumulated by the charge integrator for 25.5 msec, and the integrator output voltage was converted into 8‐bit digital values by the ADC. Figure 4d shows that the ACTANS output measured by the read‐out circuit increases with V _IN,N. The ADC outputs form five distinct branches with different slopes as a function of V _IN,N, corresponding to the updated synaptic conductance levels. For neuronal operation, the synapse output appears only when V _IN,N exceeds V _LU. Consistently, the neuron fires more rapidly as V _IN,N increases, resulting in a higher ADC output in accordance with Equation (3).

Furthermore, a differential pair scheme was employed to represent both positive and negative synaptic weights by producing an output based on the difference in conductance. This output was obtained by calculating the difference between the ADC outputs measured at the source lines of adjacent synapses. Specifically, Outputs 1 to 8 correspond to conductance differences between adjacent synapse pairs (G ₁–G ₂, G ₃–G ₄, G ₅–G ₆, G ₇–G ₈, G ₉–G ₁₀, G ₁₁–G ₁₂, G ₁₃–G ₁₄, and G ₁₅–G ₁₆), as shown in Figure 4e. The detailed configuration is shown in Figure S11. Although the conductance of an individual SONOS‐FET synapse is strictly positive, this approach enables the representation of both positive and negative weights.

Figure 4f shows the measured outputs of the differential pairs, which either increase with a positive slope or decrease with a negative slope as V _IN,N increases, depending on the synaptic weight. The positive outputs are separated into four distinct branches, while the negative outputs form four corresponding branches, clearly reflecting the updated synaptic weights. Notably, even after 16 repeated double sweeps, the outputs remain separated, demonstrating stable operation with low cycle‐to‐cycle variation. A video of this real‐time demonstration of the neuromorphic hardware system using a fan‐out‐16 ACTANS is provided as Video S1 in the Supporting Information.

The demonstrated 1 × 16 ACTANS serves as a proof‐of‐concept array that experimentally verifies the feasibility of SONOS‐FET‐based neuron‐synapse cointegration. It confirms that spikes generated from a presynaptic neuron are transmitted to 16 synapses, that synaptic currents are generated according to the programmed synaptic states, and that fan‐out‐16 operation is achieved with low cycle‐to‐cycle variation. However, to extend this small‐scale array demonstration toward large‐scale neuromorphic integration, several device‐ and array‐level scaling challenges should be considered.

First, it is important to ensure that presynaptic spikes can be delivered to a large number of synapses with sufficient amplitude. In the present structure, as shown in Figure 3a and Figure S8, the I _S generated during neuronal firing is converted into a voltage signal through the R _S, and this voltage is delivered to the V _{IN, S}. Therefore, the V _{IN, S} is not determined only by the R _S, but by the effective load formed by R _S in parallel with the equivalent resistance of the connected synapses (R _{syn, eq}). Accordingly, V _{IN, S} can be expressed as I _S∙R _{eff, load}, where R _{eff, load} is the effective load resistance given by parallel combination of R _S and the equivalent synaptic resistance R _{syn, eq} (= 1/G _{syn, total} =$1/{\sum }_i{G}_i$), that is, R _{eff, load} = R _S||R _{syn, eq}. Here, G _{syn, total} and G _i denote the total synaptic conductance and the conductance of the i‐th synapse, respectively. As the number of connected synapses corresponding to the fan‐out number (N _fan‐out) increases, G _{syn, total} generally increases, thereby decreasing R _{syn, eq} and potentially reducing V _{IN, S}. For the implemented 1 × 16 ACTANS, R _{syn, eq} and the R _{eff, load} are summarized in Figure S12. The resulting R _{eff, load} was sufficient to deliver the spike signal to the synapse array, consistent with the V _{IN, S} versus R _S relationship shown in Figure 3e. For larger fan‐out configurations, however, R _S, G _i, and N _fan‐out should be co‐optimized considering the target task, conductance range, and required input‐voltage margin.

Second, device‐to‐device variation in neurons and synapses can limit the reliability of large‐scale arrays. Variations in V _top and V _bottom of neurons can affect spike timing and signal‐transmission margin, while conductance variation in synapses can degrade weight precision and output separation. In this work, device‐to‐device variations of 30 neurons and 30 synapses were experimentally evaluated, as shown in Figure S13. As the array size increases, such variations can have a more significant impact on network‐level inference accuracy. The impact of these experimentally measured variations on network‐level inference was further examined in the software‐based simulation by incorporating the variation of the neuronal and synaptic characteristics, as discussed in the following section.

Third, inhibit‐induced drift and energy overhead in unselected synapses during P/D operations of selected synapses are also important scaling issues. To update only the selected synapse, inhibition biases are applied to unselected synapses according to the bias conditions summarized in Table S1. However, as the array size increases, each unselected synapse is exposed to repeated inhibit stress more frequently. Therefore, conductance drift during long‐term inhibition operation should be considered when determining the synaptic weight resolution and array size. In particular, to reliably represent an n‐bit synaptic weight, the inhibit‐induced conductance variation should be sufficiently smaller than the spacing between adjacent conductance levels, that is, (G _max‐G _min)/[2 ⁿ ‐1]). In larger arrays, a periodic read‐and‐correction operation or a verify‐and‐update pulse scheme may be required to compensate for the weight drift accumulated during inhibition. In addition, although the update energy of the selected synapse is very low (Figure S6), the inhibition operation can introduce non‐negligible energy overhead because a high V _D is also applied. Under the potentiation‐inhibit condition, gate‐induced drain leakage (GIDL) can occur owing to the simultaneous application of negative V _G and V _D. Under the depression‐inhibit condition, a larger channel current can flow because a V _D is applied while the channel is formed by the positive V _G. Based on the measured I _D and V _D characteristics of the SONOS‐FET shown in Figure S14, the energy consumed per event is 52.02 pJ/event for potentiation‐inhibit and 4.64 nJ/event for depression‐inhibit. Therefore, considering the present inhibit scheme, the SONOS‐FET‐based ACTANS is more suitable for inference‐oriented neuromorphic hardware, where trained weights are stored and used for a long time, rather than for frequent on‐chip learning.

Finally, endurance under repeated operation is another important scaling factor. The SONOS‐FET‐based neuron showed stable neuronal operation, with V _top and V _bottom remaining nearly unchanged even after 10⁷ spiking operations, as shown in Figure S15. In contrast, the SONOS‐FET‐based synapse exhibited a gradual decrease in conductance and a reduction in dynamic range after repeated weight updates, as shown in Figure S16. This degradation is attributed to residual charges in the charge‐trap nitride (CTN) caused by incomplete erasing, which gradually shifts up the threshold voltage and reduces the channel conductance. Such synaptic endurance degradation can be mitigated by replacing the SiO₂/Si₃N₄/SiO₂ gate dielectric stack with an Al₂O₃/Si₃N₄/SiO₂ stack and by incorporating a self‐curing or Joule‐heating‐based recovery scheme [37, 38, 39, 40]. From a system‐level perspective, these results suggest that the present SONOS‐FET‐based synapse is better suited for post‐training readout operation than for frequent in‐situ synaptic weight updating.

2.4. Letter Recognition With a Hardware Circuit Simulation

The intrinsic long‐retention characteristics of multi‐bit SONOS‐FETs, where each bit corresponds to a weight matched to a specific threshold voltage (V _T), make them suitable for inference tasks using off‐chip hardware with fixed synaptic weights. To evaluate the feasibility of a neuron–synapse cointegrated neuromorphic array based on SONOS‐FET devices for inference tasks and to explore the scalability of such an array beyond our 1 × 16 hardware prototype, we performed SPICE‐based simulations of letter pattern recognition using a 16 × 5 array. The main purpose of the SPICE simulation is to verify the circuit‐level functionality of the SONOS‐FET‐based cointegrated neuron‐synapse hardware. In particular, the simulation confirms spike transmission from presynaptic neurons to synapses, synaptic‐current generation according to programmed synaptic states, column‐wise current summation for multiply‐and‐accumulate (MAC) operation, and signal delivery to postsynaptic neurons.

Prior to the simulations, the artificial neuron exhibiting the STL phenomenon was modeled as a threshold switch connected in parallel with a capacitor. This neuron model showed good agreement with the measured data, as shown in Figure S17. For the synapse model, a conventional MOSFET supported by the SPICE simulator was employed; however, the weight of each synapse was emulated by adjusting the V _T value of each device. To simplify letter pattern recognition as a proof of concept, the V _T values were binarized as high V _T or low V _T. A high V _T value corresponds to a low synaptic weight, while a low V _T value indicates a high synaptic weight. This approach was necessary because the SPICE simulator used does not support the memory characteristics of a SONOS‐FET.

We constructed hardware capable of distinguishing five letters–“K,” “A,” “I,” “S,” and “T” –using 4 × 4 black‐and‐white pixel patterns, as shown in Figure 5a. The intensity of each pixel corresponds to the V _IN,N of the input neuron: when the pixel is black, V _IN,N is set to 6 V, and when white, V _IN,N is set to 0 V. Sixteen input neurons were labeled from Neuron 1 to Neuron 16, with input voltages denoted as V _IN,N1 to V _IN,N16, respectively. Meanwhile, the output neurons generate results corresponding to each recognized letter. Five output neurons were configured to classify the five letters, each designated from Neuron K to Neuron T, depending on the letter. As a result, we constructed a single‐layer perceptron (SLP) with a 16 × 5 array, employing a total of 80 synapses. Figure 5b presents the circuit implementation of the constructed 16 × 5 SLP array. The sixteen input neurons generate spike trains whose firing rates are determined according to the V _IN,N corresponding to each pixel intensity. Here, for each input neuron, R _D was set to 20 MΩ and R _S to 200 kΩ. Spikes are delivered along each row to D of the SONOS‐FET synapses in the same row, and each synapse produces a synaptic current at S according to the synaptic weight. Within each column, the S terminals of all synapses are connected, allowing the synaptic currents from the same column to be summed through Kirchhoff's current law. The accumulated current is then conveyed to the corresponding output neuron in the next layer. Consequently, the output neuron receiving the largest summed current exhibits the highest firing activity, indicating the recognized letter. To ensure accurate current summation and reliable signal transfer, a current mirror was used between the synapse array and each output neuron. Figure 5c shows the pattern recognition results. The input image induces the most spikes in the output neuron most strongly associated with it, enabling pattern inference. The synaptic weights are depicted in Figure S18.

FIGURE 5.

Letter recognition through a hardware‐based circuit simulation, reflecting the experimentally measured characteristics of the SONOS‐FET‐based neurons and synapses: (a) Schematic of the single‐layer spiking neural network constructed for letter classification, with each pixel corresponding to one of the 16 input neurons. (b) Circuit schematic for the SPICE simulation to classify letters. (c) Spike outputs from each output neuron, demonstrating how the network distinguishes between different input letters.

Furthermore, to improve discriminability among output neurons, we implemented lateral inhibition in the output layer, where each output was interconnected with a dedicated inhibition transistor. As shown in Figure S19, when a neuron generates a spike, the integrated charge of the other neurons is laterally inhibited by discharging it through the inhibition transistor. For this operation, D of each inhibition transistor is connected to D of its corresponding output neuron, while G is connected to S of the output neuron, allowing the inhibition to operate without an additional power supply. Consequently, the accuracy of pattern recognition in the proposed hardware can be enhanced, benefiting from the improved contrast among neuronal outputs achieved through lateral inhibition. The circuit diagram for pattern recognition is shown in Figure S20. Additionally, letter recognition under noisy conditions was demonstrated, as shown in Figure S21. The constructed simulation‐based system can accurately distinguish letters even in the presence of pattern noise, highlighting its robustness.

2.5. Pattern Recognition With a Software Simulation

In the previous section, a small‐scale fully implemented hardware system corresponding to 16 input pixels was employed. In contrast, this section presents software‐based semi‐empirical simulations that incorporate experimentally measured data from the fabricated neurons and synapses, scaled to a larger input size of 784 pixels. Rather than recognizing simple mosaic‐like character patterns on a checkerboard, we evaluate the feasibility of recognizing more complex patterns, specifically handwritten digits from the Modified National Institute of Standards and Technology (MNIST) dataset, using a software‐based approach. To this end, we investigate whether a multilayer perceptron (MLP) architecture with 784 input neurons, extending beyond the previously demonstrated SLP architecture with 16 neurons implemented in full hardware, can effectively perform digit recognition. This approach was achieved by modifying the well‐developed open‐source SNN code produced by Duan et al. [28].

As shown in Figure 6a, the SNN is composed of three layers: 784 neurons in the input layer, 100 neurons in the hidden layer, and ten neurons in the output layer corresponding to the ten digits. All neurons and synapses are modeled based on identical SONOS‐FETs, which share the same structure but operate with different functions. The parameters of the network were directly extracted from experimental measurements of the devices. Specifically, the extracted V _LU of the SONOS‐FET was used to set the firing threshold voltage of the corresponding software‐based neuron, while the resistance value in the off‐state of the device was mapped to the neuron's leaky behavior. To convert the pixel intensity of handwritten images into input spikes, we fitted the measured f _spike as a function of V _IN,N (Figure 3c), and used this mapping to generate the input spike train.

FIGURE 6.

Software‐based simulation for pattern recognition: (a) SNN configuration for the classification of handwritten digits using the MNIST dataset. (b) Sequential flow to illustrate the inference and learning processes during SNN training. (c) Simulated classification accuracy with the number of training epochs. (d) Confusion matrix of the classification results.

Figure 6b illustrates the procedure for SNN training. Spikes generated at the input neurons, based on the pixel intensity, are transmitted to the first synapse crossbar array. Depending on the synaptic conductance, the weighted signals are delivered to the hidden layer neurons. In the hidden layer, each neuron performs the LIF operation, as that in the input layer does. As the V _OUT,N of a hidden layer neuron increases and reaches V _LU, the neuron fires and transmits the spike to the next synapse crossbar array, after which V _OUT,N abruptly drops again. Subsequently, the spikes generated by the hidden layer neurons are then conveyed to the output layer neurons through the synaptic crossbar, modulated by the corresponding weights. The output layer neurons then fire spikes when V _OUT,N reaches V _LU. Lastly, the spikes at each output neuron are counted, and the digit classification is determined by the neuron with the highest firing rate. For the synaptic model used in the SNN simulation, the experimentally measured P/D characteristics in Figure 2e were fitted using Equation (1). To train the SNN, backpropagation through time was applied with a sigmoid‐based surrogate gradient for the non‐differentiable LIF firing function. Because the conductance modulation in Equation (1) is smooth and monotonic in η, the measured P/D nonlinearity and asymmetry are propagated through the forward path during training, and the gradients with respect to η are computed via the chain rule through the same nonlinear curve. It is worth noting that this is a semi‐empirical SNN simulation rather than a full pulse‐by‐pulse hardware training framework. As shown in Figure 6c, an accuracy of approximately 96.8% was achieved for the classification of handwritten digits. This result approaches the software‐based accuracy of 97.7%, obtained by assuming ideal synaptic update behavior with 𝛼_pot = 𝛼_dep = 1. Figure 6d presents a confusion matrix of the classification results, where high values along the diagonal indicate reliable classification performance.

In addition, as discussed in Section 2.3, device‐to‐device (D2D) variation in neurons and synapses needs to be considered in device‐aware simulations of neuromorphic networks. In the preceding device‐aware SNN simulation, the measured P/D characteristics were incorporated using a continuous synaptic internal state variable. However, if D2D variation is included during training, the optimizer can partially compensate for the device‐specific conductance characteristics. Therefore, in this additional analysis, the network was first trained using representative single‐device characteristics, and the trained network parameters were then fixed while the experimentally measured D2D variation was injected only during the inference/deployment stage.

Specifically, for the synapses, the conductance‐related D2D variation extracted from Figure S13 was reflected in the synaptic conductance mapping, while for the neurons, the measured V _top variation was incorporated as firing‐threshold variation. This deployment‐stage D2D injection allows us to evaluate the accuracy degradation that can occur when the trained network is deployed onto a device array with realistic D2D variation, without allowing the training process to compensate for the variation. Figure S22 compares the MNIST recognition accuracy under the representative‐device condition and the deployment condition including D2D variation. After incorporating the measured D2D variation, the recognition accuracy decreased from 96.8% to 95.2%, corresponding to a limited degradation of 1.6 percentage points. This result indicates that the SNN maintains relatively stable classification performance under the D2D variation conditions considered in this simulation. This suggests that the proposed ACTANS framework can operate under realistic device variation.

3. Conclusion

We presented the Array of Cointegrated Transistor‐based Artificial Neuron and Synapse (ACTANS), a neuromorphic hardware platform in which neurons, synapses, and transistors are homotypic SONOS‐FETs fabricated on a single silicon plane using a fully CMOS‐compatible microfabrication technique. The structure of the n ⁺ source–p‐type FB–n ⁺ drain along the channel direction enables LIF neuronal behavior, while the charge‐trapping nitride layer in the gate dielectrics realizes synaptic plasticity with multi‐level conductance states, with the intrinsic MOSFET operation providing transistor functionality. Importantly, we experimentally demonstrated reliable neuron‐to‐synapse signal transmission and established a 1 × 16 neuron–synapse array, achieving a stable fan‐out value of 16 connections.

Building on this device‐level performance, we demonstrated the feasibility of neuromorphic computation at the system level through hardware circuit simulations for letter recognition and semi‐empirical software simulations for MNIST digit classification, achieving high pattern recognition accuracy. Combined with the scalability and robustness of ACTANS, enabled by standard CMOS fabrication, these results underscore its manufacturability and potential for large‐scale integration. Overall, the demonstrated neuron–synapse cointegration using SONOS‐FETs marks a significant advance toward energy‐efficient, compact, and scalable neuromorphic computing systems capable of overcoming the limitations of the von Neumann architecture.

4. Experimental Section

4.1. Electrical Characterization

The electrical characteristics of the SONOS‐FET‐based neurons and synapses were measured using a parameter analyzer (Keysight B1500A, Keithley 4225‐PMU). The synapse input voltage was measured using a TDS 744A oscilloscope (Tektronix). Measurements of the 1 × 16 neuron‐synapse array were done with a customized measurement system consisting of a data acquisition tool (National Instruments, USB‐6363).

4.2. TEM and SEM Analysis

TEM images were acquired using a field‐emission scanning transmission electron microscope (Hitachi High‐Technologies Corporation, HD‐2300A). SEM images were obtained with a critical‐dimension scanning electron microscope (Hitachi High‐Technologies Corporation, S‐9260A).

4.3. Device Simulation

The device simulations for the neuron characteristic analysis were TCAD Sentaurus simulations (Synopsys). These simulations included Fermi‐Dirac carrier statistics to ensure an accurate carrier distribution, as well as doping‐dependent and electric‐field‐dependent mobility models, in this case, the Philips Unified Mobility model (PhuMob), the Inversion Layer Mobility model (IALMob), and high‐field saturation mobility models for electrons and holes (eHighFieldSat and hHighFieldSat). Bandgap narrowing effects were incorporated using the Old Slotboom model. Recombination mechanisms considered in the simulation included Shockley–Read–Hall (SRH) recombinations, Auger recombinations, impact ionization modeled using the Gradient Quasi‐Fermi model (GradQuasiFermi), and band‐to‐band tunneling based on the Hurkx model. Quantum mechanical effects were also included through quantum correction models.

4.4. Hardware‐Based Circuit Simulation

Circuit simulations for letter pattern recognition were conducted using LTspice software (Analog Devices). Neurons were modeled as a connection between a capacitor and a threshold switch in parallel. Synapses were represented by three‐terminal MOSFETs, with synaptic weights modulated by adjusting the threshold voltage (V _T) of the MOSFETs.

4.5. Software‐Based Simulation

Software simulations for pattern recognition were conducted using Python software.

Conflicts of Interest

The authors declare no conflicts of interest.

Supporting information

Supporting File 1: smll74638‐sup‐0001‐SuppMat.docx.

Supporting File 2: smll74638‐sup‐0002‐VideoS1.mp4.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.