Breaking the bottleneck in AI clusters with parallel photonic integration

Abstract

AI workloads demand increasing energy, scalability and transparency from data center infrastructure. Modern distributed AI models use clusters of processors to perform collective matrix operations based on 1940s pairwise designs, which remain foundational in tensor cores and scale in complexity with the number of processors. To eliminate this bottleneck in distributed AI clusters, here we present Parallel Photonic Integration (PPI), a collective computation architecture purpose-built for hyperscale AI. PPI replaces sequential electronic operations with fully parallel, photonic-simulcast computation, which enables multi-node matrix operations while also delivering real-time model transparency without added cluster load. Replacing network switches enables PPI to integrate into existing AI frameworks and perform light-based multi-matrix calculations, as shown in our early-stage proof-of-concept. Predictive modeling of AllReduce across large GPU clusters running Transformer workloads shows that PPI can reduce per-operation energy by over 50% compared with switched-fabric interconnects, while reducing AllReduce latency by over 100x at frontier scale. These results demonstrate that PPI can provide a scalable, energy-efficient, and transparent foundation for next-generation AI.

Researchers introduce parallel photonic integration, a light-based method that runs AI cluster calculations in parallel. Replacing sequential data exchange with optical broadcasts, it removes bottlenecks, which cuts energy use and reduces latency.

Introduction

The rapid growth of large-scale AI has exposed a fundamental mismatch between computational demand and the architectures used to support it. Modern AI training and inference rely on vast distributed systems that must continuously exchange information while performing collective matrix operations across thousands of processors. Despite extraordinary advances in semiconductor technology, large-scale AI systems continue to build collective computation from binary arithmetic operations and pairwise communication primitives^1,2. Matrix multiplication, reductions, and distributed collective operations are decomposed into vast numbers of two-input interactions, requiring increasingly complex communication and synchronization structures as system scale grows. While effective at smaller scales, the volume of sequential communication and pairwise operations increases dramatically as processor counts grow, creating escalating demands on network infrastructure and energy consumption^3–7. As AI clusters expand toward ever-larger scales, the efficiency of collective operations has emerged as a primary constraint on performance, scalability, and sustainability⁶. The underlying complexity and black-box architecture also limits transparency⁸.

The need for scalable solutions is underscored by the rapid growth in AI model complexity: The number of model parameters is increasing exponentially, dramatically outpacing improvements in hardware^9,10. For performance, workloads now run in parallel on many processing units (PUs). However, communication bottlenecks, especially during all-to-all exchanges, can consume over 50% of training¹¹ and inference¹² time. Primary drivers of these bottlenecks include data movement, which encompasses serialization and inter-device transfers, such as collective communication, as well as additional memory operations, such as redundant reads and writes, matrix alignment adjustments, and temporary buffer creation^9,13–15. Transforming computation to eliminate bottlenecks during collective reduction operations has become imperative.

Results

Concept: AI infrastructure limitations motivate fully parallel processing

Transformers and other advanced AI models rely on processor parallelism. However, collective operations like AllReduce remain sequential, creating bottlenecks and limiting scalability by throttling the latency of collective operations (Supplementary Information F (SI-F) and Supplementary Figs. 1, 2). These inefficiencies increase energy consumption, with data centers projected to use up to 12% of U.S. power by 2028, primarily due to AI infrastructure³. Optical interconnects¹⁶ and computing¹⁷ technologies improve bandwidth and efficiency but do not resolve bottlenecks in collective operations. Software and hardware optimizations help^18–20 but often shift bottlenecks elsewhere, leaving large-scale AI systems constrained in scalability and energy efficiency.

Drawing inspiration from neurobiological systems, we note that current sequential switched-fiber infrastructures like InfiniBand and Ethernet fail to emulate a key property of mature neural networks: spatiotemporal integration of inputs from electrochemical synapses²¹. Electrochemical signal transduction, while complex and energetically costly to maintain, enables parallel multi-signal integration from many different sources, as well as amplification, modulation, and overall energy efficiency^22,23. Recognizing the value, much work has focused on building artificial synapses²⁴, which emulate single electrochemical synaptic inputs, but do not solve the fundamental problem of collective operations across multiple parallel processors: resource contention⁷ that causes bottlenecks.

Brain neurons that perform the most sophisticated calculations integrate information from many sources in parallel across space and time within specialized cellular branches known as dendrites. While pairwise processing of modern computer systems may offer a reasonable approximation of a synapse, computers have previously had no functional hardware equivalent to dendrites. In applications other than AI, the simple elegance of pairwise processing has served us well. However, pairwise processing is not simple or elegant for collective computations run on distributed architectures. Pairwise operations in distributed systems are inherently inefficient^7,25 (Table 1). This inefficiency has real-world consequences in the form of dramatically decreasing performance (SI-F: B; Supplmentary Fig. 8) and increasing energy consumption³.

Table 1.

Summary of AllReduce scaling properties

Property	Fat-tree (no SHARP)	Fat-tree + SHARP	PPI
Serial steps	$2\mathrm{\lceil }{\log }_{2}G\mathrm{\rceil }$	$2\mathrm{\lceil }{\log }_{32}G\mathrm{\rceil }$	1
Steps at G = 4,096	24	6	1
Steps at G = 16,384	28	6	1
Scaling class	$\mathrm{\Theta }\left(\log G\right)$	$\mathrm{\Theta }\left(\log G\right)$	$\mathrm{\Theta }\left(1\right)$
BW contention at scale	70% at G > 51247,48	90% at G > 51261	None
Physical mechanism	GPU-level pairwise merge through switch fabric	In-network (switch-level) pairwise merge	Simultaneous optical superposition

System architecture

We have now developed parallel photonic integration (PPI): a computational substrate that uses simulcast light patterns for parallel collective matrix calculations. PPI technology optimizes AI infrastructure by combining many pairwise operations into one and reducing the amount of data that traverses the network and loads into memory. This approach leverages optical methods to perform collective matrix computations at scale in a single step, i.e., O(1) instead of O(n) or O(log_x n) complexity²⁶, enhancing efficiency and performance in AI systems (Table 1,SI-F).

In current AI infrastructures, PUs send data sequentially on a tiered fiber network, which involves substantial network traffic and resource contention⁷ (SI-F: §A; Supplementary Figs. 1–2). To decrease time lags due to congestion, one may implement sophisticated in-network computing^27,28 or tensor pre-slicing with precise slice routing²⁹, each of which requires computational overhead without eliminating sequential computational complexity.

Although optical intensity integration has previously been explored in the context of analog photonic computing and free-space broadcast networks, those approaches typically perform intra-device accumulation or rely on subsequent electronic reduction for multi-node collectives. In contrast, PPI integrates spatially encoded, quantized contributions from independently clocked processing units such that collective formation occurs prior to network routing or packetization. This distinction is critical: the collective is formed as a property of the communication field itself rather than through traversal of a logical communication graph (Table 2).

Table 2.

Technology differentiation: PPI capabilities versus prior approaches

Category	Demonstrated function	Communication topology	Collective complexity	Multi-PU simultaneous reduction	Native data transparency	Resource contention eliminated (α = 0)
Silicon photonic interconnects,68,69,70	Sequential: Point-to-point data transport	Pairwise: Serial optical links	O(n) or O(n log n): Unchanged from electronic collectives	Not proposed: Data serialized through switch hierarchy	Not proposed: No real-time observability of collective computation results	No: Bandwidth shared across sequential hops
Photonic matrix processors / ONNS71–73	Sequential: Single-device matrix-vector multiply (inference accelerator)	Pairwise: Intra-chip waveguide mesh	Not addressed: No multi-PU collective	Not proposed: Single chip; no multi-node aggregation	Not proposed: No real-time observability of collective computation results	Not proposed / not applicable: single device
Electronic in-network computing28,61,74	Sequential: Switch-accelerated collective reduction	Pairwise: Tree / fat-tree with serial hop reduction	O(log n): Tree-reduction through smart switches	Not proposed: Data still traverses switches sequentially (pairwise at each hop)	Not proposed: No real-time observability of collective computation results	No: Switch ports still contended
Software collective optimization75,76	Sequential: Algorithmic scheduling of electronic collectives	Pairwise: Ring / tree / hybrid logical topologies over physical network	O(n) ring or O(n log n) tree: Bound by physical serialization	Not proposed: Software cannot change the physical serial constraint	Not proposed: No real-time observability of collective computation results	No: Still contends for shared physical bandwidth
Memory-Centric / Compute Express Link (Cxl)77–79	Sequential: Shared-memory semantics over fabric	Pairwise: Bus / fabric (limited node count)	O(n) or O(n log n): Collective still serialized	Not proposed: Memory reads/writes still sequential	Not proposed: No real-time observability of collective computation results	No: Reduced within node but grows across nodes
Free-space optical communication80–82	Sequential: Data transport via free-space optics; broadcast topology demonstrated for distribution only	Pairwise: Broadcast or point-to-point; star coupler or WDM fan-out	Not proposed: Relay to electronic processing for any collective operation	Not proposed: No prior work combines broadcast with structured multi-PU computational accumulation	Not proposed: No real-time observability of collective computation results	No: Contention at optoelectronic receivers
Artificial synapse / neuromorphic photonic83,84	Sequential: Emulate single synaptic weight or neuron at device level	Pairwise: Intra-chip synaptic crossbar or spiking network	Not addressed: No multi-PU collective	Not proposed: Emulates one synapse; not multi-source dendritic integration across PUs	Not proposed: No real-time observability of collective computation results	Not proposed, Not applicable: Single device / small network
PPI (this work)	Parallel: Fully parallel collective computation + communication + transparency	All-to-all: Simultaneous broadcast with physical-layer reduction	O(1): Demonstrated single-step parallel reduction independent of PU count	Demonstrated: All PUs can contribute and receive simultaneously through spatiotemporal integration	Demonstrated: Fault detection and localization; audit trail, tamper evidence, and convergence monitoring (see SI-F)	Yes: Dedicated parallel pathways eliminate contention

Key information in bold, additional detail in regular text.

PPI totally parallelizes transmission and collective operations through simultaneous broadcast and reception across all PUs. PPI minimizes subsequent data transmission and memory loading by a factor equal to the number of sending PUs. This data reduction is achieved through optical in-network intensity summation, where data is processed in parallel and collectively reduced in one step. This requires network synchronization, which is a hallmark of higher cognitive function^30,31 and achievable with current digital infrastructure^32,33.

PPI utilizes reconfigurable light patterns displayed on a shared surface, which are then captured by photosensors for further processing. Figure 1 illustrates two representative PPI systems within a broader design space: projection (a) and μLED screens (b). Core to each design is the capacity for each PU to simulcast its own data in parallel to all receiving PUs and the ability for all PUs to simultaneously receive it, also in parallel.

Fig. 1. Example system designs for PPI.

a The projection system gives each of 4 PUs their own projector with which they transmit binary encodings of data at the lowest detectable light intensity. b Light intensity of the overlays can be decoded as the bit count of PUs that had a binary ‘1’ for the bit value encoded by that spatial position. One or more cameras read the bit counts with their in-line FPGAs and send the data to downstream PUs. c The μLED screen-based system gives each PU their own set of interdigitated pixels on a multi-controller screen. d Similar to the projection system, overall light intensity of the spatial field for a given bit value provides the bit count that can be further decoded to give the sum of matrices.

Both versions use commercially available high-speed cameras that are already capable of sampling rates sufficient for the applications discussed in this paper^34,35. Further, the speed of professional digital cameras can be accelerated by decreasing the size of the frame that is captured and sampling data in “Regions of Interest” (ROIs) larger than a single pixel. Using more cameras to subdivide the space provides faster sampling at the cost of more energy to run the cameras.

A projection-based system uses custom projectors built around a commercial digital micromirror device (DMD)^36,37 capable of 11,000 fps. Figure 1a shows a highly simplified example setup with four projectors and three cameras. In a compute cluster, each of 4 PUs sending Layer L data could have its own projector, while each of the three PUs receiving Layer L + 1 data could have its own camera (note that one camera could support more than one PU for energy efficiency and/or one PU could receive data from more than one camera for speed). Each projector emits a matrix of “flashbits” (spatiotemporally aligned light fields) that overlap with others in the cluster. Cameras capture spatial light intensity for each flashbit (Fig. 1b). Flashbits may carry no signal (bit count = 0) or varying intensity based on how many PUs projected a ‘1’ to that region. Bit counts are decoded from intensity levels.

An alternative PPI approach uses a μLED screen that consists of repeated “metapixels” that are functionally equivalent to the flashbits described above (Fig. 1c). Metapixels are contiguous spatial groupings of pixels that are each controlled by a separate PU, which individually manages a population of pixels interleaved with those from other sending PUs to enable a matrix of flashbits that simultaneously signal the data transmitted by all PUs. High frame rates, energy efficiency, and miniaturization capacity make μLED screens attractive for rack-mounted PPI devices. As shown, the relatively small μLED screens and cameras can be contained in an enclosed device and shielded from light, dust, vibration, and other noise sources. In addition, the small form factor facilitates hardware synchronization of the display and cameras. Figure 1d illustrates metapixel flashbits that result from the interdigitation of parallel, independent PU signals. Each PU controls its own set of flashbits independently, enabling fully parallel transmission. If no PU sends a ‘1’ for a given bit value, then the flashbit is dark, and the bit count is zero. Incrementally increasing the number of PUs that have a ‘1’ for that flashbit increases the overall intensity, which is decoded as bit count. Additional details can be found in SI-A: System Architecture Details and SI-F: §D, §E.

Fully parallel mechanism designed for scale

The system described above enables parallel multi-processor binary computations by summing light intensity in spatially-defined flashbits. Figure 2a shows a highly simplified example of data from three different PUs: projections of binary-encoded weighted activations for a single target neuron in the next layer. These inputs are encoded as images representing fixed-point binary numbers, where spatial location encodes information: bit value (row) and target neuron (column). The spatially aligned overlay of the three binary encodings produces four intensity levels, corresponding to the number of PUs that have a ‘1’ at each bit position, i.e., the bit count. The final sum is obtained by multiplying each bit value by its corresponding bit count and summing across all bits. Precision and range can be increased by adding more bits, at the cost of increased bandwidth. Figure 2b extends this concept to multiple target neurons (additional columns). A simpler approach, encoding numbers directly as analog intensity instead of bit values, would decrease the maximum number of PUs and the numeric range and precision, due to the limited dynamic range of photosensors.

Fig. 2. Binary summation using light intensity to encode bit count.

a In this simple example based on the projector variant, we examine the weighted activations from 3 PUs to one neuron in the next layer. Weighted activations are encoded as 16-bit fixed-point binary numbers that are transformed into spatial patterns where the spatial location of a flashbit encodes both the bit value and the target neuron. Each PU sends a separate weighted activation to the target neuron in this example, as shown on the left-hand side of the equals sign. The projection overlay on the right-hand side illustrates different intensities based on different bit counts that reflect how many PUs had a ‘1’ in that flash bit. The sum of the inputs to the neuron can be obtained by multiplying each bit value by its bit count and then summing the results. As with any precision, there will be some error based on the number of bits used for encoding. More fractional bits improve precision; more integer bits increase range—both at the cost of bandwidth. b When additional target neurons are introduced, each PU transmits a 2D matrix of flashbits in parallel. In this matrix, the rows represent bit values as in a, while the columns correspond to target neurons. The intensity of each flashbit encodes the count of occurrences for a specific bit value targeting a specific neuron.

To enable signed numbers and subtraction, two’s complement is used to represent signed numbers. To enable multiplication and division, the logarithm product rule

$$\log \left(xy\right)=\log \left(x\right)+\log \left(y\right)$$ 1

is used to sum logs and obtain the product. Element-wise logarithmic transformations can be implemented efficiently in parallel, either inline (e.g., with FPGAs or CMOS Integrated Circuits) or with minimal overhead on the cluster PUs, enabling scalable arithmetic operations without increasing sequential computational complexity in the network. These structured light operations could support the essential General Matrix Multiply (GEMM) computations required for large language models (LLMs), which would require significant redesign and retrofitting of current AI infrastructure. For this report, we focus on the performance and efficiency improvements provided by massively parallel PPI AllReduce functionality (see SI-F: §B for GEMM AllReduce improvements via PPI), which is drop-in compatible with current AI infrastructure as a network switch replacement (see prototype below).

By parallelizing the entire workflow, including communication and collective operations, bottlenecks can be eliminated, ensuring smooth and efficient data exchange across parallel processing units. Figure 3 shows fully parallel communication enabled by PPI in the μLED screen version. Unlike conventional systems where PUs process data in parallel but then serialize communication through fiber optic links and routing hardware, this approach encodes data as structured light matrices and enables simultaneous population transfer from all PUs at once: All encoded data is broadcast simultaneously and independently from each PU. Each PU contributes to a composite binary signal displayed concurrently on a screen without any points of contention. This ensures that PU data streams do not contend with one another. Optical sensors, e.g., cameras, capture and segment the incoming data in parallel (guided by tensor segmentation in the next processing layer) increasing throughput and scalability. Signal reception is also fully parallel: The sensors perform summation of binary signals, either inherently through their CMOS sensing characteristics or via integrated reconfigurable FPGA pipelines that utilize reconfigurable ROIs to add pixel intensities with DSP accumulators as they are sampled, such that addition is inherent in the processing pipeline, i.e., addition does not increase latency. The resulting signals are then decoded by the receiving PUs (Fig. 2a).

Fig. 3. PPI enables fully parallel transmission and processing, eliminating bottlenecks caused by data movement during collective operations.

a As typical for parallel systems, PUs run analyses in parallel. However, instead of sending data to a sequential fiber network, data are encoded using the approach illustrated in simplified form in Fig. 2. b Data are then simulcast using a shared display. Each square represents that processor’s contribution to a flashbit that can be either off or on. For illustration only, colors represent different source PUs; all transmissions are actually monochrome for energy efficiency. c After writing to dedicated display memory, the simulcast images from each PU are interleaved on the same μLED screen in parallel, i.e., no resource contention. d Cameras then slice the data, enabling faster data transfer and/or increased receiving PU number. Camera FPGAs sum each flash bit as a property of the receiving optical sensor and/or a result of on-camera in-line FPGA pipeline processing using DSP blocks. e The receiving PUs then decode the summed signals. To scale the system, the size of the screen, camera bit depth, camera ROIs, and the number of cameras can be increased.

This architecture scales inherently, with no latency penalty due to scale-out of PU number or tensor size. Expansion can be achieved by increasing the display area and frame rate, as well as the number of cameras. The screen size scales with both the tensor size (i.e., flashbit number) and the number of sending PUs (i.e., flashbit size). A configuration that integrates intensity across a spatial ROI can accommodate more sending PUs and pixels without saturating individual sensors. To maintain high-speed data reception as the number of receiving PUs increases, the number of cameras can be scaled accordingly. Note also that output signals from the camera will be smaller than the aggregate input signals by a factor of G GPUs, due to the AllReduce operation. Lastly, coordinated resolution and/or framerate increases in display and camera can enable even larger tensors that are packed more densely and/or span multiple frames. Additional discussion and analytical descriptions of PPI’s scalability are found in SI-F:§A.

With PPI population simulcast, PU activity and model data become transparent in the camera feed, enabling full offloading of support tasks like cluster health monitoring and auditing. This improves performance and efficiency. It also enables support and control processes to contribute inputs to live computations through their own dedicated inputs to screens or projectors, which in turn activates additional capabilities like real-time learning stabilization³⁸, contextualization³⁹, and transparent cluster collaboration⁴⁰. This modular architecture reduces compute burden and fosters scalable, adaptive AI systems that can evolve alongside models. See SI-B: PPI as a foundation for next-generation AI systems for more information on potential applications for this transparency and modularity, and SI-F: §F for more details on the mechanisms and limits of defect detection and localization transparency.

Prototype demonstration of all-reduce with light

We developed a concept validation prototype using commercial off-the-shelf (COTS) projectors and cameras (Fig. 4a). Although the system was not optimized for optical alignment, synchronization, or high frame rates, we successfully transmitted and summed binary data despite these limitations (see more detail in SI-C: Prototype Details and SI-F: §E5). This reveals the inherent robustness of the computational substrate based on the physics. The PPI prototype replaced the NVIDIA Collective Communications Library (NCCL)⁴¹ AllReduce function calls, serving as a direct, drop-in substitute for switches within the NCCL framework. The AllReduce collective operation was used to aggregate data, such as summing tensors, across multiple PUs during distributed training. PPI enabled encoding and decoding data, in-network computation, and cluster health monitoring.

Fig. 4. A PPI prototype using COTS components.

a View of the 4-projectors simulcasting loss gradient data on a shared screen. b Information contained in the header: (Blue box) Health monitoring is enabled by providing each GPU with a separate dedicated flashbit. If a given health flashbit is not illuminated, the corresponding GPU is not providing data for the frame. (Red box) Photonic quantal levels, corresponding to representative bit counts 0 to 4, are provided to the receiver for test and calibration by coordinated overlay from participating GPUs. (Yellow box) The 16-bit binary frame sequence number is encoded in flashbits by all participating GPUs. c Participation of all 4 GPUs was indicated by 4 illuminated health-monitoring flashbits. d An unhealthy GPU or PPI system results in a dark flashbit (intensity level 0), as indicated by the arrowhead. e A combined projection brightness heatmap with larger flashbits illustrates intensity variations and the need to correct sampled values based on flashbit location.

The entire system, described in detail in SI-C: Prototype Details, was tested for transmission and summation, as well as functional integration with an AI model. Figure 4a shows loss gradient summation using PPI simulcast from four projectors. These loss gradients were from a GPT-2 backward pass using the training framework llm.c⁴² that replaced NCCL AllReduce function calls with calls to PPI.

The header row included the sender health monitor, quantal levels for bit count calibration, current frame number (all shown in Fig. 4b), and block floating-point exponent (not shown). The health monitor is magnified in Fig. 4c, d, illustrating a full complement of 4 healthy GPUs (c) and with one down (d). Quantal levels for bit counts stepped up from 0 to 4 and were used to set thresholds for decoding each frame (Fig. 4b, Red box).

We now demonstrate collective (>2) simultaneous reduction across processing units using optical intensity summation. In the GPUs, 16-bit floats were encoded using two’s complement and converted into a flashbit matrix image. Data were transmitted via PPI projection, received by the camera, and decoded. We evaluated in-network computation accuracy by analyzing two key metrics:

1. Bit Error Rate (BER), which compares the bits transmitted to the bits received, and

2. encoding loss, which compares raw input values to their encoded representations.

Bit errors occur when a flashbit bit count, representing the sum of all senders, is misclassified as too high or too low. A total of 8 transmission tests (distinct samples) were completed at 240 fps, with logged data corrected for ambient lighting and analyzed offline. Across these transmissions, totaling 36.8 million flashbits (1999 frames of 576 flashbits sent by 4 GPUs over 8 runs), we observed zero classification errors. Hence, the BER for these transmissions was 0 ± 0% STD. A low bit error rate (BER) is expected, as PPI eliminates the primary sources of data loss and corruption in wired networks, network congestion⁴³ and contaminated connectors⁴⁴. Off-the-shelf projectors also produced uneven and time-varying brightness, necessitating frequent recalibration (Fig. 4e); custom optics and lighting would improve illumination stability. The fact that the system achieved zero BER in the face of multiple environmental noise factors, such as ambient light and vibration, testifies to the robustness of AllReduce using light intensity (SI-F: §E5).

Since PPI computations occur in parallel, senders cannot use individualized ranges and precisions. Therefore, 16-bit floating-point input values were transmitted using a block floating-point approach: 16-bit floats were converted to a fixed-point 16-bit range mantissa and 16-bit exponent that was transmitted in the header across all sending and receiving GPUs (SI-F: §E2). This encoding scheme introduced some loss of range and precision due to the conversion. For the dataset used during the 8 transmission tests described above, the absolute numeric error on processed input values was 1.877E-07 ± 1.591E-07 STD, which could be reduced by increasing the number of bits used for encoding.

Predictive modeling of performance and energy

Physics indicates that PPI should be faster than current AI systems for collective operations at scale (Table 1, SI-F: §A), and the prototype shows that AllReduce with PPI is possible with low error rates, even in uncontrolled conditions with COTS hardware (see above). What about real-world systems using current AI models? To quantify potential AI performance and energy efficiency impacts, we next developed predictive models to estimate PPI power, performance, and feasibility characteristics relative to state-of-the-art AI communication infrastructure. Our primary baseline is a standard Infiniband (IB) 4 ×800 Gbps Fat Tree topology, which has power consumption and maximum bandwidth equations available from manufacturer websites (see SI-D: Model Parameters, SI-F). We also compare against IB + SHARP (in-network reduction) and IB+NVLink (intra-node high-bandwidth subnetworks) estimates where noted.

While projector-based systems offer flexibility in transmission distance and matrix shape, they present challenges for miniaturization and energy efficiency, and they would be costly to mass-produce. Therefore, for direct comparison with current architecture, we grounded our model in the μLED-based system (Fig. 1c), leveraging insights from our early projector-based prototype builds and aligned with μLED technology’s increasing mass production and cost reductions⁴⁵. The modeled PPI system used transmission rates of 10,000 frames per second (fps) and components with capabilities that are either currently available or conservatively feasible with existing mature technologies.

This analysis covered only models that perform AllReduce over IB fabric in production multi-node deployments, such as LLaMA-2 70B + , GPT-3 175B, LLaMA-3 405B, Nemotron-4 340B, and similar frontier models. These are the workloads that actually use IB. Figure 5 presents AllReduce latency, throughput, and energy results while varying tensor size and GPU count. Supplementary Figs. 11, 12 show similar patterns of results for IB + SHARP in-network compute and IB+NVLink, respectively.

Fig. 5. Modeling of AllReduce latency, throughput, and energy across real AI model tensors reveals PPI outperforms InfiniBand.

All panels compare PPI (O(1) constant latency, 195 µs) against the InfiniBand fat-tree AllReduce baseline across GPU counts from 16 to 32,768 and named tensor sizes from real production models. a AllReduce time ratio (IB / PPI). For large tensors, IB fat-tree AllReduce latency is dominated by the bandwidth term 2(G − 1)/G · N/β ≈ 2 N/β; at 400 GB/s, this yields ~5 ms per GB of tensor, compared to PPI’s constant 195 µs. Green indicates PPI is faster. Cell text shows absolute latencies. b Effective AllReduce throughput ratio (PPI / IB). IB fat-tree AllReduce achieves a constant ~200 GB/s regardless of cluster size, exactly half the 400 GB/s link rate because AllReduce requires two phases (ReduceScatter + AllGather). PPI delivers substantially higher effective throughput because it completes any tensor in the same 195 µs. Cell text shows absolute throughput in GB/s. c Per-AllReduce network energy ratio (IB / PPI). This panel isolates the network fabric’s energy consumption during a single AllReduce operation, showing that PPI consumes more network energy than IB during active communication. Cell text shows absolute energy in Wh. d Per-AllReduce GPU idle energy ratio (IB / PPI). During every AllReduce, all G GPUs sit idle at ~175 W (25% of H100 TDP). GPU idle energy = G×P_idle×t_AR, so the ratio is identical to the time ratio in panel a. However, by displaying the absolute energy values, this panel reveals the dominant cost: GPU idle energy dwarfs network energy (c). At 32,768 GPUs, a single AllReduce for a ~ 1 T model wastes tens of Wh of GPU idle energy under IB, while PPI’s 195 us completion keeps GPU idle waste negligible. This panel makes explicit that the AllReduce latency advantage in a is not merely a performance metric; it is a primary driver of energy waste in large-scale AI training that PPI can eliminate.

For IB, the total time for one communication cycle was computed as previously defined⁴⁶ with effective bandwidth reduced at scale to account for fat-tree spine-link contention^47,48 For PPI, the total time was computed as the display actuation delay plus the parallelized camera capture time: a conservative, constant ~195 µs independent of PU count and tensor size, enabled by double-buffered pipelining that overlaps the PCIe data transfer and pre/post-processing with the previous frame’s optical cycle (SI-F: §E1).

Although the 10 kHz PPI frame rate is much lower than the bandwidth of typical AI networks, we found that PPI systems can achieve lower AllReduce latency and superior throughput at scale (Fig. 5a, b and Supplementary Figs. 11, 12a, b). Because spatial parallelism provides the bandwidth, PPI operates at kHz frame rates rather than GHz modulation, thereby preserving high signal-to-noise ratio (SNR) while eliminating the energy penalties and signal-integrity challenges of faster μLED switching (Fig. 7c, d and SI-F: §D, §E).

Fig. 7. Six independent analyses confirm that PPI operates with substantial safety margins under realistic, conservative assumptions.

a Monte Carlo simulation (50,000 draws, CV = 30%) shows PPI outperforms IB SHARP in >99% of draws at G > = 16 with 5.3 GB tensors (PPI latency is independent of tensor size; SHARP latency scales with tensor size, so larger tensors widen the gap further). b Tornado diagram identifies display delay and camera capture as the only parameters with meaningful latency impact; all others are second-order. c ABC recombination model shows PPI’s μLED operating point (J ~ 60 A/cm2) is 17x below droop onset, with IQE > 50%. d Drive-current-scaled SNR exceeds 40 dB at G = 4096, remaining well above the target BER <1e-9 threshold ( ~ 15.6 dB) across the full GPU range. e Environmental analysis confirms >25,500x signal-to-ambient margin under standard datacenter lighting and <0.2 μm vibration displacement vs. 10 μm pixel pitch. f PPI synchronization tolerance ±28 μs) is 5600x more relaxed than InfiniBand’s +/-5 ns requirement. a,b assume a 5.3 GB reference tensor (the per-layer gradient for a projected ~1 T dense model) and sweep GPU count G; c–f are independent of tensor size and GPU count.

In IB systems, AllReduce time increased and throughput decreased with both PU count and tensor size (Fig. 5a, b and Supplementary Figs. 11, 12). In contrast, PPI communication time remained stable across all tensor and cluster sizes examined, reflecting the absence of resource contention enabled by parallel communication pathways. As PU count and tensor size scaled, PPI’s latency advantage scaled multiplicatively, resulting in increasingly large performance benefits dominated primarily by tensor size. IB systems perform better with small tensors and few PUs. For example, with GPT-3 175B inference prefill (0.1 GB) and 256 PUs, PPI is 2.8x faster than IB (IB: 273 µs, PPI: 195 µs). As tensor size or GPU number increases, even more data throttles the available bandwidth and further increases AllReduce time. For example, with Llama-3 128 K prefill (4.3 GB) and 16 K GPUs, PPI is 143x faster than IB (IB: 28,000 µs, PPI: 195 µs).

Figure 5c, d decompose the per-AllReduce energy cost into its two components. Panel c isolates network fabric energy: IB switches and NICs drawing full power for the duration of the AllReduce (milliseconds at scale) vs. PPI’s uLEDs and cameras active only during the ~195 us optical pulse. PPI’s peak optical power during an AllReduce exceeds IB’s fabric power, so the status quo wins this comparison across the board for both IB (Fig. 5c) and IB + SHARP (Supplementary Fig. 11); against the NVLink+IB hierarchical baseline, PPI roughly matches network energy (Supplementary Fig. 12). This is expected: PPI’s energy advantage does not come from low network power. Figure 5d reveals where the advantage actually lies: GPU idle energy. All $G$ GPUs sit idle at ~175 W (25% of H100 TDP) for the entire AllReduce duration, so the ratio is identical to the time ratio in Fig. 5a. Comparing absolute values across the two panels shows that the PPI-IB difference in GPU idle energy substantially exceeds network fabric energy at scale. For example, for a single AllReduce of the GPT-3 175B inference prefill tensor (0.1 GB) with 256 GPUs, IB uses only 67.3% of PPI’s network energy (IB: 3.7 mWh, PPI: 5.5 mWh), but 275% of PPI’s GPU idle energy (IB: 6.6 mWh, PPI: 2.4 mWh). At the other extreme, for LLaMA-3 405B 128 K prefill (4.3 GB) with 16,384 GPUs, IB network energy is only 74.1% PPI’s (IB: 10.3 Wh, PPI: 13.9 Wh), but IB GPU idle energy is 14,387% PPI’s (IB: 22.3 Wh, PPI: 155 mWh). In both cases, GPU idle energy dominates the total, yielding an overall PPI energy savings over IB of 23% for GPT-3 175B inference prefill (256 GPUs) and 57% for LLaMA-3 405B 128 K prefill (16,384 GPUs). Total energy per AllReduce is ${\mathrm{E}}_{\mathrm{AR}}=\left({\mathrm{P}}_{\mathrm{network}}+\mathrm{G}\cdot {\mathrm{P}}_{\mathrm{GPU},\mathrm{idle}}\right)\cdot {\mathrm{t}}_{\mathrm{AR}}$. At scale, PPI’s higher fabric energy is a rounding error against the GPU idle savings its 195 us completion time provides.

To estimate the aggregate impact if PPI were universally adopted for AllReduce across an entire year of U.S. AI datacenter operation³, we weighted per-operation physics across four model-size bins^4,49 and propagated them through four savings channels (Fig. 6). Critically, the training workload was held fixed so that both technologies execute the same total number of AllReduce operations: the same layers, the same training steps, the same tokens; what differs is the per-operation latency and the network power profile between collectives. First, faster AllReduce shortens each training layer via Amdahl’s law⁷ (compute + 4 AllReduces per layer), reducing total training wall-clock time and thus energy. Second, inference benefits similarly: two tensor-parallel AllReduces per layer per generated token mean that the latency gap in Fig. 5a compounds across billions of tokens. Third, IB network fabric draws full power around the clock regardless of utilization, while PPI power-gates between collectives; this 24/7 duty-cycle asymmetry scales to persistent infrastructure savings. Fourth, every watt of IT energy saved also eliminates the associated cooling overhead (Power Usage Effectiveness, PUE^50,51). Under bracketed assumptions (AI = 30–50% of 320 TWh U.S. datacenter energy, PUE = 1.10–1.30), these four channels yield a range of 35.8–113.3 TWh/yr energy savings (11.2–35.4% of U.S. datacenter energy; Fig. 6a), with a mid-range scenario (AI = 40%, PUE = 1.20) of 65.9 TWh/yr (20.6%). The spread reflects compounding uncertainty across multiple input fractions and should be read as a scale indicator rather than a point forecast. The largest single contributor is training-time reduction for frontier-scale models (175B-1T + ; Fig. 6b), where per-layer communication fractions are greatest and the PPI speedup (Fig. 5a, b) translates most directly into wall-clock savings; however, the distribution of training compute across model-size bins is the least well-constrained input in the scenario analysis. Note that additional PPI-enabled energy savings opportunities were not included in this analysis, including the relocation of support and control functions outside the primary AI compute cluster (SI-B, SI-F).

Fig. 6. Annual U.S. datacenter-scale energy impact of replacing IB fat-tree all-reduce with PPI.

a All-up savings under three bracketed scenarios (Conservative, Mid-range, Aggressive), stacked by channel: training time reduction, inference communication reduction, network infrastructure idle power, and cooling (PUE) overhead. Assumptions follow the mid-range scenario: AI accounts for 40% of U.S. datacenter energy (320 TWh baseline; Shehabi et al. ³), inference communication overhead is 15%, and cooling overhead PUE = 1.20. b Savings decomposed by model-size tier and scenario. Per-layer speedups apply Amdahl’s law (compute + 4 AllReduces per layer); the communication fraction grows with model dimension, so frontier-scale models (175B-1T + ) contribute the largest share of training-time savings.

In summary, with model sizes that require IB, the model predicts that PPI outperforms IB, IB + SHARP, and IB+NVLink while using less energy. As data volumes grow, whether due to larger tensor sizes or expanded cluster configurations, PPI delivers increasingly superior performance along with enhanced energy efficiency.

System-level analysis of scalability, robustness, and performance limits

PPI describes a system-scale collective communication fabric, optimized for large, tightly coupled AI training and inference deployments. Its architectural assumptions (optical summation, fixed-point arithmetic, and centralized physical-layer aggregation) favor regimes in which communication dominates iteration time and where amortization across many accelerators is critical. As a result, PPI is not intended to replace conventional interconnects in small or latency-insensitive clusters supporting small AI models, but rather to address the scaling limits that emerge as a result of growing AI model sizes^9,10.

To assess whether these architectural choices introduce fundamental constraints in scalability, robustness, noise accumulation, or precision-bandwidth trade-offs, we performed a comprehensive system-level quantitative evaluation (SI-F). 33 simulation experiments characterized PPI across physical, architectural, and workload dimensions, explicitly addressing the technical concerns raised for large-scale deployment. Together, they establish both the performance envelope and the operating limits of the proposed system. Figure 7 focuses on key findings (for additional information, see SI-F).

A natural concern is whether PPI’s latency advantage survives real-world hardware variation. To address this, we performed a Monte Carlo analysis over 50,000 parameter draws with 30% coefficient of variation around the conservative baseline (Fig. 7a). PPI outperforms IB + SHARP in 100% of samples at G = 16 and above; the IB + SHARP latency at G = 16 (13,594 µs) is so far beyond the PPI distribution that the two do not overlap on any reasonable axis scale. Importantly, a tornado sensitivity analysis (Fig. 7b) shows that only two of six hardware parameters, display delay and camera capture time, affect PPI latency at all; the remaining four govern power consumption but not timing. This narrows the engineering challenge to two well-characterized optoelectronic quantities whose tolerances are already met by commercial components.

The optical link itself operates with substantial physical-layer headroom. The µLED array drives at 60 A/cm², a factor of 17 below the onset of efficiency droop (Fig. 7c), leaving ample room for future increases in pixel count or modulation depth. Per-count SNR at G = 4096 is 43 dB (Fig. 7d), more than 27 dB above the threshold for BER < 10^-9, and even the worst-case bit pattern remains comfortably above that floor across the full GPU range. Because PPI uses drive-current scaling to hold total well fill constant, the SNR degrades only gradually with G ($-10{\log }_{10}\left(G\right)$ in the shot-noise-dominated regime), remaining well above the BER <10^-9 threshold across the full operating range.

The mantissa reconstruction itself is G-independent: drive-current scaling holds the per-frame relative error at ~0.26% (8.6 effective bits) with a 32k-electron well, comfortably below BF16’s 0.39% quantization noise and 50-130x smaller than methods (1-bit SGD⁵², TernGrad⁵³) that report convergence with no accuracy loss (Supplementary Fig. 33). The optical channel also preserves data transparency at scale: 1-frame fault detection remains above 95% across all GPU counts and ADC resolutions tested, and 21-frame majority voting (2.1 ms at 10 kHz, running passively on frames already collected during normal training) keeps fault localization above 80% even at G = 16,384 (Supplementary Fig. 41).

Environmental interference is similarly a non-issue. The enclosed rack module suppresses ambient light by a factor of 1,280,000 relative to the optical signal; even an open benchtop demonstrator at 500 lux retains a 25,600x margin (Fig. 7e). Typical datacenter vibration displaces the optical path by less than one-eightieth of the 10 µm pixel pitch, eliminating the need for active alignment correction. Finally, PPI’s synchronization requirement of ±28 µs (set by the camera exposure window) is 5600x more relaxed than InfiniBand’s ±5 ns constraint (Fig. 7f), reducing clock distribution from a nanosecond precision problem to one solvable with standard datacenter timing infrastructure and less synchronization overhead.

Crucially, these physical-layer margins translate to training-level robustness: across 60 training runs (CIFAR-10 ResNet-18 and a 33.6 M-parameter WikiText-2 transformer, 5 seeds each), gradients passed through the full PPI noise stack—and through a deliberately pessimistic 10×-scaled version of it—converge statistically equivalent (TOST, α = 0.05) to an electrical fp32 baseline on both benchmarks (Fig. 8; SI-G; illustrative miniature SI-F: §I).

Fig. 8. Training-convergence robustness under the modeled PPI gradient-noise stack.

a,b ResNet-18 on CIFAR-10: a training cross-entropy (symlog y-axis) and b held-out test accuracy versus epoch. c,d A 33.6M-parameter decoder-only transformer on WikiText-2: c training cross-entropy and d validation perplexity (log y-axis; geometric mean ± 1 s.d. computed on log-perplexity). e,f Final-epoch summaries with every per-seed value overlaid as points: e CIFAR-10 test accuracy (bar = mean ± 1 s.d.) and f WikiText-2 validation perplexity (bar = geometric mean ± 1 s.d. on log-perplexity; lower is better). The electrical baselines (fp32, bf16), the modeled PPI operating point (ppi), and the 10× noise-margin probe (ppi10) track one another closely on both benchmarks; the two gradient-compression references behave differently (terngrad does not reach baseline accuracy on CIFAR-10, and both onebit and terngrad settle at higher perplexity on WikiText-2). The absolute perplexity floor reflects the model and corpus scale and is not a state-of-the-art claim; the comparison isolates relative convergence under identical optimizer, data order, initialization, and seed budget. Pre-specified equivalence tests supporting the parity claims are reported in the main text. Experiments were performed across two standard benchmarks and six gradient-channel conditions (n = 5 random seeds; shaded bands and error bars are mean ± 1 s.d. unless noted).

The constant-latency property of PPI is an explicit architectural trade-off, not a free lunch. Holding the AllReduce frame time fixed as the cluster scales requires the optical front end—display area, camera pixel count, readout channels, and the FPGA reduction tree—to grow with the number of participating PUs G. PPI exchanges a serial-time bottleneck (the multi-hop reductions that dominate ring, tree, and SHARP collectives) for a parallel area, power, and integration-complexity budget that scales roughly linearly with G under conservative assumptions (SI-F: §C, §D, §E4, §G). The principal scaling consideration at the largest cluster sizes is tile count: because each AllReduce frame must display N × G × P µLED elements simultaneously (N tensor elements, G GPUs, P flashbit planes) and each 8-inch wafer tile holds ~373 million LEDs, tile count grows rapidly with both tensor size and GPU count (SI-F: §E4, §G). GPT-3 175B inference prefill (0.1 GB) at G = 256 requires ~549 tiles (35 shelves, 3 racks), but at G = 4096 that grows to ~8779 tiles (35 racks), and a projected ~1T-parameter model (5.3 GB) at G = 4096 would require ~465,237 tiles (1818 racks). Continued miniaturization of tile and optics packaging, together with hierarchical tiling strategies, will therefore be essential for production deployment at the largest scales; however, no individual physical-layer parameter approaches a fundamental limit. Although PPI introduces additional system-level hardware, the quantitative analysis presented here identifies scaling regimes in which PPI-enabled AI systems may reduce reliance on the performance-driven cooling, power-delivery, and communication infrastructure otherwise required by large-scale AI training. Other limitations of PPI technology are discussed in SI-E.

Discussion

This work introduces a low-energy, scalable communication and computation substrate, PPI, that addresses the challenges of AI energy demands and infrastructure limitations through parallel simulcast communication with in-network computing and real-time, no-load data transparency. This advance presents a fundamentally different solution to AI bottlenecks at scale (Table 2; SI-H): PPI combines fully parallel multi-PU reduction with O(1) collective complexity, native data transparency, and elimination of resource contention—capabilities not achieved by any existing approaches because they are all bound by pairwise, sequential operations. These scaling advantages are not emergent properties of a particular system design but rather the predicted consequence of Amdahl’s Law⁷ applied to the elimination of serial communication steps: Any architecture that replaces $O\left(G\right)$ or $O\left(\log G\right)$ contention with an $O\left(1\right)$ constant-time physical operation will exhibit this widening advantage at scale. Also, unlike traditional AI infrastructure, PPI enables transparent access to internal system states, supporting auxiliary functions, such as health monitoring, explainability, checkpointing, and dynamic model control without burdening the compute cluster.

Prototype tests using unoptimized, off-the-shelf components confirm that PPI integrates into existing distributed frameworks, with continued optics miniaturization providing a clear path to production-scale deployment. Our modeling demonstrates that PPI reduces per-AllReduce network energy by over 50% compared with switched-fabric interconnects at frontier scale (Fig. 5d), while achieving up to ~180x lower AllReduce latency as tensor size and cluster scale increase (Fig. 5a). As AI workloads scale, PPI offers a forward-looking infrastructure foundation that exceeds existing systems in performance, energy efficiency, and transparency.

Methods

This section describes the simulation model used to evaluate PPI relative to existing AI communication infrastructures. Experimental prototype method details are presented in the main text, with additional supporting information provided in SI-C. SI-D, SC-F, and SI-G provide further information on model methods and results.

Scalability framework

PPI’s scaling properties derive from the Universal Scalability Law (USL)⁵⁴, which models distributed system throughput as a function of the number of processors G:

$$C\left(G\right)=\frac{G}{1+\alpha \left(G-1\right)+\kappa G\left(G-1\right)}$$ 2

where $\alpha$ is the contention coefficient (serialization due to shared resource competition) and $\kappa$ is the coherency delay coefficient (synchronization overhead). In conventional store-and-forward networks (for example, InfiniBand fat-tree), processors compete for switch ports, buffer memory and bus bandwidth, yielding $\alpha >0$. PPI provides each processing unit (PU) with a dedicated parallel broadcast and reception path on a shared optical medium, eliminating resource contention ($\mathrm{\alpha }=0$). The coherency coefficient $\kappa$ remains, reflecting synchronization overhead common to any distributed system. Under Amdahl’s Law⁷, PPI replaces the $\mathrm{O}\left(\mathrm{logG}\right)$ or $O\left(\log G\right)$ sequential pairwise steps of conventional AllReduce with a single $O\left(1\right)$ simultaneous operation.

AllReduce latency models

We derive latency equations for four AllReduce algorithms. Throughout, $G$ denotes GPU count, $M=G/D$ the number of nodes ($D$ GPUs per node), $N$ the per-node tensor size, and $\mathrm{\beta }$ the per-node link bandwidth. Per-message startup latency is denoted $\mathrm{\lambda }$ to distinguish it from the USL contention coefficient $\mathrm{\alpha }$ defined in the scalability framework.

Ring AllReduce^55,56 decomposes the operation into reduce-scatter and all-gather phases, each requiring $G-1$ steps. Each step incurs both a fixed startup latency $\lambda$ and a bandwidth-dependent transfer:

$${\mathrm{T}}_{\mathrm{ring}}=2\left(G-1\right)\left(\mathrm{\lambda }+\frac{N}{G\cdot \mathrm{\beta }}\right)$$ 3

Recursive halving/doubling^55,57 on fat-tree topologies requires $\mathrm{O}\left(\mathrm{G}\right)$ pairwise exchange steps. For both fat-tree algorithms below, the per-step startup latency is negligible compared to the data transfer term at the tensor sizes relevant to LLM training (0.5–6 + GB). All results therefore use the NCCL bandwidth-optimal formula^46,58, which retains only the bandwidth term:

$$T=\frac{2\left(M-1\right)\cdot N}{M\cdot {\beta }_{eff}}$$ 4

The two IB models differ only in effective bandwidth ${\mathrm{\beta }}_{\mathrm{eff}}=\mathrm{\beta }\cdot {\mathrm{\eta }}^t$, where $t=\mathrm{\lceil }{\log }_{k}M\mathrm{\rceil }$ is the number of fat-tree tiers (k = switch radix) and $\eta$ is the per-tier bandwidth degradation factor^47,48,59,60.

Fat-tree AllReduce (no SHARP):

$$T_{\mathrm{fat}-\mathrm{tree}}=\frac{2\left(M-1\right)\cdot N}{M\cdot \beta \cdot {\eta }_{\mathrm{IB}}^t}$$ 5

where ${\eta }_{\mathrm{IB}}={0.70}^{1/4}\approx 0.915$ per tier, derived from the most favorable end of published plain-IB measurements (70% of nominal bandwidth at 4 tiers)^47,48,59,60.

Fat-tree + SHARP performs in-network reduction at each switch tier⁶¹, using the same bandwidth-optimal formula with less contention:

$$T_{\mathrm{SHARP}}=\frac{2\left(M-1\right)\cdot N}{M\cdot \beta \cdot {\eta }_{\mathrm{SHARP}}^t}$$ 6

where ${\eta }_{\mathrm{SHARP}}={0.95}^{1/2}\approx 0.975$ per tier, from Graham et al.⁶¹, who measured 95% of nominal bandwidth at 2 tiers with SHARP active. A fixed per-tier $\eta$ is optimistic, as real degradation compounds superlinearly due to congestion cascades.

Two-tier NVLink + IB (NVIDIA DGX/HGX⁶²) uses a hierarchical AllReduce in which $D$ GPUs within each node communicate over NVLink and $M=G/D$ nodes communicate over the IB fat-tree. The total latency is the sum of three sequential bandwidth-optimal phases:

$$T_{\mathrm{NVL}+\mathrm{IB}}={\underbrace{\frac{2\left(D-1\right)\cdot N}{D\cdot {\beta }_{\mathrm{NVL}}}}}_{\mathrm{intra}-\mathrm{node}\mathrm{reduce}-\mathrm{scatter}}+{\underbrace{\frac{2\left(M-1\right)\cdot N}{M\cdot {\beta }_{\mathrm{IB},\mathrm{eff}}}}}_{\mathrm{inter}-\mathrm{node}\mathrm{AllReduce}}+{\underbrace{\frac{2\left(D-1\right)\cdot N}{D\cdot {\beta }_{\mathrm{NVL}}}}}_{\mathrm{intra}-\mathrm{node}\mathrm{allgather}}$$ 7

where $D$ is the NVLink domain size (8 for DGX H100, 72 for GB200 NVL72), ${\beta }_{\mathrm{NVL}}$ is the per-direction NVLink bandwidth (450 GB/s for H100, 900 GB/s for GB200 NVL72; all simulations use 900 GB/s, the most favorable value for the status quo baseline), and ${\beta }_{\mathrm{IB},\mathrm{eff}}$ is the effective IB bandwidth after per-tier contention as defined above. NVLink fabric power is estimated at 50 W per GPU for NVLink I/O plus 150 W per NVSwitch chip.

PPI completes the full reduction in a single broadcast-and-capture cycle, requiring no multi-hop or pairwise message steps:

$$T_{\mathrm{PPI}}=T_{\mathrm{eo}}+\frac{T_{\mathrm{capture}}}{N_{\mathrm{cam}}}$$ 8

where $T_{\mathrm{eo}}$ is the display actuation delay (115 μs), $T_{\mathrm{capture}}$ is the camera capture time (480 μs), and $N_{\mathrm{cam}}=6$ cameras per tile fire in parallel. This yields a constant latency of 195 μs, independent of both GPU count and tensor size.

All IB latency models use the NCCL bandwidth-optimal formula, which captures data transfer time only; the element-wise reduction arithmetic at each step is performed by the receiving GPU and overlapped with communication (standard in NCCL benchmarks). For PPI, the parallelized post-processing arithmetic is an FPGA shift-and-add tree that reconstructs tensor sums from per-bit-plane population counts ( ~ 5 us at G = 4096, 200 MHz); this completes within the 195 us frame period and is pipelined with the subsequent display/capture cycle, adding zero time to the steady-state critical path (SI-F: §E1).

System parameters

To make detailed comparisons to existing AI infrastructure, one concrete PPI design was formulated. This design is illustrative, not definitive; multiple avenues for improvement exist, including miniaturization, higher-density emitter/sensor arrays, advanced optical configurations, and optimized encoding schemes. All PPI parameters use conservative, commercially available values (SI-D). The μLED display tile is an 8” x 8” wafer with 10 μm element pitch, 5 mm edge margin, yielding 19,304 elements per side and approximately 373 million elements per tile ( ~ 746 MB per frame at 2 bytes per element). Each tile is imaged by 6 cameras in a 2 × 3 arrangement, all firing simultaneously. Tensor values are encoded in block floating-point with a 16-bit fixed-point (FxP16) mantissa encoded across 16 spatial metapixels using flashbit encoding; each spatial location defines the positional bit weight (Fig. 2; SI-F: §E2).

InfiniBand parameters follow the NVIDIA Quantum InfiniBand datasheet: 4 × 800 Gb/s per node (400 GB/s), 32-port switch radix, 1 μs per-hop latency. SHARP switch latency is 1.5 μs per tier. NVLink models use 900 GB/s effective unidirectional bandwidth per GPU. GPU idle power during AllReduce is estimated at 175 W ( ~ 25% of H100 TDP). All latency models use the NCCL bandwidth-optimal formula from the NVIDIA nccl-tests documentation⁵.

Gradient and activation tensor sizes

Per-layer gradient sizes are derived from published model architectures: LLaMA-2 70B (0.47 GB)⁶³, GPT-3 175B (1.2 GB)⁶⁴, LLaMA-3 405B (1.7 GB)⁶⁵, Nemotron-4 340B (2.7 GB)⁶⁶, and a projected ~1 T dense model (5.3 GB; ~1 T dense projection: standard transformer formula P ~ 12 × n_layers × d_model²). Activation tensor sizes for tensor-parallel inference are batch x seq_len x $d_{\mathrm{model}}$ x 2 bytes; for example, LLaMA-3 405B at 128 K context yields a 4.3 GB activation tensor per AllReduce call (SI-F: §C). During tensor-parallel inference, AllReduce is called twice per transformer layer per generated token and lies on the critical path (each token depends on the previous AllReduce result).

Sensitivity and robustness analysis

We test sensitivity under three parameter regimes: original (conservative values provided by the manufacturers), conservative (more conservative baseline used for all results), and pessimistic (deliberate worst-case). One-at-a-time (OAT) sweeps vary each parameter individually while holding others at the conservative baseline. Monte Carlo simulation (50,000 samples) varies all parameters simultaneously using realistic uncertainty distributions with a 30% coefficient of variation on latency parameters. Breakeven analysis identifies, for each parameter, the value at which PPI latency equals IB + SHARP at a given GPU count and tensor size. A two-dimensional heatmap displays sweep delay and camera capture time jointly. See SI-F for detailed results.

Energy model

Per-AllReduce energy is computed as:

$$E_{\mathrm{AR}}=\left(P_{\mathrm{network}}+G\cdot P_{\mathrm{GPU},\mathrm{idle}}\right)\cdot t_{\mathrm{AR}}$$ 9

where $P_{\mathrm{network}}$ is the network infrastructure power and $P_{\mathrm{GPU},\mathrm{idle}}\approx 175$ W. IB network power includes NICs (25 W each) and switches (1,720 W each) at full draw continuously. PPI network power includes display PCIe cards (25 W each), μLED arrays (1.15 μW per element, 50% duty cycle, 23 μs pulse per frame), camera bodies (24 W each) and camera PCIe cards (9 W each), with uLEDs and cameras power-gated to near-zero between AllReduces. PPI can power down its optical components between AllReduces because it is stateless and performs a single synchronous broadcast-capture per cycle with zero inter-event traffic, whereas InfiniBand must stay energized 24/7 to maintain distributed connection state and service continuous asynchronous protocol exchanges. Annual datacenter-scale projections use three scenarios (conservative, mid-range, aggressive) varying the AI share of U.S. datacenter energy (30–50% of 320 TWh baseline³), inference communication fraction (8–30%), and PUE (1.10–1.30). Per-layer training speedups apply Amdahl’s Law⁷:

$$S_{\mathrm{layer}}=\frac{t_{\mathrm{compute}}+4\cdot t_{\mathrm{IB}}}{t_{\mathrm{compute}}+4\cdot t_{\mathrm{PPI}}}$$ 10

Tensor value summation

The optical channel provides per-bit population counts at each metapixel position. The FPGA computes the aggregate tensor sum via a shift-and-add tree:

$$\mathrm{sum}={\sum }_{b=0}^{15}{\mathrm{count}}_b\times 2^{w_b}$$ 11

where each multiplication by $2^{w_b}$ is a zero-cycle bit-shift (wire routing), and the 16 shifted values are summed in a balanced parallel adder tree of depth $\mathrm{\lceil }{\log }_{2}16\mathrm{\rceil }=4$ stages ( ~ 12 clock cycles at 200 MHz with 3x routing overhead). At $G=4,096$, each camera processes ~950 tensor values in ~5 μs, completing well within the 195 μs frame period (SI-F: §E1.1). Value summation from frame k is pipelined with the display/capture of frame $k+1$ (SI-F: §E1.2), adding zero time to the steady-state critical path.

SNR and dynamic range

Each μLED operates in binary mode at a current density of ~60 A/cm² (SI-F: §E2). Drive current scales as $1/G$ to maintain constant per-pixel photon flux as PU count increases, so SNR improves (not degrades) with $G$.

Synchronization

The synchronization tolerance model (SI-F: §E3) assumes a 115 µs frame period with 80 µs camera exposure, 2 µs µLED settle time, and PU write arrivals uniformly distributed over a jitter window that must complete before the exposure window opens (double-buffered DMA with 5 µs nominal completion). For the InfiniBand baseline, we use a generous 5 ns synchronization tolerance, approximately 1000x above the actual CDR constraint ( ~ 5.6 ps at 53.125 Gbaud PAM4, 0.3 UI). Within each PPI shelf, camera-μLED synchronization uses a hardware GPIO trigger from the shelf FPGA (<100 ns jitter). Across racks, GPUs write gradient data to tile memory via PCIe RDMA; the display FPGA fires the μLED trigger after counting incoming write completions or at a fixed offset within the jitter budget. Multi-tile synchronization uses LVDS trigger fanout ( < 1 μs total propagation across a rack). No PTP or distributed clock is required, which decreases synchronization overhead.

Physical integration

Each PPI module occupies ~3U of a standard 42U OCP Open Rack V3, using a short-focal-length lens array ($f=4$ mm, optical path <25 mm; SI-F: §E4). Each shelf holds up to 16 tiles. GPUs connect to display columns via PCIe 5.0 × 16 (64 GB/s) optical active cables, the same bus used by InfiniBand ConnectX NICs. Per-tile power consumption is ~204 W, active for only ~23 μs per AllReduce. The enclosed rack module shields optics from ambient light ( < 0.1 lux, <0.001 dB SNR impact) and mechanical vibration (relative camera-tile displacement <0.9 μm at 0.1 g peak, <9% of the 10 μm pitch).

Data transparency and fault recovery

PPI provides an independent physical verification channel. The camera observes $z_{\mathrm{camera}}={\sum }_i{a}_i\cdot w_{i,:}$; correctness is verified by comparing against the digitally computed expectation: $\mathrm{\mid \mid }{z}_{\mathrm{camera}}-z_{\mathrm{expected}}\mathrm{\mid \mid }<ϵ$. If the residual exceeds the threshold, fault localization correlates the residual vector against each PU’s weight signature to identify the faulty unit (SI-F: §F). Multi-frame majority voting over 21 frames at 10 kHz (2.1 ms, running asynchronously during normal training) converts moderate single-frame localization accuracy into high-confidence identification. Dedicated per-PU health pixels (unsuperposed, single-pixel liveness indicators) independently flag complete PU dropouts with zero latency cost.

Author contributions

T.A.N. conceived the technology, designed experiments, created the model, and led manuscript preparation. P.L. and J.B. developed the prototype. I.K. and H.R. contributed values from their custom μLED and projector designs, respectively. S.D., N.J. and H.A. provided key technical and organizational support. All authors reviewed and approved the manuscript.

Peer review

Peer review information

Nature Communications thanks Shupeng Ning and the other anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

All supporting funds provided by Microsoft.

Data availability

The dummy data generated in this study for testing and reproducibility of the prototype have been deposited in the Zenodo database under accession code 17610466 https://doi.org/10.5281/zenodo.17610466⁶⁷. This is a non-sensitive, synthetic dataset created solely for testing and reproducibility of the prototype described in the manuscript. The processed model data are available at Code Ocean.

Code availability

Custom prototype and model code are available from Code Ocean.

Competing interests

T.N. has patent applications pending related to the subject matter of this manuscript, assigned to Microsoft Corporation. All other authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-76764-1.