Regulated liquid metal via semiconductor valve toward highly stretchable topological circuits

Abstract

Wearable electronics with complex circuits and three-dimensional (3D) structure are indispensable to advanced next-generation flexible technologies like e-skins and soft robotics. However, fabricating 3D flexible electronics remains challenging, primarily due to the difficulty in obtaining highly stretchable materials with precise current control and complex topological structures. This work reports a unidirectional conductive semiconductor valve in liquid metals (LM-SV) constructed via interfacial barrier engineering to enable soft, complex topological circuits. The LM-SV exhibits ultrahigh stretchability (~1000% strain), robust unidirectional conductivity over 1000 cycles at 500% strain, and stable operation across wide temperature ( − 5–100 °C) and frequency (1 Hz – 5 MHz) ranges. Switching voltages (0.43—0.80 V) are conveniently tunable through LM composition modulation. Leveraging these features, LM-SV circuits can be topologically reconfigured from 2D layouts into 3D architectures with real-time functional switching. Furthermore, a wirelessly powered stretchable logic circuit demonstrates the potential of this LM-SV strategy for advanced flexible electronic systems.

Fabricating 3D flexible electronics is challenging due to the difficulty in obtaining highly stretchable materials with precise current control and complex topological structures. Here, the authors report a unidirectional conductive semiconductor valve in liquid metals for soft, complex topological circuits.

Introduction

The growing demand for flexible electronics such as wearable devices^1,2, electronic skins^3,4 and soft robotics^5,6 has shifted the focus in stretchable circuits from mere conductivity to the integrated optimization of mechanical compliance, electrical stability, and multifunctionality. However, there are two major challenges that need to be addressed to achieve this goal. First, the selection of highly stretchable conductive materials is relatively limited, as existing conductors (e.g., conventional metals^7,8, carbon nanotubes^9,10 and conductive polymers^11,12) exhibit an inevitable trade-off between stretchability and conductivity. Besides, the predominant two-dimensional (2D) planar structures in current flexible circuits restrict the spatial design freedom of complex circuit topologies, thereby constraining functional integration density^13–15. Therefore, developing three-dimensional (3D) circuits with enhanced stretchability and spatial reconfigurability has emerged as a critical direction for future flexible electronics^16–20.

Liquid metals (LMs) have become promising candidates for 3D stretchable circuit fabrication due to their room-temperature fluidity^21–23, high electrical conductivity (~3.4 × 10⁴S/cm)^24–26, and low toxicity^27–29. Their distinct rheological behavior enables the fabrication of complex circuits via techniques such as in-situ microchannel filling^30–33 and direct ink writing^34–36. Meanwhile, they maintain stable conductivity during dynamic deformation and allow the transition from 2D planar layouts to 3D spatial architectures. However, unlike semiconductors, the intrinsic Ohmic properties of LMs prevent them from regulating carrier transport. Consequently, they have been limited to passive conductive interconnects, with directional electrical functions such as rectification in 3D soft circuits relying entirely on external discrete components^37–39. While existing flexible rectifiers (e.g. organic stretchable diodes^40,41, metal-semiconductor contacts^42,43, and molecular rectifying interfaces⁴⁴) have achieved notable progress in high-frequency rectification, optoelectronic integration, and quantum tunneling, their stretchability is typically limited (<100%) due to material brittleness or interfacial instability. Moreover, their 2D thin-film morphology restricts 3D circuit integration and topological reconfiguration. Consequently, current approaches still rely on external discrete components for directional control inevitably compromising the mechanical compliance and integration density of 3D soft circuit^5,15. Therefore, introducing asymmetric charge transport characteristics into LM while preserving its intrinsic fluidity and conductivity, would enable electrical signal directional control, providing a strategy for highly integrated 3D stretchable circuits.

This work investigated the carrier transport behavior at the LM-semiconductor heterointerface. The work function difference between the LM and the single-sided Au-coated p-type silicon wafer (p-Si) induces an asymmetric interfacial barrier, enabling unidirectional carrier transport within the LM. This mechanism enabled the successful development of a unidirectional liquid metal-semiconductor valve (LM-SV), while exploiting the inherent fluidity of the LM facilitated the facile fabrication of flexible 3D topological circuits. This finding fundamentally changes the role of LM from a passive conductive interconnect to an active participant in interfacial carrier transport regulation. The LM-SV exhibited ultrahigh stretchability (~1000% strain), stable unidirectional conductivity (1000 cycles at 500% strain), broad environmental tolerance (−5– 100 °C) and a wide frequency response (1 Hz–5 MHz) with a switching voltage tunable between 0.43 and 0.80 V via LM composition. The LM-SV based circuit topology could be dynamically reconfigured through stacking, connection, and blocking operations. This capability enabled real-time functional transition (rectification, OR gate, and AND gate), which was challenging to realize in traditional LM flexible circuits. A wirelessly powered stretchable logic circuit was developed by integrating the LM-SV with a stretchable antenna that maintains its functionality under high strain (200%), confirming the applicability of the LM-SV strategy for wearable flexible electronic systems. This work reveals the interfacial carrier transport mechanism that enables the unidirectional conduction at the LM-semiconductor heterointerface. The integration of this mechanism with the intrinsic fluidity of the LM enables circuit topology reconfiguration, opening opportunities for research in next-generation wearable electronic systems.

Results

Structure and unidirectional conductive performance of the LM-SV

The liquid metal with semiconductor valve (LM-SV) utilized interfacial barrier engineering between LM and semiconductor (p-type silicon wafer, p-Si) to achieve precise electric current direction control in flexible circuits. The p-Si used in the LM-SV was processed with a single-sided gold (Au) coating. As shown in Figs. S4 and S5, energy-dispersive X-ray spectroscopy (EDS) elemental analysis was performed on the Au-coated and polished surfaces of the p-Si, confirming the successful deposition of Au. Here, the Au-coated side and non-coated side of the p-Si were defined as the anode and cathode of the LM-SV, respectively. As shown in Fig. 1a₁, the LM-SV was built by embedding a single-sided Au-coated p-Si into LM fluid, where the LM directly participated in forming a functional LM/Au-p-Si/LM heterointerface. The unidirectional conduction of this valve originates from the asymmetric distribution of the interfacial barrier on the two sides of the p-Si, in which the LM contributes to the formation of the barrier height and thereby regulates the direction of carrier injection. On the LM/Au-p-Si side, the higher work function of Au interlayer compared to p-Si (Fig. S6) created an ohmic junction (contact barrier ≈ 0 eV), enabling bidirectional carrier transport^45,46. In contrast, a rectifying junction (contact barrier > 0 eV, Fig. 1b) forms at the LM/p-Si interface due to the lower work function of LM relative to p-Si (Figs. S6 and S7). This LM-induced rectifying junction enabled unidirectional carrier transport, acting as a dynamic gateway for carrier injection influenced by the external bias. Specifically, the external bias dynamically modulates the effective barrier height for carrier at the interface by controlling the extent of band bending on the semiconductor side. This interfacial confinement of carrier migration acts as a microscopic valve, which directly determines the direction of carrier flow in the LM. At forward bias ($V>0$), the hole carriers in p-Si overcame the reduced barrier (${\mathrm{\Phi }}_{\mathrm{bi}}-\mathrm{q}V$) to move into LM (Fig. S7b), enabling anode-to-cathode current conduction (Fig. 1a₂), where the current density showed a proportional relationship to the forward bias. Conversely, reverse bias ($V<0$) enhanced the barrier to ${\mathrm{\Phi }}_{\mathrm{bi}}+\mathrm{q}\mid V\mid$ (Fig. S7c), preventing hole carriers from flowing into LM and maintaining a cut-off state that blocks reverse current (Fig. 1a₃). All data were obtained using gallium (Ga) as the LM unless specified. Consequently, as illustrated in the J–V curve (Fig. 1c), the LM-SV exhibited markedly asymmetric electrical behaviors under forward and reverse bias conditions. Application of forward bias (0–3 V) produced exponential growth in current density with increasing voltage, whereas reverse bias (0 to −3 V) yielded negligible current. This pronounced asymmetry in charge transport clearly confirms the exclusive current flow from anode to cathode, establishing the LM-SV as an effective current-gating element (Fig. S8). Furthermore, the J–V characteristic (Fig. S9) of the LM/p-Si/LM-structured LM-SV revealed negligible current conduction under both forward and reverse bias conditions, indicating a cut-off state of the device. This result confirms that asymmetric contact engineering via single-sided Au deposition on the p-Si is essential for achieving unidirectional conductivity in the LM-SV. Therefore, the LM-SV was encapsulated into a silicone tube (inner diameter: 0.8 mm) to integrate the unidirectional conductivity and flexibility, forming a liquid metal wire (LMW) with a semiconductor valve (LMW-SV, Fig. 1d₁ and Fig. S10). Elemental mapping via EDS (Fig. 1d₂ and Fig. S11) reveals a clear interfacial distribution of Ga (white) and Si (blue) elements, confirming the LM/p-Si structure in the LM-SV. Optical microscopy (Fig. S12) demonstrates intimate contact between the LM and the p-Si without observable gaps. This close contact serves as the key structural foundation for establishing a stable contact barrier. In addition, LMW-SV was integrated into a flexible light-emitting diode (LED) control circuit (Fig. 1e, Fig. S13, and Movie S1) to validate the utility. A sinusoidal AC voltage (3 V, 0.2 Hz) was applied to the circuit. Both LEDs were off under 0 V at the beginning ($t=0\text{ s}$). At $t=1.25\text{ s}$ (3 V), the lower LM-SV was conducting (LED-1 on) and the upper LM-SV was cut off (LED-2 off). In contrast, at $t=3.75\text{ s}$ (−3 V), the lower LM-SV was cut off (LED-1 off), whereas the upper LM-SV was conducting (LED-2 on). The periodic switching of the LED intuitively demonstrates the precise directional current control of the LMW-SV, highlighting its potential in programmable circuits. Furthermore, the LMW-SV can be used for the construction of a LM flexible circuit with multi-modal shape adaptation (Fig. 1f), with corresponding circuit schematic and output characteristic shown in Fig. S14. Based on the spatial reconfiguration and interpenetration of LMW-SV in 3D space, the circuit could freely switch between a stacked state (Fig. 1f₁), a free-standing 3D architecture (Fig. 1f₂), and a 2D planar layout (Fig. 1f₃). This characteristic overcomes the wiring constraints of traditional 2D circuits, enabling the free topological interconnection of conductive traces in 3D space, thereby simplifying the integration of flexible circuits.

Fig. 1. Structure and unidirectional conductive performance of the LM-SV.

a Schematic structure and characteristics of LM-SV. a₁ The single-sided Au-coated p-type silicon wafers (p-Si) placed within the LMs fluid form the semiconductor valves to regulate current direction in the LMs. Insets: Cross-sectional view of the contact interface between LM and p-Si. a₂ Current smoothly flows from the gold (Au)-coated side to the non-coated side of p-Si. a₃ Current is blocked from the non-coated side to the Au-coated side of p-Si. b Energy band diagram of LM/p-Si contact. When the LMs contact p-Si at $V=0$, the energy band of p-Si bends upward to form a contact barrier. At this point, the Fermi levels of the LM and p-Si become aligned. V: bias voltage, E_F,m and E_F,s: Fermi energy levels of LM and p-Si, E₀: vacuum energy level, E_c and E_v: the conduction band minimum and the valence band maximum of the p-Si, E_bi: built-in electric field, Φ_bi: built-in potential in p-Si, Φ_B: contact barrier on the LM side. c J–V characteristic of the LM(Ga)-SV. J: current density, V: applied voltage. d Unidirectional conductive LM wire with integrated semiconductor valve (LMW-SV). d₁ Photograph of LMW-SV, current (I) flows only along the white arrow in LMW-SV. Scale bar: 2 cm. The LM-SVs are positioned by blue circles. d₂ Energy-dispersive X-ray spectroscopy (EDS) mapping of the LM/p-Si (non-Au-coated side) interface in the LMW-SV, showing Ga (white) and Si (blue) distribution. Scale bar: 50 μm. e LEDs control via LMW-SV in an alternating current (AC) circuit (3 V, 0.2 Hz). I denotes the current through the LEDs. Scale bar: 2 cm. When $t=0\text{ s}$ (0 V), both LEDs remain off. When $t=1.25\text{ s}$ (+3 V), the lower LM-SV conducts (LED-1 on) and the upper LM-SV is cut off (LED-2 off). Conversely, when $t=3.75\text{ s}$ (−3 V), the lower LM-SV is cut off (LED-1 off), and the upper LM-SV conducts (LED-2 on). f LM flexible circuit fabricated using LMW-SV, with f₁ stacked, f₂ 3D, and f₃ 2D configurations. Scale bar: 2 cm.

Performance of LM-SV

To demonstrate the potential of the LM-SV integrated in flexible circuits for broad-scenario applications, its performance was tested under large tensile strain, temperature variations, and wide-frequency signal inputs. Firstly, the LMW combined the inherent stretchability of the polymer with the fluidity of the LM, exhibiting deformability capable of withstanding up to 1000% strain (Fig. S15). Importantly, the LM-SV showed no damage under such significant deformation (Fig. 2a), indicating excellent compatibility with the flexible circuit. Meanwhile, the stability of the unidirectional conductivity of the LM-SV was measured in the LMW circuit under mechanical deformation. As shown in Fig. 2b, J–V curves were obtained by sweeping the bias voltage from −3 V to 3 V over step increased strains from 0% to 1000% (0%, 200%, 400%, 600%, 800% and 1000%). The LM-SV exhibited high robustness, with nearly identical J–V characteristics from 0% to 1000% strain. Such strain-insensitivity stems from the conformal LM/p-Si interface, which maintains continuous carrier transport pathways under deformation, outperforming traditional solid-state stretchable rectifiers. Moreover, the LM-SV-based rectifier (Fig. S16) maintained stable half-wave rectification across 0–1000% strain (2 V, 1 Hz AC input; Fig. S17a), generating a consistent output peak voltage of ~1.2 V (Fig. S17b). It also preserved rectifying functionality under 0–90° bending (Fig. S18) and torsion (Fig. S19), sustaining ~1.1 V peak output. Apart from LMW systems, the J–V characteristics of the LM-SV in a planar flexible circuit also showed negligible variation under 0–100% strain (Fig. S20), demonstrating superior dynamic deformation tolerance and broad applicability. Furthermore, the LM-SV strategy demonstrates compatibility with flexible semiconductors. A poly(3-hexylthiophene-2,5-diy) (P3HT)-based LM-SV maintains stable unidirectional conduction even under bending (Fig. S21), which confirms the potential of this architecture for intrinsically soft electronics. All measurements in this study were conducted in LMW-SV-based flexible circuits unless otherwise specified.

Fig. 2. Performance of LM-SV in the LM-based flexible circuit.

a Optical photographs of LM flexible circuit (e.g., LMW) with a LM-SV under 0%, 100%, and 1000% tensile strain (Scale bar :4 cm), showing the excellent compatibility between the LM-SV and highly stretchable circuit. Inset: magnified LM-SV region at 1000% strain, scale bar: 3 mm. b J–V characteristics of the LM-SV in the flexible circuit at strains ranging from 0% to 1000%. Strain rate: 50 mm/min. c Forward and backward currents of the LM-SV during 1000 stretching cycles at a strain of 500%. Strain rate: 50 mm/min. d J–V characteristics of the LM-SV from −5 °C to 100 °C. e Voltage-frequency characteristics of the LM-SV under strains from 0% to 1000%, obtained from the half-wave rectifier circuit in the inset. V_in and V_out represent the input (AC) voltage and the output direct current (DC) voltage, respectively. C and R denote the filter capacitor and the load resistor. The input is a 2 V sinusoidal AC signal. f Ripple-free voltage output from the half-wave rectifier circuit with the LM-SV under varying tensile strains (0% – 1000%). The input is a sinusoidal AC signal with frequencies of 1 Hz and 5 MHz at an amplitude of 2 V. g Gallium (Ga)-indium (In) binary phase diagram. L: liquid phase; S: solid phase. The blue region represents the solid-liquid coexistence phase. The red dashed line is the isotherm at 25 °C. The vertical blue dashed lines indicate Ga_0.5In_0.5 and Ga_0.3In_0.7 compositions. h Energy alignments of the Fermi energy levels of different metals including Ga, Ga_0.5In_0.5, Ga_0.3In_0.7, and In with respect to the vacuum energy level. i Switching voltages of LM-SVs fabricated with different metals (Ga, Ga_0.5In_0.5, Ga_0.3In_0.7, and In). Data are the mean ± SD; n = 3.

The electromechanical stability of LM-SV was further investigated via cyclic tensile tests at 500% strain. After every 100 cycles, the forward and reverse currents of LM-SV were measured via a −3 V to +3 V bias voltage sweep under 500% strain, followed by identical measurements at 0% strain post-relaxation. As exhibited in Fig. 2c, the forward current (9.3 mA under strain) consistently exceeded the reverse current (1.6 mA under strain) after 1000 cycles. Optical microscopies (Fig. S22) revealed a continuous and intact LM/p-Si interface without observable delamination after stretching cycles. These electrical and structural results confirmed the robust resistance of the LM-SV to dynamic mechanical fatigue. Dynamic response tests at different stretching rates (50, 500 and 1000 mm/min) showed no significant current fluctuations during stretch-release cycles at 500% strain (Fig. S23), indicating the robust strain-rate independence in electrical performance of the LM-SV. Moreover, the LM-SV maintained stable J–V characteristics after 100 days of storage under ambient (Fig. S24), 7 days in a damp-heat environment (40 °C, 80% relative humidity, Fig. S25) and 1000 cycles of 45° bending (Fig. S26). Cross-sectional EDS mapping (Fig. S27) further confirms that the interfacial Au distribution remains stable with no continuous elemental diffusion after 10 days. These results demonstrated that both the effectiveness of the silicone tube encapsulation in suppressing LM oxidation and the excellent stability of the LM/Au-p-Si interface, ensuring long-term reliability of the LM-SV. The unidirectional conduction performance of LM-SV was also characterized under different temperatures. As shown in Fig. 2d, the LM-SV maintained a relatively stable forward current density (approximately 2000 mA/cm² at +3 V) from −5 °C to 100 °C, while the reverse current density at −3 V increased from 2.05 mA/cm² to 15.45 mA/cm². This temperature-dependent behavior in reverse current is attributed to a thermally activated trap-assisted tunneling mechanism, where carriers are initially thermally excited into interfacial trap states and then tunnel into the semiconductor (see Note S1 and Fig. S28 for detailed analysis)^47,48. Nevertheless, the LM-SV maintained sufficient rectified voltage (Fig. S29) for AC signals across −5–100 °C to meet practical application requirements, demonstrating reliable operation in thermally dynamic environments.

Additionally, the broadband rectification capability of the LM-SV was characterized using a half-wave rectifier circuit. As shown in Fig. 2e inset, the LM-SV was connected in series with the AC input in the half-wave rectifier circuit with a filter capacitor (C) and a load resistor (R) connected in parallel. The frequency-voltage characteristics of the LM-SV were obtained by applying a sinusoidal AC input ($V_{\mathrm{in}}=\pm 2\mathrm{V}$) with a frequency sweep from 1 Hz to 5 MHz to the circuit under stepped strains from 0% to 1000% (0%, 200%, 400%, 600%, 800%, and 1000%). Figures 2e and f showed that the integrated LM-SV half-wave rectifier circuit maintained a stable 1.1 V direct current (DC) output across 1 Hz-100 kHz under 2 V sinusoidal AC excitation, even under 1000% strain. However, the DC output voltage gradually decreased (e.g., 0.35 V at 5 MHz) when the frequency exceeded 100 kHz. This behavior is related to the reverse recovery time of the LM-SV. At 100 kHz, the AC half-cycle duration (5 μs) is longer than the measured reverse recovery time ($t_{\mathrm{rr}}=3.4\mathrm{\mu }\mathrm{s}$, Fig. S30), allowing the LM-SV to fully switch off during each negative half-cycle and maintain stable rectification. As the frequency increases, the half-cycle duration becomes shorter than t_rr, resulting in incomplete recovery during the negative half-cycle and a gradual reduction in the net rectified output voltage. Nevertheless, the 0.35 – 1.1 V output range under 2 V AC input over 1 Hz–5 MHz remained sufficient for low-operating-voltage stretchable devices, validating the operational rectification capability of LM-SV across frequencies essential for flexible electronics⁴⁰. Furthermore, the frequency characteristics of the LM-SV can be further improved by reducing the contact area to decrease the junction capacitance at the interface⁴⁷. As illustrated in Fig. S31, reducing the contact area effectively enhances the output performance above 2 MHz compared to the LM-SV with larger area. Therefore, miniaturizing the contact dimensions through micro and nanofabrication techniques provides a feasible strategy for further extending the operating frequency range of LM-SV devices.

Regulating the switching voltage of LM-SV is critical for optimizing energy consumption and adapting it to diverse application scenarios. In order to achieve this goal, further research investigated the influence of Ga-In composition on the switching voltage of LM-SV. As shown in Fig. 2g, the Ga-In binary alloy phase diagram can be divided into five characteristic regions: one liquid phase region (L(Ga+In)), two solid phase regions (S(Ga) + S(In) and S(In)), and two solid-liquid coexistence regions (L + S(Ga) and L + S(In)). The blue vertical dashed lines in Fig. 2g represented the Ga_0.5In_0.5 and Ga_0.3In_0.7 compositions, respectively. Notably, Ga_0.5In_0.5 and Ga_0.3In_0.7 alloys were in a solid-liquid biphasic state at ambient temperature (25 °C, red dashed lines). Here, Ga_xIn_y was used to represent Ga-In alloy, where x and y correspond to the atomic fractions of Ga and In, respectively. Differential scanning calorimetry (DSC) analysis (Fig. S32) revealed distinct endothermic peaks for both Ga_0.5In_0.5 (18.5 and 69.8 °C) and Ga_0.3In_0.7 (16.2 and 84.5 °C) alloys. This result was consistent with the theoretical phase diagram, confirming the successful preparation of the target Ga-In alloy. The liquid fraction within these biphasic alloys ensures conformal and intimate contact with the p-Si (Fig. S33). Ultraviolet photoelectron spectroscopy (UPS) was used to measure the work functions of the metals (Ga, Ga_0.5In_0.5, Ga_0.3In_0.7, and In) (Fig. S34). The measured work functions of Ga, Ga_0.5In_0.5, Ga_0.3In_0.7, and In were 4.20 eV, 4.06 eV, 4.00 eV, and 3.96 eV, respectively (Fig. 2h). We further measured the J–V characteristic of LM-SVs prepared with different metals (Fig. S35) and extracted their corresponding switching voltages (Fig. 2i and Table S3). The switching voltages were measured 0.43 V, 0.53 V, 0.60 V, and 0.80 V for LM(Ga)-SV, LM(Ga_0.5In_0.5)-SV, LM(Ga_0.3In_0.7)-SV, and LM(In)-SV, respectively. This increase in switching voltage is attributed to the increasing In content, which lowers the work function of the alloy and thereby raises the interfacial contact barrier (detailed mechanism in Note S2). Benefiting from its excellent stretchability, MHz-level operating frequency, and tunable switching voltage, the LM-SV exhibited superior overall performance compared with existing flexible rectifiers (Table S4).

Topology transitioning in LM-SV-based circuit

To enable circuit switching and multifunctional integration in flexible electronics, we performed dynamic topological reconfiguration of LM-SV circuits through three physical operations: stacking, connection, and blocking. First, a LM-SV-integrated flexible circuit with a common-cathode connection was constructed (Fig. 3a₁). The corresponding equivalent circuit diagram can be found in Fig. 3a₂. The crossing nodes in the circuit were in stacking state (yellow circles; structure in Fig. S36a). Under 2 V, 1 Hz sinusoidal AC input, the output voltage approached zero (V_out,a, Fig. 3c). This resulted from mutual cancellation of unidirectional conduction between the LM-SVs, preventing effective current (I) pathways (blue dashed line, Fig. 3a₁) and producing diode-like cut-off behavior.

Fig. 3. Real-time topology transitioning in LM-SV-based flexible circuits.

a and b Optical photograph a₁ and b₁ and equivalent circuit diagram a₂ and b₂ of the LM flexible circuit integrated with LM-SVs. Yellow circles represent the LMWs in a simple stack with no electrical connection. The blue dashed line shows the current (I) path. V_in and V_out denote the input voltage and the output voltage. GND is short for ground. Blocking constraints (pink dashed circles) and connection operations (green circles) reconfigure the LM-SVs in the circuit from common-cathode a₁ to same-direction series connection b₁. c Output signals of circuits a₁ and b₁ with identical sinusoidal AC (2 V, 1 Hz) input. d and e Optical photograph d₁ and e₁ and equivalent circuit diagram d₂ and e₂ of the LM-SV-based OR and AND gate circuit. Through stacking, connection, and blocking of LMWs, the OR gate d₁ and d₂ is reconfigured into an AND gate e₁ and e₂. V_cc (3 V) is the power supply of the AND gate, maintaining a high-level output and ensuring proper functionality of the logic gate. f Input and output characteristics of the LM-SV-based OR gate. g Input and output characteristics of the LM-SV-based AND gate.

In order to switch the circuit from the cut-off state to the rectification state with fixed input/output terminals, blocking operations were applied to the target regions (pink dashed circles, Fig. 3b₁), physically interrupting local conductive pathways (Fig. S36c). Meanwhile, electrical connections were established at the stack nodes (green circles; structure in Fig. S36b and Fig. S37). This topological reconfiguration transformed the LM-SVs from common-cathode to same-direction series (Fig. 3b₁), with the equivalent circuit shown in Fig. 3b₂. Under 2 V, 1 Hz sinusoidal AC input, the circuit generated a 1.3 V peak DC output (V_out,b, Fig. 3c), confirming transition from cut-off to rectification. Notably, the flowing LM autonomously repaired the pathway after removing the blocking (Fig. S36c and Fig. S38) and connection operation, reverting the LM-SVs to a common-cathode connection and resetting the circuit to the cut-off state (Fig. S39). This reversible topological restoration is driven by the high surface tension and room-temperature fluidity of the LM, which immediately restores a continuous equipotential network upon the release of mechanical constraints. This phenomenon demonstrated mutual functional switching in the LM circuit via topology control using stacking, connection, and blocking operations. Further research focused on introducing the dynamic topological reconfiguration strategy to logic circuits to enable reversible function switching. Figure 3d₁ showed an initial logic OR gate circuit using two common-cathode LM-SVs with anodes as inputs (equivalent circuit in Fig. 3d₂). Here, the input logic states 0 and 1 correspond to 0 V and 2 V, respectively, while the output logic states 0 and 1 refer to ≤1 V and ≥1.5 V, respectively. Logic gate functionality was characterized by measuring output voltages for four input combinations (V_in,a, V_in,b) that correspond to (0,0), (1,0), (0,1), and (1,1) states. Figure 3f showed that the OR gate outputs (V_out) were at logic state 1 whenever either input (V_in,a and V_in,b) was at logic state 1, and only dropped to logic state 0 (0V) when both inputs were at logic state 0. The corresponding truth table of the OR gate was presented in Table S5.

Similarly, the common-cathode connection of LM-SVs in the OR gate could be reconfigured into the common-anode connection (Fig. 3e₁) through stacking, connection, and blocking operations. The equivalent circuit is shown in Fig. 3e₂. Based on the logic gate functionality test, the output (V_out) was at logic state 1 only when both inputs (V_in,a and V_in,b) were at logic state 1. All other input combinations resulted in logic 0 output (Fig. 3g). This behavior was consistent with the truth table of the AND gate (Table S6). Correspondingly, the circuit topology could be reversibly switched between logic AND and OR gate by applying or removing the blocking/connection operations. This switching of circuit functions originates from the synergy between the unidirectional charge transport at the LM-semiconductor heterointerface and the fluidic reconfigurability of the LM. This strategy offers a facile route for constructing dynamic topological electronic systems, enabling multifunctional integration through physical programming. Voltage transfer characteristics (VTC) showed switching thresholds (V_th) of 1.5 V and 0.7 V for the OR and AND gates, respectively, with logic swings exceeding 1.4 V. Although the passive diode-based architecture introduced voltage offsets and negative noise margins (Note S3 and Fig. S40), the large logic swing could ensure reliable signal recognition in these reconfigurable circuits. Dynamic response tests (Figs. S41 and S42) revealed a propagation delay of ~40 ns and a maximum transition time of ~492 ns for the LM-SV logic gates, corresponding to a theoretical operating frequency of ~1 MHz. Furthermore, the LM-SV was integrated with a commercial transistor to construct a functional diode-transistor logic (DTL) NAND gate (Fig. S43a). This hybrid configuration yielded logic outputs (Fig. S43b) matching the standard NAND truth table (Table S7), confirming the excellent compatibility of LM-SV in advanced logic applications.

Stretchable LM-SV-based radio-frequency logic gate

To further validate the functional potential of the LM-semiconductor interfacial barrier engineering strategy, and assess the electrical compatibility of this physical model in complex electronic systems, a stretchable logic circuit integrating wireless power harvesting and logic computing was designed and fabricated. As shown in Fig. 4a, the stretchable LM-SV-based radio-frequency (RF) logic gate (LM-SV RF gate) consists of two core modules: a stretchable rectenna and a LM-SV-based AND gate. The rectenna serves as the front-end functional unit, incorporating a stretchable dipole antenna for capturing electromagnetic waves and a rectifier circuit for converting the RF AC signal into a DC signal. The LM-SV-based AND gate directly utilizes the intrinsic unidirectional conductivity of the LM-SV to perform the logic operation. Through the synergistic operation of these two parts, the system achieves a stretchable integration from energy capture to information processing. The detailed fabrication procedures and circuit schematic were provided in Fig. S45 and S46. As shown in Fig. 4b, the circuit maintained its structural integrity without physical damage under mechanical deformations such as twisting and bending, demonstrating excellent deformation adaptability and mechanical robustness. Figure 4c showed the continuous wireless communication between the LM-SV RF gate and the transmit antenna. The LM-SV RF gate received and converted the RF energy from the transmit antenna to drive the subsequent logic operations of the LM-SV-based AND circuit.

Fig. 4. Stretchable LM-SV-based radio-frequency (RF) logic gate.

a Photograph of the stretchable LM-SV-based RF logic gate (LM-SV RF gate). The circuit comprises a stretchable rectenna and a LM-SV-based AND gate. GND indicates ground. V_in,ANT represents the input signal from the rectenna to the AND gate. V_in,a denotes the external input signal to the AND gate. V_cc (3 V) is the power supply for the AND gate. Scale bar: 1 cm. b Photographs of the LM-SV RF gate under twisting b₁ and bending on a cylindrical surface b₂, demonstrating its excellent mechanical conformability. Scale bar: 2 cm. c Schematic diagram of the continuous wireless communication between the LM-SV RF gate and the transmit antenna. The LM-SV RF gate converts the RF signal from the antenna into a DC signal to drive subsequent logical operations. The Tx antenna refers to the transmit antenna. Scale bar: 5 cm. d Photograph d₁ and corresponding circuit schematic d₂ of the rectifier based on a flexible printed circuit board. ANT represents the antenna. L indicates the matching inductor, while C₁ and C₂ represent capacitors. D₁ and D₂ denote the rectifying diodes. R_L stands for the load resistor. Scale bar: 3 mm. e Simulated reflection coefficient (S₁₁) of the antenna and the rectifier. The dashed rectangle indicates the −10 dB impedance bandwidth of the rectifier, which fully encompasses that of the antenna. The center frequency of both components is 2.44 GHz. f Output voltage of the LM-SV RF gate under different transmission distances and RF power ($V_{\text{cc}}=3\text{ V}$, $V_{\text{in},\text{a}}=2\text{ V}$). The transmission distance is defined as the vertical distance between the transmit antenna and the receiving antenna. g Optical photographs of the LM-SV RF gate under 0%, 100%, and 200% tensile strain. h Input-output characteristics of the LM-SV RF gate under step increased tensile strains from 0% to 200%.

As a key component of the rectenna, the RF rectifier circuit converted the captured RF energy into a DC input signal for the logic gate. The rectifier followed a first-order Greinacher-type topology (Fig. 4d) with two low-threshold diodes (SMS7621-005LF), two capacitors (100 pF), and a load resistor (1 kΩ), functioning as a voltage doubler for efficient rectification. An inductor (12 nH) was used to match the impedance between the antenna and the rectifier, thereby enhancing the power transfer efficiency. The reflection coefficient (S₁₁) of the antenna and the rectifier circuit was simulated to evaluate their impedance matching. As shown in Fig. 4e, the S₁₁ of rectifier circuit was below -10 dB across a frequency range from 1.98 to 3.04 GHz, indicating good impedance matching. This frequency band entirely covered the −10 dB bandwidth of the front-end receiving antenna (2.22 – 2.72 GHz). This broad operating bandwidth provides a tolerance margin for resonant frequency shift induced by mechanical deformation, thereby ensuring the continuity of system functionality. Both the antenna and rectifier circuit shared a center frequency of 2.44 GHz, confirming effective impedance matching and reliable energy harvesting in the 2.45 GHz industrial scientific medical (ISM) band.

The logic states 0 and 1 for the LM-SV RF gate are defined as output voltages of ≤0.6 V and ≥1.0 V, respectively. Under the conditions of $V_{\mathrm{cc}}=3\mathrm{V}$, $V_{\mathrm{in},\mathrm{a}}=2\text{ V}$, and an RF power of 25 dBm, the LM-SV RF gate maintained correct logical outputs within a transmission range of 0 to 16 cm (Fig. 4f). At the maximum distance of 16 cm, the output voltage remained at 1.0 V, indicating a logic state of 1. Furthermore, at a transmission distance of 8 cm, the output voltage was sustained at 1.1 V (logic 1) even when the RF power was lowered to 19 dBm (Fig. 4f), confirming reliable logic functionality of the gate at RF power ≥19 dBm. These results demonstrate strong resilience of the circuit system to fluctuations in RF signal, underscoring its potential for e-skins and smart textiles where stable logic operations are required despite signal variations from user motion. Since the rectenna provided an output voltage (V_in,ANT) of 2 V at a transmission distance of 8 cm and an RF power of 25 dBm (Fig. S47), all subsequent tests were conducted under these conditions unless otherwise specified. As shown in Fig. 4g, the LM-SV RF gate retained its structural integrity without fracture under tensile strains from 0% to 200%. The rectenna system maintained an RF-to-DC energy conversion under deformation, with efficiencies ranging from 16.1% to 1.4% across the 0% to 200% strain range (Fig. S48). Despite this decline, the 0.65 V rectenna output at 200% strain is still enable to maintain the output logic 1 level in the system (Fig. 4h and Movie S2), indicating continuous and reliable logic functionality under extreme dynamic deformation. Further tests under bending and folding (Fig. S49) confirmed its robustness under common deformations in practical wearables, such as those induced by joint movements or skin stretching. Furthermore, after 1000 stretching cycles at 100% strain, the logic functionality basically remained consistent with the initial state (Fig. S50), confirming the excellent mechanical durability and long-term reliability of the LM-SV RF gate.

Discussion

This work demonstrated that the asymmetric interfacial barrier formed by the contact between LM and single-sided Au-coated p-Si is the underlying mechanism responsible for interfacial unidirectional carrier transport. Combining this feature with the inherent fluidity of LM enables the successful fabrication of a unidirectional LM-SV and the straightforward assembly of flexible 3D topological circuits. In the LM-SV, LM directly participates in interfacial barrier formation, thereby transforming its functional role from a conventional conductive interconnect to a functional component capable of directional carrier transport. The LM-SV exhibited high stretchability (~1000% strain), stable cyclic unidirectional conductivity (over 1000 stretching cycles at 500% strain), and maintained excellent performance across a broad temperature range (−5–100 °C) and a wide frequency band (1 Hz–5 MHz). The switching voltage of LM-SV (0.43–0.80 V) can be conveniently adjusted by modulating the LM composition. The circuit topology could be reconfigured in real-time to switch between various functions including rectification, OR gate, and AND gate via physical operations such as stacking and connecting. In addition, the LM-SV was integrated with a stretchable antenna to realize unified wireless power harvesting and logic computing even under 200% strain. This work offers a pathway for introducing directional carrier regulation into LM and enabling dynamic circuit topology reconfiguration. Future efforts will focus on interfacial miniaturization to alleviate local stress concentration while investigating intrinsically soft semiconductors and locally doped LM-semiconductor heterostructures to further bridge the gap toward practical applications. This study provides an insight into the integration of interfacial semiconductor physics with liquid metal systems, offering a conceptual framework for developing adaptive and reconfigurable soft electronic architectures.

Methods

Materials: All materials used in this work were commercially available. Gallium (Ga, 99.999%, melting point: 29.8 °C) and indium (In, 99.999%, melting point: 157 °C) were purchased from Shenyang Jiabei Trading Co., Ltd. The low-doped p-type silicon (p-Si, resistivity: 1–20 Ω·cm, thickness: 500 ± 25 μm), featuring a 100 nm-thick gold (Au) layer on one side, was supplied by Changsha Lanxin Semiconductor Co., Ltd. Silicone tube (inner diameter: 0.8 mm, outer diameter: 1.5 mm) and latex tube (inner diameter: 1 mm, outer diameter: 2.2 mm) were obtained from Shanghai Xinrong Rubber and Plastic Products Co., Ltd. and Wuxi Tongsu New Material Co., Ltd., respectively. Ecoflex 0050 was purchased from Smooth-On Industrial Corporation.

Preparation of liquid metal wire with a semiconductor valve: The liquid metal wire with a semiconductor valve (LMW-SV) was prepared using a vacuum-filling method (a schematic of the process was shown in Fig. S1). The procedure is briefly described as follows: Circular p-Si (diameter: 1 mm) were ultrasonically cleaned in acetone, anhydrous ethanol, and deionized water for 15 min each to remove surface organic contaminants. Next, the cleaned p-Si was inserted sideways into a silicone tube (inner diameter: 0.8 mm, outer diameter: 1.5 mm) using a flat-tipped copper guide rod. After reaching the desired position, the guide rod applied an asymmetric force to the edge of the p-Si, causing it to flip 90° inside the elastic tube. Following this rotation, it was vertically secured by the radial clamping force of an interference fit (see Fig. S2 for details). Subsequently, vacuum filling of Ga was performed: both open ends of the silicone tube were completely sealed with liquid metal (LM). The sealed assembly was placed in a vacuum oven, which was evacuated to −0.1 MPa at room temperature. After the target vacuum was achieved, the pressure was slowly released back to atmospheric pressure. The resulting pressure differential drove the Ga into the silicone tube, filling its internal cavity and establishing intimate contact with both sides of the vertically fixed p-Si, thus completing the preparation of the LMW (Ga)-SV. During this vacuum-filling process, the shear stress from the flowing LM continuously disrupts its surface oxide layer while the low-oxygen environment inhibits re-oxidation, ensuring negligible oxide formation before LM-Si contact (verified by J–V comparison with glovebox-fabricated samples in Fig. S3).

For the preparation of LMW (Ga_0.5In_0.5)-SV and LMW (Ga_0.3In_0.7)-SV, the cleaned p-Si was similarly inserted and vertically secured inside the silicone tubes. Both open ends of the tubes were completely sealed with the respective LM alloys. The sealed assemblies were then placed in a vacuum oven and evacuated to −0.1 MPa. The key distinction lay in the temperature control during the vacuum process. Since the melting points of the Ga_0.5In_0.5 and Ga_0.3In_0.7 alloys are approximately 69.8 °C and 84.5 °C, respectively, the vacuum oven temperature was set to 75 °C for the LMW (Ga_0.5In_0.5)-SV and 90 °C for the LMW (Ga_0.3In_0.7)-SV to ensure the alloys were completely molten for effective filling. After achieving the target vacuum (−0.1 MPa) at these elevated temperatures, the pressure was slowly released back to atmospheric pressure to drive the respective molten alloys into the silicone tubes, completing the preparation.

Preparation of LM(In)-SV: Given the solid state of In at room temperature and its high melting point (157 °C), the vacuum-filling method was unsuitable for filling In into the silicone tube. Therefore, an In thin film (thickness: ~1 μm) was deposited onto the p-Si surface via vacuum thermal evaporation to facilitate optimal electrical contact, enabling the preparation of the LM (In)-SV. The evaporation process was conducted in a thermal evaporation system (EVD-400). The initial chamber pressure was lowered to below 3 × 10⁻⁴ Pa before deposition. The evaporation rate was controlled at approximately 0.1 nm/s, and the film thickness was monitored in real-time using a thickness monitor (SQM-160).

Preparation of the LM-SV RF gate: First, a replica molding process was employed: ecoflex was cured in a polytetrafluoroethylene (PTFE) mold featuring a circuit pattern (the morphology and dimensions were shown in Fig. S44 and Table S8, respectively) to produce a flexible substrate with circuit grooves. Subsequently, the LMW-SV was fabricated by vacuum filling the LM into a silicone tube pre-fixed with a p-Si. Next, this LMW-SV was embedded into the grooves of the flexible substrate to complete the circuit assembly. Finally, the LM-SV RF gate was obtained after encapsulating by another layer of ecoflex. (Fig. S45).

Characterization and testing of material: A function generator (SIGLENT SDG 1022X) and a DC power supply (Henghui HLR-3660D) were employed to characterize the LM-SV-based rectifier, as well as the OR and AND logic gate circuits. The output voltage was measured with an oscilloscope (UNI-T UPO1201S-E) and digital multimeters (Keysight 34461 A and Keithley DMM6500), while the output current was measured using digital multimeters (VICTOR VC890C, Keysight 34461 A, and Keithley DMM6500). The contact interface (LM/p-Si) of the LM-SV was characterized using a deep depth-of-field microscope (Leica DVM6) and a scanning electron microscope (SEM, FEI Inspect F50). Elemental distribution across the LM/p-Si interface was analyzed by energy-dispersive X-ray spectroscopy (EDS). The solidification and melting points of the biphasic liquid metals (Ga_0.5In_0.5 and Ga_0.3In_0.7) were characterized by differential scanning calorimetry (DSC, TA DSC 25). Tensile testing of the liquid metal wire (LMW) was performed on a universal testing machine (MTS E42). The work function of metal was measured by ultraviolet photoelectron spectroscopy (UPS, Thermo Fisher Scientific). Considering the zero-point offset of the power supply, the current density at 0 V in the J–V curves is fixed at 10⁻¹⁰mA/cm² to accommodate the logarithmic axis. Similarly, the power inputs for the logic circuit tests are uniformly recorded as nominal values (0 V and 2 V) and the rectenna output is plotted as 0 V when the transmission source is turned off. For comparison, logic circuit waveforms were plotted on an identical time scale.

Author contributions

J.Y.Z. proposed the idea and conceived the project. J.L.W. designed the experiment and analyzed the results. J.L.W., Z.H.K., Y.P., Z.W.L. and Y.Z. conducted the experiment. J.Y.Z., Y.P. and J.L.W. wrote the manuscript. All authors commented on the manuscript.

Peer review

Peer review information

Nature Communications thanks the anonymous reviewers for their contribution to the peer review of this work. A peer review file is available.

Funding

The work is supported by Young Scientists Fund of the Natural Science Foundation of Jiangsu (Grant No. BK20241359, to Y.P.), the National Key Research and Development Program of China under Grant (grant number 2023YFB4404200, to J. Y. Z.), Basic Research Program of Jiangsu (grant no. BK20250075, to J. Y. Z.) and National Natural Science Foundation of China (grant no. 52173249, to J.Y. Z.).

Data availability

The data generated in this study are provided in the Supplementary Information/Source Data file. Source data are provided with this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-77296-4.