Ultra-low-power probabilistic graphical computing based on memristors enabling communications signal processing

Abstract

Improving the energy efficiency of baseband processors has become a critical challenge in mobile communications, especially for energy-constrained edge devices. Applications in conventional baseband signal processors usually adopt independently optimized algorithmic architectures and primarily rely on digital systems, whose energy efficiency is fundamentally limited by frequent data movement and computationally intensive dynamic operations. To overcome the fundamental energy-scaling bottleneck in modern signal processing, here we report a probabilistic graphical computing paradigm based on memristors, which not only unifies the framework of Bayesian inference-based baseband signal processing algorithms, but also achieves a substantial improvement in energy efficiency via memristor-based in-memory computing. Results demonstrate that the proposed approach achieves energy consumption below 10 pJ per bit and up to an 11.4-fold improvement in energy efficiency over conventional implementations, while maintaining error rates below 1×10⁻⁴ in the representative application. These results provide a flexible, noise-resilient route to ultra-low-power signal processing in edge devices.

To address the energy bottleneck in modern mobile communications, Jiang et al. introduce a memristor-based framework unifying key wireless signal-processing tasks. It achieves sub-10 pJ/bit consumption and an 11.4-fold efficiency gain while maintaining low error rates for edge communications.

Introduction

In edge communication devices operating under stringent energy constraints (e.g., RedCap 5G devices, LTE Cat.1/Cat.4 devices, 3GPP NTN edge terminals), the baseband signal processor overwhelmingly dominates the power budget of communication receivers^1–3. For example, in fourth-generation long-term evolution (4G LTE) and fifth-generation (5G) mobile communications, the baseband processor consumes 71–85% and 69–79% of the receiver’s total power⁴, respectively. Therefore, its optimization is important for enabling sustained connectivity. Existing baseband signal processing applications encompass multiple-input and multiple-output (MIMO) detection, channel decoding, channel estimation, etc., which are commonly implemented using independently optimized algorithmic architectures. Those algorithms serving as independent hardware modules are usually integrated into a baseband processor in a divide-and-conquer manner⁵, while their commonality in Bayesian inference architecture has received relatively limited attention (Supplementary Note 1).

In addition, conventional baseband processors primarily rely on digital implementations^6–8—such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and software-defined radios (SDRs), which struggle to deliver  the required ultra-high energy efficiency. The fundamental challenge originates from the frequent data movement^9,10 and large-scale, dynamically variable digital computations^11–13 required across the entire communication signal-processing chain. Specifically, conventional digital signal processing architectures, such as those based on FPGAs or SDRs implementations, exhibit limited energy efficiency, typically consuming around 10⁴ pJ per bit^7,14, while ASIC implementations are slightly more efficient at ~10²−10³ pJ per bit^15–19. Nevertheless, given the strict power constraints of communication platforms, such efficiency levels struggle to satisfy the demanding communication requirements of energy-constrained edge devices in the 6G era²⁰. To address these challenges, it is crucial to develop ultra-low-power signal processing paradigms that should be adaptable to the diverse communication processing requirements, thereby enabling ubiquitous connectivity in the next generation of wireless networks.

As an emerging technology, memristors hold potential to overcome fundamental bottlenecks, including power consumption, computational efficiency, and scalability. The ability of memristors to electrically switch between multiple stable, non-volatile resistance states²¹ makes them promising candidates for next-generation computing systems, including artificial neural networks^22,23, reservoir computing²⁴, Ising solvers²⁵, and sampling²⁶. Owing to their highly scalable structure, memristors enable dense matrix integration via crossbar arrays²⁷ and 3D stacking²⁸, and align naturally with energy-efficient compute-in-memory (CIM) architectures²⁹. This combination of attributes renders them suitable for matrix multiplication and accumulation (MAC) operations that are pivotal to AI and signal processing. Moreover, their low switching energy and negligible static power consumption contribute to improved overall energy efficiency³⁰.

Although memristors have proven highly suitable for energy-limited edge applications, efforts to integrate them with communication signal processing remain relatively limited. Existing research on in-memory computing for wireless communications primarily focuses on individual functional modules, such as MIMO detection^31–34 and constellation point identification^35–37. However, these methods predominantly rely on directly mapping classical algebraic formulas, which necessitates loading dynamic channel matrix information onto the hardware. Consequently, they face significant challenges in adapting to time-varying environments due to the substantial overheads associated with repetitive memristor reprogramming and latency. Furthermore, many signal processing phases lack compatibility with vector-matrix multiplication (VMM) and predominantly operate using dynamic dataflow architectures. These factors hinder the widespread implementation of memristors in communication systems.

In this work, we propose a unified probabilistic graphical computing architecture for baseband signal processing and implement it based on memristors. It is worth mentioning that the proposed unified architecture allows the baseband signal processing applications to share the same iteration structure and the same memristor-based hardware implementations. Specifically, by configuring the values stored in the memristor array, our approach supports various communication applications, including multiple-input multiple-output (MIMO) detection and low-density parity-check (LDPC) decoding. Moreover, our approach also includes in-memory computing hardware schemes incorporating memristors, sparse optimization, and dataflow level optimization to fully exploit the low-power potential of probabilistic graphical computing technology. This work unifies baseband signal processing architectures within a probabilistic graphical computing framework implemented using memristors. Through synergistic optimization of the strategies above, we achieve ultra-low energy consumption of less than 10 pJ per bit for both MIMO detection and LDPC decoding applications, while maintaining error correction capability under environmental noise. This demonstrates a potential route toward low-power deployment on edge devices.

Figure 1a illustrates the distinction between our proposed architecture and traditional paradigms. Diverging from traditional signal processing methods that employ distinct processing hardware modules for each algorithm, this work introduces a unified probabilistic graphical computing (UPGC) architecture that converts application-specific algorithms and hardware modules into static configuration parameters storable in reconfigurable memristor arrays. The detailed optimization workflow of our framework is illustrated in Fig. 1b. Integrating memristors into communication systems presents significant challenges. Specifically, traditional communication algorithms exhibit incompatibility with memristor-based hardware primarily due to a mathematical form mismatch, where workflows such as LDPC decoding rely on logical operations (e.g., XOR, sorting) that lack explicit VMM formulations. Furthermore, dynamic deployment conflicts arise even in mathematically compatible tasks like MIMO detection, as the requirement for frequent array updates is incompatible with the high write overhead of non-volatile memristors. Furthermore, memristors’ limited write endurance³⁸ makes them better suited for static data patterns, such as those found in neural network inference^39,40. In contrast, communication algorithms involve highly dynamic dataflows that complicate the identification and exploitation of long-term invariants. To address these challenges, we introduce optimizations at both the algorithmic and hardware levels. At the algorithmic level, we optimize the probabilistic graphical computing framework to transform core message-passing operations into memristor-compatible MAC operations. At the dataflow level, we propose a quantization-based static dataflow scheme that better aligns with memristor characteristics across diverse applications. We also develop a pruning strategy specifically tailored to the unified probabilistic graphical computing architecture, which enables fine-grained trade-offs between algorithmic performance and energy efficiency. Additionally, we explore practical deployment optimizations, such as algorithmic fixed-point conversion and dataflow simplification, and evaluate their applicability within the proposed architecture. To demonstrate the effectiveness of our approach, Fig. 1c provides a comparative visualization between conventional methods and our proposed framework. Additional information about the general workflow in this work is available in Supplementary Fig. 1~5.

Fig. 1. Overview of our proposed work.

a The overall workflow of our approach. b The optimization loop of the unified probabilistic graphical computing diagram based on memristors. By introducing memristors into our system, we leverage their configurable and low-power characteristics. We also propose a pruning scheme tailored for probabilistic graphical computing, offering a broad trade-off space between performance and power consumption. c A comparison of the architecture we propose with traditional architectures in terms of reconfigurability and low power consumption. This highlights the advantages of reconfigurability and the potential for low-power applications of our unified probabilistic graphical architecture.

Results

Memristor characteristics and device implementation

As an emerging memory technology, memristors provide key advantages such as long-term data retention, re-configurability, and low-power operation, though device-level characteristics can also influence the overall performance of hardware systems. To provide a comprehensive understanding of our study, we begin by introducing the principles, characteristics, and advantages of memristors supported by experimental statistical data from large-scale memristor arrays, as illustrated in Fig. 2.

Fig. 2. Illustration and implementation of 2D memristors.

a The basic principle of memristors. b The radar chart comparing RRAM (memristor array in this case) with two conventional memory technologies (SRAM, DRAM) shows the advantages of memristors in terms of leakage power consumption, integration potential, long-term storage and radiation resistance in more dimensions, which makes memristor highly suitable for edge applications in communication scenarios. c Comparison of digital and memristor-based MAC implementations. d The experimental resistance state probability distributions of our fabricated memristor devices demonstrate relatively high on-off ratio of over 1000 and a relatively low device variation. e Retention data of our fabricated memristor devices with V_read = 0.2 V. f Comparison of test results with other similar memristor works. We compared with other works in two dimensions: device switching ratio (affecting performance) and endurance (affecting the number of configurable times of the system).

As shown in Fig. 2a, our integration approach combines the memristor with a 2D transistor. Unlike conventional CMOS technology, which places the transistor on the bottom layer during the doping process, 2D materials offer inherent advantages for transistor fabrication (e.g., high carrier mobility, excellent gate control) and can be transferred to most lattice-matched substrates without significant loss of functionality⁴¹. This transfer compatibility allows our fabrication method to achieve greater simplicity.

Figure 2b further demonstrates the performance of resistive random-access memory (RRAM, crossbar array of memristors) across multiple critical metrics using a radar chart for intuitive visualization. These metrics include leakage power⁴², integration scalability⁴², long-term retention⁴³, and radiation hardness^44,45. In comparison with traditional memory technologies such as SRAM and DRAM, RRAM exhibits clear advantages in most aspects. Notably, RRAM achieves a favorable balance between retention time (indicating data stability) and access latency (reflecting read/write speed). A detailed comparison of RRAM with conventional memory technologies, including SRAM, DRAM, and Flash, can be found in Supplementary Fig. 6. Owing to these characteristics, RRAM is particularly suitable for low-power, high-reliability edge computing applications within communication systems.

Figure 2c compares traditional digital units with the memristor array implementation of MAC operations, which are fundamental computing blocks extensively used in AI and signal processing. Conventional digital MAC units, composed of multipliers and adders, occupy considerable area and require multiple memory accesses per operation—specifically three reads and one write. This results in high energy and latency costs⁴⁶, as exemplified by models like AlexNet⁴⁷, which involve 724 million MACs and require ~3 billion DRAM accesses during inference. In contrast, memristor-based crossbar arrays perform matrix-vector multiplication in a single step by applying Ohm’s and Kirchhoff’s laws, mapping weights as conductance values and computing currents in parallel. This approach achieves O(1) time complexity, drastically reducing both access and energy overhead. However, device non-idealities, such as conductance variability and on/off ratio limitations, can affect the stored weight values, thus degrading the precision of MAC operations.

Figure 2d presents the probability distributions of the low resistance state (LRS) and the high resistance state (HRS), showing that our device exhibits relatively low variability and a high switching ratio, both of which contribute to the accurate execution of MAC operations. Figure 2e illustrates the retention characteristics of our device, revealing no significant resistance change across different states after 2 × 10⁴ S at 120 °C. Based on the JEDEC JEP122H standard, this corresponds to 10 years of retention at room temperature. The experimental setup used for device testing is shown in Supplementary Fig. 7, and the readout characteristics of our devices are provided in Supplementary Fig. 8.

We benchmark the performance of our memristor devices against previously reported ones (Fig. 2f^48–54), with emphasis on two key performance metrics: switching ratio and endurance. Given that edge applications typically require infrequent updates to the storage configuration, the endurance of our devices is sufficient, even when accounting for redundancy. Furthermore, the switching ratio directly influences computation accuracy and, consequently, algorithm performance. A case study illustrating the impact of memristor non-idealities on neural network inference accuracy is provided in Supplementary Fig. 9, while the complete simulation workflow is summarized in Supplementary Fig. 10.

Unified probabilistic graphical computing with memristors

The operational principle of the UPGC stems from the mathematical similarity across diverse signal-processing units, as shown in Fig. 3a. Typically, an observed signal is obtained through a linear transformation of the transmitted signal with additive unknown disturbances, expressed as:

$$\mathbf{y}=\mathit{\Theta }\mathbf{x}+\mathbf{n},$$ 1

where y and x denote the feature vectors of the received and transmitted signals, respectively. The association mapping matrix $\mathit{\Theta }$ characterizes the coupling relationship between observations and unknown variables, while n represents unknown noise disturbances. For example, in a MIMO detector, $\mathit{\Theta }$ corresponds to channel parameter matrix, y is the received symbol vector, and x is the vector of transmitted signals to be recovered. The goal is to infer x from y. In a channel decoder, $\mathit{\Theta }$ embodies constraint relationships between encoded bit sequences x. By reinterpreting the physical significance of $\mathit{\Theta }$, this universal model reveals intrinsic connections among diverse signal-processing procedures, thereby establishing a foundation for UPGC across distinct signal-processing algorithms and hardware modules. Table 1^{9,10,35,55,56} compares signal processing applications from existing research with those in this work. While many existing hardware approaches are designed for a specific application scenario, the proposed technique showcases versatility across multiple scenarios.

Fig. 3. Unified probabilistic graphical computing architecture based on memristors.

a The principle of unified probabilistic graphical computing. Heterogeneous signal processing applications are abstracted as unknown variable estimation based on observed signals and known mapping laws, creating a multi-application compatible architecture. This architecture maps observation results to observation check nodes, maps unknown variables to hidden variable nodes, and characterizes the mapping laws through the connection relationships between these two types of nodes. b Hardware implementation diagram enabled by RRAM. Message iteration updates are reformulated as VMM. Memristor crossbar conductances are dynamically programmed to implement application-specific mapping laws, allowing on-demand reconfiguration for diverse communication applications.

Table 1.

Compatibility of the proposed framework with diverse signal-processing applications

	Application Compatibility
	Multi-antenna mixed signal detector	Channel decoder	Channel estimator	Multi-user detector	Frequency identifier	Filter	Symbol detector
Nature Electron9	×	×	×	×	✓	✓	×
Nature Electron.10	✓	×	×	×	×	×	×
NC 35	×	×	×	×	×	×	✓
ISSCC55	×	×	×	✓	×	×	×
ISSCC56	×	✓	×	×	×	×	×
This work	✓	✓	✓	✓	✓	✓	✓

UPGC integrates the diverse signal processing units by transforming them into a unified computational architecture. The UPGC architecture comprises three parts: (1) variable nodes $\left\{V_1,V_2,\dots ,V_J\right\}$ representing unknown variables $\left\{x_1,x_2,\dots ,x_J\right\}$, where each $x_j$ belongs to a discrete state space $M$ with cardinality $K=\parallel M\parallel$; (2) check nodes $\left\{C_1,C_2,\dots ,C_I\right\}$ characterizing coupling relationships among unknown variables, observed variables, and the association mapping matrix; (3) connectivity between variable nodes and check nodes, which is defined by $\Theta$. Messages between nodes are iteratively updated as:

$${\beta }_{ij}\left(u_k\right)={\sum }_{\mathbf{x}\in {\Omega }_k^{ij}}\left(G_i\left(\mathbf{x}\right)P\left(\left\{{\alpha }_{li}\left(x_l\right)\right\}{\mid }_{l\ne j}\right)\right),$$ 2

$${\alpha }_{ji}\left(u_k\right)=g\left(\left\{{\beta }_{lj}\left(u_k\right)\right\}{\mid }_{l\ne i}\right),$$ 3

where ${\beta }_{ij}\left(u_k\right)$ denotes the message passed from check node $C_i$ to variable node $V_j$ regarding $x_j=u_k$, ${\alpha }_{ji}\left(u_k\right)$ denotes the message passed from variable node $V_j$ to check node $C_i$ regarding $x_j=u_k$. $P\left(\left\{{\alpha }_{li}\left(x_l\right)\right\}{\mid }_{l\ne j}\right)$ specifies the joint distribution for a vector $\mathbf{x}\in {\Omega }_k^{ij}$, ${\Omega }_k^{ij}$ denotes the set of vectors formed by the combinations of the states of variable nodes that are connected to check node i and satisfy $x_j=u_k$. $G_i\left(\mathbf{x}\right)$ denotes a configurable memristor function supporting dynamic parameterization for distinct applications. The configurable function $G_i\left(\mathbf{x}\right)$ essentially characterizes the likelihood probability of the observed data vector y given the association mapping matrix $\mathit{\Theta }$ and the vector x to be estimated, satisfying $G_i\left(\mathbf{x}\right)\propto p\left(y_i\mid \mathbf{x},\mathit{\Theta }\right)$. UPGC essentially aims to maximize a posterior probability, i.e., $p\left(x_i\mid \mathbf{y},\mathit{\Theta }\right)={\sum }_{\mathbf{x}\backslash x_i}p\left(\mathbf{x}\mid \mathbf{y},\mathit{\Theta }\right)$,and the estimated variable is obtained by ${\widehat{x}}_i={\text{arg}\max }_{x_i\in \mathcal{M}}p\left(x_i\mid \mathbf{y},\mathit{\Theta }\right)$. The applicability boundary of Eqs. (2)–(3) and the concrete mappings of representative tasks to the unified formulation are further discussed in Supplementary Note 2 and Supplementary Fig. 11.

The core of memristor-based UPGC lies in the iterative belief updating and propagation between variable nodes and check nodes. The operations, as defined in Eqs. (2) and (3), occur in two coupled phases per iteration: (1) Posterior Propagation (Backward Propagation): Each check node $C_i$ computes posterior messages ${\beta }_{ij}$ using prior messages ${\alpha }_{ji}$ from neighboring variable nodes and broadcasts the results to connected variables. (2) Prior Propagation (Forward Propagation): Each variable node $\left\{V_1,V_2,\dots ,V_J\right\}$ updates prior messages ${\alpha }_{ji}$ using posteriors ${\beta }_{ij}$ from adjacent check nodes and propagates the updates to all linked check nodes. Supplementary Figs. 3-5 illustrate the temporal dataflow and parallel computation patterns.

The UPGC is hardware-accelerated through analog implementation on memristor arrays, significantly reducing power consumption while enhancing computational speed, as shown in Fig. 3b. Specifically, the K messages from the check node $C_i$ to the variable node $V_j$ are reformulated as VMM operations, as follows:

$${\mathit{\beta }}_{ij}^{\mathrm{T}}={\mathbf{p}}_{ij}^{\mathrm{T}}{\mathbf{G}}_i,$$ 4

where

$${\mathit{\beta }}_{ij}^T=\left[{\beta }_{ij}\left(u_1\right){\beta }_{ij}\left(u_2\right)\cdots {\beta }_{ij}\left(u_K\right)\right],$$ 5

$${\mathbf{p}}_{ij}^{\mathrm{T}}=\left[p\left({\mathbf{x}}_1\right)p\left({\mathbf{x}}_2\right)\cdots p\left({\mathbf{x}}_N\right)\right],$$ 6

$${\mathbf{G}}_i=\left[\begin{array}{cccc}\hfill G_i\left({\mathbf{x}}_{1,1}\right)\hfill & \hfill G_i\left({\mathbf{x}}_{1,2}\right)\hfill & \hfill \cdots \hfill & \hfill G_i\left({\mathbf{x}}_{1,K}\right)\hfill \\ \hfill G_i\left({\mathbf{x}}_{2,1}\right)\hfill & \hfill G_i\left({\mathbf{x}}_{2,2}\right)\hfill & \hfill \cdots \hfill & \hfill G_i\left({\mathbf{x}}_{2,K}\right)\hfill \\ \hfill ⋮\hfill & \hfill ⋮\hfill & \hfill \ddots \hfill & \hfill ⋮\hfill \\ \hfill G_i\left({\mathbf{x}}_{N,1}\right)\hfill & \hfill G_i\left({\mathbf{x}}_{N,2}\right)\hfill & \hfill \cdots \hfill & \hfill G_i\left({\mathbf{x}}_{N,K}\right)\hfill \end{array}\right].$$ 7

Here, ${\mathbf{x}}_{n,k}$ denotes the nth element of ${\Omega }_k^{ij}$, and N denotes the total number of elements in ${\Omega }_k^{ij}$. The corresponding neighboring-variable combination excluding $x_j$ is denoted by ${\mathbf{x}}_n={\mathbf{x}}_{n,k}/x_j$. For a fixed n, different values of k correspond to different states assigned to $x_j$, while the neighboring-variable combination ${\mathbf{x}}_n$ remains unchanged. Accordingly, ${\mathit{\beta }}_{ij}^{\mathrm{T}}\in {\mathbb{R}}^{1\times K}$, ${\mathbf{p}}_{ij}^{\mathrm{T}}\in {\mathbb{R}}^{1\times N}$, and ${\mathbf{G}}_i\in {\mathbb{R}}^{N\times K}$. The terms $p\left({\mathbf{x}}_n\right)=P\left({\left\{{\alpha }_{li}\left(x_l\right)\right\}}_{x_l={\mathbf{x}}_n\left(l\right)}\right)$ are obtained from the incoming messages passed from the neighboring variable nodes to check node i, while the dynamically configurable memristor function $G_i\left(\cdot \right)$ is physically encoded in the conductance values of the RRAM crossbar. The specific mapping strategy depends on the temporal characteristics of the association matrix $\mathit{\Theta }$. For applications defined by time-invariant constraints (e.g., LDPC decoding), the values are directly mapped onto the array and remain constant during operation. However, for tasks involving time-varying channel state information (e.g., MIMO detection), direct mapping is impractical due to the conflict between rapid channel variations and the device’s write endurance. To address this, we introduce a static quantization mechanism where the interaction term involving the time-varying channel is treated as a unified Gaussian variable. Further clarification of the approximation object and its effect on message distributions is given in Supplementary Note 3~4 and Supplementary Fig. 12~13. The memristor array is configured to store the static quantization levels of this distribution, while the dynamic channel variations are handled via digital row selection logic at the input interface (see Supplementary Note 5 for details). A direct comparison between the proposed static mapping strategy and conventional dynamic remapping is further provided in Supplementary Fig. 14. This design ensures that the conductance weights remain static even under dynamic channel conditions, effectively bypassing the endurance constraint. When voltage signals proportional to ${\mathbf{V}}_{\mathrm{P}}$ are applied to the array rows, output currents on columns execute weighted summation according to Kirchhoff’s current law. This method eliminates power-hungry register accesses inherent in iterative digital processing and avoids complex calculations associated with digital implementations. For arbitrary-scale computations, the memristor-based UPGC framework achieves O(1) complexity per iteration via single-step analog operations—a significant reduction from traditional O(N) digital implementations. A more explicit comparison between the conventional digital dataflow and the proposed memristor-based in-memory dataflow is further provided in Supplementary Fig. 15. Additionally, programming distinct conductance values in memristors allows for the processing of a variety of applications, including but not limited to MIMO detection, channel decoding, channel estimation, multi-user identification, and others.

Sparse optimization of probabilistic graphical computing

Figure 4a shows constellation sets of transmitted symbols under typical communication scenarios with modulation orders K∈{4,8,16,64}. Figure 4b illustrates the normalized probabilities versus Euclidean distances (EDs) between the candidate vector set (composed of all possible combinations of variable node states) and the observed vector. It can be seen that the probability distribution of the candidate vectors is sparse, mainly concentrated in smaller-ED annular regions. As a result, the memristor-based UPGC circuit selectively updates only high-probability candidate vectors with smaller EDs from the observed vector and removes low-probability candidates, thereby further reducing power consumption.

Fig. 4. Sparse optimization in probabilistic graphical computing circuit based on memristors.

a Hidden variable node state examples. These correspond to four modulation schemes commonly used in communication signal transmission: quadrature phase shift keying (QPSK), 8-phase shift keying (PSK), 16-quadrature amplitude modulation (QAM), and 64-QAM. b Normalized probability distribution versus Euclidean distance ED for information symbol sets (I = J = K = 4). Each point represents the normalized probability of a symbol vector. c Architecture comparison of sparse optimization and non-sparse optimization. The top panel depicts the message passing and fully activated crossbar structure of the probabilistic graphical computing without sparse optimization; The bottom panel depicts the message passing and partially activated crossbar structure of the probabilistic graphical computing with sparse optimization. d Corresponding hardware workflow illustrating the operational mechanism and effectiveness of the pruning module. e Complexity-performance tradeoff under varying sparsity parameters (D, W, Z). Annotations show sparsity ratios (‰), with performance gaps measured against maximum-likelihood bounds.

In the baseline implementation without sparsity optimization, the messages propagated among check nodes and variable nodes contain all possible combinations of the variable node states. This requires activating all row voltages for RRAM array inputs and reading all column currents, as illustrated in Fig. 4c. With sparsity optimization, memristor-based UPGC prunes the messages passed among nodes to reduce the computational scale and optimizes the dataflow of message passing. From a hardware perspective, it enables dynamic activation of RRAM array row inputs and selective column reads, minimizing power consumption. The core optimization principle lies in eliminating low-contribution states in the variable node state space, where these states have a negligible impact on the probabilistic calculation due to their low probabilities. This sparsity scheme operates bidirectionally: (1) For check-to-variable node messaging, each check node transmits only the D highest-probability states from the variable nodes, reducing message volume from the full state space K to a smaller D. This reduces the message passing scale from ${\mathit{\beta }}_{ij}=\left\{{\beta }_{ij}\left(1\right),{\beta }_{ij}\left(2\right),\dots ,{\beta }_{ij}\left(K\right)\right\}$ to ${\mathit{\beta }}_{ij}=\left\{{\tilde{\beta }}_{ij}\left(1\right),{\tilde{\beta }}_{ij}\left(2\right),\dots ,{\tilde{\beta }}_{ij}\left(D\right)\right\}$, where ${\tilde{\beta }}_{ij}$ represents the messages corresponding to the D largest states in ${\mathit{\beta }}_{ij}$. (2) For the messages from variable nodes to check nodes, Z variable nodes are selected, and their values are fixed to the states with the highest probabilities. For the remaining nodes, only those messages corresponding to the W most probable states in their state set are propagated. This operation is analogous to activating only a subset of the voltage inputs in a memristor array.

The hardware system architecture for UPGC, based on sparsity optimization, is shown in Fig. 4d. First, we feed the input prior knowledge into the pruning module, which identifies the most probable candidate states and constructs a reduced set of potential states. This refined set is then passed to the computational iteration module to generate the final results. Importantly, both the pruning module and the downstream computational module can be implemented in a pipelined architecture, minimizing idle time and reducing overall system latency.

Figure 4e demonstrates the bit error rate (BER) performance of the proposed sparsity optimization scheme across various parameter configurations (D, W, Z). Through this sparsity-aware approach, near-lossless inference performance, close to the approximate maximum-likelihood benchmark, can be achieved when the sparsity ratio is below 1.5‰, with a bit error rate loss of less than 0.5 dB compared to the performance bound. More details on the impact of parameter selection on performance are provided in Supplementary Note 6. The adaptive selection of sparsity parameters under different SNR conditions and system settings is further illustrated in Supplementary Fig. 16 and discussed in Supplementary Note 7. Compared to minimum mean square error (MMSE)⁵⁷ and interference cancellation (IC) detectors⁵⁷, the proposed method demonstrates clear advantages in terms of both performance and complexity trade-offs. These results validate that the proposed method offers greater flexibility, supporting on-demand adjustments between performance and complexity in order to accommodate various application requirements.

Signal detection and channel decoding demonstrations

To more clearly highlight the advantages of the proposed architecture in terms of low-power deployment and reconfigurability, we implemented and evaluated it in two key communication scenarios: MIMO detection and LDPC decoding. The results are summarized in Fig. 5.

Fig. 5. Implementation demo of MIMO system and LDPC decoding.

a System diagram of our work. Scale bar in the 1T1R device micrograph, 1 μm. b Diagram introducing the concepts of LDPC Decoding and MIMO. c Flowchart for LDPC Decoding and MIMO. d Effectiveness of hardware deployment-oriented optimization, such as fixed-point and data flow reduction. This demonstrates the robustness of our method to variations in numerical precision. The power consumption results are normalized using actual FPGA measurement data. e The resistance states that need to be configured in the RRAM arrays for LDPC Decoding and MIMO, respectively. f Energy efficiency comparison between the proposed method and other works in MIMO scenarios. g Energy efficiency comparison between the proposed method and other works in LDPC scenarios. h Performance of our method in MIMO systems. The error bars indicate the standard deviation of the error rates across these 10 batches, reflecting the statistical fluctuation of the results. The left panel shows ~1–2 dB gains over zero-forcing ZF and minimum mean-square error MMSE detection. The right panel shows a higher gain with lower H ($\mathbf{H}=\mathit{\Theta }$) matrix precision, demonstrating the ability to compensate for quantization-induced errors. i Low-density parity-check LDPC decoding performance. Left panel: The proposed architecture (both full-precision and fixed memristor versions) achieves near-optimal performance, closely matching the log-domain sum-product algorithm Log-SPA and belief-propagation BP algorithms with negligible loss, and significantly outperforms the bit flipping algorithm by over 5 dB. Right panel: Performance versus the number of iterations. Lines of different colors correspond to different signal-to-noise ratios, showing a reduction in bit error rate with more iterations.

Figure 5a shows the overall experimental setup of our work. The RRAM array uses a standard 1T1R (one transistor–one resistor) architecture, as illustrated in the microscope image. This architecture ensures device reliability and facilitates high integration density, making it suitable for large-scale deployment in hardware systems. The detailed fabrication process is described in the Methods. The digital component of our system is implemented in FPGA and validated through a hardware-in-the-loop (HIL) system. For the performance evaluation, the communication link is emulated using a standard independent and identically distributed (i.i.d.) Rayleigh fading channel model⁵⁸. Additional validation under more representative channel conditions is further provided, including spatially correlated Rayleigh fading and Rician fading in Supplementary Fig. 17 and the 3GPP time-varying channel in Supplementary Fig. 18. The HIL system and detailed workflow are shown in Supplementary Fig. 19 and 20, respectively.

Figure 5b provides an overview of two target applications, MIMO detection and LDPC decoding, highlighting their distinct roles in modern wireless communication systems. MIMO detection focuses on recovering transmitted symbols from multi-antenna mixed signals with channel interference, while LDPC decoding is primarily used for error correction of transmitted bits at the receiver. Despite their functional differences, both applications can be unified within a common probabilistic graphical computing framework based on memristors, enabling efficient hardware resource sharing. This architectural unification is further explained in Fig. 5c, which presents the computing flowcharts for both applications. These diagrams show how the message-passing mechanism operates within the same computational architecture, achieving flexible reconfiguration across different communication applications.

The resilience of our method to quantization distortion supports its deployment on low-precision hardware. The statistical structure of the weight distribution in our probabilistic graphical model is shown in Supplementary Fig. 21. As shown in Fig. 5d, this work demonstrates robustness against fixed-point quantization and dataflow simplifications, both of which are essential optimizations for reducing hardware complexity and power consumption. Notably, even with aggressive bit-width reduction, the proposed method maintains high accuracy, proving its suitability for edge deployment. Power consumption metrics are normalized based on actual FPGA measurements, offering a realistic assessment of energy efficiency improvements achieved through these optimizations. The detailed schematic flowchart and theoretical derivation of edge deployment optimization are shown in Supplementary Fig. 22 and 23.

As previously mentioned, RRAM devices store application-specific coefficient matrices. In the LDPC scenario, the weight values stored in memristors require no additional operations and are inherently 1-bit in nature. For the MIMO scenario, the specific statistical distribution of the weight values themselves inspired us to develop a corresponding weight compression method, which reduces the storage and computation requirements while incurring minimal performance loss. Benefiting from the aforementioned properties, we can use a single binarized memristor to store each weight value. This not only simplifies the computation process but also leverages the greater technological maturity and robustness of binarized memristors. By combining the dataflow staticization technique with the fixed-point optimization discussed earlier, we successfully map the MIMO and LDPC coefficient matrices onto a 128 × 128 RRAM crossbar. Figure 5e provides a visual comparison of the RRAM resistance patterns for these two applications.

We finally validate our optimized workflow through FPGA-based HIL testing. The design is further synthesized with a 65 nm standard cell library to obtain the final power consumption results. The resulting energy efficiency comparisons are summarized in Figure 5f^{6,14,17,19,59–62} and Fig. 5g^7,19,63–66. These results demonstrate the potential of deploying our work on low-power hardware systems. More detailed power consumption information can be found in Supplementary Fig. 24 and 25, Supplementary Tables 1 and 2. We also provide area-efficiency data for a more comprehensive comparison, as shown in Supplementary Fig. 26 and 27.

Fig. 5h^32,67–69 shows the performance comparison of MIMO detection methods. The performance of MIMO detectors is evaluated using the bit error rate (BER) versus the signal-to-noise ratio (SNR) curves. It is evident that combining MMSE detection with the proposed architecture results in a ~2 dB gain over the MMSE-only baseline, demonstrating better anti-noise performance. Importantly, this performance advantage becomes more significant as the precision of the channel matrix $\Theta$ decreases, demonstrating the robustness of our approach in mitigating quantization errors.

Figure 5i provides a comprehensive comparison of LDPC decoding performance. The blue and green lines indicate the nearly optimal performance bound, while the orange line represents full-precision simulation results. The yellow line shows the performance with the incorporation of memristor non-idealities and fixed-point quantization. The performance loss of the lightweight fixed-point version relative to the nearly optimal performance bound is within 0.5 dB, suggesting minimal degradation due to hardware non-idealities. The right panel shows the convergence behavior of our approach by plotting the BER versus the number of iterations. As expected, the BER decreases significantly as the number of iterations increases, validating the effectiveness and stability of the iterative message-passing mechanism. See Supplementary Note 8 for a detailed discussion of the simulation results. The practical positioning of the reported throughput and its relevance to representative energy-constrained edge-terminal scenarios are further discussed in Supplementary Note 9.

Discussion

In summary, we have presented a unified probabilistic graphical computing driven baseband signal processing architecture that unifies Bayesian inference-based signal processing algorithms within a single reconfigurable and energy-efficient hardware framework based on memristors. By leveraging the intrinsic advantages of memristor-based in-memory computing, our approach addresses the long-standing bottlenecks of data movement and dynamic operation overhead in conventional digital architectures, achieving sub–10 pJ per bit energy consumption and significantly enhanced noise robustness. The proposed architecture has been validated by large-scale fabricated memristor arrays, confirming its feasibility under realistic device non-idealities and its applicability to diverse signal processing applications, including MIMO detection and LDPC decoding. These results highlight the potential of integrating probabilistic graphical computing with emerging memory technologies to meet the requirements of edge devices, such as ultra-low power, flexibility, and reliability. Looking ahead, the unified and reconfigurable nature of our work paves the way for the broader adoption of memristor-based accelerators in heterogeneous edge computing platforms, extending their impact beyond communications to other data-intensive, inference-driven applications.

Methods

Device fabrication

The designed 1T1R structure was fabricated as follows: First, lithography and electron-beam evaporation Ti/Pd with 2 nm/35 nm thickness was selected as the back gate metal. After that, the 10 nm-thick HfO₂ layer acted as the gate dielectric; this layer was deposited via ALD at 200 °C using the PICOSUN R200 Advanced system with TDMA-Hf and H₂O. Subsequently, AZ601 photoresist was spin-coated, and through-hole etching of the oxide was performed in the ULVAC NE550H system with Cl₂ to expose the underlying metal. Then, MOCVD-grown MoS₂ on sapphire was wet-transferred: PMMA was spin-coated at 1500 rpm, baked at 180 °C for 2 min, the stack was released in deionized water, transferred to the target substrate, dried, and the PMMA was removed in acetone. MoS₂ was patterned by O₂ plasma etching (150 W, 150 sccm, 8 min). Contact metal Ti/Pd (5 nm/35 nm) was deposited by electron-beam evaporation. Next, a 50 nm SiO₂ interlayer was grown by ICP-PECVD at 130 °C; via holes were etched with F₂ in the NE550H. A 5 nm HfO₂ resistive switching layer was then deposited by ALD at 200 °C. Finally, the 40 nm TiN top electrode was deposited by magnetron sputtering.

Author contributions

C.J., J.W. and Z.P. contributed equally to this work. C.J. and J.W. conceived the idea and initiated the project. J.W. and Z.P. performed the simulations and experiments. Y.L. and Y.H. provided part of the experimental data and comments on the manuscript. H.T., L.K. and J.L. supervised the project. All authors discussed the results and commented on the manuscript.

Peer review

Peer review information

Nature Communications thanks the anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

This work was supported by the National Natural Science Foundation of China under Grant 62325108.

Data availability

The source data generated in this study are provided in the Source Data file. Additional data related to this paper can be requested from the authors. Source data are provided with this paper.

Code availability

The core RTL codes of this work are available online at https://doi.org/10.5281/zenodo.21833844.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-77169-w.