Wafer-scale synthesis of WSe₂ for high-performance p-type top-gated transistors and logic circuits

Abstract

Two-dimensional (2D) transition metal dichalcogenides (TMDs) offer a promising pathway for next-generation electronics due to their exceptional electrical characteristics at atomically thin thickness. Nevertheless, the realization of high-quality p-type 2D-FETs remains a significant challenge for CMOS device integration due to surface damage and unintended n-doping induced during dielectric deposition. In this work, we report the wafer-scale synthesis of p-type WSe₂ films using metal-organic chemical vapor deposition and the fabrication of top-gate p-FETs through a buffer layer strategy, which provides superior electrostatic control and channel stability. The transistors exhibit excellent p-type performance, achieving a hole mobility of 10.49 ± 2.35 cm²V⁻¹ s⁻¹ with on/off current ratio exceeding 10⁹. By leveraging the process’s scalability, which ensures uniform and damage-free fabrication, we successfully produced reliable wafer-scale PMOS logic circuits. This study provides a scalable, damage-free integration solution for 2D electronics, paving the way for the practical realization of all 2D-based high-density electronics and circuits.

INTRODUCTION

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as compelling alternatives to conventional bulk semiconductors, owing to their exceptional electrical and optical properties, mechanical flexibility, and relatively low synthesis temperatures (1–6). A key advantage of these materials is the preservation of their electronic integrity at sub-nanometer thicknesses, which offers a distinct scaling advantage over conventional bulk semiconductors for the fabrication of ultra-high-density integrated circuits. Early fundamental studies primarily utilized micron-sized TMD flakes obtained via mechanical exfoliation or small-scale chemical vapor deposition (CVD) technique (7–10). However, translating these unique properties of TMDs into practical technology requires large-area films with electrical and structural uniformity.

Recent advances in metal-organic chemical vapor deposition (MOCVD) have enabled the synthesis of 2D TMD films up to the scale of as high as 100 mm wafers (11). This breakthrough has sparked extensive research into various scalable synthesis methods, including CVD, MOCVD, and single-crystalline epitaxial growth, to enable the integration of 2D TMDs into practical electronic devices (12–15). The sulfur-based TMD films synthesized via CVD and MOCVD are among the most widely studied 2D materials. However, these films typically exhibit n-type behavior due to inherent sulfur vacancies and are therefore mainly used in developing n-channel of FETs and n-type metal-oxide-semiconductor (NMOS) devices (5, 11, 12, 16). Achieving high-performance p-type metal-oxide-semiconductor (PMOS) devices is essential to realizing complementary metal-oxide-semiconductor (CMOS) logic circuits with performance comparable to their n-type (NMOS) counterparts. While n-type 2D TMDs have reached significant technical maturity, offering high carrier mobility, scalability, and uniformity, developing p-type TMDs with reliable semiconducting characteristics remains a major challenge (17, 18).

Selenium- and tellurium-based 2D TMDs, such as WSe₂ and MoTe₂, typically exhibit intrinsic p-type characteristics due to their unique point-defect profiles (19–21). However, their synthesis technology remains significantly less mature than that of their n-type counterparts. Furthermore, the fabrication of 2D PMOS devices is hindered by poor interfaces between the gate oxide and the TMD channel. Conventional high-k dielectrics (HfO₂, ZrO₂, and Al₂O₃) often induce unintentional n-type doping via oxygen-vacancy-mediated surface charge transfer (22–24). This process also introduces additional defects that degrade the electrical performance of the underlying p-type channel. Consequently, the 2D TMD based PMOS fabrication typically utilizes back-gate (BG) structures to bypass the dielectric deposition induced n-doping and defect creation which inherently occurred in top-gated device fabricated using atomic layer deposition (ALD) process, which is commonly employed in developing standard metal-oxide-semiconductor (MOS) architectures (25–29). From an application perspective, the top-gate (TG) structure is desirable as it enables individual transistor addressability with reduced parasitic capacitance, which is critical in attaining high-speed operations in complex CMOS logic arrays (17). Furthermore, for monolithic 3-dimensional (M3D) integration, direct oxide deposition is necessary for both gate- and insulating interlayer-dielectrics (ILD) (18). Therefore, it is vital to develop strategies that simultaneously suppress ALD-induced n-doping and enable stable oxide deposition on p-type 2D channels. Addressing these dielectric integration challenges, alongside the scalable production of p-type materials, is essential for realizing high-performance 2D p-MOSFET suitable for practical semiconductor systems.

In this work, we report the wafer-scale synthesis of p-type 2D WSe₂ with high spatial uniformity and precise thickness control on amorphous SiO₂ substrates using the MOCVD technique. To address the undesirable n-doping issue during dielectric deposition, we fabricated WSe₂-based TG FETs over large area with high hole mobility by inserting a wafer scale WO_X buffer layer between the WSe₂ channel and ALD grown high-k gate oxide. The transferred wafer scale WO_X buffer layer forms a clean van der Waals (vdW) interface with the underlying WSe₂ channel, preventing chemical and physical damage during oxide deposition. By suppressing n-doping and inducing p-type carrier enrichment, the WO_X buffer layer enabled TG FETs exhibit hole mobility of 10.49 ± 2.35 with maximum value of 15.63 cm² V⁻¹ s⁻¹ accompanied by high on/off ratio of 10⁹. By using this device architecture, we successfully demonstrated a wafer-scale device array consisting of not only FET array but also PMOS logic circuits with reliable operation.

RESULTS

Wafer-scale growth of WSe₂ on Si/SiO₂ wafer

To synthesize the wafer-scale WSe₂ with high spatial uniformity and reliability, we adopted a MOCVD method utilizing all-vapor-phase precursors (Fig. 1A). All the precursors including tungsten hexacarbonyl (THC) and dimethyl selenide (DMSe) are injected into the chamber through the bubbler with the help of Ar/H₂ carrier gas and the flow rate was precisely regulated by mass flow controller (MFC). A NaCl plate is positioned upstream of the growth substrate to promote grain enlargement of WSe₂ (30, 31). Optical image of WSe₂ grown on 50 mm amorphous Si/SiO₂ wafer demonstrates complete wafer-scale coverage, validating our MOCVD approach for large-area film synthesis (Fig. 1B).

Fig. 1. Wafer-scale synthesis of highly uniform WSe₂ films via MOCVD.

(A) Schematic representation of the used MOCVD system. (B) Optical image of the WSe₂ film grown on a 2-inch Si/SiO₂ wafer. (C) Schematic illustration of the MOCVD growth mechanism utilizing organic precursors with H₂O co-injection. The H₂O effectively etches amorphous carbon, facilitating the lateral growth of WSe₂ grain. (D) Raman intensity mapping images of monolayer (1L-) and bilayer (2L-) WSe₂ films. (E) Raman and (F) PL spectra recorded from multiple positions across the wafer-scale 1L- and 2L-WSe₂ films. Inset in Fig. 1E represents the magnified view of the spectra recorded within the range of 280 to 340 cm⁻¹ showing the B_2g peaks.

The unintended incorporation of amorphous carbon (a-C) remains a primary obstacle in the MOCVD synthesis of high-quality, semiconducting TMD films, specifically WSe₂. During synthesis, a-C modulates the surface energy of growth sites, which suppresses the lateral growth rate and prevents grain coalescence (32, 33). This issue is particularly pronounced when using organic chalcogen precursors because their decomposition yields methyl radicals (-CH₃), which are well-known precursors for graphene and carbon growth. Consequently, the synthesized TMD films are usually contaminated with a-C and exhibit high surface roughness and undesirable semi-metallic behavior (figs. S1A and S2D). While inorganic hydride precursors (such as H₂Se) can eliminate carbon contamination, their extreme toxicity and volatility pose significant operational hazards and require stringent safety protocols (34–36). To bypass these safety risks while simultaneously mitigating a-C formation, we adopted a dual-strategy approach: (i) use of organic precursor, DMSe (ii) suppressing the carbon deposition and etching the residual carbon during MOCVD process. Herein we first adopted the decrease in the growth temperature to suppress carbon deposition, which inhibits the reactivity of methyl groups (-CH₃) (5, 33). Secondly, the flow rate of THC was optimized, since THC can serve as a catalyst for DMSe decomposition which can directly increase the a-C deposition rate (37). Finally, to etch the deposited carbon species, H₂O co-injection was conducted accompanied by the optimization of H₂ flow rate, which is a widely used a-C reducing method (33).

The Raman spectra recorded in the range of 1000–2000 cm⁻¹ exhibit no detectable D band (at 1350 cm⁻¹) or G band (at 1580 cm⁻¹) peaks (figs. S1 and S2). To directly confirm this purity, x-ray photoelectron spectroscopy (XPS) was performed. The deconvoluted C 1 s core-level spectra reveal a markedly reduced W-C peak intensity in the optimized sample grown without a-C relative to the sample grown with a-C (fig. S3). Together, these vibrational and chemical state analyses confirm that the optimized growth conditions effectively suppress carbon incorporation, yielding WSe₂ films with negligible carbon contamination. Furthermore, the co-injection of H₂O not only eliminated the a-C impurities, but also significantly enlarged the grain size of WSe₂. While the average grain size of WSe₂ grown without H₂O was limited to approximately 200 nm, the optimized H₂O flow yielded grains as large as 1.35 μm, a six-fold increase compared to the control group (fig. S4, A and B). This grain enlargement is driven by two etching effects of H₂O (Supplementary Text S1). First, the removal of a-C facilitated the lateral growth of WSe₂ domains. Second, as H₂O etches WSe₂ as well as carbon, tiny WSe₂ nuclei rarely survive (38). This leads to an increased critical radius of WSe₂, thereby the nucleation density was reduced and the average grain size was increased (39–41). However, excessive H₂O flow is detrimental, as it induces significant oxidation of the WSe₂ film that suppresses lateral growth, as confirmed by XPS characterization (fig. S5). Under optimized H₂O flow, nucleation is selectively suppressed and oxidation-induced degradation is minimized, promoting lateral expansion of triangular domains that progressively coalesce into a continuous monolayer film, as confirmed by time-dependent AFM images (fig. S6). The resulting wafer-scale WSe₂ film exhibits larger grain sizes than those achieved with organic chalcogen precursors, on both amorphous and epitaxial substrates. This achievement is particularly significant as the synthesis was performed at moderate growth temperature (∼580°C) on an amorphous substrate, whereas previous reports typically require epitaxial substrates and higher growth temperatures (fig. S4F).

Raman intensity mapping data confirms that our MOCVD process can synthesize both wafer-scale monolayer (1L) and bilayer (2L) WSe₂ films with high uniformity and precise thickness control (Fig. 1D). The spatial uniformity of NaCl vapor delivery, confirmed by computational fluid dynamics (CFD) simulation (fig. S7), contributes to this wafer-scale homogeneity, as further supported by statistical analysis of Raman and PL spectra collected across the 2-inch wafer showing narrow standard deviations (fig. S8). All the Raman spectra are normalized with silicon peak (520.7 cm⁻¹) to systematically analyze the intensity and peak position (Fig. 1E). The overlapping E and A peaks of 1L- and 2L-WSe₂ are located at 250.5 cm⁻¹, 250.4 cm⁻¹, respectively, while the 2LA(M) peaks appear at 264.02 cm⁻¹, 265.62 cm⁻¹, respectively. Additionally, the magnified Raman spectra in the inset of Fig. 1E exhibit the absence and presence of B_2g peak (∼ 310 cm⁻¹) for 1L- and 2L-WSe₂, respectively, indicating the thickness of WSe₂ was precisely controlled at the mono- and bilayer scale (42). PL spectroscopy confirms the high crystallinity of synthesized WSe₂ films as depicted in Fig. 1F. The 1L-WSe₂ exhibits a PL peak at 1.63 eV, which corresponds to a slightly larger optical bandgap and higher emission intensity compared to 2L-WSe₂ (1.62 eV). Sharp PL spectra were observed for both 1L- and 2L-WSe₂ with full-width half-maximum (FWHM) of 85.7 meV and 93.6 meV, respectively, which are comparable to the WSe₂ films epitaxially grown at high temperature and using inorganic chalcogen precursor (13, 25).

WO_X buffer layer

In general, the use of an appropriate ultrathin buffer layer between the 2D channel and gate dielectric circumvents unwanted doping and surface defects that typically arise during dielectric deposition, such as ALD, which is necessary for the fabrication of the TG devices (43, 44). In the fabrication of WSe₂ based TG FETs, we utilized WO_X as an effective buffer layer to mitigate the unintentional n-doping in WSe₂ channels during Al₂O₃ deposition by ALD process. This doping typically arises from process-induced damage and surface charge transfer doping (SCTD) caused by sub-stoichiometric oxides (22–24). Furthermore, WO_X layer can effectively accept the electrons from the underlying WSe₂ that can effectively increase the hole concentration in the channel (45, 46). Although WO_X can be formed by directly oxidizing the surface of a multilayer WSe₂ film, this approach lacks the precision required for selective and uniform oxidation over large areas, particularly in polycrystalline MOCVD-grown films, which inherently contain localized adlayers. To overcome this limitation, we employed a transfer-based strategy for reproducible, well-controlled WO_X buffer formation at wafer scale. A wafer-scale monolayer WSe₂ film grown by MOCVD is first converted into WO_X via controlled UV-ozone (UVO) oxidation (Fig. 2, A to C), then transferred onto the target WSe₂ channel (Fig. 2D). This approach ensures a pristine interface and precise buffer layer thickness control, effectively shielding the channel from external doping.

Fig. 2. Preparation of the WO_X buffer layer.

(A) Photograph of the transfer of wafer-scale WSe₂ film using thermal release tape. (B) Photograph of the wafer-scale peeled-off WSe₂ film on thermal release tape and (C) Photograph of fully oxidized WSe₂ film obtained after optimized UVO treatment. The transparent nature of the oxidized film can be clearly noticed, signifying the complete conversion of WSe₂ to WO_X. (D) Schematic representation of WO_X/WSe₂ heterostructure formation process and protection of the WSe₂ channel by utilizing transferred WO_X buffer layer during oxide deposition using ALD technique. (E) Optical image of the prepared WO_X/WSe₂ heterostructure on Si/SiO₂ wafer using transfer and stacking approach. (F) Cross-TEM image of fully integrated top-gate FET stack (WSe₂/WO_X/Al₂O₃). (G) High-resolution TEM image (top) and corresponding EDS elemental maps (bottom) of the interface region showing clean vdW gap between WSe₂ channel and gate dielectric. (H) Raman spectra of pristine WSe₂, ALD-exposed WSe₂, WO_X/WSe₂ heterostructure, and WSe₂/WO_X/Al₂O₃ stack. XPS spectra of the (I) W 4f and (J) Se 3d core level peaks obtained for pristine WSe₂, WO_X, and WSe₂/WO_X heterostructure.

XPS and Raman spectra confirm the progressive conversion of WSe₂ to WO_X with increasing UVO treatment duration (figs. S9 and S10). Complete conversion at 60 min is evidenced by disappearance of the Raman peak (fig. S10C), insulating behavior across the full gate voltage range (fig. S10B), and near-zero WSe₂-to-WO_X peak area ratio (fig. S9C). Notably, conductivity evolves through three distinct phases: short-term UVO preferentially oxidizes point defects and grain boundaries, forming an in-plane WSe₂/WO_X heterostructure (47); prolonged oxidation yields sub-stoichiometric WO_X approaching WO₂ composition with degenerate semiconductor behavior (45, 48); and at 60 min, a fully insulating WO_X layer (WO₃-like phase, x ≈ 3) is obtained. Thus, the term WO_X specifically refers to this fully oxidized WO₃-like phase, not the transient sub-stoichiometric intermediates, and the WO_X buffer layer integrated into all FET devices exclusively represents this fully insulating phase (Supplementary Text S3). This buffer layer has two major effects; (i) passivating the WSe₂ channel from direct exposure to the ALD process, (ii) p-doping the WSe₂ channel through SCTD mechanism. The wafer-scale WO_X buffer layer transferred onto the underlying WSe₂ channel serves as an interfacial layer, forming a vdW gap at the interface between underlying channel that preserve the intrinsic properties of underlying WSe₂ and protect it from the ALD-induced damage (Fig. 2D).

To verify the role of WO_X film as protective buffer layer, we conducted cross-sectional transmission electron microscopy (TEM) analysis on the WSe₂ channel / WO_X buffer layer / Al₂O₃ gate oxide stack (Fig. 2, F and G). A 1.49 nm of 2L-WSe₂ channel and 1.5 nm of WO_X buffer were identified by the TEM image. This observation is consistent with the reported thickness increase of approximately 0.7 nm during the oxidation of monolayer WSe₂ to WO_X, which was further confirmed by the AFM measurements (fig. S11) (45). As shown in the high-resolution TEM image (Fig. 2G), the interface between the ALD-grown Al₂O₃ and the underlying buffer layer appears relatively blurred, indicating that chemical reactions and bonding have occurred, in contrast to the clean vdW interface observed between the channel and the buffer layer. TEM energy-dispersive x-ray spectroscopy (TEM-EDS) mapping visualized two distinct tungsten layers of equal thickness (∼1.5 nm) separated by a clear interface. While the underlying layer, identified as WSe₂, is rich in selenium, the upper layer shows deficiency of selenium content, characteristics of WO_X, confirming a clear boundary between channel and the buffer. An elevated O signal in the WO_X region relative to the WSe₂ channel is further visible in the EDS line profile (fig. S12), consistent with the oxygen-rich nature of the buffer. XPS corroborates the chemical identity of the WO_X buffer, revealing characteristic W 4f peaks alongside attenuated Se signals (Fig. 2, I and J). These TEM observations confirm that the buffer layer effectively protects the underlying channel during the ALD process. Notably, this buffer insertion process exhibits robust reproducibility across wafer-scale areas, as evidenced by the optical image in Fig. 2E, where continuous coverage with minimal defects is achieved (fig. S11D). It demonstrates the practicality of our approach for large-area integration in practical applications.

Beyond its protective effects against ALD-induced damage, we also investigated the effects of the buffer layer on retaining structural integrity and p-doping using Raman and XPS. Raman spectroscopy analysis quantifies the reversal of the ALD process induced n-doping effects when WO_X buffer was inserted between WSe₂/Al₂O₃ interface (Fig. 2H). The WSe₂ film exposed to ALD-grown Al₂O₃ exhibits n-doping effect as a redshift in $E_{2g}^1$ peak to 249.63 cm⁻¹ (∼1.06 cm⁻¹ shift) is observed in comparison to the peak for pristine film at 250.69 cm⁻¹ (25, 49). In contrast, the WSe₂ film passivated with WO_X buffer layer shows a blue shift to 251.73 cm⁻¹ (∼1.04 cm⁻¹ shift), which is a typical characteristic of p-doping (50, 51). Importantly, the fully integrated structure (buffer + ALD) retains a blueshift to 251.53 cm⁻¹ (∼0.84 cm⁻¹ shift), indicating that the p-doping nature is preserved even after ALD process. Although the slight reduction in the blueshift suggests partial charge compensation due to electron transfer from sub-stoichiometric ALD oxide, the effective hole doping by the buffer layer remains dominant.

The XPS spectra of as-grown WSe₂, oxidized WO_X, and WSe₂/WO_X heterostructure recorded for W and Se elements are illustrated in Fig. 2, I and J, respectively. The as-grown WSe₂ exhibits a near-stoichiometric composition with a W:Se atomic ratio of 1:2.01 with distinct peaks of W and Se existing in 2H-WSe₂. After the UVO oxidation, the tungsten and selenium peaks arising due to chemical bonding between W and Se are diminished and replaced by their oxidized species. The appearance of characteristic WO₃ satellite or plasmon loss peaks at 50.95 eV clearly demonstrates the formation of a fully oxidized WO_X buffer layer (Fig. 2J) (26), whose thermodynamically stable WO₃-like phase ensures the absence of semi-metallic characteristics associated with sub-stoichiometric WO_X phases in the final device structure (Supplementary Text S3). Notably, XPS analysis of the WSe₂/WO_X heterostructure reveals significant shifts in the core-level binding energies of the underlying WSe₂ layer compared to pristine WSe₂. The W 4f_7/2 and 4f_5/2 peaks exhibit a pronounced shift of ∼0.19 eV toward lower binding energy side as 31.33 eV and 33.47 eV, respectively, whereas, the Se 3d_5/2, 3d_3/2 peaks shift to 53.63 eV and 54.48 eV (∼0.18 eV shift), respectively. These consistent shifts to lower binding energy across both tungsten and selenium core levels directly indicate the incorporation of p-type doping in WSe₂ film by the overlying WO_X layer through SCTD mechanism (52, 53). This SCTD mechanism is consistent with theoretical predictions and experimental reports, wherein the high work function of WO_X facilitates hole injection into WSe₂ (27, 46, 54).

Statistical analysis of WSe₂ FETs

To demonstrate the use of synthesized WSe₂ film in electronic device applications, we have fabricated p-type TG FET arrays using the transferred WO_X buffer layer. The TG WSe₂ FET arrays over a large area were fabricated by transferring bilayer WSe₂ film from a 50 mm growth substrate onto a substrate pre-patterned with source/drain electrodes. Following channel patterning (channel length, L = 6 μm; channel width, W = 50 μm), the WO_X buffer layer was transferred onto the target substrate. Finally, 25 nm thick Al₂O₃ gate dielectric was deposited via ALD, followed by the formation of Cr/Pd gate electrode (fig. S13). To attain high-performance transistor operation in 2D TMDs based FETs, the selection of appropriate metal electrodes with proper contact engineering is essential. Pd or Pt are commonly employed as contact metals in WSe₂ based PMOS fabrication due to their suitable work function, which offers low contact resistance (28, 55–57). In this work, we also utilized thermally evaporated Cr/Pd (3/30 nm) films as source-drain (S/D) metal contacts which provided improved electrical characteristics. Transistors with Cr/Au contact exhibit ambipolar behavior with lower p-branch current compared to the Pd contact devices, which show distinct p-type characteristics (fig. S14).

The transfer characteristics (I_ds-V_gs at V_ds = −1 V) for 70 randomly selected WSe₂ transistors fabricated with (red line) and without (blue line) WO_X buffer layer are displayed in Fig. 3C. As evident from the I_ds-V_gs plots, the devices with WO_X buffer layer exhibited significantly enhanced performance, showing a drain current approximately three orders of magnitude higher than that of control devices. Statistical analysis further confirms that the improvements in electrical performance can be achieved through buffer layer insertion. As shown in Fig. 3D, the hole mobility of the fabricated FETs increased from an average value of 0.02 ± 0.01 to 10.49 ± 2.35 cm² V⁻¹ s⁻¹ with a maximum value of 15.63 cm² V⁻¹ s⁻¹. The mean value of threshold voltage (V_th) of control and buffer inserted devices is located at −4.91 ± 0.08 V and − 3.80 ± 0.27 V, respectively (Fig. 3E). The observed enhancement in carrier mobility and a positive shift in V_th confirm the effectiveness of the WO_X buffer layer in preventing the unwanted damage and doping occurred during the ALD-based gate oxide deposition in TG FET fabrication (58, 59).

Fig. 3. Electrical performance and statistical analysis of wafer-scale WSe₂ TG FET array.

(A) Optical image of wafer scale fabricated WSe₂ TG FET array on a 2-inch wafer. (B) 3D schematic and corresponding cross-sectional representation of buffer inserted TG FET. (C) Transfer characteristics (I_ds-V_gs) of control and buffer inserted FETs recorded at V_ds = −1 V. (D to G) Statistical histograms of device performances: (D) field-effect hole mobility, (E) threshold voltage (V_th), (F) on/off current ratio (I_on/I_off), and (G) subthreshold swing (SS). (H and I) Dual sweep of transfer characteristics of (H) buffer inserted and (I) control devices, showing hysteresis properties.

To further verify that the performance enhancement reflects genuine improvements in intrinsic channel transport, we examined the contact characteristics and decoupled contact resistance from channel transport. Conformal film coverage across the electrode region was confirmed by AFM and cross-sectional TEM (fig. S15), excluding large-scale delamination as a contributing factor. Transfer length method (TLM) analysis reveals that while buffer insertion significantly reduces R_contact, R_sheet remains substantially higher in the control devices, confirming that improved intrinsic channel transport is the dominant contributor (fig. S16). Carrier density-dependent mobility analysis corroborates this conclusion, with the mobility enhancement persisting across the entire overlapping carrier density range (fig. S17). These results collectively indicate that the performance improvement arises from three synergistic effects of the WO_X buffer: suppression of ALD-induced n-type doping and channel damage, p-type doping via the SCTD mechanism, and consequent lowering of the Schottky barrier height at the metal-semiconductor contact.

Additionally, a significant enhancement in on/off current ratio (from 5.1 × 10⁶ to 2.4 × 10⁹) has also been observed with inserting WO_X buffer layer (Fig. 3F). This enhancement is attributed not only to the increased on-current but also to the maintained low off-state leakage current. As described below, improved interface properties through buffer insertion can enhance the on-current by reducing the interfacial trap charges and surface scattering. Furthermore, as evidenced by Raman and XPS data, the insertion of the buffer layer induces p-doping in the WSe₂ channel via SCTD mechanism, additionally contributing to the increased on-current in buffer inserted device. Besides the increased on-current, it may be noted that the fully oxidized buffer layer exhibits electrically insulating behavior that prevents any additional carrier transport (fig. S10B), thereby maintaining the low off-current in the fabricated TG FETs.

A careful analysis of the observed subthreshold swing (SS) and hysteresis characteristics further confirms the existence of improved interface quality in buffer layer integrated devices. The SS distribution presented in Fig. 3G shows an improvement in SS from 488.40 ± 18.91 mV dec⁻¹ (control) to 140.43 ± 13.67 mV dec⁻¹ (WO_X buffer). Furthermore, hysteresis measurements, defined as ΔV_hys = V_{th, backward} – V_{th, forward}, indicate that V_th shift was suppressed, reducing from −1.88 V in control devices to −0.79 V after buffer insertion (Fig. 3, H and I). It is because the buffer layer can contribute to the improvements of interface properties by mitigating the charge trapping with preserving a clean vdW interface and protecting the channel from ALD induced damage. Previous study has reported that a WO_X interfacial layer between an underlying high-k dielectric and a WSe₂ channel can effectively improve the interface properties by passivating the interface traps (27). Additionally, buffer layers can effectively prevent the dangling bond induced charge trapping. The direct ALD process of high-k dielectrics on 2D TMDs typically increases the interface trap density (D_it), deteriorating device performance, since the dangling bonds of the high-k materials at the interface cannot be passivated due to the vdW surface of 2D TMDs (25). On the other hand, the sub-stoichiometric WO_X buffer provides the bonding sites for the high-k materials, as confirmed in Fig. 2G, that result in reduced D_it with negligible increase of charge trap at interface of buffer and ALD-grown oxide, or fixed oxide charge (Q_f) (figs. S18 and S19). Thereby, the buffer inserted device exhibits a significantly reduced hysteresis and D_it of (2.10 ± 0.35) × 10¹² cm⁻² eV⁻¹, in contrast to the high D_it of (1.11 ± 0.05) × 10¹³ cm⁻² eV⁻¹ observed in the control device. Consequently, the buffer inserted device can demonstrate superior interface properties even with ALD-grown gate oxides because it can effectively suppress trap charge formation.

The buffer inserted transistors fabricated in this work over large area exhibit higher carrier mobility and on/off ratio in comparison to the reported TG FETs fabricated with MOCVD grown WSe₂. Notably, the performance of the MOCVD grown WSe₂ based TG FETs fabricated in this work is comparable to that of the BG FETs reported in previous studies, which are inherently free from ALD-induced damage (Table S1). These results highlight the importance of the transferred ultrathin WO_X buffer layer, that improves device performance through avoiding damage in 2D channel during ALD process together with preserving the p-type characteristics of the MOCVD grown wafer scale WSe₂ films, thereby ensuring highly stable device operation.

WSe₂ PMOS-based logic gates

The integration of logic circuits for functional electronics requires the scalable and high-yield fabrication of multiple FETs over large area. Leveraging the excellent spatial uniformity of the synthesized high quality WSe₂ film over wafer scale area, we developed various PMOS logic circuits. Figure 4A presents optical images of the fabricated PMOS logic circuits, including NOT, NAND, NOR, AND, and OR gates. In the fabricated logic circuits, the depletion-mode transistors were employed for both the load and driver transistors, in which the dimensions of transistors were carefully optimized to achieve a near-zero output low voltage (V_OL). While the channel length was fixed at 6 μm, the channel widths were designed with a distinct asymmetry, 10 μm for the driver and 200 μm for the load. The voltage transfer characteristic (VTC) of the inverter was measured at a supply voltage (V_dd) of 5 V (Fig. 4B and fig. S20). Consequently, the optimized inverter exhibited a peak voltage gain of 7.9 and a switching threshold voltage (V_M) of 4.2 V. Notably, when the input voltage (V_in) is below V_M, the output voltage (V_out) reaches a high voltage approximate to V_dd, and conversely, approaches 0 V at high inputs. Furthermore, the dynamic response measurements confirm the stability of our devices in high operational frequency. Well-defined rectangular output signals were obtained for a square-wave input signal with frequency from 10 Hz to 10 kHz (Fig. 4, C and D and fig. S20). Such stable dynamic operation is attributed to the robust reliability of our devices. The buffer inserted FETs exhibit stable performance over 100 switching cycles, ensuring the stability required for dynamic circuit measurements (fig. S21). Consequently, the performance of our PMOS inverter is comparable to that of 2D TMDs based reported NMOS devices, offering a promising solution to the critical bottleneck in 2D CMOS integration (5).

Fig. 4. PMOS logic circuits based on wafer-scale WSe₂ FETs.

(A) Optical microscope images of PMOS logic circuits including inverter, NAND, NOR, AND, and OR gates. (B) Static voltage transfer characteristics (black line) and voltage gain (red line) of the PMOS inverter measured at supply voltage (V_dd) of 5 V. (C and D) Dynamic switching response of the inverter under square-wave input signal at frequencies of (C) 10 Hz and (D) 1 kHz (V_dd = 5 V). (E) Truth table corresponding to the NAND, NOR, AND, and OR logic gates. (F) Dynamic output characteristics of the NAND, NOR, AND, OR logic gates measured at V_dd = 5 V.

Based on the uniform FETs and inverters demonstration, we extended the circuit to basic PMOS logic gates, specifically NAND, NOR, AND, and OR, by integrating 3, 3, 5, and 5 FETs, respectively. The dynamic output characteristics of these logic gates are presented in Fig. 4F, which is consistent with the corresponding truth table presented in Fig. 4E. The NAND gate exhibits accurate Boolean functionality with distinct logic levels; the output maintains a high state for inputs (0,0), (1,0), and (0,1), switching to a low state only when both inputs are high (1,1). Conversely, the NOR gate demonstrates the expected operation by maintaining a high output exclusively for the (0,0). The AND and OR gates, constructed by connecting an inverter with NAND and NOR respectively, show opposite logic outputs to the NAND and NOR gates, as expected. All logic gates exhibit stable and repeatable output characteristics with clear high and low logic levels that demonstrate proper circuit functionality which confirm the potential of synthesized wafer scale WSe₂ films in developing WO_X buffer inserted TG FETs for functional electronics.

DISCUSSION

In summary, we have demonstrated a scalable approach to address the fundamental challenges of p-type 2D TMD integration. By synthesizing wafer-scale WSe₂ films with high spatial uniformity and developing a robust WO_X buffer layer strategy, we successfully fabricated high-performance TG transistors. The MOCVD-grown WSe₂ films, synthesized using organic precursors, achieved high-quality, carbon-free characteristics with precise control over layer thickness and morphology properties rigorously validated by Raman, PL, and AFM measurements.

The integration of a UV-ozone-oxidized WO_X buffer between the channel and the ALD-grown gate dielectric effectively protected the WSe₂ channel from deposition-induced damage and unintentional n-doping effect. Consequently, the resulting TG transistors exhibit superior electrical characteristics, including a hole mobility of 10.49 ± 2.35 cm² V⁻¹ s⁻¹, an on/off ratio exceeding 10⁹, a subthreshold swing of 140.43 ± 13.67 mV dec⁻¹, and minimal hysteresis (<1 V). Statistical analysis across the wafer confirms the high yield and reproducibility of this fabrication process. Finally, the successful implementation of various PMOS logic gates (NOT, NAND, NOR, AND, and OR) underscores the operational stability and potential of our WSe₂ approach for large-scale, low-power integrated circuits.

MATERIALS AND METHODS

Synthesis of WSe₂ and WO_X buffer layer

The mono- and bi-layer WSe₂ films over wafer scale were synthesized using a customized hot-wall MOCVD system. Prior to the synthesis, the surface of 2-inch Si/SiO₂ wafer was functionalized with diluted HF (1:20) for 1 minute to ease the transfer process. After functionalization, the growth substrate was sequentially cleaned using deionized water (DI water), isopropyl alcohol, and acetone. The substrate was then located vertically in the MOCVD chamber with a NaCl plate positioned upstream of the substrate to enlarge the grain size of WSe₂. Tungsten hexacarbonyl (W(CO)₆, THC; Sigma-Aldrich, catalog no. 472956) and dimethyl selenide [(CH₃)₂Se, DMSe; Sigma-Aldrich, catalog no. 41572] were loaded into the individual bubblers. The chamber was heated to 580°C at 12.5 torr and 220 standard cubic centimeters per minute (sccm) of Ar and 20 sccm of H₂ were supplied as a carrier gas. 3 sccm of THC, 0.2 sccm of DMSe and 4 sccm of THC, 0.4 sccm of DMSe were injected into the chamber for 26 hours to synthesize the monolayer and bilayer WSe₂, respectively. To obtain WO_X buffer layer, MOCVD grown monolayer WSe₂ was oxidized via UV-ozone process. UVO oxidation process was performed at room temperature with ambient oxygen condition.

Material characterization

The Raman and PL spectra of as-grown WSe₂ films were measured under the micro-Raman backscattering configuration using Andor Tech spectrometer equipped with a 532 nm laser (Coherent, EN60825–1) as an excitation source. The low laser power of around 0.15 mW with a spot size of ∼1 μm was used to avoid laser-induced film degradation. The surface topographic images of the samples were obtained by atomic force microscopy (AFM, Park System, NX-10) in the tapping mode to confirm the thickness and surface morphologies. The chemical identification of the samples was performed by XPS instrument (Κ-Alpha, Thermo Scientific) using a conventional monochromatic aluminum x-ray source (Al Κα line 1486.6 eV) with a power of 12 kV and 3 mA, pass energy of 40 eV, step size of 0.05 eV and base pressure of 3.6 × 10⁻⁹ torr. The cross-sectional view of the samples was visualized by TEM imaging using JEM-F200 (JEOL) system operated at accelerating voltage of 200 kV.

Device fabrication

The WSe₂ p-type top-gate transistor was fabricated on Si/SiO₂ (300 nm) substrate. Source and drain electrodes were first defined by conventional photolithography, followed by thermal evaporation of Cr/Pd (3/30 nm) and a lift-off process. Subsequently, a 2L WSe₂ film was transferred onto the substrate using a DI-water-assisted wet transfer method. The transferred WSe₂ was then patterned and etched by reactive ion etching (RIE) to define the channel with SF₆/Ar plasma (15/10 sccm, 100 W, 30 s). Separately, buffer layer was dry transferred onto the pre-patterned WSe₂ channel, followed by thermal treatment to facilitate tape detachment. Subsequently, a 25 nm thick Al₂O₃ dielectric layer was deposited via atomic layer deposition technique. Finally, the top-gate electrode (Cr/Pd, 3/30 nm) was formed using photolithography and lift-off process (fig. S13).

Device characterization

Electrical measurements were conducted at room temperature under ambient conditions using a semiconductor parameter analyzer (Keithley 4200 SCS, Keithley Instruments Inc.). For transistor characterization, transfer characteristics (I_ds-V_gs) were measured by sweeping V_GS from −6 to +2 V in 0.1 V increments at a fixed drain bias of V_DS = −1 V, while simultaneously monitoring the gate leakage current. Forward and backward V_GS sweeps were performed to evaluate hysteresis, defined as ΔV_hys = V_th,backward − V_th,forward. Output characteristics (I_ds-V_ds) were obtained by sweeping V_DS from 0 to −8 V at gate voltages V_GS = 0 to −5 V with a step of 0.5 V. Logic-gate operation (inverter, AND, OR, NAND, and NOR) was evaluated at a supply voltage of V_DD = 5 V by applying input pulses (V_A and V_B) switched between 0 and 5 V using a function generator, and the corresponding output voltage (V_out) was recorded at input switching frequencies from 10 Hz to 10 kHz.

Supplementary Materials

This PDF file includes:

Supplementary Text S1 to S3

Figs. S1 to S21

Table S1

References