Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit

Abstract

The downscaling of silicon field-effect transistors is approaching fundamental limits, with the international roadmap for devices and systems (IRDS) projecting a 12 nm channel length plateau by 2037. Two-dimensional (2D) semiconductors have emerged as promising candidates for extended transistor scaling. However, no experimental demonstration has thus far surpassed the fundamental switching limits of advanced silicon. Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 10⁶. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration. We implement a design–technology co-optimization approach featuring an air-gap isolation and gate-contact overlap design to effectively suppress short channel effects. This work demonstrates subthreshold transport in a 2D semiconductor transistor beyond the silicon limit, showing a viable pathway for extending transistor scaling and energy-efficient computing.

2D semiconductors have emerged as promising candidates to extend Moore’s law beyond silicon limits. Here, the authors report the fabrication of wafer-scale monolayer MoS₂ transistor arrays with sub-5 nm channel length and optimized design of the dielectric environment to suppress short channel effects.

Introduction

Silicon has long served as the foundational material enabling the exponential scaling of very-large-scale integrated circuits (VLSI) under Moore’s law¹. However, its continued scaling is also fundamentally constrained by silicon’s intrinsic material limitations². Such limitations are reflected starkly in the projections of the International Roadmap for Devices and Systems (IRDS), which foresees a 12-nm channel length plateau by 2037³. State-of-the-art silicon technologies, such as TSMC’s N2 and Samsung’s SF3 node, feature gate-all-around field-effect transistors (GAAFETs) with channel lengths typically around 15 nm and nanosheet thicknesses of approximately 5 nm^4,5. The projected stagnation in the IRDS roadmap largely stems from the increasing drain electrostatic influence and direct source-to-drain tunneling at deeply scaled dimensions, which undermines gate control and gives rise to short channel effects (SCE)⁶. Among these, a particularly critical manifestation of SCE is the degradation in subthreshold swing (SS), which directly impacts the switching energy and power efficiency of VLSI. The static power consumption of a chip relates to SS through the relation⁶

$$\mathrm{P}~{\mathrm{e}}^{-\frac{{\mathrm{V}}_{\mathrm{th}}}{\mathrm{SS}}}$$ 1

where P is the standby power consumption, V_th is the threshold voltage of a transistor and SS is the subthreshold swing. The exponential dependence of power consumption on SS makes it increasingly challenging to scale metal-oxide-semiconductor field-effect transistors (MOSFETs) to hundreds of billions per chip without exceeding power budgets.

Emerging semiconductors, including two-dimensional (2D) materials^7–10, metal oxides^11,12, and carbon nanotubes (CNT)^13,14, have been actively explored for further extending transistor scaling beyond silicon. Progress has been made in the on-state regime, for instance, ballistic InSe transistors have shown superior current drive capabilities compared to silicon¹⁵. However, in the off-state regime, where SS and leakage current control are crucial, no experimental demonstration has yet convincingly surpassed the switching metrics of silicon at deeply scaled dimensions. Previous studies have demonstrated gate lengths of 1 nm or below using CNT or graphene edge as electrodes^16,17, but these devices often feature widely spaced source and drain terminals, significantly underestimating short channel electrostatic challenges and limiting their scalability. Moreover, tunneling field effect transistors leverage band-to-band tunneling to enable sub-60 mV/dec switching^18,19, but they often rely on abrupt doping profiles, which makes it difficult to scale down to sub-10 nm and the presence of band tails can lead to increased leakage currents²⁰. Additionally, ferroelectric field effect transistors have also been investigated as a means to improve SS by exploiting negative capacitance in ferroelectric materials²¹, however, their practical viability remains under debate due to challenges in achieving hysteresis-free operation and issues of physical stability of the negative capacitance effect²². The key question thus remains: how can transistor scaling be extended into the “silicon-forbidden” territory of the extreme sub-5 nm regime? From a fabrication perspective, techniques such as directed self-assembly^23,24, manual lamination²⁵, shadow evaporation²⁶ and van der Waals heterostructure stacking²⁷ have been employed to realize sub-10 nm MOSFETs^14,28–32. While these approaches have enabled aggressive gate length scaling, they often exhibit limited scalability and low throughput that hinder wafer-scale integration. More importantly, their experimentally demonstrated SS values have not surpassed the intrinsic limits of silicon.

In this work, we adopt a design-technology co-optimization (DTCO) strategy to realize wafer-scale sub-5 nm channel monolayer MoS₂ transistors, achieving an SS of 88 mV/dec that surpasses the theoretical subthreshold limit of silicon. Here, the channel length (L_ch) is defined as the physical distance between the source and drain boundaries, rather than the gate length. Despite the sub-5 nm L_ch, our MoS₂ transistor exhibits an on/off current ratio above 10⁶ and effectively suppresses SCE, showing excellent electrostatic control. We develop a high-throughput and complementary metal oxide semiconductor (CMOS)-compatible fabrication process and demonstrate MoS₂ transistor arrays on a wafer scale, with statistically repeatable results and scalable manufacturing. The fabrication process and device architecture are co-optimized to mitigate parasitic electrostatic coupling by introducing a low-κ air gap beneath the channel and incorporating gated contact regions, both critical as transistor dimensions approach the sub-5 nm regime. Quantum transport modeling is performed to elucidate the underlying device physics and reveal the origins of the subthreshold performance observed in the scaled devices. This combined experimental-computational approach provides critical design rules for maintaining electrostatic integrity for future extremely scaled transistors.

Results

Device design and fabrication

Figure 1a shows the wafer-scale implementation of the monolayer sub-5 nm channel MoS₂ transistor arrays. The devices employ a channel-on-top architecture developed to co-optimize channel scaling and electrostatic control (Fig. 1b). Targeting the regime where silicon scaling becomes fundamentally challenging, we aim to scale L_ch of MOSFETs below 5 nm using monolayer MoS₂, which is well beyond the projected IRDS scaling limit (Fig. 1c). As the body thickness of silicon drops below 3 nm, carrier mobility degrades sharply³³ (Supplementary Fig. 1), imposing a lower bound on the ultimate scaling limit of silicon MOSFETs’ physical channel lengths near or above 8 nm^3,33,34. To realize MOSFETs at such deeply scaled dimensions, it requires not only precise control on the channel’s lateral and vertical dimensions, but also strategic engineering of the dielectric environment and overall device architecture. Especially, the drain-induced electrostatic interference plays a central role in triggering many SCE³⁵, and suppressing capacitive coupling among drain, channel, and source is critical for maintaining electrostatic integrity. These constraints necessitate a co-optimization of device structure, fabrication process, and material system.

Fig. 1. Wafer-scale demonstration and device design of sub-5 nm channel MoS₂ transistors.

a Photograph of a 4-inch wafer with monolayer MoS₂ transistors fabricated using a photolithography-based, complementary metal-oxide-semiconductor (CMOS) compatible, high throughput process. The physical channel length (L_ch) is below 5 nm. b Schematic illustration of the device architecture, featuring an engineered low-κ air gap and gate-contact overlap to suppress short channel effects (SCE). κ is the relative dielectric constant of the gap region underneath the channel. The electrostatic coupling between the contacts and channel (C_S/D) is minimized, while contact gating enables co-modulation of the contact Fermi level and channel barrier, reducing subthreshold leakage. E_C represents the conduction band edge and E_F represents the Fermi level of the channel. c Benchmark comparison of physical channel lengths of transistors. Our device achieves a 4.8 nm channel length (red star), surpassing both the state-of-the-art silicon gate-all-around field-effect transistors (GAAFETs) (~ 15 nm) and the 12 nm plateau projected by the International Roadmap for Devices and Systems (IRDS)³.

To address this challenge, we used a DTCO approach to precisely define L_ch via the controlled thickness of atomic layer deposition (ALD) spacers in a self-aligned manner, while simultaneously creating a low-κ air gap beneath the channel to suppress SCE (Fig. 1b). The fabrication process flow is illustrated in Fig. 2a and detailed in the “Methods” section. The source contacts were first patterned, followed by the deposition of a sacrificial spacer (thickness: ~ 4 nm) using an ALD process that conformally coats both the top and sidewalls of the source contacts. After global deposition of the layer of drain contact, a critical step involved a tilted reactive ion milling process, which selectively removed part of the sacrificial spacer to disconnect the overlapping metal from the functional contacts and simultaneously define L_ch in a self-aligned fashion. Following this, we developed a tape-assisted “etch and delamination” method to remove the sacrificial overlapping metal across a 4-inch wafer scale with high yield (Fig. 2b, detailed in “Methods”). By design, this process also created an air gap beneath the channel, which, as discussed later, played a key role in suppressing the SS. While the tape-based approach demonstrates excellent scalability, we note that it is not CMOS compatible. Therefore, we also developed an alternative wet-etching process to remove the sacrificial oxide and metal layers uniformly at wafer scale. Process flow and representative devices fabricated using the wet-etch approach are shown in the “Methods” section and Supplementary Information (Supplementary Figs. 2 and 3).

Fig. 2. Fabrication process and leakage performance.

a Schematic illustration of the fabrication process flow. A sacrificial spacer is first deposited conformally on pre-defined source contacts using atomic layer deposition (ALD), followed by global deposition of the drain metal. The sacrificial spacer and overlapping metal are then removed across the wafer using either a tape-assisted “etch-and-delamination” process or a CMOS-compatible wet-etching process, which simultaneously defines the sub-5-nm channel length and forms an air gap between the source and drain. The part of sacrificial layer underneath the drain does not interfere with device operation. Monolayer metal-organic chemical vapor deposition (MOCVD) MoS₂ is then transferred across the sub-5-nm trench, followed by gate stack fabrication. b Photograph of the tape-based “etch and delamination” step on a 4-inch wafer. c Measured source-to-drain leakage current (prior to MoS₂ transfer), confirming excellent insulation below 1 pA/μm up to 2.5 V bias. d False-color scanning electron microscopy (SEM) of a pair of sub-5 nm channel MoS₂ metal-oxide-semiconductor field-effect transistors (MOSFETs). Scale bar: 10 μm.

Photolithography was used throughout the fabrication process to ensure high throughput and CMOS compatibility. After forming the self-aligned sub-5 nm structure, the current between the source and drain contacts was measured to be sub-pA/μm under a bias of up to 2.5 V, confirming excellent electrical insulation prior to the 2D channel formation (Fig. 2c). This fabrication process is deliberately designed to naturally realize a channel-on-top architecture that incorporates a low-κ air gap beneath the channel and enables a gate-contact overlap design. Both structural features are critical for subthreshold performance and will be discussed later. This co-engineering of device structure and fabrication flow exemplifies a DTCO strategy that proves essential for deeply scaled transistors.

We used large-area monolayer MoS₂ synthesized by metal-organic chemical vapor deposition (MOCVD) as channel material. The synthesis setup, optical image, Raman spectroscopy and photoluminescence of the MOCVD MoS₂ samples are shown in Supplementary Fig. 4. The MOCVD monolayer MoS₂ was then transferred on top of the as-fabricated self-aligned structures, followed by gate stack fabrication atop the suspended channel (See “Methods”). A wafer-scale sub-5 nm channel MoS₂ MOSFET arrays was demonstrated (Figs. 1a and 2b). A false-color scanning electron microscopy (SEM) image of a pair of individual MoS₂ transistors is shown in Fig. 2d.

The transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS) cross-sectional views of the MoS₂ channel are shown in Fig. 3a, b, respectively. The L_ch was confirmed to be about 4.8 nm, consistent with the ALD process. Given the extremely scaled channel, statistical variations in channel boundary roughness become increasingly critical, as localized narrowing could strongly impact carrier transport. To accurately quantify the spatial variation of L_ch within a single device, we systematically sampled L_ch at multiple positions along the channel width of the same transistor to obtain its statistical distribution. The resulting distribution in Fig. 3c represents these intra-device measurements, yielding a mean L_ch of 4.8 nm with a standard deviation of $\mathrm{\sigma }=0.9$ nm. Notably, the shortest measured L_ch within the same device was below 3 nm.

Fig. 3. Structural and electrical characterization of sub-5 nm MoS₂ transistors.

a Cross-sectional high-resolution transmission electron microscopy (TEM) image of a fabricated MoS₂ transistor, showing a physical channel length (L_ch) of ~ 4.8 nm. b Corresponding energy-dispersive X-ray spectroscopy (EDS) elemental mapping confirms the presence of monolayer MoS₂ between the source and drain electrodes. c Statistical distribution of the local channel length extracted from 980 segmented SEM measurements at different positions along the channel width. The mean channel length is 4.8 nm, with a standard deviation of 0.9 nm. The distribution reflects intra-device variation along the channel width rather than device-to-device variation. d Transfer I–V characteristics of a representative device under various drain-source voltage (V_DS) values, showing a subthreshold swing (SS) of 88 mV/dec and pA/μm level gate leakage current. I_D is the drain current and V_GS is the gate-source voltage. e Output I–V characteristics at V_GS = −1.4, 0, 0.5, 1, and 1.4 V (from bottom to top). The maximum on-state conductance is 841 μS/μm. f Statistical distribution of subthreshold swing (SS) values.

Device performance and benchmark

With such extremely scaled MOSFETs, we systematically investigated their electrical characteristics to evaluate their gate control capability, leakage suppression, and switching performance. Figure 3d shows the quasi-static transfer I–V characteristics of a typical sub-5 nm channel MoS₂ MOSFET measured at various drain biases V_DS. At V_DS = 0.5 V, the current ratio evaluated between V_GS = −1 V and V_GS = 1 V was approximately 1.1 × 10⁶. Across the full measured gate voltage range, the device exhibited a maximum current modulation of approximately 8 × 10⁷ (Fig. 3d). The most critical figure of merit for evaluating the switching performance is the SS, which was measured to be about 88 mV/dec in the subthreshold region. From the output I–V characteristics, the maximum on-state conductance was found to be about 841 μS/μm under V_GS of 1.4 V and V_DS of 0.5 V (Fig. 3e). The linear output I–V characteristics indicate Ohmic contact between the Au electrodes and monolayer MoS₂. The transconductance ${\mathrm{g}}_{\mathrm{m}}=\frac{\mathrm{d}{\mathrm{I}}_{\mathrm{D}}}{\mathrm{d}{\mathrm{V}}_{\mathrm{GS}}}$ is extracted as well (Supplementary Fig. 5). The device exhibits a peak ${\mathrm{g}}_{\mathrm{m}}$ of 168 µS/µm, which is benchmarked against state-of-the-art results in Supplementary Fig. 6.

To assess reproducibility, we measured 138 devices and analyzed the statistical distribution of key performance metrics. The SS exhibits a median value of 92 mV/dec with a standard deviation of approximately 10 mV/dec (Fig. 3f). Additional statistical analyses of on-state conductance, on/off current ratio, and off-state leakage current are presented in Supplementary Fig. 7, collectively demonstrating excellent reproducibility at the sub-5 nm scale.

To contextualize the performance of our sub-5-nm MoS₂ transistors, we benchmark key metrics against state-of-the-art nanoscale transistors with physical L_ch below 50 nm, including the IRDS projections, CNT, 2D semiconductors, metal oxides, germanium and III–V compound semiconductors^{3,12,14,15,24,25,28–32,36–64} (Fig. 4a–c). The benchmark includes comparisons of SS, on-state conductance and off-state leakage current. This work demonstrates an SS of 88 mV/dec at a physical channel length of 4.8 nm, lower than previously reported values for MOSFETs in the same size regime (Fig. 4a). Most importantly, we also benchmarked our results against the theoretical SS limit of silicon with 3 nm body thickness, derived from quantum transport modeling (detailed in “Methods” and the next section). Theoretical modeling suggested a lower bound of ~150 mV/dec for SS of silicon MOSFETs at L_ch = 5 nm and ~100 mV/dec at L_ch = 8 nm, which can be regarded as the intrinsic electrostatic limit of silicon⁶⁵.

Fig. 4. Benchmarking key performance metrics of nanoscale transistors with L_ch below 50 nm.

This benchmarking evaluates three key performance metrics. a SS, b off-state current Ioff, c on-state conductance go. Physical channel length L_ch here is defined as the physical distance between source and drain boundaries. The blue dash line in (a) represents the theoretical limit of silicon. The off-state current (I_off) is taken as the minimum measured drain current in the vicinity of V_GS = −1 V at V_DS = 0.5 V and is linearly extrapolated to V_DS = 0.65 V for comparison with the IRDS targets. HP and HD denote the high-performance and high-density targets, respectively. Marker code: yellow solid circle (CVD MoS₂), hollow circle (exfoliated MoS₂), hollow up triangle (WS₂), hollow square (CNT), hollow down triangle (metal oxides), hollow right arrow (III–V compounds), solid diamond (InSe), solid hexagram (Ge), hollow diamond (IRDS) and red solid circle (this work). Note that devices with ultrashort gate length but physical channel length greater than 50 nm are not included. Benchmark data are from references^{3,12,14,15,24,25,28–32,36–64}.

At a physical channel length of 4.8 nm, our devices exhibit an SS (88 mV/dec) lower than previously reported values for sub-5 nm transistors and the theoretical limit of silicon derived from quantum transport modeling. Our devices achieve pA/μm level off-state current in the sub-5 nm regime (Fig. 4b). For fair comparison, all reported data are normalized to the IRDS standard bias condition (V_DS = 0.65 V). The on-state conductance of 841 μS/μm is achieved here and benchmarked in Fig. 4c. While further improvements are required to fully meet the IRDS on-current targets, this work primarily focuses on the subthreshold regime, where mitigating SCE and suppressing leakage currents are the dominant challenges. We also note that our devices can reliably operate under 105 °C (Supplementary Fig. 8).

For sub-5 nm MOSFETs operating in the on state, the source and drain contact resistances dominate the overall device resistance. Therefore, we estimate the upper limit of the total contact resistance (2R_c) by extracting the total resistance from the output characteristics (Supplementary Fig. 9). This extracted total resistance provides an upper bound for 2R_c in our MoS₂ transistors. The upper bound of the contact resistance is R_c ≤ 486 Ω·µm. We note that, as shown in Supplementary Fig. 7, the on-state conductance varies from approximately 100 µS/µm to 1 mS/µm, indicating that R_c also exhibits device-to-device variation.

We note that the present devices exhibit a negative threshold voltage V_th and therefore operate in depletion mode (Fig. 3d). Although this does not affect the extraction of the SS, a negative V_th is undesirable for low-power logic IC because the transistor remains partially conducting at V_GS = 0 V, which can increase standby leakage and static power consumption. Such threshold voltage shifts in MoS₂ transistors have been associated with a combination of fixed dielectric charge, interface traps, surface adsorbates, processing residues, and defect-induced n-type doping, including sulfur vacancies^66–68. Future optimization will require deliberate threshold voltage engineering to shift V_th towards positive. One possible route is defect healing through oxygen-mediated passivation of sulfur-vacancy-induced donor states, which can reduce unintentional n-type doping and shift MoS₂ transistors toward enhancement-mode operation without measurable mobility degradation⁶⁶. Recent studies also demonstrated positive threshold voltage tuning in MoS₂ transistors using van der Waals dielectric encapsulation and gate stacks⁶⁷.

Quantum transport simulation and understanding

To gain a deeper understanding of the device physics and the origin of the subthreshold behaviors, we performed quantum transport simulations based on the nonequilibrium Green’s function (NEGF) formalism (see “Methods”). Fig. 5a shows the simulated electrostatic potential profile of the MoS₂ transistor under subthreshold bias conditions, revealing a well-defined energy barrier at the source-channel interface and strong gate control across the channel. Fig. 5b shows the conduction band edge (E_c) profile across the source, channel, and drain as the gate voltage (V_GS) decreases. This progressive barrier modulation with gate bias illustrates effective electrostatic control over the channel. Using the same computational framework, the theoretical limit of silicon MOSFETs, assuming a 3 nm body thickness and double-gate structure, was calculated and benchmarked in Fig. 4a. A detailed description of the methodology is available in our prior work⁶⁵. We also calculated the local density of states (DOS) and energy resolved current spectrum of the monolayer MoS₂ transistor under both subthreshold and on-state bias conditions (Supplementary Fig. 10), with the simulated current modulation showing good agreement with experimental measurements.

Fig. 5. Quantum transport simulations elucidating the impact of high-κ environment and gate-contact overlap.

κ denotes the relative dielectric constant of the region underneath the MoS₂ channel, rather than that of the dielectric layer above the channel. a Simulated electrostatic potential profile of the MoS₂ transistor under subthreshold bias conditions. b Conduction band edge E_c profiles under varying gate voltage V_GS, highlighting strong gate modulation across both the gated contact and channel regions. c Effect of high-κ environment on SS and I_off, showing degraded electrostatic control and increased leakage with increasing κ of the region underneath the channel. d Simulated E_c profile for κ = 1, 3, 5, 12, 18, 25, showing barrier lowering with increasing κ. The inset schematically shows the simulated transistor structure with a gap region underneath the channel. e Simulated carrier density profiles along the transport direction under different V_GS, confirming carrier modulation across the gated contact and channel. f Impact of gate-contact overlap length on SS and I_off, showing improved subthreshold behavior and leakage suppression with increased overlap. The inset schematically illustrates the device geometry and defines the lateral overlap (L_ov) between the gate and the adjacent MoS₂ contact region.

A key factor contributing to the suppressed SS is the engineered low-κ air gap beneath the channel, which minimizes parasitic capacitive coupling between the contacts and the channel (Fig. 1b). Quantum transport simulations confirm that SS and off-state current I_off are highly sensitive to the dielectric constant κ of the spacer region between source and drain contacts. Increasing κ from 1 to 25 leads to a substantial degradation in both metrics, with SS exceeding 300 mV/dec for κ = 25 (Fig. 5c). Concurrently, the I_off would increase by more than four orders of magnitude at V_GS = –2 V, indicating a loss of electrostatic control. As shown in Fig. 5d, the corresponding conduction band profiles (E_c) illustrate a pronounced reduction in the channel barrier height as κ increases, consistent with the observed sensitivity of SS and I_off to κ. The observed air-gap effect can be understood using the equivalent capacitance network model (Supplementary Fig. 11). The SS quantifies how effectively V_GS modulates the channel current in the subthreshold regime and can be approximately given by³⁵:

$$\mathrm{SS}={\left[\frac{\mathrm{dlog}\left({\mathrm{I}}_{\mathrm{DS}}\right)}{\mathrm{d}{\mathrm{V}}_{\mathrm{GS}}}\right]}^{-1}=\frac{{\mathrm{k}}_{\mathrm{B}}\mathrm{T}}{\mathrm{q}}\ln 10\cdot \left(1+\frac{{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{D}}+{\mathrm{C}}_{\mathrm{it}}}{{\mathrm{C}}_{\mathrm{G}}}\right)$$ 2

Where I_DS is the channel current, V_GS is the gate to source voltage, C_S/C_D denote the parasitic capacitance between the source/drain and the channel, C_G is the gate capacitance and C_it is the interface trap capacitance. As the channel dimensions shrink to just a few nanometers, the source and drain capacitances C_S and C_D become increasingly significant and can dominate the SS. Introducing a low-κ air gap beneath the channel effectively reduces C_S and C_D, leading to suppressed electrostatic coupling and a lower SS. From a manufacturing standpoint, the air-gap structure is inherently CMOS compatible, leveraging the same void spacer and selective etch processes already employed in advanced interconnects⁶⁹ and 3D NAND flash memories⁷⁰. Its implementation here at the transistor level extends a proven industry technology into the active 2D device domain, combining demonstrated process scalability with new physical functionality. This design thus represents not only a materials innovation but also a practical architectural strategy for sustaining electrostatic control in future sub-5 nm transistors. The extremely scaled regime demands such a holistic DTCO approach, wherein the channel material, dielectric environment, device architecture, and fabrication processes are co-engineered to maintain both electrostatic integrity and manufacturability at the nanometer scale, as demonstrated here.

Another critical factor enabling the suppressed SS in the deeply scaled regime is the deliberate overlap between the gate and the MoS₂ contact regions (Figs. 1b and 3a). This overlap allows the gate field to modulate not only the channel potential but also the local Fermi level within the adjacent MoS₂ contact regions. This dual modulation was found to be important for suppressing the SS and mitigating SCE. The theoretical limit of SS in MOSFETs originates from the thermionic emission of carriers over the source-channel barrier governed by Boltzmann statistics, which imposes a minimum value of 60 mV/dec at room temperature⁶. For conventional silicon GAAFETs, the contacts are typically heavily doped silicon with E_F essentially fixed. In monolayer MoS₂, the intrinsically low DOS in the source/drain regions allows the gate to effectively tune their carrier density, influencing thermionic emission over the potential barrier in the subthreshold regime. This gate-controlled “Boltzmann tail” helps suppress SS beyond what is typically achievable in conventional silicon devices (Fig. 1b and Supplementary Fig. 12).

This dual modulation behavior can be described by the relation⁶:

$${\mathrm{J}}_{\mathrm{E}}={\mathrm{qn}}_{\mathrm{s}}\left({\mathrm{V}}_{\mathrm{GS}}\right){\mathrm{v}}_{\mathrm{inj}}\cdot {\mathrm{e}}^{-\frac{\mathrm{q}{\mathrm{\phi }}_{\mathrm{ch}}\left({\mathrm{V}}_{\mathrm{GS}}\right)}{{\mathrm{k}}_{\mathrm{B}}\mathrm{T}}}$$ 3

Where J_E is the channel current density, q is the elementary charge, n_s(V_GS) is the gate-dependent carrier density in the contact region, φ_ch(V_GS) is the gate-controlled source-to-channel potential barrier, v_inj is the carrier injection velocity, k_B is the Boltzmann constant and T is the temperature. This contact gating effect is only possible in low DOS semiconductors like MoS₂ and requires the semiconducting channel to be positioned above the contacts; in contrast, conventional metal contacts on top would screen the gate field, preventing electrostatic modulation of the contact regions. This effect is directly validated by our quantum transport simulations. Applying a negative gate bias simultaneously increases the channel energy barrier and reduces the carrier density in the MoS₂ contacts, both of which contribute to a steeper turn-off and suppressed SS (Fig. 5b and e). Our simulations further reveal that the extent of gate-contact overlap strongly influences subthreshold performance. An overlap of just a few nanometers significantly reduces SS and I_off, as shown in Fig. 5f. As the gate-contact overlap is reduced to zero, the SS would increase to nearly 120 mV/dec, and I_off would rise by nearly two orders of magnitude under the same V_GS and V_DS biases. Such effect largely saturates beyond 5 nm, consistent with the MoS₂ contact transfer length, which is on the order of a few nanometers^45,71,72. We note that state-of-the-art silicon GAAFETs often employ an underlap contact design (Supplementary Fig. 12), wherein the source and drain extension regions are deliberately positioned outside the gate’s direct electrostatic reach. These underlapped regions are intentionally introduced in GAAFET design to suppress SCE; however, these extensions also remain electrostatically decoupled from the gate, thereby limiting access to modulating the gate-dependent carrier density term n_s(V_GS).

From a material perspective, the relatively high effective mass of MoS₂ (m* ≈ 0.55 m₀, where m₀ is the free electron mass) and its larger bandgap (~ 1.8 eV) compared to silicon both help suppress source-to-drain tunneling^34,73, while silicon MOSFETs suffer from severe source-to-drain tunneling at a sub-5 nm channel length⁷⁴. Through a DTCO approach, we harness both the material and structural advantages of 2D semiconductors to push the limits of transistor scaling. Our results demonstrate that, with proper electrostatic engineering and DTCO-guided design, monolayer MoS₂ transistors can surpass the scaling limits of silicon, offering a promising pathway toward next-generation low-power logic technologies. While this work focuses primarily on the subthreshold characteristics, we note that the on-state performance can be further improved through optimized contact engineering and strategic material selection that balances key parameters such as effective mass and bandgap. Recent work demonstrated an advance in self-aligned integration through a dual self-aligned vertical MoS₂ transistor with a 0.34 nm graphene-edge gate and an approximately 10 nm physical channel⁷⁵. The reported SS of approximately 412 mV/dec further highlights that gate length scaling and physical channel length scaling represent distinct aspects of transistor miniaturization, and that suppressing SCE requires concurrent optimization of the physical channel length and electrostatic environment.

In summary, we have demonstrated wafer-scale fabrication of extremely scaled transistors based on monolayer MoS₂ with physical channel length below 5 nm. By engineering the dielectric environment and implementing a gate-contact overlap design, we achieve strong electrostatic control, with an SS of 88 mV/dec and an on/off ratio above 10⁶. In the on-state regime, the devices exhibit a maximum on-state conductance of 841 μS/μm. Quantum transport simulations corroborate the experimental results and elucidate the underlying transport physics. Our devices not only outperform previously reported sub-10 nm transistors but also surpass the theoretical subthreshold limit projected for silicon at comparable dimensions. These results establish a viable pathway for 2D semiconductors to extend transistor scaling beyond the intrinsic limits of silicon, offering a promising route toward next-generation low-power logic technologies.

Methods

MOCVD synthesis and transfer of wafer-scale monolayer MoS₂

Wafer-scale continuous monolayer MoS₂ was synthesized via the MOCVD approach. Molybdenum hexacarbonyl (Mo(CO)₆, Sigma-Aldrich, 99.9% purity) and diethyl sulfide ((C₂H₅)₂S, Sigma-Aldrich, 98% purity) were used as chemical precursors with argon as the carrier gas. MoS₂ synthesis was conducted at approximately 800 °C with flow rates of 5 sccm for Mo(CO)₆, 0.6 sccm for diethyl sulfide, 1 sccm for H₂, and 800 sccm for Ar. A continuous monolayer MoS₂ was achieved on the substrate of sapphire, after a one hour synthesis period. For film transfer, a wafer-scale PMMA-assisted method was employed. A support layer of PMMA A4 was spin-coated onto the MoS₂ film at 3000 rpm for 60 seconds and baked at 70 °C for 5 minutes. The PMMA/MoS₂ stack was then delaminated using an ammonia solution and rinsed with deionized water. The floating PMMA/MoS₂ film was transferred to the target substrate by fishing it from the wafer surface, followed by air drying and vacuum baking to eliminate residual moisture. Finally, PMMA was removed using acetone and isopropanol, leaving the MoS₂ monolayer on the target substrate.

Wafer-scale device fabrication and characterization

All devices were fabricated on a 4-inch intrinsic silicon wafer capped with 285 nm SiO₂. Photolithography was used to define the first metal layer (source layer). After development, 1 nm titanium (Ti) as an adhesion layer and 41 nm Au were deposited by electron-beam evaporation (EBE). A nominal 4 nm-thick AlO_x spacer was subsequently deposited via optimized ALD at 250 °C, using trimethylaluminum and water as precursors. The second layer of Au (40 nm) was then globally deposited by EBE. To eliminate the unwanted overlapping metal atop the source electrode, reactive ion milling was performed at a tilting angle to disconnect the overlapping metal from the drain electrode. Following this, Scotch tape was carefully laminated onto the chip surface and gently heated on a 60 °C hotplate to remove any trapped air bubbles. The tape was then slowly and uniformly peeled off, lifting away the unwanted overlapping metal and thereby forming a self-aligned sub-5 nm nanogap structure. The baking process is critical in achieving high device yield. As an alternative to the tape-assisted metal lift-off, the overlapping second metal layer can also be removed using a wet-etch process. After the tilted reactive ion milling step, the wafer was immersed in an ammonium nitrate/nitric acid wet etchant, which selectively dissolves the exposed Cr and AlO_x spacer layer. During this step, the overhanging Au on top of the source electrode is simultaneously released, resulting in a self-aligned nanogap. A monolayer MOCVD MoS₂ was then transferred on top of the as-fabricated wafer. Mesa isolation was then performed using photolithography and oxygen plasma etching. The AlO_x gate dielectric was formed through three sequential Al deposition and natural oxidation cycles. Al layers with nominal thicknesses of 1.5, 1.5, and 1.0 nm were successively deposited by EBE, with each layer allowed to oxidize under ambient conditions overnight before the subsequent deposition. The resulting AlO_x dielectric thickness was approximately 5.5 nm. Photolithography was used to define the top gate electrode, followed by EBE deposition of 2/50 nm Cr/Au and a lift-off process. For structural analysis, TEM lamellae were prepared using a FEI Scios Dual Beam system. Cross-sectional TEM and EDS imaging were conducted on a 200 kV FEI Tecnai F20. Electrical characterization was performed using a probe station and a Keysight B1500A semiconductor parameter analyzer.

Quantum transport simulation

The quantum transport properties of the MoS₂ MOSFET are simulated by self-consistently solving the NEGF formalism with the Poisson equation. The Poisson equation is discretized using the finite difference method and solved numerically. For the NEGF treatment of carrier transport in the 2D MoS₂ channel, an effective mass description of the MoS₂ channel Hamiltonian is used. The self-energies of the metal source and drain contacts are incorporated using a phenomenological approach⁷². The NEGF transport equation and the Poisson equation are solved iteratively until convergence is achieved. Once self-consistency is reached, the source-to-drain current and other relevant device characteristics are extracted. The theoretical limit of silicon MOSFETs, assuming a 3 nm body thickness and double gate configuration, is derived using the same computational approach⁷².

The schematics in Figs. 1b, 2a, and 5d, f and Supplementary Figs. 7 and 8a, b, d, e were created using Blender software.

Author contributions

X. Zhang, S.S., and S.L. conceived the project. S.L. and T.H. led the device design, fabrication and characterization. J.G., N.Y. and H.Y. led the quantum transport simulations. J.K. and X. Zheng led the MoS₂ synthesis and transfer. K.X., S.L., and G.T. led the TEM and EDS characterization. The data analysis was led by S.L., T.H., N.Y., H.Y., X. Zheng, J.G., S.S. and X. Zhang, with contributions from all co-authors.

Peer review

Peer review information

Nature Communications thanks the anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

S.L., T.H., Y.Z., J.Z., and X. Zhang acknowledge the support from National Science Foundation (Grant number ECCS-2426252 and ECCS-2239822). T.H., H.Y., Y.Z., and S.S. acknowledge the support from National Science Foundation (Grant number CBET-1931964) and Defense Threat Reduction Agency (Grant number HDTRA1-19-1-0028 and HDTRA1-26-1-0003). The work at the University of Florida was supported by the National Science Foundation (Grant number 2426253 and 2203625). X. Zheng, K.Z., and J.K. from MIT acknowledge the support from the Semiconductor Research Corporation Center 7 in JUMP 2.0 (award number 145105-21913) and the U.S. Army DEVCOM ARL Army Research Office through the MIT Institute for Soldier Nanotechnologies under Cooperative Agreement number W911NF-23-2-0121.

Data availability

Relevant data supporting the key findings of this study are available within the article and the Supplementary Information file. All raw data generated during the current study are available from the corresponding authors upon request.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-77186-9.