Lithography‐Compatible Conductive Metal–Organic Frameworks for Scalable Electronics

ABSTRACT

Conductive metal–organic frameworks (MOFs) have emerged as promising electronic materials, yet their integration as functional components in semiconductor devices remains limited by challenges in device‐level fabrication. Here, we demonstrate chemical vapor deposition (CVD)‐grown Cu₃(C₆O₆)₂ thin films, a highly conductive two‐dimensional (2D) MOF, as gate electrodes, enabled by their suitable work function and stable electronic structure. A sequential APS–Cr etching strategy enables high‐conformity patterning of MOF thin films fully compatible with standard photolithographic processes, while preserving the integrity of the underlying device layers. Field‐effect transistors were realized across three technologically relevant semiconductor platforms, including n‐type MoS₂, p‐type MoTe₂, and indium gallium zinc oxide (IGZO), demonstrating the generality of Cu₃(C₆O₆)₂ MOF as a gate electrode material. The resulting devices exhibit transfer characteristics and charge mobilities comparable to conventional metal gates in MoS₂, while large‐area IGZO transistor arrays show uniform and highly reproducible electrical performance. These results establish conductive MOF thin films as viable gate materials and expand their potential toward source–drain electrodes and even channel materials, in next‐generation semiconductor devices.

Conductive MOF thin films are integrated as gate electrodes in semiconductor devices through a photolithography‐compatible patterning strategy. CVD‐grown 2D MOF thin films enable stable operation across bottom‐gate MoS₂/MoTe₂ field‐effect transistors and top‐gate IGZO arrays, highlighting the potential of conductive MOFs as functional electronic materials for next‐generation semiconductor devices.

1. Introduction

The electronics industry has historically advanced through the discovery of new materials, spanning from silicon‐based semiconductors to high‐k dielectrics [1, 2] and, more recently, atomically thin two‐dimensional (2D) crystals [3, 4], with each class of materials enabling successive generations of device innovation and performance enhancement. However, as conventional device scaling approaches its fundamental physical limits, this largely discovery‐driven paradigm is becoming increasingly insufficient, prompting a fundamental shift in how materials for electronic systems are conceptualized and developed. In this context, an important question emerges: rather than continuing to rely on the identification of materials with inherently suitable properties, can materials instead be deliberately designed to exhibit targeted functionalities? This question is particularly relevant as the electronics industry moves beyond traditional Moore's law scaling and toward increasingly complex device architectures that integrate a wide range of material classes—including 2D semiconductors [5, 6], metal oxides [7], and organic components [8, 9]—within a single platform to achieve new and often synergistic functionalities. While such heterogeneous integration offers significant opportunities, it simultaneously introduces substantial challenges, as existing materials are rarely able to satisfy multiple performance requirements in parallel, and their intrinsic properties, once selected, are difficult to modulate or adapt within an integrated system. Consequently, the limitations associated with fixed material properties are becoming more pronounced, highlighting the importance of alternative strategies that allow for greater control over electronic behavior at the materials level.

Within this framework, a design‐oriented approach to materials development represents a compelling path forward, wherein functionality is not passively inherited from existing materials but is instead actively engineered through the rational selection and assembly of constituent building blocks, thereby enabling the creation of materials systems with properties tailored to meet the increasingly demanding requirements of next‐generation electronic technologies. Metal–organic frameworks (MOFs) exemplify this design paradigm particularly well, as they are porous crystalline materials constructed through coordination bonding between metal cations/clusters and organic ligands [10, 11, 12, 13, 14, 15]. Among them, two‐dimensional layered MOFs have emerged as especially promising electroactive materials owing to their high electrical conductivity [16], comparable to that of heavily doped silicon semiconductors. Their electronic structures can be synthetically tuned across multiple parameters through selection of metals [17] and ligands [18], control of orbital and energy overlap [19, 20, 21], and pore confinement doping [22], thereby enabling fine control over key electronic properties such as band gap [23, 24], work function [25, 26, 27], charge carrier mobility [28], and even p–n carrier polarity switching [29]. Such molecular‐level control over the work function is particularly attractive for gate electrodes, as it could enable threshold‐voltage engineering through chemical design rather than the selection of different gate metals [30, 31, 32, 33]. This combination of structural tunability and high electrical conductivity has enabled MOFs to be explored across diverse technological fields, including energy conversion and storage [34, 35, 36], sensing electronics [37, 38], and bioelectronic supercapacitors [39].

However, despite these capabilities, the integration of conductive 2D MOFs into functional electronic devices has been limited by two key challenges. The first is the difficulty in translating their intrinsically tunable electronic properties into device‐compatible thin‐film architectures. The second is the lack of reliable, photolithography‐compatible patterning strategies for conductive MOFs. This challenge is particularly critical when MOFs are employed as device electrodes, for which surface roughness becomes a key consideration. Surface roughness and morphological non‐uniformities can propagate into the overlying device stack, increasing interfacial trap density and compromising device uniformity and electrical reliability [40, 41]. As a result, approaches that enable microscale patterning of MOF electrodes while preserving their structural integrity, electronic properties, and low surface roughness remain limited, hindering their implementation in practical semiconductor device architectures.

To address the first challenge, a range of thin‐film synthetic strategies has been explored, including solution‐phase methods such as layer‐by‐layer assembly [26, 42], liquid–liquid and gas–liquid interfacial growth [43, 44, 45], and microfluidic‐assisted assembly [46, 47], as well as vapor‐phase approaches such as molecular layer deposition (MLD) [48], solid–vapor conversion [49], and chemical vapor deposition (CVD) [50, 51], which have led to significant advances in MOF thin‐film fabrication. In particular, mild CVD growth provides a potentially less damaging route to electrode integration than physical vapor deposition of conventional metals, which can expose underlying surfaces to energetic species [52, 53]. However, unlike conventional metal electrodes, which can be readily patterned using established sputtering and lift‐off processes, MOF thin films are chemically complex coordination networks that are susceptible to degradation under typical photolithographic processing conditions. Patterning has been investigated for insulating MOFs [54], particularly within the ZIF series [55, 56], and has more recently been extended to conductive 2D MOFs through laser ablation [57] and photolithography [58]. These studies establish the feasibility of patterning conductive 2D MOFs, while also revealing challenges associated with maintaining the integrity of the MOF film during patterning. Building on these considerations, this work explores the use of conductive MOF thin films as functional electrodes in semiconductor devices.

Herein, we demonstrate for the first time that conductive MOF thin films can serve as directly integrable electrodes for semiconductor field‐effect transistor arrays. The Cu₃(C₆O₆)₂ thin film is synthesized by CVD and exhibits characteristic crystalline structure (Figure 1a,b). The MOF gate is incorporated into bottom‐gate transistor architectures based on transition metal dichalcogenide (TMD) channels, including n‐type MoS₂ and p‐type MoTe₂ (Figure 1c), as well as top‐gate devices based on indium gallium zinc oxide (IGZO) (Figure 1d), demonstrating compatibility with distinct device geometries and channel polarities. The same gate architecture further enables array‐level device integration on semiconductor platforms commonly used for thin‐film electronics (Figure 1e). These results lay the foundation for conductive MOFs as a versatile platform for next‐generation electronics beyond gate electrodes.

FIGURE 1.

Schematic illustration of CVD growth and device integration of conductive 2D MOF thin films. (a) Schematic illustration of the face‐to‐face inner tube CVD setup for the growth of Cu₃(C₆O₆)₂ thin films growth. (b) Crystal structure of Cu₃(C₆O₆)₂. Schematic device architectures using Cu₃(C₆O₆)₂ as the gate electrode for field‐effect transistors (FETs) based on (c) two‐dimensional transition metal dichalcogenides (2D TMDs), including MoTe₂ and MoS₂, and (d) indium gallium zinc oxide (IGZO). (e) Optical micrograph of a device array fabricated on a pre‐patterned IGZO substrate, highlighting MOF gate electrodes defined via photolithography. The scale bar represents 50 µm.

2. Results and Discussion

Large‐area, high‐quality Cu₃(C₆O₆)₂ thin films were fabricated by CVD via a vapor‐phase ligand substitution reaction between bis(2,4‐pentanedionato)copper(II) (Cu(acac)₂) and tetrahydroxy‐1,4‐benzoquinone (THQ), following a previously reported method with slight modifications to improve film morphology and surface uniformity [50]. For device fabrication, the film thickness was optimized to 50 nm by tuning the precursor amount. The films exhibited a smooth and uniform surface over a 1 × 1 cm² area (Figure 2a). Atomic force microscopy (AFM) measured on a representative film revealed a polycrystalline morphology with a notably smooth surface exhibiting a surface roughness (R _q) of 2.86 nm (Figure 2b), which is essential for forming stable gate–dielectric interfaces in subsequent device fabrication. The film thickness determined from a mechanically scratched AFM topography image was 50.7 nm (Figure 2c) and can be tuned from 13 nm to 50 nm according to the precursor amount (Figure S1). High‐resolution transmission electron microscopy (HRTEM) analysis performed on powder obtained by scraping the MOF film revealed that the film possesses a honeycomb lattice with a pore diameter of ∼1.1 nm when viewed along the [001] zone axis (Figure 2d) with interlayer distance of ∼0.31 nm (Figure S2). Synchrotron GIWAXS measurements were performed to examine the crystallographic orientation of the Cu₃(C₆O₆)₂ thin films (Figure 2e). Bragg reflections indexed to the (020), (040), and (060) planes appear predominantly along the out‐of‐plane direction, whereas the (001) and (002) reflections are observed mainly in the in‐plane direction, corresponding to an interlayer spacing of ∼0.32 nm. This reciprocal‐space distribution indicates that the layered frameworks are oriented perpendicular to the substrate, characteristic of an edge‐on configuration. Consistently, powder x‐ray diffraction (XRD) patterns exhibit dominant (hk0) reflections, further confirming the preferred edge‐on orientation of the films (Figure S3).

FIGURE 2.

Characterization of Cu₃(C₆O₆)₂ thin films. (a) Optical image. (b) AFM image. The scale bar represents 1 µm. (c) AFM height profile with corresponding topography image. The scale bar represents 1 µm. (d) HRTEM image overlaid with the corresponding crystal structure; inset shows the simulated HRTEM image. The scale bar represents 10 nm. (e) Two‐dimensional GIWAXS pattern. (f) UPS spectra of the resulting Cu₃(C₆O₆)₂ thin films on a SiO₂/Si substrate.

X‐ray photoelectron spectroscopy (XPS) spectra were analyzed to further verify the chemical composition and bonding environment (Figure S4). XPS analysis reveals mixed Cu²⁺/Cu⁺ states in the Cu 2p spectrum with an intensity ratio of ∼2:1. The C 1s spectrum shows distinct C═O and C─O components with a ratio of ∼1:1.5, corresponding to semiquinone and catecholate ligands, respectively [59]. The electronic band structure was examined using ultraviolet photoelectron spectroscopy (UPS) to evaluate the suitability of Cu₃(C₆O₆)₂ as a universal gate material (Figure 2f). The secondary electron cutoff yielded a work function of 4.51 eV, a value strategically positioned between those of typical n‐type (e.g., MoS₂, ∼4.3 eV) and p‐type (e.g., MoTe₂, ∼4.6 eV) semiconductors, thereby enabling effective Fermi level alignment and gate modulation for both electron‐ and hole‐transporting channels. Furthermore, the lateral charge transport in the as‐grown films was evaluated using a direct probe‐tip contact configuration, and even in the absence of lithographically defined contacts, the films sustained currents in the tens of microamperes range (Figure S5); the corresponding I–V characteristics exhibit nearly linear behavior over a thickness range of 20–50 nm. Collectively, these results highlight the potential of Cu₃(C₆O₆)₂ as a micro‐patterned electrode across diverse semiconductor platforms.

As a practical gate electrode in semiconductor devices, the MOF thin film must be reliably patterned using methods compatible with standard device fabrication. To establish such a patterning strategy, we systematically evaluated two distinct etchants: ammonium persulfate (APS; oxidant) and chromium etchant (acidic/oxidant). Each etchant removes the MOF through distinct chemical pathways that ultimately disrupt the Cu–ligand coordination bond. While APS promotes radical‐mediated ligand oxidation [60], the chromium etchant accelerates Cu–O bond cleavage under strongly oxidative acidic conditions [61, 62], resulting in different reaction rates, selectivity, and degrees of framework degradation. Compared to the pristine Cu₃(C₆O₆) (Table S1), the quality and selectivity of pattern formation after photolithographic patterning and etchant exposure under optimized conditions, determined through iterative trials (Figures S6 and S7; Tables S2–S4 and S5–S7), were assessed by optical microscopy (OM), scanning electron microscopy (SEM), and energy‐dispersive x‐ray spectroscopy (EDS). This systematic approach enabled identification of the etching chemistry best suited for selective MOF framework. Optical and SEM images of the pristine Cu₃(C₆O₆)₂ film confirmed a smooth, uniform surface and a homogeneous micrometer‐scale morphology, while EDS mapping showed well‐defined and spatially uniform distributions of carbon and copper (Figure 3a–e).

FIGURE 3.

Photolithographic patterning of Cu₃(C₆O₆)₂ MOF thin films with preserved film integrity. (a and b) Optical microscopy. (c and d) scanning electron microscopy. (e and f) EDS elemental mapping of Cu₃(C₆O₆)₂ films before and after sequential APS–Cr etching: (a, c, and e) Pristine film; (b, d, and f) film after sequential APS–Cr etching. The scale bars represent 10 µm.

The differences in etching kinetics and process windows are critical for device fabrication, as they directly determine pattern accuracy and process controllability. Although OM, SEM, and EDS images demonstrate selective pattern formation with both APS and chromium etchants, further analyses are required to verify whether the MOF has been completely removed to a degree compatible with reliable device fabrication. APS enables relatively mild and controllable ligand oxidation; however, when applied alone, it may leave residual fragments (Figure S8). In contrast, the chromium etchant induces rapid MOF decomposition without leaving metal residues, but requires precise control of exposure time to prevent excessive material loss (Figure S9). Considering these complementary characteristics, we adopted an APS–Cr sequential etching strategy. In this approach, APS defines the initial pattern through controlled oxidation, followed by a brief chromium etchant treatment to remove remaining Cu‐containing residues and decomposed organic fragments. OM and SEM images after sequential APS–Cr etching showed clearly resolved MOF patterns, while EDS elemental mapping further confirmed selective retention of the MOF in the protected regions (Figure 3b–f). AFM analysis further showed that the retained MOF thickness after sequential APS–Cr etching (48.9 nm) remained comparable to that of the pristine film (50.7 nm) (Figure S10). Quantitative SEM analysis of the optimized patterns yielded measured linewidths of 4.183 ± 0.098 and 4.199 ± 0.102 µm for a nominal linewidth of 5 µm design, with corresponding mean line‐edge roughness (LER) values of 200.87 and 205.69 nm, equivalent to approximately 4.8%–4.9% of the measured linewidths (Figure S11 and Table S8).

XPS analysis of the etched regions after APS–Cr sequential etching was conducted to examine the chemical state of the film following pattern formation (Figure S12). Relative to the pristine MOF, the Cu 2p signal was completely suppressed, indicating effective removal of the Cu‐based framework in the etched areas. The remaining C 1s signal indicates the presents of a small amount of residual carbon‐containing residues, while O 1s spectrum is dominated by a broad SiO _x /O─H contribution associated with the exposed SiO₂ surface, with a weak C═O‐related component arising from these residual species [63, 64]. These results indicate that the APS–Cr sequential etching conditions employed in this study enable chemically well‐defined pattern formation, producing cleared regions in which the original MOF coordination network is effectively removed.

To further evaluate the integrity of the retained MOF regions after the complete photolithographic patterning process, PXRD, XPS, and current–voltage (I–V) measurements were performed on both the pristine MOF film and the retained MOF film after processing (Figure S13a). The characteristic PXRD patterns were preserved after patterning, indicating that the crystallinity of the MOF was maintained throughout the process (Figure S13b). Similarly, the I–V curves before and after patterning exhibited comparable profiles and current levels, indicating that the electrical conduction characteristics of the retained MOF were largely preserved (Figure S13c). XPS analysis further showed that the characteristic Cu 2p, C 1s, and O 1s features of the pristine MOF remained largely unchanged after processing (Figure S13d–f). Collectively, these results demonstrate that the structural, electrical, and chemical characteristics of the retained MOF regions are well preserved throughout the complete photolithographic patterning process.

Using the optimized APS–Cr sequential etching strategy, a two‐gate MoS₂ architecture was fabricated, enabling direct side‐by‐side comparison between the MOF gate and a standard Pt gate on the identical channel (Figure 4a). A cross‐sectional TEM image confirms the well‐defined multilayer device structure, consisting of the MoS₂ channel, the PS‐brush/Al₂O₃ dielectric stack, and the patterned Cu₃(C₆O₆)₂ gate (Figures 4b and S14). The clearly resolved Al₂O₃/MOF interface indicates that the MOF layer remains chemically stable during device fabrication. An optical image further verifies that both the Pt gate and MOF gates are properly positioned between the source and drain electrodes (Figure 4c, inset). Transfer and output characteristics measured using the Pt and MOF gates exhibit nearly identical n‐type behavior, with comparable threshold voltages, subthreshold slopes (Figures 4c and S15) [65, 66, 67], and field‐effect mobilities (Figure 4d), demonstrating that the patterned MOF gate provides electrostatic control equivalent to that of a noble metal gate. Consistently, the field‐effect mobilities extracted from linear‐regime transfer curves show similar values from Pt‐gated operation, confirming that the MOF electrode functions effectively as gate for n‐channel transistors. Long‐term ambient stability was further evaluated using the same two‐gate MoS₂ FET, which retained comparable Pt‐ and MOF‐gated transfer characteristics after approximately 1 year of storage (Figure S16).

FIGURE 4.

Operation of bottom‐gate field‐effect transistors enabled by Cu₃(C₆O₆)₂ MOF gate electrodes. (a–d) Electrical characterization of the n‐MoS₂ FET equipped with a two‐gate structure (Pt/Cu₃(C₆O₆)₂): (a) schematic device architecture, (b) cross‐sectional TEM image prepared by FIB. The scale bar represents 20 nm, (c) transfer curves measured through the Pt gate and the MOF gate in the separate‐gate configuration (inset: optical image of the device. The scale bar represents 10 µm), where the black and red curves correspond to the Pt gate and the MOF gate, respectively, (d) field‐effect mobility extracted from the corresponding transfer curves. (e–h) Electrical characterization of the p‐MoTe₂ FET using Cu₃(C₆O₆)₂ as the gate electrode: (e) schematic device architecture, (f) optical image of the fabricated device. The scale bar represents 10 µm, (g) transfer curves (gray line: leakage current), and (h) field‐effect mobility measured at different drain voltages.

We extended this validation to p‐type transport using MoTe₂ FETs (Figure 4e,f). The p‐MoTe₂ channel device was fabricated with a Cu₃(C₆O₆)₂ thin film serving as a single bottom‐gate electrode (Figure 4e). An optical image confirms that the source and drain electrodes, together with the patterned MOF gate, are properly aligned on the MoTe₂ flake (Figure 4f). The transfer characteristics exhibit clear p‐type behavior with a smooth and well‐defined gate response, demonstrating that the Cu₃(C₆O₆)₂ thin film effectively modulates the channel (Figure 4g). The output characteristics display linear I _d–V _d behavior at low drain voltages and a monotonic increase in drain current with increasingly negative gate bias, consistent with efficient hole accumulation in the MoTe₂ channel (Figure S17) [68]. Field‐effect mobilities extracted from the linear‐regime transfer curves show consistent hole transport across devices (Figure 4h), demonstrating that the Cu₃(C₆O₆)₂ MOF thin film serves as an effective gate electrode not only in n‐type MoS₂ but also in p‐type MoTe₂ systems.

To examine the scalability and reproducibility of MOF‐based electrodes in technologically relevant oxide semiconductors, top‐gate IGZO FETs were fabricated by depositing Cu₃(C₆O₆)₂ MOF thin film onto the Al₂O₃ dielectric layer (Figure 5a). Subsequent photolithographic patterning produced a well‐defined array of MOF gate electrodes aligned over the IGZO channels array (Figure 5b), enabling statistical evaluation of device‐to‐device uniformity across 23 individual transistors. All devices exhibit stable n‐type transfer characteristics with consistent gate‐dependent modulation (Figure 5c), confirming that the MOF electrode reliably controls electron accumulation in IGZO‐based field effect transistor. The output curves show linear behavior at low drain voltages and increasing drain current under positive gate bias (Figure 5d), consistent with standard IGZO transport behavior. Interesting to note is that the extracted transistor parameters display exceptionally narrow distributions: the threshold voltages cluster around 0.14 V with minimal variation (Figure 5e), and the field‐effect mobilities average 4.5  ±  1.5 cm² V⁻¹ s⁻¹ (Figure 5f), comparable to values reported for IGZO FETs employing conventional metal gate electrodes [69, 70, 71]. These results demonstrate that the patterned Cu₃(C₆O₆)₂ gate provides uniform gating across a large substrate without inducing performance instability or dielectric degradation. Such uniform operation across the array also highlights the importance of sufficient lateral conductivity of the MOF gate electrode, as a more resistive MOF film could lead to lateral voltage drops and thereby hinder uniform application of the gate potential across a large‐area array. The device maintained stable operation over 400 consecutive gate‐voltage cycles, with negligible changes in the transfer characteristics and comparable I–V characteristics of the MOF gate before and after cycling (Figure S18). Collectively, these findings establish that the patterned MOF thin film is compatible with large‐area oxide electronics and functions as a reliable gate electrode in both 2D and amorphous oxide semiconductor devices.

FIGURE 5.

Uniform and scalable operation of IGZO transistor arrays enabled by Cu₃(C₆O₆)₂ MOF gate electrodes. (a) Schematic device architecture. (b) Optical image of the device array fabricated on a pre–patterned IGZO substrate, showing MOF gate electrodes defined by photolithography. The scale bar represents 50 µm. (c) Transfer curves measured from 23 individual devices in the array. (d) Output characteristics of a representative device. (e) Histogram of threshold voltages extracted at V _D = 1.0 V. (f) Histogram of field‐effect mobilities extracted at V _D = 1.0 V.

3. Conclusion

We demonstrate that CVD‐grown Cu₃(C₆O₆)₂ MOF thin films can be uniformly deposited, patterned, and integrated as gate electrodes in semiconductor field‐effect transistors, enabled by their high electrical conductivity and suitable work function. Using a sequential APS–Cr etching strategy, FETs with patterned MOF gate were fabricated across three representative semiconductor systems such as MoS₂, MoTe₂, and IGZO, yielding stable and reproducible device operation. These results establish the practical integration of conductive 2D MOF thin films as gate electrodes within standard semiconductor device architectures. Beyond demonstrating gate operation, this work establishes an experimental platform for translating the chemically tunable electronic structure of MOF into electrostatic functionality in semiconductor devices. It further opens opportunities to explore MOF thin films as chemically programmable platforms, enabling their use as versatile device elements through the tailored design of key electronic properties, including band gap, work function, charge mobility, and carrier density.

4. Experimental Section

4.1. Materials

Bis(2,4‐pentanedionato)copper(II) (C₁₀H₁₄CuO₄, >97.0 % (T)) and tetrahydroxy‐1,4‐benzoquinone hydrate (C₆H₄O₆∙xH₂O, >96.0 % (T)) were purchased commercially from TCI and used without purification process. p‐Type SiO₂/Si substrates (285 nm thermally grown SiO₂ (dry oxidation), B‐doped, orientation: (100), single‐side polished, NAMKANG HI‐TECH Co., Ltd.) were diced into 11 mm × 11 mm pieces and used after sequential cleaning with deionized water, acetone, and isopropanol. Quartz tubes (Φ ₂₅ × t _1.5 × h ₆₀₀ mm, Dawon Materials Science) were used without any treatment. Test tubes (glass test tube, Φ ₁₀ × h ₁₀₀ mm, Daihan Scientific Co., Ltd.) were used to construct face‐to‐face inner tube system inside the quartz tube. Argon (99.999 %, Donghae Gas Ind. Co., Ltd.) was used as carrier gas. For device fabrication, Ammonium persulfate (APS, (NH₄)₂S₂O₈, >99.99 %) and chromium etchant (85% volatile) were purchased commercially from Sigma‐Aldrich and used without purification process. Dimethyl chlorosilane terminated PS (Product No. P3881–SSiCl) was purchased from Polymer Source. All 2D transition metal dichalcogenide flake were purchased from HQ graphene.

4.2. Synthesis of Cu₃(C₆O₆)₂ Thin Film by Chemical Vapor Deposition Method

Cu₃(C₆O₆)₂ thin films were synthesized in a tube‐type furnace (Lindberg/Blue M, model TF55030C–1) using a chemical vapor deposition (CVD) method, based on a previously reported procedure [50] but with deliberate modifications to optimize film morphology and surface uniformity. The mass ratio of Cu(acac)₂ to THQ was fixed at 1:3, and the amount of Cu(acac)₂ was varied from 0.1 mg to 0.4 mg to control the film thickness from approximately 10 nm to 50 nm. The two precursors were placed in separate test tubes and loaded into a quartz tube positioned inside the tube furnace. The test tube containing Cu(acac)₂ was placed 15.0 cm upstream from the furnace center, while the test tube containing THQ was placed 10.5 cm downstream from the furnace center. SiO₂/Si substrates diced into 1.1 cm × 1.1 cm pieces were sequentially rinsed with deionized water, acetone, and ethanol for 5 min each to remove surface contaminants, and then loaded into the quartz tube. The center of the substrate was positioned 1.5 cm downstream from the furnace center to collect the Cu₃(C₆O₆)₂ thin films. Prior to heating, the quartz tube was evacuated to 10 mTorr using a vacuum pump. The chamber was then purged with argon gas at a flow rate of 100 sccm for 10 min. After purging, the argon flow rate was adjusted to 20 sccm, resulting in an internal pressure of approximately 140 mTorr. The furnace temperature was then ramped to 205°C at a rate of 30°C per minute and maintained for 60 min to allow film growth. After the reaction, the furnace power was turned off and the lid was opened to allow natural cooling to room temperature. Once cooled, the Cu₃(C₆O₆)₂ thin films on SiO₂/Si substrates were collected for subsequent characterization and device fabrication. Compared with films reported in our previous study, the modified conditions yield significantly reduced surface roughness (2.86 nm vs. 10.7 nm).

4.3. MoS₂ and MoTe₂ Channel Device Fabrication

For the single‐gated device, SiO₂/Si substrates were sequentially cleaned with deionized water, acetone, and ethanol in an ultrasonicator. A 50 nm Cu₃(C₆O₆)₂ thin film, serving as the gate electrode, was then deposited on the substrates via CVD. After the CVD process, the gate electrode was patterned using a conventional photolithography method. For the first etching of the photoresist, the substrate was immersed in a 0.20 M APS solution for 30 s, followed by rinsing with deionized water. Subsequently, a second etching process was carried out by dipping the substrate in chromium etchant (Sigma Aldrich, Catalog No. 651826) for 1 s, followed by deionized water rinsing. For dielectric deposition, a 40 nm Al₂O₃ film was grown on the substrate using atomic layer deposition (ALD) at 100°C. Native Al₂O₃ surfaces contain a large number of hydroxyl groups and defects, which can induce surface traps and scattering during the transfer of MoS₂ and other transition metal chalcogenide (TMD) materials [72, 73]. To mitigate these issues, a PS‐brush (chemical structure) layer was deposited through the following procedure [73]. Dimethyl chlorosilane‐terminated PS (Polymer Source, product No. P3881–SSiCl) was dissolved in toluene (99.9%). The Al₂O₃ surface was pretreated by oxygen plasma (100 W, O₂ 50 sccm, 20 s). Subsequently, the PS‐brush solution (10 mg mL⁻¹) was spin‐coated onto the Al₂O₃ substrate and annealed at 170°C for 24 h in a vacuum oven to promote interfacial reaction between the PS chains and the Al₂O₃ surface. After annealing, unreacted PS was removed by rinsing with excess toluene, followed by an additional heat treatment at 100°C for 24 h in a vacuum oven. The resulting PS‐brush layer exhibited a final thickness of ∼6 nm. In the next step, MoS₂ flakes were mechanically exfoliated using polydimethylsiloxane (PDMS) and transferred onto the PS‐brush‐treated Al₂O₃ substrate. After the transfer, 50 nm gold source/drain electrodes were formed using conventional photolithography and a subsequent lift‐off process. Finally, post‐annealing was carried out using a rapid thermal annealing system at 250°C for 2 min to improve the contact between platinum and MoS₂.

For the double‐gated device, the fabrication steps up to the MOF gate electrode patterning and etching were identical to those of the MoS₂ single‐gated device. Subsequently, a platinum gate electrode was patterned next to the MOF gate using conventional photolithography and a lift‐off process, with platinum (15 nm)/titanium (5 nm) deposition performed by magnetron DC sputtering. The remaining steps, from Al₂O₃ deposition to post‐annealing, were the same as for the single‐gated device. For the MoTe₂ channel device, the fabrication process was identical to that of the MoS₂ single‐gated device, except for the source and drain metal fabrication. Platinum (30 nm) was used as the contact metal. The MoTe₂ device was annealed on a hot plate at 200°C for 2 min in ambient conditions to improve the metal/MoTe₂ contact and to enhance p‐doping of the channel [74].

4.4. IGZO Channel Device Fabrication

The indium–gallium–zinc–oxide (IGZO) was deposited RF‐sputtering and the channel was etched by wet etchant. Source and drain electrodes were then fabricated using conventional photolithography and a lift‐off process, with 5 nm titanium and 15 nm gold deposited by magnetron DC sputtering. Subsequently, a 7.5 nm Al₂O₃ dielectric layer was deposited by ALD at 200°C. To form the MOF gate electrode, a 100 nm Cu₃(C₆O₆)₂ film was deposited by CVD and patterned using conventional photolithography. The MOF etching was carried out in two steps: first, the substrate was immersed in a 0.20 M APS solution for 30 s, followed by DI water rinsing; second, the same substrate was dipped into the chromium etchant for 1 s, and again rinsed thoroughly with DI water.

4.5. Characterizations

Grazing incidence wide‐angle x‐ray diffraction (GIWAXS) patterns were collected using synchrotron radiation (λ = 1.23944 Å) at 3C beamlines respective of the Pohang Accelerator Laboratory (Pohang, Korea). Atomic force microscopy (AFM) images were obtained at 12D beamlines respective of the Pohang Accelerator Laboratory (Pohang, Korea), using NEASPEC nano‐FTIR near‐field scanning optical microscope. Transmission electron microscopy (TEM) were analyzed at the National Institute for Nanomaterials Technology (NINT, Pohang, Korea) using JEM–2200FS (JEOL, 200 kV) with image Cs‐corrector. Focused ion beam (FIB) was conducted at the national institute for nanomaterials technology (NINT, Pohang, Korea) using HELIOS 650 with EBSD. XPS analysis was carried out using a monochromated Al ka source (1486.6 eV) at a pressure of 4.8 × 10⁻⁹ mbar (AXIS SUPRA, KRATOS Analytical Ltd.). UPS analysis was performed with He Ia (21.22 eV) at a base pressure of 8.5 × 10⁻¹¹ torr. The secondary electron cutoff (SEC) was measured with −5 V of applied bias. All electrical measurements of the devices were performed with a semiconductor parameter analyzer (Agilent 4155C) in the dark at room temperature.

4.6. Mobility Measurement of MoS₂ and MoTe₂ FET

The field‐effect mobility was extracted from transfer characteristics measured in the linear regime of device operation. In linear regime, the drain current can be approximated as

$$\mu =\left(\frac{L}{W{C}_{\mathrm{OX}}{V}_{\mathrm{DS}}}\right)\times \frac{d\left(I_D\right)}{d{V}_{\mathrm{GS}}}$$

here, µ is the field‐effect mobility, C _ox is the gate‐dielectric capacitance per unit area, and W and L denote the channel width and length, respectively. The gate–dielectric capacitance C _ox was calculated by considering the series combination of the PS‐brush (thickness ∼ 6 nm, k ∼ 2.6) and Al₂O₃ dielectric layers. For MoS₂ and MoTe₂ field‐effect transistors, the total gate capacitance was calculated by treating the two dielectric layers as capacitors connected in series, yielding an effective capacitance of C _ox ∼ 121 nF/cm². For IGZO transistors, the yielding capacitance was calculated to be 944 nF/cm². For MoS₂ and MoTe₂ field‐effect transistors, the mobility was evaluated from the slope of linear‐regime transfer curves measured at low drain voltages, yielding gate‐dependent mobility values shown in Figure 4d,h. For IGZO transistors, the same extraction procedure was applied to devices measured at V _D = 1.0 V, and the resulting mobility values were statistically analyzed across 23 devices, as summarized in Figure 5f.

Funding

This work was supported by grants from the National Research Foundation of Korea (NRF), funded by the Korean government (RS‐2024‐00451160, RS‐2026‐25582850, RS‐2025‐25431788, and RS‐2024‐00347241).

Conflicts of Interest

The authors declare no conflicts of interest.

Supporting information

Supporting File: adma75003‐sup‐0001‐SuppMat.pdf

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.