High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Abstract

Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al₂O₃ nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm²/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

Graphene has attracted considerable interest as a potential electronic material due to its exceptionally high carrier mobility and tunable band gap (1–6). Various strategies have been explored to fabricate field-effect transistors based on graphene or graphene nanostructures (6–13). Most of these efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectric, which have led to many interesting scientific discoveries, but will be of limited use for practical applications due to the high-gate switching voltage required and the inability to independently address individual devices on the same chip. Top-gated devices with high-κ dielectrics can significantly reduce the required switching voltage and readily allow independently addressable device arrays and functional circuits, and therefore are of significant interest (14, 15).

The gate dielectric is an essential component of a transistor, which can significantly impact the critical device parameters including transconductance, subthreshold swing and frequency response. Exploring graphene for future electronics requires effective integration of high quality gate dielectrics, in particular the high-κ dielectrics. However, it has been rather challenging to deposit oxide dielectrics onto graphene without introducing defects. The deposition of high-κ dielectrics is usually achieved using atomic layer deposition (ALD), which requires reactive surface groups (16–20). Functionalization of graphene surface for ALD either introduces undesired impurities or breaks the chemical bonds in the graphene lattice, inevitably leading to a significant degradation in carrier mobilities (20). Physical vapor deposition (PVD) such as electron-beam evaporation or sputtering process has also been used to deposit dielectrics without the need of surface functionalization. Although the PVD process usually yields lower quality dielectrics and can also cause significant damages to graphene (21, 22). As a result, the mobility values observed in the top-gated devices are typically nearly one order of magnitude smaller than what can be achieved in the back-gated devices (20–23). Recently, the introducing of polymer or aluminum buffer layer for high-κ deposition was demonstrated with improved the device mobility (24, 25), which is still lower than that of the best back-gated graphene devices (1, 4, 5). To eventually realize high-performance graphene-based electronics, alternative approaches must be developed to deposit high quality high-κ dielectrics without damaging the pristine graphene.

Here we describe an entirely unique strategy to integrate graphene with high quality high-κ dielectrics using free-standing dielectric nanoribbons. Nanoribbons can be synthesized at high temperature with nearly perfect crystalline structure, but manipulated and assembled at room temperature. This flexibility allows the integration of normally incompatible materials and processes and can enable unique functions in electronics or photonics (26–30). In this report, the dielectric properties of aluminum oxide (Al₂O₃) nanoribbons are explored for graphene-based electronics. Specifically, high quality dielectric Al₂O₃ nanoribbons were first synthesized, and then transferred onto graphene as the gate dielectrics for top-gated graphene transistors. This integration approach preserves the pristine nature of the graphene and allows us to achieve the highest room temperature carrier mobility (up to 23,600 cm²/V·s) in top-gated graphene transistors to date.

Results and Discussion

Fig. 1 illustrates our approach to fabricate top-gated graphene transistors. Mechanically peeled graphene flakes on silicon substrate were used as the starting materials in initial studies, although the approach described here can be readily extended to graphene obtained through chemical exfoliation or chemical vapour deposition. Al₂O₃ nanoribbons were aligned on top of the graphene through a physical dry transfer process (Materials and Methods), followed by e-beam lithography and metallization process to define the source and drain electrodes (Fig. 1A). Oxygen plasma etch was then used to remove the exposed graphene, leaving only the graphene protected underneath the dielectric nanoribbon and the source drain electrodes (Fig. 1B). The top-gate electrode was then fabricated (Fig. 1C). A typical device consists of source, drain and top-gate electrodes (Ti/Au, 50 nm/50 nm), Al₂O₃ nanoribbon as the top-gate dielectric, a highly doped p-type silicon substrate (< 0.004 ohm·cm) as the back gate, and a 300 nm thermal silicon oxide layer as the back-gate dielectric.

Fig. 1.

Schematic illustration of the fabrication process to obtain top-gated graphene transistors using dielectric oxide nanoribbons as the etching mask and top-gate dielectric. (A) A dielectric nanoribbon is aligned on top of graphene using a dry-transfer process without any additional chemical functionalization to minimize the possibility of introducing defects/impurities into the graphene-dielectric interface, and the source-drain electrodes are fabricated by electron-beam lithography. (B) Oxygen plasma etch is used to remove the unprotected graphene, leaving only the graphene underneath the dielectric nanoribbon connected to two large graphene blocks underneath the source and drain electrodes. (C) The top-gate electrode is defined through lithography and metallization process.

Aluminum oxide, with a dielectric constant of 9.1, is an important high-κ material with excellent dielectric properties, thermal and chemical stability (30). In our studies, Al₂O₃ nanoribbons were used as an example to demonstrate our concept of using preformed free-standing nanoribbons as the top-gate dielectrics. Al₂O₃ nanoribbons were synthesized through a physical vapor transport approach at 1400 °C (Materials and Methods). Transmission electron microscope (TEM) studies show that the Al₂O₃ nanoribbons typically have a width of 1–3 μm, and a length on the order of 10 μm (Fig. 2A). Selected area electron diffraction (SAED) study shows the nanoribbon has a single crystalline α-Al₂O₃ structure, oriented along 〈110〉 direction in its long axis, and along 〈001〉 direction (c-plane) in its thickness (Fig. 2A and Inset). The high resolution TEM (HRTEM) image confirms that the nanoribbon is a single crystal with nearly perfect crystalline structure free of any obvious defects (Fig. 2B). Atomic force microscopy (AFM) studies show that the nanoribbons typically have a thickness around 15–150 nm (Fig. 2C), and nearly atomically smooth surface with root mean square roughness < 0.2 nm (Fig. 2D).

Fig. 2.

Evaluation of the Al₂O₃ nanoribbons as dielectric material. (A) TEM image (SAED pattern, Inset) and (B) HRTEM image of an Al₂O₃ nanoribbon show nearly perfect crystalline structure with α-Al₂O₃ structure. (C) AFM image of an Al₂O₃ nanoribbon with thickness approximately 50 nm. The image area is 5 μm × 5 μm. (D) AFM image of the surface of the Al₂O₃ nanoribbon, highlighting the smooth surface with a rms roughness < 0.2 nm. The image area is 250 nm × 250 nm. (E) The schematic device diagram (Inset) and SEM image of an Al₂O₃ nanoribbon metal-insulator-metal (MIM) device. (F) Current density-electric field (J-E) curve of an MIM device made from an Al₂O₃ nanoribbon, and the inset shows the corresponding (F–N) curve.

To understand the intrinsic dielectric properties of the nanoribbons, we have fabricated metal-insulator-metal (MIM) devices (Fig. 2E) to characterize the current tunnelling, breakdown, and dielectric characteristics. Electrical measurements of the MIM device show that current density (J) vs. electric field (E) relation exhibits typical Fowler–Nordheim (F–N) tunneling behavior with a breakdown field of 8.5 MV/cm (Fig. 2F and Inset), comparable to the best quality ALD Al₂O₃ film (31). This type of field-assisted tunnelling can be described by charge carrier tunnelling through a triangular barrier with

[1]

where

[2]

and

[3]

J is current density, E_ox is the oxide electric field, and m^∗ is the effective mass of the charge carrier, which is about 0.23 m_e, and Φ_B is the barrier height (31). Fitting the J - E characteristics with the F–N tunnelling model gives a tunnel barrier of about 2.0 eV between Al₂O₃ and Ti, comparable to previous reports of the barrier height between ALD Al₂O₃ and metals of similar work function (31, 32). The relative dielectric constant is also determined from capacitance-voltage measurement as 8.5, which is larger than typical values observed in ALD Al₂O₃ films (31). These studies clearly demonstrate that the Al₂O₃ nanoribbons have dielectric properties comparable to or better than the best quality ALD Al₂O₃ film (31), and can function as an excellent dielectric material for top-gated graphene transistors.

The Al₂O₃ nanoribbons can be aligned onto the top of the graphene through a physical transfer process (Materials and Methods). Previous studies have shown that the deposition of oxide on top of graphene often introduces significant defects into the graphene structure with an obvious defect band (D-band) emerging around 1350 cm^-1 in Raman spectra. To this end, we have employed micro-Raman spectroscopy to investigate the interaction between an Al₂O₃ nanoribbon and the underlying graphene (Fig. 3A and Inset). Micro-Raman spectra were collected from bare graphene (Point a) and Al₂O₃ nanoribbon covered graphene (Point b). Significantly, there is no clear difference between two Raman spectra and there is no obvious D-band (Fig. 3A), in contrast to previous studies where an obvious D-band is observed (33).

Fig. 3.

Characterization of the graphene/Al₂O₃ nanoribbon interface. (A) Raman spectra of the graphene with (Point b) and without (Point a) Al₂O₃ nanoribbon covering. The inset shows the optical image of an Al₂O₃ nanoribbon on graphene, the scale bar is 2 μm. There is no D-band in either spectrum, indicating that Al₂O₃ nanoribbon does not introduce any appreciable defects into graphene lattice. (B) A cross-section TEM image of the top-gate stack, the scale bar is 100 nm. The inset shows an SEM image of a typical device, the scale bar indicates 5 μm. The dotted line in the inset shows the cross-section cutting direction. (C) A cross-section HRTEM image of the interface between Al₂O₃ nanoribbon and a trilayer graphene. The partially incomplete grahene layers in the image are caused by electron-beam damage during the TEM imaging process.

The excellent dielectric properties observed in the single crystalline α-Al₂O₃ nanoribbons readily allows us to employ them as the gate dielectrics for top-gated graphene transistors (Fig. 3B and Inset). Cross-section TEM was used to study the graphene–dielectric interface (Fig. 3 B and C). The gate stack (SiO₂/graphene/Al₂O₃/Ti/Au) could be observed in Fig. 3B. The HRTEM image of the device shows that the graphene layers are intimately integrated with the crystalline Al₂O₃ nanoribbon without any obvious gap or impurities between them (Fig. 3C). Together, these studies clearly demonstrate that the physical assembly approach can effectively integrate Al₂O₃ nanoribbon with graphene without introducing any appreciable defects into the graphene lattice, and thus can effectively preserve the high carrier mobility in the resulting devices.

The electrical transport studies of the top-gated graphene transistors were carried out at room temperature. Fig. 4A shows the drain-source current (I_ds) versus drain-source voltage (V_ds) output characteristics of the transistor at various top-gate voltage (V_TG) of -1.5, -1.0, -0.5, 0.0, and 0.5 V. The device delivers an on current of 675 μA at V_ds = 1 V and V_g = -1.5 V. To evaluate the top-gated devices versus standard back-gated devices, we have measured the transfer characteristics, I_ds versus top-gated voltage (V_TG) and back-gated voltage (V_BG) (Fig. 4B and Inset). Significantly, the required gate voltage swing to achieve similar current modulation in top-gate configuration is > 1 order of magnitude smaller than that in back-gate configuration. The transconductance can be extracted from the I_ds-V_TG curve (Fig. 4C). At V_ds = 1 V, the top-gated device exhibits a max g_m of about 290 μS, which is about 15 times larger than that of the back-gated configuration (g_m ∼ 19.5 μS).

Fig. 4.

Room temperature electrical properties of the top-gated graphene device using Al₂O₃ nanoribbon as the gate dielectric. (A) I_ds-V_ds output characteristics, the channel width and length of the device is 2.1 μm and 4.1 μm. (B) Transfer characteristics at V_ds = 1 V for the device using top and back gate (Inset). (C) Transconductance g_m as a function of top-gate voltage V_TG, the inset shows the g_m vs. V_BG. The plots indicate the top gate g_m is about 15 times higher than the back-gate g_m. (D) Two-dimensional plot of the device conductance at varying V_BG and V_TG bias. The unit in the color scale is μS. (E) The top-gate Dirac point V_{TG_Dirac} at different V_BG. (F) Experimental plot (Black Line) and modeling fitting (Red Line) of R_tot vs. V_TG-V_{TG_Dirac} relation to derive the contact resistance and carrier mobility.

Fig. 4D further shows two-dimensional plot of the device conductance as a function of varying V_BG and V_TG bias, from which we can determine the top-gate Dirac point (V_{TG_Dirac}) shift as a function of V_BG (Fig. 4E). It gives the ratio between top-gate and back-gate capacitances, C_TG/C_BG ≈ 14.3. This gate capacitance ratio is consistent with the improvement factor (approximately 15) in transconductance of top- versus back-gated configurations. Using the back-gate capacitance value of C_BG = 11.5 nF/cm², the top-gate capacitance is estimated to be C_TG = 164.5 nF/cm², corresponding to a relative dielectric constant of 8.4 for Al₂O₃ nanoribbon, which is also consistent with the value obtained from MIM devices.

To further gauge the transistor performance, it is important to determine the carrier mobility. To accurately derive the mobility value, it is necessary to exclude the contact resistance that is comparable to the graphene transistor channel resistance. The total resistance of the device can be expressed as the following (25):

[4]

Where R_channel is the resistance of the graphene channel covered by top-gate electrode, the contact resistance R_contact consists of the uncovered graphene section resistance and the metal/graphene contact resistance, L is the channel length, W is the channel width, and n is the carrier concentration in the graphene channel region, and can be approximated by the following equation

[5]

where n₀ is the residual carrier concentration, representing the density of carriers at Dirac point (34); n_TG = C_TG(V_TG - V_{TG_Dirac})/e is the carrier concentration induced by the top-gate bias away from the Dirac point, C_TG can be approximated by the oxide capacitance of 164.5 nF cm^-2 (the quantum capacitance is neglected here as it is > 1 order of magnitude larger approximately 2000 nF cm^-2).

By fitting this model to the measured data in Fig. 4B, we can extract the relevant parameters, n₀, R_contact and μ. Fig. 4F shows the measured R_tot versus V_TG (Black Line), along with the fitted curve derived from Eq. 4 (Red Line). The fitted curve agrees well with the experimental data, with a single value of the residual concentration n₀ = 4.1 × 10¹¹ cm^-2, R_contact = 1240 Ω, and the mobility μ = 22,400 cm²/V·s, which represents the highest carrier mobility value observed in top-gated graphene devices to date. The fitted contact resistance R_contact =  ∼ 1240 Ω is comparable to the R_contact determined by four-probe measurements of similar devices (Fig. S1). The mobility value derived from top-gated configuration is also consistent with that obtained from back-gated measurement (25,600 cm²/V·s). We have studied multiple devices fabricated with the same approach, all of which exhibited carrier mobilities well exceeding 10,000 cm²/V·s (Table 1), comparable to the best reported values in back-gated devices and about one order of magnitude better than typical values previously reported for top-gated devices (17, 20, 21). The variation in mobility values is commonly seen in graphene-based devices (35), which may be attributed to variable local environment with different local potential, defects, impurities, or stress. Together, these studies clearly demonstrate that the presence of Al₂O₃ nanoribbon on top of graphene does not lead to any mobility degradation, in contrast to previous efforts in using ALD or PVD to deposit dielectrics on graphene.

Table 1.

The mobility values observed in multiple top-gate graphene transistors with variable Al₂O₃ thickness.

Device No.	1	2	3	4	5	6	7	8	9
Thickness (nm)	38	45	48	50	60	65	75	82	150
Mobility (cm2/V·s)	23600	22400	18200	22600	11200	15300	21100	11800	13300

Conclusions

In conclusion, a unique strategy has been demonstrated to integrate pristine graphene with high quality high-κ dielectrics by physically assembling free-standing oxide nanoribbons. Using the Al₂O₃ nanoribbons as the gate dielectrics, the top-gated graphene transistors have been fabricated to exhibit superior performance with the highest carrier mobility observed in top-gated device to date. This method opens a unique avenue to integrate high-κ dielectrics on graphene with the preservation of high carrier mobility. With further optimization of nanoribbon growth and assembly process to precisely control their physical dimension and spatial location (36–40), large arrays of top-gated graphene transistors or circuits can be envisioned. This physical assembly and integration approach can thus open a unique avenue to high-performance graphene electronics to impact broadly from high frequency high speed circuits to flexible electronics.

Materials and Methods

Synthesis of Al₂O₃ Nanoribbons.

Aluminum oxide (Al₂O₃) nanoribbons were synthesized through a physical vapor transport approach at 1400 °C. To grow Al₂O₃ nanoribbons, aluminum, and nanometer-sized Al₂O₃ powders with a molar ratio of 4∶1 were used as the starting materials. The ceramic boat with the mixture was placed at the center of a horizontal tube furnace and an alumina piece was placed at the downstream as the deposition substrate. The temperature was raised to target temperature with a flow of 400 sccm Ar as the carrying gas. The temperature was maintained for 1 h and then naturally cooled to the room temperature.

Dry Transfer of Al₂O₃ Nanoribbons.

The overall process involves physical transfer of Al₂O₃ nanoribbons directly from a Al₂O₃ nanoribbon growth substrate to a graphene substrate via contact printing. Specifically, a graphene device substrate is first firmly attached to a benchtop, and the Al₂O₃ nanoribbon growth substrate is placed upside down on top of the graphene substrate so that the Al₂O₃ nanoribbons are in contact with the graphene. A gentle manual pressure is then applied from the top followed by slightly sliding the growth substrate. The Al₂O₃ nanoribbons are aligned by sheer forces during the sliding process. The sliding process results in direct dry transfer of nanoribbons from the growth substrate to the desired graphene substrate. The sample is then rinsed with isopropanol followed by nitrogen blow-dry, in which the capillary drying process near the Al₂O₃ nanoribbons can help the Al₂O₃ nanoribbons to be firmly attached to the substrate surface.

Characterization of Al₂O₃ Nanoribbons, Device Fabrication, and Measurements.

The microstructures and morphologies of the Al₂O₃ nanoribbons were characterized by a JEOL 6700 SEM. The lattice image of the Al₂O₃ nanoribbons was observed by an FEI Titan HRTEM. The thickness was measured using atomic force microscope (AFM, Veeco Dimension 5000). Oxygen plasma (Diener Electronic) was used to selectively etch away the unprotected graphene region and leave graphene ribbons underneath the Al₂O₃ nanoribbon mask protection. The etch time is about 160 s at a power level of 40 W. The electrical transport properties were measured by a Lakeshore probe station with home built data acquisition system