Top-Gated Graphene Nanoribbon Transistors with Ultra-Thin High-k Dielectrics

Abstract

The integration ultra-thin high dielectric constant (high-k) materials with graphene nanoribbons (GNRs) for top-gated transistors can push their performance limit for nanoscale electronics. Here we report the assembly of Si/HfO₂ core/shell nanowires on top of individual GNRs as the top-gates for GNR field-effect transistors with ultra-thin high-k dielectrics. The Si/HfO₂ core/shell nanowires are synthesized by atomic layer deposition of HfO₂ shell on highly-doped silicon nanowires with a precise control of the dielectric thickness down to 1–2 nm. Using the core/shell nanowires as the top-gates, high performance GNR transistors have been achieved with transconductance reaching 3.2 mS μm⁻¹, the highest value for GNR transistors reported to date. This method, for the first time, demonstrates the effective integration of ultra-thin high-k dielectrics with graphene with precisely controlled thickness and quality, representing an important step towards high performance graphene electronics.

Graphene, a nearly perfect two-dimensional material, has generated a great deal of interest due to its extraordinary properties and potential applications.^1–5 It has been demonstrated that graphene exhibits many unique electronic characteristics, such as ultrahigh carrier mobility exceeding 200,000 cm²V⁻¹s⁻¹,⁶ a micrometer-scale mean free path, electron-hole symmetry, finite conductivity at zero charge-carrier concentration, and quantum hall effect.⁷ However, the zero band gap in graphene limits its potential applications in semiconductor technology. Formation of graphene nanostructures, such as nanoribbons or nanomeshes, with the critical dimension below 10 nm can open up an effective conduction band gap⁸ and enable semiconducting behaviour,^9–18 which makes these graphene nanostructures promising candidates for the fabrication of nanoscale transistors.^{19, 20}

To enable high performance graphene or graphene nanoribbon (GNR) transistors requires seamless integration of graphene with high quality high-k dielectric materials. However, deposition of oxide dielectrics on prstine graphene is not straightforward due to the strikingly different chemical nature of these two materials. In particular, it has been proven rather challenging to nucleate and grow a uniform thin layer of high-k dielectrics on graphene using atomic layer deposition (ALD).^{13, 21–25} To enable effective ALD deposition of oxide dielectrics on graphene requires surface functionalization that either introduces undesired impurities or breaks the chemical bonds in the graphene lattice. These additional processes can often result in a significant degradation in carrier mobilities.²⁶ Introduction of a polymer buffer layer prior to high-k deposition mitigates the potential damage to graphene lattice, ²⁷ but can limit the effective gate coupling due to the low-k polymer layer, and is practically not applicable for the integration of ultra-thin high-k dielectrics with graphene.

We have recently developed a new strategy to integrate high quality dielectric materials with graphene by first synthesizing free-standing oxide dielectric nanostructures at high temperature and then transferring them onto graphene at room temperature. This approach allows graphene-dielectric integration without introducing any appreciable defects into the carbon lattice, and has enabled the highest carrier mobility (>20,000 cm²/Vs) in top-gated graphene transistors.^{28, 29} In these studies, pure dielectric nanostructures are explored as the top-gate dielectrics for graphene transistors. The dielectric thickness is controlled by the overall dimension of the nanostructures and is difficult to scale down very small thickness (e.g. 1–2nm), due to the difficulties in synthesizing and assembling the oxide nanostructures at such small dimensions. On the other hand, it is of vital importance that one can integrate graphene with ultra-thin dielectric to push the performance of the device.

Here we report a method to fabricate top-gated GNR transistors with ultra-thin high-k dielectrics, by exploiting conductor/dielectric core/shell nanostructures (nanowires or nanoribbons) as the top gate, in which the high-k dielectrics are deposited on conducting (e.g. metal or highly doped semiconductor) nanostructures using ALD with a precise control of the thickness down to 1 nm regime. For example, we have synthesized Si/HfO₂ core/shell nanowires by ALD deposition of HfO₂ on highly-doped silicon nanowires. Using such core/shell nanowires as the top-gates, we have fabricated GNR transistors with the HfO₂ shell as the ultra-thin gate dielectric and the silicon nanowire core as the self-integrated gate electrode. This approach allows effective integration of ultra-thin high quality top-gate dielectrics with graphene, and preserves the integrity of the graphene lattice to afford GNR devices with the highest transconductance of 3.2 mS μm⁻¹ reported to date.

Figure 1 illustrates our approach to fabricate top-gated GNR transistors using a Si/HfO₂ core/shell nanowires as the top-gates. The core/shell nanowires were first aligned on top of mechanically peeled graphene flakes on silicon substrate through a physical dry transfer process, followed by an e-beam lithography and metallization process to define the source and drain electrodes (Fig. 1a and e). Oxygen plasma etch was then used to remove the exposed graphene, leaving only the graphene protected underneath the nanowire to form a GNR connected to two big blocks of graphene protected under the source and drain electrodes (Fig. 1b and f). To contact the silicon core gate to external electrode, the top-half of the dielectric shell is etched away using argon plasma (Fig. 1c and g), and the top gate electrode was deposited (Fig. 1d and h). A typical GNR device consists of source, drain and top gate electrodes (Ti/Au, 50 nm/50 nm), Si/HfO₂ core/shell nanowire as the top-gate, a highly doped p-type silicon substrate (<0.001 ohm·cm) as the back gate, and a 300 nm thermal silicon oxide layer as the back-gate dielectric.

Fig. 1.

Schematic illustration of the fabrication process to obtain top-gated graphene transistors using Si/HfO₂ coreshell nanowires as the etching mask and top-gate. (a) and (e), An Si/HfO₂ coreshell nanowire is aligned on top of graphene using a dry-transfer process, and the source-drain electrodes are fabricated by electron-beam lithography. (b) and (f), Oxygen plasma etch is used to remove the unprotected graphene, leaving only the GNR underneath the nanowire connected to two large graphene blocks underneath the source and drain electrodes. (c) and (g), The top-half of the HfO₂ shell was etched away using argon plasma to expose the silicon core gate for contact to external electrode. (d) and (h), The top gate electrode is defined through lithography and metallization process.

Hafnium oxide has been widely explored in silicon electronics due to its hardness, high chemical stability and excellent dielectric properties, including a high dielectric constant (~ 27), a wide band gap (~ 5.8 eV).³⁰ To grow Si/HfO₂ core/shell nanowires, the highly-doped silicon nanowires were first exposed to hydrogen fluoride (HF) vapour to remove the native oxide, and then immediately transferred into ALD chamber to grow HfO₂ shell with controlled thickness at 250°C by using tetrakis(dimethylamido) hafnium and water as the precursor and oxidant, respectively (Fig. 2a). The relative dielectric constant is determined to be ~15 based on capacitance-voltage measurement using a planar metal/HfO₂/Si control structure, consistent with previous reports on ALD deposited HfO₂ film.³¹ Transmission electron microscope (TEM) image show a uniform coating of the amorphous HfO₂ (dark contrast) surrounding the silicon core (light contrast) (Fig. 2b). High resolution TEM image clearly shows the single crystalline silicon core and amorphous HfO₂ shell of higher contrast (Fig. 2c). Additionally, there is a thin layer of SiO_x transition layer (~0.5 nm) of lower contrast between the silicon core and HfO₂ shell, which is also commonly seen in ALD HfO₂ film on planar silicon.^32–34 The HfO₂ film on Si nanowires is generally very smooth with few defects, suggesting that the thickness of HfO₂ could be readily controlled with a high degree of uniformity.

Fig. 2.

TEM characterization of Si/HfO₂ coreshell nanowires. (a) Schematic illustration of the synthesis of Si/HfO₂ coreshell nanowires. Highly doped p-type silicon nanowire arrays were synthesized using catalytic chemical vapour deposition. Atomic layer deposition was used to grow HfO₂ shell with controlled thickness. (b) TEM and (c) HRTEM images of Si/HfO₂ coreshell nanowires.

Figure 3a shows a typical top-gated GNR device with Si/HfO₂ core/shell nanowire as the top-gate. The gate length is about 500 nm and the diameter of the nanowire is 30 nm. Here the Si/HfO₂ core/shell nanowire also functions as a nanoscale etch mask to define a narrow GNR with width in the 10–20 nm regime through aggressive over etch. Cross-section TEM image was used to study the overall gate-stack integration and graphene-HfO₂ interface. The complete gate stack (SiO₂/graphene/HfO₂/Si/Ti/Au) could be readily observed in the low magnification cross-section TEM image (Fig. 3b). A high resolution TEM image of the grapheme-HfO₂ interface shows that the graphene layers are intimately integrated with the Si/HfO₂ nanowire without any obvious gap or impurities between them (Fig. 3c). A TEM image of multi-layer graphene device is shown here because it is very difficult to visualize the mono- or few-layer of graphene nanoribbon under the nanowire due to significant electron-beam damage while conducting TEM studies. Together, these studies clearly demonstrate that the physical assembly approach can effectively integrate an ultra-thin layer of HfO₂ with graphene.

Fig. 3.

Characterization of the graphene/HfO₂ interface. (a) A SEM image of a typical device. (b) A cross-section TEM image of the top gate stack. (c) A cross-section HRTEM image of the interface between nanowires and a multi-layers graphene, which indicate that the graphene layers are intimately integrated with the Si/HfO₂ nanowire without any obvious gap or impurities between them. A TEM image of multi-layer graphene device is shown here because it is very difficult to visualize the mono- or few-layer of graphene nanoribbon under the nanowire due to significant electron-beam damage while conducting TEM studies.

Electrical transport studies of the top-gated device were carried out in ambient condition at room temperature. We have first tested the gate leakage across the Si/HfO₂/GNR gate stack before transistor characterization. Importantly, the gate tunnelling leakage current (I_gs) from the Si/HfO₂ core/shell nanowire to the underlying GNR is negligible within the gate voltage range of ± 1 V range (Fig. 4a). This measurement demonstrates that the 2 nm HfO₂ dielectrics can function as an effective gate insulator for top-gated GNR transistors and afford high gate capacitance critical to the high transconductance. The drain-source current (I_ds) vs. drain-sourcevoltage (V_ds) plots at various top-gate voltages (V_TG) show clearly that the device conductance decreases as the gate potential increases towards positive direction (Fig. 4b), demonstrating that the GNR is p-type doped, which can be attributed to edge oxidation or the physisorbed O₂ from ambient or during the device fabrication process. Figure 4c shows the transfer characteristics drain-source current (I_ds) versus top-gated voltage (V_TG) curves for the same device at V_ds = 0.1 and 1.0 V. The transfer characteristics show the device can be switched on and off with < 1 volt of gate swing, the smallest on-off gate swing ever achieved in GNR transistors. The device delivers an on-current of 27 μA at V_ds = 1 V and V_g = −1.0 V, and shows a room temperature on/off ratio of ~ 70 at V_ds = 0.1 V, consistent with a GNR with estimated width of ~10 nm.^9–11 To evaluate the top-gated devices versus standard back-gated devices, we have measured the transfer characteristics, I_ds-V_TG and back-gated voltage (V_BG). Significantly, the required gate voltage swing to achieve a similar current modulation in top-gate configuration is more than one order of magnitude smaller dI than that in back-gate configuration (Fig. 4d). The transconductance $g_m=\frac{{dI}_{ds}}{{dV}_g}$ can be extracted from the I_ds-V_TG curve. The maximum g_m in the top-gated device at V_ds = 1V is about 32 μS (Fig. 4e), nearly 19 times of the value obtained in the back-gated configuration (~1.7 μS) (inset, Fig. 4e).

Fig. 4.

Room temperature electrical properties of the top-gated GNR device by using Si/HfO₂ coreshell nanowire as the top-gate. (a) Gate leakage current versus top-gate voltage. The leakage current is negligible within ± 1 V range. (b) I_ds-V_ds output characteristics at variable top-gate voltage starting from 0.6 V at bottom to −1.0 V at top in the step of −0.2 V. (c) The transfer characteristics I_ds-V_TG at V_ds = 0.10 and 1.0 V. (d) I_ds-V_TG and I_ds-V_BG transfer characteristics at V_ds = 1 V. (e) Transconductance as a function of top-gate voltage V_TG and back gate voltage V_BG (inset). (f) Two-dimensional plot of the device conductance at varying V_BG and V_TG bias, the unit in the colour scale is μS.

To further understand the device performance, it is important to determine the gate capacitance, which is not straightforward in our devices due to the complex geometry. To this end, we have employed three-dimensional finite element method to calculate the capacitance of the device, which yields an electrostatic capacitance (C_e) of 3530 nF/cm² for a 10 nm ribbon under a 30 nm Si/HfO₂ core/shell nanowire with 0.5 nm SiO_x and 2 nm HfO₂ shell. Significantly, these value is already larger than the quantum capacitance (C_q ~ 2000 nF/cm²) in graphene.³⁵ Taking the top-gate capacitance (C_top) as being the series combination of the electrostatic capacitance (C_e) and the quantum capacitance (C_q), we can obtain C_top = C_qC_e/(C_e+C_q) = 1276 nF/cm². Similarly, we can also calculate the back gate capacitance per area C_back1= 135 nF/cm² for section without top-gate metal electrode covering, and C_back2 = 11.5 nF/cm² for the part with top-gate metal electrode covering. The substantial differences are due to the screening effect of the top-gate metal electrode that can significantly decrease (by ~ 1 order of magnitude) the spreading electric field from the back gate. Based on these calculations, a capacitance ratio between the top-gate and the back-gate configuration can be obtained: (C_Top·W·L)/(C_Back1·W· (L-L_top)+C_Back2·W·L_top) = ~18.5, where, W is the GNR width, L is the whole channel length, L_top is width of top-gate metal electrode. To experimentally confirm this capacitance ratio, we have measured the deviceconductance as a function of both V_BG and V_TG bias (Fig. 4f). This measurements give threshold voltage (V_t) shifts in the top-gate configuration as a function of the applied V_BG (Fig. 4f), which can yield the experimental capacitance ratio between top-gate and back-gate configuration, C_TG/C_BG≈20, consistent with finite element calculation described above. This capacitance ratio is also roughly consistent with the transconductance ratio between the top- and back-gate configurations. Based on these capacitance analyses, we can calculate the hole mobility in the GNR device to be $\mu =\frac{g_{m}L}{C_{\mathit{top}}{V}_{ds}W}=880{\text{cm}}^2/\text{Vs}$, comparable to the best values reported in GNR transistors.²⁹

It is interesting to compare the top-gated GNR devices with the state-of-the-art silicon MOSFETs. The effective on-current I_on for a transistor is usually characterized at V_ds= V_g(on-off) = V_dd, where V_g(on-off) is the gate voltage swing from off- to on-state and V_dd is the power supply voltage. Considering V_ds = V_g(on-off) = V_dd = 1V, the I_on of our device at V_ds =1V and 1 V gate swing from the off state is ~27μA. Taking the channel width of the GNRs ~ 10 nm, we obtain the scaled values of I_on and g_m of our device to be ~2.7 mA μm⁻¹ and ~ 3.2 mS μm⁻¹, exceeding the typical values in sub-100-nm silicon p-MOSFET and n-MOSFET (0.7 mA μm⁻¹ and 0.8 mS μm⁻¹ for p-MOSFET, and 1.66 mA μm⁻¹ and 1.3 mS μm⁻¹ for n-MOSFET) employing high-k dielectrics,³⁶ and is the highest value reported for GNR transistors.²⁹ This is significant because high transconductance is critical to the performance of transistors and voltage gains of transistor-based devices including amplifiers and logic gates.

In conclusion, we have described a rational strategy to integrate pristine graphene with ultra-thin high-k dielectrics, and for the first time demonstrated the fabrication of high performance top-gated GNR transistors with a dielectric thickness as small as 2 nm. This method opens a new avenue to integrate high-k dielectrics on graphene with a precise control of dielectric thickness and quality, and can thus open a new avenue to high performance graphene electronics to impact broadly from high speed circuits to flexible electronics.