An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

Abstract

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm² of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested.

I. Introduction

Implantable microelectronic devices (IMD) powered by internal batteries suffer from their large volume, limited lifetime, replacement hardship, and cost. Therefore, they are only suitable for medical treatments with ultra low power requirements, such as pacing the heart, which have extended battery lifetimes in the range of several years [1]. On the other hand, there are treatments, such as neuroprostheses like cochlear and retinal implants, which require orders of magnitude higher currents for stimulation or recording regardless of the circuit efficiency [2]. There are also applications such as radio frequency identification (RFID), in which the size and cost of neither primary nor secondary (i.e., rechargeable) batteries are justified [3]. To address these limitations, wireless power transmission techniques using inductive links have been utilized to supply size-, cost-, and power-constrained devices and applications.

Inductively powered systems in general consist of three main components: reader, inductive link, and transponder, as shown in Fig. 1. On the reader side, which is also the power transmitter, a power amplifier drives the primary coil, L₁, at the power carrier frequency, f_c. This signal is induced on to the secondary coil, L₂, through the inductive link, and generates an ac voltage across the transponder resonance circuit, L₂ and C₂. Following the L₂C₂ tank, there is always a rectifier to convert the ac signal to dc (V_REC) for supplying the rest of the transponder. The efficiency and performance of this rectifier, which is the focus of this article, is key to the overall power efficiency of the system, because all the usable received power passes through it. Since the dc voltage varies significantly with the coils’ relative distance, d, and alignment, a low dropout regulator often follows the rectifier for providing a constant supply voltage, V_DD, to the IMD or RFID load.

Fig. 1.

Block diagram of an inductively powered implantable microelectronic device (IMD) with emphasis on the power transmission/conditioning circuitry.

Considering the power flow from the external energy source (i.e., the battery) to the load, R_LR, the total power conversion efficiency (PCE) can be calculated from

$${\eta }_{\text{total}}={\eta }_{PA}\times {\eta }_{\text{link}}\times {\eta }_{\text{rectifier}}\times {\eta }_{\text{regulator}}$$ (1)

where η_PA, η_link, η_rectifier, and η_regulator are the efficiencies of the power amplifier, inductive link, rectifier, and regulator, respectively. Achieving higher PCE (η_total) is very important in inductively powered applications because it allows IMDs to operate with smaller received power from a larger distance. Lower received power also reduces the risk of tissue damage from overheating [2]. In the IMD applications, η_link is limited due to the size constraint of the secondary coil [4]. The regulator, on the other hand, already has a high η_regulator because of its low dropout topology. Therefore, improving the rectifier PCE (η_rectifier) is a key factor for safe IMD operation.

Passive rectifiers using diodes or diode-connected transistors have been used in the past for inductively powered applications [5]–[9]. However, PN junction diodes induce large forward voltage drops and power dissipation. Schottky diodes have low dropout voltages [10]. However, they have a high leakage current, they are not available in most standard CMOS processes, and may need extra fabrication steps. Their reverse breakdown voltages may not be high enough either. Several V_Th cancellation techniques have been proposed to reduce the passive diode voltage drop [11]–[14]. However, these are sensitive to process variations and still unable to provide high PCE. Therefore, active synchronous rectifiers using comparator controlled rectifying switches are currently considered the most promising solutions for increasing the PCE in ASICs [15]–[24]. In these rectifiers, voltage drop across the main rectifying switches is much lower than the diode voltage drop, dissipating less power within the rectifier. We previously reported power efficient active rectifiers using phase lead in [16] and [24]. The maximum operating frequency of those rectifiers, however, was limited to 1–2 MHz. Active rectifiers need significantly faster comparators to drive their switches at the right times for higher carrier frequencies, such as 13.56 MHz in the Industrial, Scientific, and Medical (ISM) band, and maximize the forward current flow, while minimizing the reverse currents.

In this paper, we propose an integrated power efficient active rectifier with offset-controlled high speed comparators for inductively powered applications. Comparators are equipped with offset control functions to compensate for both turn-on and turn-off delays, optimizing the power transfer from the secondary coil to the load (regulator). Section II presents the operating principles and the PCE analysis of our new active rectifier architecture. Section III describes the concept, implementation, and effects of the proposed offset-control functions on the high speed comparators. The simulation and measurement results are depicted in Section IV, followed by conclusions in Section V.

II. Active Rectifier Architecture

A. Operating Principle and Implementation

The new full-wave active rectifier employs a pair of high-speed comparators (CMP₁ and CMP₂) to drive the main rectifying elements (P₁ and P₂) in Fig. 2. Ideally, the input voltage of the rectifier, V_IN = V_IN1 − V_IN2, has a sinusoidal waveform. Hence, P₁ and P₂ turn on alternatively depending on the polarity and amplitude of V_IN.

Fig. 2.

Schematic diagram of our active rectifier including offset-controlled high speed comparators, dynamic body biasing, and load shift keying (LSK) back telemetry functions.

When V_IN > V_ThN (the NMOS threshold voltage) and |V_IN| < V_REC, the positive feedback operation of the cross-coupled NMOS pair (N₁ and N₂) connects V_IN2 to V_SS through N₂ and turns off N₁. In this case, CMP₂ output goes high because V_REC > V_SS, and P₂ is turned off. P₁ also remains off as long as |V_IN| < V_REC. When |V_IN| > V_REC, CMP₁ output goes low and turns P₁ on. Therefore, current flows from V_IN1 to V_REC, and charges the rectifier’s resistive/capacitive load (R_LC_L). In the next half cycle, when V_IN < –V_ThN, V_IN1 is connected to V_SS through N₁, N₂ turns off, and both P₁ and P₂ are also initially off for the period of |V_IN| < V_REC. Then, after |V_IN| > V_REC, CMP₂ turns P₂ on and current flows from V_1N2 to V_REC to charge the resistive/capacitive load again.

To avoid latch-up and substrate leakage problems among P₁ and P₂, potentials at their separated N-well body terminals (V_B1 and V_B2) need to be the highest potentials on-chip. We adopted the dynamic body bias control technique from [6] and [25] by utilizing auxiliary PMOS transistors, P₃ to P₆. With this method, V_B1 and V_B2 are automatically connected to the highest potential between the input voltages, V_In1 and V_IN2, and the output voltage, V_REC, of the rectifier.

B. Back Telemetry and Overvoltage Protection

To add back telemetry capability, which is desired to inform the reader about the status of the IMD, deliver measured biosignals, or close the power control loop [26], [27], we have employed the load shift keying (LSK) scheme by shorting the secondary coil, L₂, with the short-coil (SC) data signal [9]. A pair of NMOS switches, N₃ and N₄, has been added in parallel to the cross-coupled N₁ and N₂, respectively. When the data signal is high, the input nodes of the rectifier are shorted together, leading to increased secondary quality factor, Q₂, and increased voltage across the primary coil, L₁. Back telemetry data from the transponder to the reader is detected by sensing these variations across the external LSK sensing block in Fig. 1.

V_IN highly depends on the coils mutual coupling, M, which is in turn highly dependent on the coils separation, d, and alignment [4]. Loading variations also change Q₂ and affect V_IN even when M is constant. Unexpected variations in M and R_LR may cause V_REC to exceed the safe voltage limits of the application or fabrication process and result in transistor breakdown. To prevent this problem, we have added an overvoltage protection (OVP) circuit to the rectifier by comparing a quarter of V_REC with a constant reference voltage. When V_IN exceeds a certain level, the comparator output goes high and a detuning capacitor (Covp) is added in parallel across the secondary tank circuit, as shown in Fig. 1, to reduce V_IN by detuning it. The advantage of this method over current leakage based techniques [10] is that no extra heat is dissipated within the ASIC and IMD as a result of this protective safety measure.

C. PCE Analysis and Considerations

PCE depends on the size of the rectifying PMOS and the cross-coupled NMOS pairs because these transistors are in the main current path. For example, when V_IN1 – V_IN2 > V_REC, P₁ and N₂ turn on and open a current path to the load, as shown in Fig. 3. In this case, the total lost power, P_Loss;total, will be dominated by the switching loss of P₁(P_Loss,Cgp), R_on loss of P₁ (P_Loss,Ronp), and R_on loss of N₂ (P_Loss.Ronn). Since the gate of N₂ is always connected to the input node of the rectifier, there is negligible switching loss for charging and discharging the gate capacitance of N₂. Therefore, P_Loss,total can be approximated by

Fig. 3.

Simplified schematic diagram of the active rectifier depicting the current path and power dissipating components when V_IN1 – V_IN2 > V_REC.

$$\begin{array}{l}{P}_{\text{Loss},\text{total}}=P_{\text{Loss},C_{gp}}+P_{\text{Loss},R_{\mathit{onp}}}+P_{\text{Loss},R_{\mathit{onn}}}\\ =C_{gp}{V}_{\text{REC}}^{2}2f_c+I_p^2{R}_{\mathit{onp}}{D}_{\text{eff}}+I_n^2{R}_{\mathit{onn}}{D}_{\text{eff}}\\ =W_p{C}_{gp}^{\ast }{V}_{\text{REC}}^{2}2f_c+{\left(\frac{V_{\text{REC}}}{R_L{D}_{\text{eff}}}\right)}^2\times D_{\text{eff}}(R_{\mathit{onp}}+R_{\mathit{onn}})\end{array}$$ (2)

where $C_{gp}^{\ast }$ is the gate capacitance per unit width of P₁, f_c is the carrier frequency (13.56 MHz), D_eff is the effective duty cycle including comparator delay, and W_p is the width of P₁.

In this design, we have assumed W_n = W_p for the sake of simplicity. However, we have also proven in [24] that the optimal size ratio of the PMOS and NMOS transistors can be found from

$${\left(\frac{W_p}{W_n}\right)}_{\mathit{opt}}=\sqrt{\frac{K_n·(V_{\text{REC}}-V_{\mathit{ThN}})}{K_p·(V_{\text{REC}}-\mid V_{\mathit{ThP}}\mid )}}$$ (3)

where K_p =μ_pC_ox and K_n = μ_nC_ox are the PMOS and NMOS transconductances, respectively. One should note that even though larger transistor size decreases the R_on loss, it increases the switching loss and comparator delays due to the larger gate capacitance. Therefore, the main rectifying transistors have an optimal size for minimum power dissipation depending on f_c and R_L, which should also comply with the total chip area that is allocated to the rectifier [24].

T_PHL and T_PLH, the turn-on and turn-off delays of CMP_1,2, affect the rectifier PCE because these delays hinder P_1,2 switches from turning on and off at proper times and cause back current. Our model considers the size of the rectifying transistors and comparator delays to estimate the maximum PCE. In the Appendix, we have defined W_p, R_onp + R_onn, and D_eff as functions of the switching duty cycle (D), T_PHL, and T_PLH, and differentiated (2) with respect to D to minimize P_Loss,total. With the power loss from (2), we can estimate the maximum PCE of the rectifier

$${\eta }_{\text{rectifier}}=\frac{P_{\text{Load}}}{P_{\text{Load}}+P_{\text{Loss},\text{total}}+2P_{\text{Comparator}}}$$ (4)

where P_Load is the output power, and P_comparator is the total power consumption of each comparator excluding the charging and discharging power consumption of P_1,2 gates, which has already been considered in P_Loss.total.

Fig. 4 shows the calculated rectifier PCE versus W_p for various comparator delays, using parameters from the ON Semi 0.5-μum standard CMOS process. In this calculation, we assume that P_Load = 20 mW, V_REC = 3.2 V, R_L = 500 Ω, and P_comparator = 0.1 mW, which are based on the simulation results. It can be seen that with W_p = 2100 μm and T_PHL = T_PLH = 0 ns, the rectifier achieves the highest PCE of 92%. This is the theoretical upper limit for the PCE that can be obtained by choosing optimized transistor width and eliminating the effect of comparators’ delay by utilizing offset-controlled high speed comparators that are described in Section III.

Fig. 4.

Calculated rectifier power conversion efficiency (PCE) versus W_p depending on the comparator delays when V_REC = 3.2 V and R_L = 500 Ω. Curve-a: T_PHL = 0 ns and T_PLH = 0 ns; Curve-b: T_PHL = 5 ns and T_PLH = 0 ns; Curve-c: T_PHL = 0 ns and T_PLH = 3 ns; Curve-d: T_PHL = 3 ns and T_PLH = 3 ns; Curve-e: T_PHL = 0 ns and T_PLH = 4 ns; and Curve-f: T_PHL = 4 ns and T_PLH = 4 ns.

III. Offset-Controlled High Speed Comparators

A. Concept of the Offset-Control Function

In order to drive the large rectifying PMOS transistors at high operating frequency of 13.56 MHz, high speed comparators with low power consumption and high driving capability are required. Typically, the comparator operating speed is limited by its propagation delay, T_P, which is how quickly the output responds to a change at the input. In this rectifier application, the comparator propagation delay adversely affects the PCE. Due to T_PHL, the comparators turn P_1,2 on too late and reduce the input power that could otherwise be transferred to the load during this delay. Moreover, due to T_PLH, comparators lag in turning P_1,2 off, and current can instantaneously flow from C_L back to the secondary coil when V_IN < V_REC.

Since it is not possible to reduce T_P to zero, in order to overcome such limitations, we have utilized offset control function in the high speed comparators used in this rectifier. Fig. 5 shows the block diagram of this comparator, which consists of a common-gate type comparator (CG Cmp), two offset-control blocks (Offset_F and Offset_R), and current-starved (CS) inverters. Offset-control blocks inject a programmable offset current, OS_F and OS_R, to the inputs of the CG comparator alternately depending on the state of the V_OUT feedback signals, FB_F and FB_R. Therefore, V_OUT expedites the falling or rising transition by sensing them ahead of time.

Fig. 5.

Block diagram of the high speed comparator employing offset control functions for both falling and rising V_OUT transitions.

Segment-(a) in Fig. 6 exhibits a falling V_OUT transition, occurring when |V_IN| = |V_IN1 – V_IN2| > V_REC. At this point, the CG comparator output, V_OUT, falls to turn on P₁ (or P₂). FB_F is low during this period, and only the Offset_F block operates to inject offset current to the negative input of the CG comparator. With the help of Offset_F, V_OUT can be forced to fall even before |V_IN| exceeds V_REC at the end of segment-a, compensating for the comparators’ turn-on delay. It is important, however, to note that Offset_F has to be turned off after the V_OUT falling transition so that it does not affect the following V_OUT rising transition. Otherwise, Offset_F can delay the rising V_OUT transition, which is counterproductive. This is why in Fig. 5 the Offset_F block receives a feedback signal from V_OUT and properly turns off after every falling transition of V_OUT.

Fig. 6.

Simulated waveforms and timing diagram showing the operation of the offset-control blocks in the high speed comparators.

On the other hand, during the V_OUT rising transition in segment-(b), when |V_IN| < V_REC, FB_R that has gone low after V_OUT falling, turns on the Offset_R block. The Offset_R block injects offset current to the positive input of the CG comparator and can force V_OUT to start rising even before |V_IN| falls below V_REC. This helps P₁ (or P₂) to turn off at a proper time and prevents the back current.

If the Offset_R block turns on just after V_OUT starts to fall, this instantaneous negative feedback mechanism hinders V_OUT from falling down fully and causes V_OUT to fluctuate. To avoid this problem, we have added two current-starved inverters in the feedback loop to add a delay between V_OUT, FB_F, and FB_R transitions, thus assuring stable comparator feedback operation. This delay does not need to be precise as long as it is less than one carrier cycle period. It results in a short period, segment-(c), during which both Offset_F and Offset_R blocks are on.

B. Circuit Implementation

Fig. 7 shows the schematic diagram of the high speed comparator with two offset-control functions, Offset_F and Offset_R. Without considering offset-control blocks and CS inverters, it basically works as a simple common-gate comparator with start-up capability [15]. Two input voltages, V_REC and V_IN1, are applied to the sources of input transistors, P₇ and P₈, respectively. When V_IN1 > V_REC, the current flowing through P₈ becomes larger than that of P₇. Therefore, the gate voltage of the output inverter, V_A, rapidly increases, and V_OUT falls to turn P₁ on. The Offset_F and Offset_R blocks are implemented by using current sources, P₁₃–P₁₄ and P₁₀–P₁₁, within the comparator, MUXs, and the control switches, P₁₅ and P₁₂. These blocks inject offset currents to the comparator inputs alternatively, inducing the desired timing. For example, when V_OUT is high, P₁₅ turns on, and an offset current flows into the comparator positive input branch (V_REC) through OS_F, causing V_A to increase. Therefore, V_OUT starts to fall earlier before V_IN1 exceeds V_REC. The offset current is programmable by using 2-bit off-chip control signals per offset-control block, CTL0:1 and CTL2:3, in order to adjust the rectifier timing in response to process variations.

Fig. 7.

Schematic diagram of the high speed comparator with two offset-control functions, Offset_F for the V_OUT falling edge and Offset_R for the V_OUT rising edge.

C. Effects of Offset-Control Functions on PCE

Simulation results depicting the relationship between the PCE and offset-control functions are shown in Fig. 8. To understand the effects of the offset-control functions better, we have overlapped the rectifier input/output voltages, input current, and input power waveforms while adjusting V_IN amplitude to achieve a constant V_OUT = 3.2 V for R_L = 500 Ω. Fig. 8(a) shows that with no comparator offset-control function in place, the back current resulting from the turn-off delay severely degrades the PCE. This back current can be prevented by using the Offset_R function, as shown in Fig. 8(b). Even though Offset_R improves the PCE significantly, the input power to the rectifier is still being reduced due to the comparators’ turn-on delay, T_PHL. Therefore, there is room to further improve the rectifier PCE as well as voltage conversion efficiency (VCE) by using both Offset_F and Offset_R functions to compensate for T_PHL and T_PLH delays, respectively. Fig. 8(c) clearly shows that with both functions in place V_OUT transitions happen at the right times, and the PCE is maximized.

Fig. 8.

Simulation results of the active rectifier showing waveforms of the input/output voltages, input current, and input power with V_REC = 3.2 V and R_L = 500 Ω, (a) without any offset-control function, (b) with only Offset_R function, and (c) with both Offset_F and Offset_R functions.

Since the offset-control blocks consume additional power to provide the offset currents, the power overhead for employing these functions needs to be considered. Fig. 9 shows the simulated comparator power consumption versus V_REC and its break down between the two blocks. When V_REC increases, the power consumption of the CG comparator, curve-(b) also increases, contributing a large portion of the comparator power consumption, curve-(a). This is because both the static current of the CG comparator and the shoot-through current of the output inverter increase with V_REC. Moreover, since the comparator offsets have been tuned for V_REC = 3.12 V, power consumption becomes more severe at higher V_REC. On the other hand, curve-(c), the offset-control blocks’ power consumption shows a mild increase when V_REC increases. It is because the offset-control blocks consume only dynamic power for a short period. For V_REC = 3.12 V, the entire high speed comparator consumes 135 μW, 40 μW of which is the power consumption of the offset-control blocks. The entire comparator power consumption is little affected by the load conditions as long as V_REC is fixed.

Fig. 9.

Simulated power consumption of the comparator versus V_REC showing power overheads for employing the offset-control functions (f_c = 13.56 MHz, R_L = 500 Ω, and C_L = 10 μF). Curve (a) shows the total power consumption of the high speed comparator, (b) is the power consumption of the CG comparator and CS inverters, and (c) indicates the consumption of the offset-control blocks.

D. Startup Capability

Since no supply voltage is available before the active rectifier starts its operation, it is necessary for the rectifier to have self startup capability. Our high speed comparator, shown in Fig. 7, has a common-gate input stage, in which the two comparator input voltages, V_IN1 and V_REC, are also the positive supply voltages. Hence the rectifier sinusoidal input voltage, V_IN1,2, guarantees that the rectifier reliably starts up even before V_REC is sufficiently charged up. For example, when V_REC = 0 V, the input voltage of the output inverter, V_A, follows V_IN1 through P₈, since N₆ is turned off. Therefore, when V_IN1 > V_ThN7, V_OUT of the comparator will be connected to V_SS through N₇ leading the rectifying PMOS to turn on and charge V_REC.

Since the comparator bias current is generated by P₇–P₉–N₅ branch, it properly turns on when V_REC > V_ThP7 + V_ThN5. On the other hand, when 0 < V_REC < V_ThP7 + V_THN5, the comparator still turns on the rectifying PMOS for conducting current to V_REC, as explained above, but it does not turn them off at the right time, resulting in back current. Now, if V_IN,_peak is high enough (> 2.9 V in our design), then it will be sufficient for charging V_REC to surpass the V_THP7 + V_THN5 level even in the presence of the back current. While V_REC is being charged, the gate voltage of N_5,6 also increases, and V_A decreases to turn off the rectifying PMOS during V_IN1 < V_REC. Moreover, the comparator operation and the rectifier PCE move towards their optimal points as V_REC increases toward the target value of 3.12 V. Therefore, once V_REC exceeds V_ThP7 + V_ThN5, it can easily charge up to 3.12 V. Fig. 10 shows simulated waveforms for the rectifier self startup process, which guarantees that V_REC is charged up to 3.12 V when V_IN,peak = 3.4 V (3.8 V in measurements). In this design, for an input voltage of V_IN,_peak = 2.9 V (3.2 V in meas.), the suboptimal operation of the rectifier results in V_REC = 2.5 V.

Fig. 10.

Simulated waveforms for self startup operation of the active rectifier (f_c = 13.56 MHz, V_IN,_Peak = 3.4 V, V_REC = 3.12 V, R_L = 500 Ω, and C_L = 2.5 nF).

IV. Simulation and Measurement Results

The active rectifier was fabricated in the ON Semiconductor 0.5-μm 3M2P standard CMOS process (minimum transistor length of 0.6 μm) for its relatively high voltage handling capability. Fig. 11 shows the chip micrograph, which includes the active rectifier, overvoltage protection circuit, and the low dropout regulator, occupying 0.4 mm² of the Si area with Wp/L_p = W_n/L_n = 2100 μm/0.6 μm. Since each comparator offset-control function can be enabled or disabled by external control lines, we were able to evaluate the rectifier performance with and without the comparator offset functions.

Fig. 11.

Fabricated chip micrograph and its floor plan, including the active rectifier, overvoltage protection circuit, and low dropout regulator.

A. Measured Waveforms and Parasitic Effects

Fig. 12 shows the lumped model of the circuit used in the rectifier measurements with emphasis on the inductive and capacitive parasitic components, which combined with the measurement instrument (oscilloscope) parasitic, cause distortion in the measured waveforms at this relatively high operating frequency (f_c = 13.56 MHz). For instance, when the rectifier starts conducting, there is a sudden drop in V_IN1 – V_IN2, and when it stops conducting, the stored energy in the interconnect inductors cause a sudden voltage hike across the rectifier inputs. Therefore, it is important to note that the voltages measured across the coil or load, V_XY, are not exactly the same as those measured on the rectifier packaged IC pins, $V_{XY}^{\ast }$ (LQFP176). For example, L_bond, the parasitic inductance of the wirebond, and L_wire, the parasitic inductance of the external interconnects, cause the rectifier input voltage at the package, $V_{\text{IN}1}^{\ast }-V_{\text{IN}2}^{\ast }$, to be distorted and have a peak voltage higher than the sinusoidal input voltages at the secondary coil, V_IN1 – V_IN2.

Fig. 12.

Lumped model of the circuit used in active rectifier simulations, showing capacitive and inductive parasitic components of the wire-bond and external interconnects. It is important to note that because of these parasitics, voltages measured on the coil or load, V_Xy, are not exactly the same as those measured on the asic package (lqfp176), V_Xy*.

Moreover, the instantaneous input current flows into the rectifier through the parasitic inductors only during the rectifier turn-on, which is much shorter than one operating cycle (see Fig. 8(c). Therefore, the frequency components, which affect the parasitic inductors and distort the voltage waveforms, are effectively much higher than the carrier frequency at 13.56 MHz. Unfortunately, this effect has not been considered in the recent literature on active rectifiers, and consequently, depending on how the measurements are done, the reported results on the rectifier efficiency might have been optimistic.

Fig. 13 shows the active rectifier measured input and output voltage waveforms. In these measurements we refrained from directly probing V_OUT because it could load and affect the comparator performance. Instead, C_L was reduced from 10 μF to 100 pF to better show the effects of offset-control functions. For all measurements and simulations in this section, we enabled the Offset_R to prevent the back currents. When the Offset_F function was enabled, V_REC started to increase ~ 5 ns earlier than without Offset_F. This comparison, which is consistent with the simulation results in Fig. 8, shows that the comparators turn the rectifier on faster to deliver current for a longer time period. Therefore, the Offset_F function not only improves the PCE but also reduces the rectifier dropout voltage, V_drop, which is defined as the difference between V_IN1,Peak* and V_REC. There is also a small phase shift between the ripple on V_REC and V_IN1,2* due to the parasitic components.

Fig. 13.

Measured waveforms of the input and output voltages of the rectifier with and without the Offset_F function (f_c = 13.56 MHz, V_IN,peak = 4.1 V, R_L = 500 Ω, and C_L = 100 pF).

B. PCE and Dropout Voltage Measurements

We measured the PCE and V_drop by sweeping 1) V_REC ;2) R_L connected directly across the rectifier, substituting the regulator; and 3) f_c. In order to measure the rectifier input current, we connected a small resistor, R_sense = 10 Ω, in series with the rectifier input as a current sensor and differentially measured the voltage across it. The rectifier input power was calculated offline by integrating the instantaneous product of the input current and voltage samples. The output power for the PCE was obtained by measuring the V_REC,_RMS. The peak input voltage, V_IN,_Peak, can be expressed as the sum of V_REC and V_drop.

Fig. 14 shows the measured and simulated PCE and V_drop versus V_REC with C_L = 10 μF, R_L = 500 Ω, and f_c = 13.56 MHz. All simulated results in this section are postlayout and include the estimated parasitic components of the LQFP176 package (see Fig. 12). Fig. 14(a) shows that for V_REC = 3.12 V, the maximum PCE with both offset-control functions was measured to be 80.2% (curve-b), which was slightly lower than the maximum postlayout simulated PCE of 84.5% (curve-a) and schematic simulated PCE of 87% due to the effects of parasitics and the current sensing resistor. The measured PCE without Offset_F (curve-c) is ~ 10% lower than the PCE with Offset _F. When V_REC was higher or lower than 3.12 V, the PCE gradually decreased because the comparator offsets were only adjusted for V_REC = 3.1–3.2 V. For other V_REC values, the comparator offsets can be easily readjusted using CTL0:3 in Fig. 2.

Fig. 14.

Measured and simulated (a) PCE and (b) V_drop versus V_REC when R_L = 500 Ω, C_L = 10 μF, and f_c = 13.56 MHz.

In Fig. 14(b), the measured V_drop with Offset_F (curve-b) shows 0.7 V dropout, which is 0.4 V higher than the simulated V_drop with Offset_F (curve-a). This is due to the interconnect inductances increasing $V_{\text{IN}1,\text{peak}}^{\ast }$ as explained earlier. For example, $V_{\text{IN}1,\text{peak}}^{\ast }$ was measured ~ 250 mV higher than V_IN1,Peak in Fig. 12 after shorting R_sense. By including these parasitic inductors in our simulations (L_bond + L_wire = 25 nH), we were able to verify the cause of V_drop variations by producing results (curve-d) that were closer to the measured V_drop (curve-b). V_drop is also affected by the output current, I_REC, and PCE. In Fig. 14(b), a higher V_REC with fixed R_L requires higher I_REC through the rectifier, which generates a larger voltage drop across the rectifying transistors, increasing V_drop. Furthermore, a rectifier with lower PCE requires more current from the coil to reach a certain V_REC, which also increases V_drop. Overall, measured and simulated results clearly showed that V_drop is reduced by using both offset-control functions.

Fig. 15(a) shows the measured and simulated PCE versus R_L with C_L = 10 μF, V_REC = 3.12 V, and f_c = 13.56 MHz. As R_L increases, the rectifier output power for the same V_REC decreases. Therefore, the rectifier internal power dissipation for switch losses, P_Loss,total, and comparators, P_comparator, become more significant in (4) and reduce the PCE. The measured and simulated V_drop versus R_L in Fig. 15(b) shows that V_drop decreases by increasing R_L. It is because larger R_L requires smaller I_REC, leading to smaller voltage drop across the rectifying transistors.

Fig. 15.

Measured and simulated (a) PCE and (b) V_drop versus R_L with V_REC = 3.12 V, C_L = 10 μF, and f_c = 13.56 MHz.

Fig. 16(a) shows the measured and simulated PCE versus f_c with C_L = 10 μF, V_REC = 3.12 V, and R_L = 500 Ω. The transistor dimensions and comparator offsets of our rectifier were optimized for operating at 13.56 MHz. Therefore, the PCE decreases at higher frequencies due to the comparator delays. At lower frequencies, the PCE also decreases a little bit since the fixed comparator offset turns off the rectifier earlier. Fig. 16(b) shows the measured and simulated V_drop versus f_c. Even though I_REC is fixed in these experiments, the PCE variation by frequency also affects V_drop. Therefore, lower PCE at higher frequencies leads to higher V_drop.

Fig. 16.

Measured and simulated (a) PCE and (b) V_drop versus f_c with V_REC = 3.12 V, C_L = 10 μF, and R_L = 500 Ω.

C. Back Telemetry Measurements

To demonstrate the built-in back telemetry capability of our active full-wave rectifier, we applied a random stream of serial data bits at 500 kbps and 0.2 μs pulse width (10% duty cycle) to the rectifier short-coil (SC) input terminal (see Fig. 2). A pair of planar spiral coils with d = 4 cm were used similar to the setup described in [26] (see Fig. 1 and Table II). The LSK back telemetry data was recovered using a commercial RFID reader ASIC (TRF7960) from Texas Instruments (Dallas, TX). In Fig. 17, measured waveforms from top show the data signal applied to SC, voltages across the load (R_LC_L = 500 Ω||10 μF), secondary coil (V_IN1), primary coil (V_L1), and recovered serial data bit stream at TRF7960 output, which has ~ 1.2 μs delay with respect to SC. Shorting L₂ with SC = High in Fig. 1 results in a sudden drop in V_IN1 and increased current in L₁, which also increases the voltage across L₁ [9]. Current and voltage variations in L1 are detected by the RFID reader and amplitude shift keying (ASK) demodulated to recover the LSK back telemetry data. It can be seen in Fig. 17 that V_REC remains constant during the LSK operation because of the large C_L(10 μF) and small SC duty cycle (10%).

TABLE II.

Additional Active Rectifier and LDO Specifications

VThN/VThP	0.78 V/0.92 V
Nominal rectifier output power	20 mW
Minimum rectifier input voltage	3.2 V (2.9 V*)
Ripple rejection capacitor (CL)	10μF(ESR=80mΩ)
Output ripple	80 mVpp
Comparator power consumption	135 μW*
Comparator turn-on delay with OffsetF	0.75 ~ 1.5 ns*
Comparator turn-off delay with OffsetR	−0.7 ~ 0.5 ns*
Primary coil diameter/inductance (L1)	16.8 cm/0.88 μH
Secondary coil diameter/inductance (L2)	3.0 cm/0.41 μH
LDO/BGR current consumption	17μA*/7μA*
LDO output/dropout voltage	3V/150mV
Size of rectifying switches (Wp/Lp = Wn/Ln)	2100 μm/0.6 μm
Total area on chip	0.4 mm2

^*From simulation

Fig. 17.

Measured waveforms showing the active rectifier’s built-in LSK back telemetry capability through its short-coil (SC) input terminal (data signal = 500 kbps with 10% duty cycle, R_L = 500 Ω, and C_L = 10 μF). Data was recovered across the primary coil using a commercial RFID reader ASIC (TRF7960, Texas Instruments, Dallas, TX).

D. Overvoltage Protection Measurements

The OVP circuit is activated when V_REC increases above a certain threshold voltage, V_threshold = 4.4 V, which is determined by comparing 0.25 V_REC with a reference voltage, V_REF = 1.1 V, generated by the regulator. The comparator in Fig. 1 connects C_ovp to V_ss to deviate the resonance frequency of L₂C₂ from 13.56 MHz and decrease V_IN1,2 as well as V_REC. Once V_REC is reduced, C_ovp is disconnected and the L₂C₂ can return back to 13.56 MHz, unless V_REC > V_threshold condition is persistent. This closed-loop mechanism regulates V_REC around V_threshold as long as the input voltage is too high without dissipating extra heat within the rectifier. However, the amount of frequency deviation depends on C_ovp value. To cope with larger input voltages, larger C_ovp is required. Fig. 18 shows the measured V_REC versus V_L1 for two C_ovp values. It can be seen that with the frequency deviation resulted from C_ovp = 40 pF, the rectifier can be protected against V_L1 up to ~ 60 V, while C_ovp = 120 pF can protect the rectifier against V_L1 up to ~ 68 V. In practice, V_L1 is often constant and a sudden reduction in d or I_REC activates the OVP circuit.

Fig. 18.

Measured V_REC versus primary coil voltage, V_L1, with overvoltage protection (OVP) circuit in Fig. 1 using C_ovp = 120 pF (curve-a), C_ovp = 40 pF (curve-b), and without overvoltage protection (curve-c) when R_L C_L — 500Ω||10μF.

E. Performance Summary and Comparison

Table I shows the full-wave rectifier benchmarking table, comparing our work with previously reported rectifiers. It can be seen that despite its relatively large feature length process and size, the active rectifier reported here, to the best of our knowledge, provides the highest measured PCE = 80.2% ever reported at 13.56 MHz, thanks to its high speed comparators that are equipped with offset-control functions for both rising and falling edges. With an input peak voltage of 3.8 V, this rectifier can deliver more than 20 mW at V_REC = 3.12 V, which is required for high power IMDs such as the implantable multichannel wireless neural recording and stimulating system that is being developed in our lab [26]. By shortening the connection between L₂ and the rectifier input port when they are both embedded in an IMD and thus reducing the parasitic components shown in Fig. 12, we expect the rectifier PCE to move closer to the simulated level of 87%. Further, migrating to a smaller feature length process is expected to further improve the PCE and bandwidth by lowering the threshold voltages and comparator delays. Table II summarizes some additional specifications of the rectifier and LDO that are not listed in Table I.

TABLE I.

Full-Wave Rectifier Benchmarking

Publication		[28]	2006 [15]	2007 [10]	2008 [16]	2009 [14]	2009 [17]	2009 [18]	This work
Technology		Discrete (1N4148)	0.35 μm CMOS	0.5 μm (Schottky)	0.5 μm CMOS	0.18 μm CMOS	0.18 μm CMOS	0.35 μm CMOS	0.5 μm CMOS
VIN, peak (V)		6	3.5	5	5	0.8	1.25	2.4	3.8
VREC(V)		4.3	3.22	4.2	4.36	1.8	0.96	2.08	3.12
RL (kΩ)		1.3	1.8	2.8	1	270	2	0.1	0.5
fc(MHz)		13.56	13.56	4	0.1~2	13.56	10	0.2~1.5	13.56
Area (mm2)		3.08	0.0055	N/A	0.4	0.83	0.86	0.4	0.18
PCE(%)	Simulation	N/A	87	N/A	90.4	N/A	N/A	87	87
	Measurement	50	N/A	75	84.8	54.9	76	N/A	80.2

V. Conclusions

An integrated power-efficient full-wave active rectifier equipped with offset-controlled high speed comparators has been presented for inductively powered applications, such as RFID and IMD. The main switches in this rectifier are driven by a pair of comparators, which keep them closed precisely when V_IN1,₂ > V_REC, while compensating for both turn-on and turn-off propagation delays of the comparators by a pair of programmable offsets. As a result, the rectifier conducts for the maximum possible period of time and delivers maximum forward current to the load, while minimizing the back current.

In addition, the sizes of the rectifying transistors were optimized for minimizing their R_on and switching losses at the rectifier operating frequency. We have reported the highest measured PCE of 80.2% with 3.12 V dc output across a 500 Ω load from a 3.8 V ac input at 13.56 MHz. The rectifier’s built-in LSK back telemetry capability can be utilized for communication, such as establishing a closed loop wireless power transmission system to adjust the transmitted power for a constant rectifier output voltage [27]. The rectifier has also been equipped with a detuning-based overvoltage protection circuit, which is a necessary safety feature for situations in which the rectifier input signal has grown too large as a result of the coils being too close or the load current being too small.

Biographies

Hyung-Min Lee (S’06) received the B.S. degree in electrical engineering (summa cum laude) from Korea University, Seoul, in 2006, and the M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2008. Since 2009, he has been with the GT-Bionics lab in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, where he is working toward the Ph.D. degree.

His research interests include analog/mixed-signal integrated circuits and power management integrated circuits for biomedical implantable systems.

Mr. Lee has received the Silver Prize in the 16th Human-Tech Thesis Prize from Samsung Electronics, Korea, and the Commendation Award in the 4th Outstanding Student Research Award from TSMC, Taiwan, both in 2010.

Maysam Ghovanloo (S’00–M’04–SM’10) was born in 1973 in Tehran, Iran. He received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1994, the M.S. degree in biomedical engineering from the Amirkabir University of Technology, Tehran,in 1997, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2003 and 2004, respectively.

From 2004 to 2007, he was an Assistant Professor in the Department of Electrical and Computer Engineering at North Carolina State University, Raleigh. He joined the faculty of the Georgia Institute of Technology, Atlanta, in 2007, where he is currently an Assistant Professor and the founding director of the Georgia Tech Bionics Laboratory in the School of Electrical and Computer Engineering. He has authored or coauthored more than 80 conference and journal publications.

Dr. Ghovanloo is an Associate Editor of the IEEE Transactions on Circuits and Systems—Part II: Express Briefs and the IEEE Transactions on Biomedical Circuits and Systems. He has received awards in the 40th and 41st Design Automation Conference (DAC)/International Solid-State Circuits Conference (ISSCC) Student Design Contests. He has organized special sessions and was a member of Technical Review Committees for several major conferences, such as ISSCC and ISCAS, in the areas of biomedical circuits, sensors, and systems. He is a member of the Tau Beta Pi, the Sigma Xi, and the IEEE Solid-State Circuits Society, the IEEE Circuits and Systems Society, and the IEEE Engineering in Medicine and Biology Society.

Appendix

In this section we derive (2) and (4) for PCE analysis using simplified rectifier waveforms, shown in Fig. 19. D is the rectifier switching duty cycle, D_charge is the charging duty cycle, T = 1/2 f_c is the period of the full-wave rectified signal, and T_PHL and T_PLH are the delays in high-to-low and low-to-high transitions of the comparator output (V_OUT), respectively. In this model, we assume: 1) V_IN is sinusoidal, 2) R_L is constant, 3) C_L is large enough to maintain V_REC almost constant despite the rectifier operation, and 4) the rising and falling times of the comparator output are negligible compared to T (or they have been included in T_PHL and T_PLH). The rectifier turns on (i.e., conducts) from T_a to T_d = DT and turns off from T_d to T_e = T – DT. The assumption is that the additional charge that is stored in C_L during DT maintains V_REC constant while the rectifier is supplying R_L for the entire period of T. Therefore,

Fig. 19.

Simplified voltage waveforms of the active rectifier used in the PCE theoretical analysis. To simplify the equations, we have assumed ΔV → 0 V.

$$\begin{array}{l}\underset{T_a}{\overset{T_d}{\int }}{I}_{\text{in}}(t)dt=\underset{T_a}{\overset{T_d}{\int }}\left(\frac{V_{\text{IN}}(t)-V_{\text{REC}}}{R_{\mathit{onp}}+R_{\mathit{onn}}}\right)dt\\ =\underset{T_a}{\overset{T_e}{\int }}\left(\frac{V_{\text{REC}}}{R_L}\right)dt=\frac{V_{\text{REC}}}{R_L}T\end{array}$$ (5)

where T_a = (T–DT + T_PHL + Tp_LH)/2, T_d = (T + DT + T_PHL + T_PLH) 2, and T_e = (3T – DT + T_PHL + T_PLH)/2 are indicated on Fig. 19. The sinusoidal input voltage, V_IN, can be expressed as

$$\begin{array}{l}{V}_{\text{IN}}(t)=V_{\text{IN},\text{peak}}sin\left(\frac{\pi }{T}t\right)\\ =\frac{V_{\text{REC}}}{sin\left((T_a-T_{\mathit{PHL}})\frac{\pi }{T}\right)}sin\left(\frac{\pi }{T}t\right).\end{array}$$ (6)

Using (6) in (5), R_onp + R_onn can be expressed as a function of D

$$R_{\mathit{onp}}+R_{\mathit{onn}}=R_L\left(\frac{\frac{1}{\pi }\left(cos(T_a\frac{\pi }{T})-cos(T_d\frac{\pi }{T})\right)}{sin\left((T_a-T_{\mathit{PHL}})\frac{\pi }{T}\right)}-D\right).$$ (7)

If T_PLH = 0,. D_charge would be the same as D because the rectifier only supplies R_LC_L during its conducting period. However, with T_PLH > 0, the back current can discharge C_L when V_REC > |V_IN|. In Fig. 19, the back current from T_c to T_d(D₂T) discharges C_L as much as the forward current from T_b to T_c(D₁T) charges C_L. Therefore,. D_charge can be derived as a function of D by obtaining T_b

$$\{\begin{array}{ll}{I}_{\text{in}}=I_{C_L,\text{charge}}+I_{R_L}\hfill & T_b<t<T_c\hfill \\ I_{\text{in}}=I_{C_L,\text{discharge}}+I_{R_L}\hfill & T_c<t<T_d\hfill \end{array}$$ (8)

$$\underset{T_b}{\overset{T_c}{\int }}{I}_{C_L,\text{charge}}(t)dt+\underset{T_c}{\overset{T_d}{\int }}{I}_{C_L,\text{discharge}}(t)dt=\underset{T_b}{\overset{T_d}{\int }}\left(\frac{V_{\text{IN}}(t)-V_{\text{REC}}}{R_{\mathit{onp}}+R_{\mathit{onn}}}-\frac{V_{\text{REC}}}{R_L}\right)dt=0.$$ (9)

By solving (5)–(9) for T_b using MATLAB, -D_charge can be expressed as

$$D_{\text{charge}}=D-\left(\frac{T_d-T_b}{T}\right).$$ (10)

Note that even though the input current from T_b to T_d does not affect V_REC, -R_on power losses still occur during this period (D₁T + D₂T). Therefore, the R_on loss term with D_cff in (2) can be represented as

$$\begin{array}{l}{P}_{\text{Loss},R_{\mathit{onp}}}+P_{\text{Loss},R_{\mathit{onn}}}={\left(\frac{V_{\text{REC}}}{R_L{D}_{\text{eff}}}\right)}^2{D}_{\text{eff}}(R_{\mathit{onp}}+R_{\mathit{onn}})\\ =\left({\left(\frac{V_{\text{REC}}}{R_L{D}_{\text{charge}}}\right)}^2{D}_{\text{charge}}+{\left(\frac{1}{D_{1}T}\underset{T_b}{\overset{T_c}{\int }}{I}_{\text{in}}(t)dt\right)}^2{D}_1+{\left(\frac{1}{D_{2}T}\underset{T_c}{\overset{T_d}{\int }}{I}_{\text{in}}(t)dt\right)}^2{D}_2\right)(R_{\mathit{onp}}+R_{\mathit{onn}})\end{array}$$ (11)

where the first, second, and third terms of the right-hand side equation correspond to the R_on loss during D_chargeT, D₁T, and D₂T, respectively. If T_PLH = 0, the second and third terms will be eliminated because T_b = T_c = T_d. Therefore, using (5)–(11), the R_on loss in (2) can be expressed as a function of D.

R_onp + R_onn can also be represented as a function of W_p = W_n

$$R_{\mathit{onp}}+R_{\mathit{onn}}=\frac{1}{W_p}\left(\frac{L_{min}}{k_p(V_{\text{REC}}-\mid V_{\mathit{ThP}}\mid )}+\frac{L_{min}}{k_n(V_{\text{REC}}-V_{\mathit{ThN}})}\right)$$ (12)

where L_min is the length of the PMOS and NMOS transistors. By substituting W_p with (12), the switching loss term, P_Loss,Cgp, in (2) can be expressed as a function of D

$$P_{\text{Loss},C_{gp}}=W_p{C}_{gp}^{\ast }{V}_{\text{REC}}^{2}2f_c=C_{gp}^{\ast }{V}_{\text{REC}}^{2}2f_c\times \frac{1}{R_{\mathit{onp}}+R_{\mathit{onn}}}\times \left(\frac{L_{min}}{k_p(V_{\text{REC}}-\mid V_{\mathit{ThP}}\mid )}+\frac{L_{min}}{k_n(V_{\text{REC}}-V_{\mathit{ThN}})}\right).$$ (13)

Therefore, by substituting (11) and (13) in (2) and differentiating it with respect to D, we can obtain the optimized D for minimum power loss inside the rectifier. Using the optimal D, the optimal W_p can be derived from (7) and (12), and the maximum PCE can be calculated from (4) by minimizing the power loss in (2).