Abstract
VIP-PIX will be a low noise and low power pixel readout electronics with digital output for pixelated Cadmium Telluride (CdTe) detectors. The proposed pixel will be part of a 2D pixel-array detector for various types of nuclear medicine imaging devices such as positron-emission tomography (PET) scanners, Compton gamma cameras, and positron-emission mammography (PEM) scanners. Each pixel will include a SAR ADC that provides the energy deposited with 10-bit resolution. Simultaneously, the self-triggered pixel which will be connected to a global time-to-digital converter (TDC) with 1 ns resolution will provide the event’s time stamp. The analog part of the readout chain and the ADC have been fabricated with TSMC 0.25 μm mixed-signal CMOS technology and characterized with an external test pulse. The power consumption of these parts is 200 μW from a 2.5 V supply. It offers 4 switchable gains from ±10 mV/fC to ±40 mV/fC and an input charge dynamic range of up to ±70 fC for the minimum gain for both polarities. Based on noise measurements, the expected equivalent noise charge (ENC) is 65 e− RMS at room temperature.
Keywords: Analog-digital conversion, application specific integrated circuits, energy resolution, gamma-ray detectors, low-power electronics, positron emission tomography, semiconductor radiation detectors
I. INTRODUCTION
High performance pixelated CdTe detectors are commonly used in X-ray and Gamma-ray imaging devices because CdTe is a high Z material that makes them excellent absorbers for the high energy range X-ray photons. Moreover, they can be used at room temperature due to CdTe large ionization gap of 4.6 eV. Since detectors are fabricated with millimeter thickness, the equivalent detector capacitance per channel is of the order of few tens of femto Farads for a millimeter size pixel pad when connected to the front-end electronics by bump bonding technology. This low capacitance feature makes CdTe detectors very attractive for low noise and very low power front-end applications [1], [2]. Besides, low volume detectors enable very high integration and compactness which is of crucial importance for head-size PET scanners as described in [3]. In such stacked systems, the volume of the readout ASICs and the interconnection board should be minimized to avoid unwanted passive material form traps for the gamma photons.
For the head-size PET scanner based on the VIP design [3], the number of channels is of the order of 6 million considering a voxel size of 1 mm×1 mm×2 mm. Such high density of channels/mm3 imposes a limitation on power consumption of 200 μW/channel to keep the cooling system of the PET scanner manageable.
Most of the readout application specific integrated circuits (ASICs) for pixelated CdTe or CdZnTe detectors that have been reported in the literature are based on multiplexing the analog output of every pixel cell into the ASIC output bus or into a common analog to digital converter (ADC) for later digital readout [4]–[6]. VIP-PIX provides a “smart pixel” solution where each pixel front-end electronics includes a 10-bit ADC and outputs a fast trigger signal for time stamp registration. The VIP-PIX ASIC will have an array of 10 by 10 smart-pixels readout for the next generation PET scanner and Compton gamma camera.
II. Voxel Imaging PET Pathfinder Project (VIP)
The proposed VIP readout integrated circuit is specifically designed for the PET scanner based on pixelated CdTe detectors described in [3]. Fig. 1 shows the different parts of the PET scanner designed for human-head size. The PET ring has an inner diameter of 40 centimeters and an outer of around 60 centimeters. From the center of the scanner, the radial thickness of the ring is composed by 4 cm of pixelated Cadmium Telluride material with total 1 cm of air gaps followed by 5 centimeters with passive components and extra electronics. The equivalent 4 cm-thick CdTe detector offers 85% absorption for 511 keV gamma photons, or 70% efficiency for a PET event.
Fig. 1.
Description of the components of the PET design presented in [3].
PET scanners as the proposed in the VIP pathfinder project offer spatial resolution of the order of 1 mm for human-head size, energy resolution of the order of 1% full width half maximum (FWHM) at 511 keV, sensitivity up to 21 cps/kBq, and timing resolution of the order of few nanoseconds.
The dimensions of all the CdTe detectors to be used in the first rectangular prototype of the VIP detector module are 10 mm×10 mm×2 mm. They are pixelated into a 10 by 10 pixel array with uniform voxels size of 1 mm×1 mm×2 mm. To have a good time and energy resolution, a high biasing voltage of 1000 V/mm is necessary to overcome the effects of the limited mobility of electrons and holes in 2 mm-thick detector. Such a high DC bias induces a leakage current per pixel of the order of 250 pA at room temperature [7]. The drift time for electrons and holes at 1000 V/mm for 2 mm thickness CdTe detector is 18 ns and 200 ns respectively. The expected capacitance per pixel is about 80 fF after the high voltage is applied and the Schottky diode is reversed biased and the semiconductor is totally depleted. The VIP-PIX ASIC can be used with CdZnTe and Si detectors as long as the input capacitance per pixel matches the specification. Given that VIP-PIX will operate with both polarities, it can be used with CdTe ohmic and schottky electrodes. For Si detectors, we expect the VIP-PIX response to be better than with Cd(Zn)Te detectors given that electrons and holes in Si have similar mobility.
The energy acceptance window of the proposed PET scanner is set to 511 keV ±6 keV based on an energy resolution of 1% FWHM at 511 keV of the pixelated detector [8]. According to this, an energy resolution of the electronics of 0.1% RMS for full range is required. Therefore, an analog to digital converter (ADC) with a minimum of 10 bit resolution is necessary.
Table I summarizes the specifications of the pixelated CdTe detector and the readout integrated circuit.
TABLE I.
Specifications of CDTE Detector and Pixel Electronics
| Specification | Value |
|---|---|
| Detector size | 10 mm ×lO mm × 2 mm |
| Voxel size | 1 mm × 1 mm × 2 mm |
| Detector DC bias voltage | 2000 V |
| Detector leakage current | 250 pA/pixel |
| Electron/Hole drift time | 18 ns/200ns |
| Pixel capacitance | 80 fF |
| Energy resolution of pixel electronics | 10 bits for 511 keV |
| Maximum Jitter of time stamp | 10 ns |
| Maximum power consumption | 200 μW/pixel |
III. Readout Electronics Architecture OF THE Planned VIP-PIX
A. Readout ASIC Architecture
The architecture of the ROIC for the VIP project is shown in Fig. 2. Note that the ASIC is divided into two main regions. The first region is a 2D array of independent pixel electronics of 10 by 10 pixels where the pixelated CdTe detector will be connected via bump-bonding. The second region is where the back-end of the ASIC is located. The total area of the chip is 10 mm×12 mm where 2 mm×10 mm are occupied by the back-end circuitry.
Fig. 2.
Architecture of the proposed readout integrated circuit for the pixelated CdTe detectors of the VIP project.
The ASIC back-end contains a temperature and supply voltage compensated current reference. In addition, it has three 6-bit digital to analog converters (DAC), a digital output temperature sensor, and a time to digital converter (TDC). To indentify each chip, we have implemented a customized chip ID based on salicide agglomeration of poly [9]. A digital controller is also part of the back-end and its role is to send the control signals to the pixels according to the active operation mode, and to communicate with the digital controller in the PCB to transmit and receive the acquired data and the configuration data respectively.
Note that the supply lines going to the pixel array are separated into digital bus, mixed-signal bus and analog bus. Digital lines are placed in the odd rows while the analog bus is located in the even rows.
B. Readout Pixel Architecture
Fig. 3 shows the architecture of the pixel electronics. The pixel is divided into three regions according to the position of the supply lines mentioned last section. In the particular case of pixels in odd rows, (e.g., 1, 3, 5, 7, and 9), the analog front-end electronics is placed at the top. The mixed-signal circuits such as the ADC and the DACs are placed at the center, and the digital circuits, (e.g., digital controller, and configuration registers) at the bottom of the pixel. For the pixels located at the complementary rows, the placement is flipped horizontally in such a way that the analog front-end is at the bottom and the digital circuitry at the top.
Fig. 3.
Architecture of the proposed pixel readout electronics.
The analog front-end is composed by a charge sensitive amplifier with constant current feedback resistor, a CR-RC shaper connected to a peak and hold circuit, and a discriminator connected to the pre-amplifier. A detailed schematic of the analog front-end is shown in Fig. 4. The output of the peak and hold circuit is connected to the 10-bit analog to digital converter and the digital output is stored in a first-input first-output (FIFO) memory.
Fig. 4.
Architecture of the proposed pixel readout electronics.
The control of every active resistor in the front-end is connected to a current-based DAC. The pre-amplifier discharging rate, the peak time of the shaper and the fine control of the discriminator threshold are adjustable so an online equalization of the response of every pixel can be applied.
Every operational amplifier is implemented using differential folded-cascoded architecture to provide reasonable dynamic range for both detector bias polarities and improved power supply rejection ratio (PSRR). Every integrating stage, (i.e., charge sensitive amplifier, CR-RC shaper, and peak-and -hold circuit) includes a minimum charge-injection reset circuit to provide fast baseline restoration after the value of the peak-and-hold circuit has been digitized by the ADC. During normal operation, the clock of every ADC is off and is only activated when the pixel is selected for digitalization by the ASIC back-end controller.
As shown in Fig. 4, the feedback capacitor and the test pulse capacitor are switchable. Although PET applications require a full dynamic range of the order of 511 keV, the gain of the pre-amplifier can be selected for higher energies. Also, the capacitors of the CR-RC shaper can be switched within two values to set the proper range of peak time for different applications and detectors.
The operational amplifier of the pre-amplifier uses a PMOS input differential pair to lower the flicker noise contribution. The input transistor has a width of 100 μm with a length of 350 nm, and draws 5 μA. The open loop gain and bandwidth of the amplifier are designed to be higher than 65 dB and 20 MHz respectively in any condition.
The discriminator is based on two stages NMOS-input folded cascoded architecture. To provide fine tuning of the threshold, a fully differential 6-bits plus polarity-bit current DAC controls the current consumption of the second stage. This solution provides DC control without extra parasitic that would increase the delay and the jitter of the discriminator.
The analog front-end works for both detector bias polarities in such a way that the proper reference voltage (e.g., REF_HIGH or REF_LOW) is applied to the positive input of the operational amplifier of every stage. For positive polarity, we expect a negative pulse at the output of the preamplifier so the reference voltage is set to REF_HIGH, and a positive pulse is expected at the output of the shaper so REF_LOW is connected to the reference terminal. For negative polarity, the reference values are inverted and the output of the shaper is connected to a polarity inverter such that the output pulse of the peak-and-hold circuit is always positive and the output DC signal always falls between REF_LOW and REF_HIGH.
The analog to digital converter is based on a successive approximation register (SAR) architecture. Fig. 5 shows the design circuit and the digital to analog converter cell of the ADC. Note that the four most significant bits are implemented using a capacitor array with C equal to 64 fF and the six least significant bits by a resistor DAC with resistors of 2.3 kΩ . This scheme improves dramatically the linearity of the ADC and offers smaller loading to the peak-and-hold circuit compared to a design entirely based on a capacitor array [10].
Fig. 5.
Architecture of the decision cell and DACs of the proposed ADC.
C. Calibration Procedure
The performance of every pixel will vary with the leakage current of the CdTe detector once the ASIC is connected via bump-bonding to the detector. Therefore, the biasing conditions of the pre-amplifier should be optimized prior to normal operation. The leakage current compensation is based on a current-controlled active resistor. The optimization condition for such control current is that for a full-range input pulse, the base-line restoring time of the pre-amplifier should be much larger than the peak time of the shaper (i.e., 100 us for nominal operating conditions). To find such optimum value of the feedback resistor we use the internal test pulse, the discriminator and the DAC of the global threshold to measure the time over threshold (TOT) iteratively. Once the feedback resistor is tuned properly, we characterize and store the data from the energy path and the discriminator delay and jitter versus a set of different amplitudes of internal test pulse. After the linearity and time response are obtained versus relative amplitudes of injected pulses, the ASIC-Detector module can be calibrated with a set of radioactive sources such the absolute gain of the front-ends will be obtained and the ASIC is ready for data acquisition with off-line calibration.
IV. Experimental Results
The analog front-end and the ADC which are parts of the pixel electronics have been designed and fabricated as two independent ASICs in order to perform separated measurements and check individual functionality. Simulations have been performed with CADENCE Spectre simulator. The microphotography of the analog front-end ASIC is shown in Fig. 6. The ASICs are fabricated with TSMC 0.25 μm CMOS with mixedsignal devices such as metal-insulator-metal (MIM) capacitors. With the exception of the detector input pad, all the I/O pads are HBM-complaint ESD protected.
Fig. 6.
Microphotography of the fabricated analog-front end ASIC.
A. Analog Front-End Characterization
The readout ICs work with a single supply of 2.5 V. The analog-front end has been characterized with pulses coming from an external waveform generator. The value of the test pulse on-chip capacitor was chosen to match the value of the feedback capacitor so that the output voltage of the preamplifier would match the input voltage step. The functionality of the analog front-end is demonstrated in Figs. 7 and 8. Fig. 7 shows the output waveforms of the shaper and the discriminator and Fig. 8 depicts the output waveform of the peak-and-hold circuit to show the discharging rate during the holding state. We can observe that the baseline of the shaper is restored smoothly without undershot after 25 μs. The output of the peak and hold circuit shows a discharging rate of 800 mV in 5 seconds (i.e., 160μV per millisecond). Such a low leakage ensures more than 10 bits resolution if we digitize the output voltage of the peak and hold circuit even after 1 millisecond from the shaper peak time.
Fig. 7.
Measured output waveforms of the shaper (Ch2) and the discriminator (Ch4) with the waveform of the injected test pulse (Ch3).
Fig. 8.
Measured output waveform of the peak and hold circuit (solid line) with the waveform of the injected test pulse (dashed line).
The time response of the front-end has been characterized using 50 test pulses per point with 35 ns rise/fall time to mimic the drift time of the electrons inside the detector biased at 500 V/mm. Fig. 9 shows the mean values of the absolute delay of the discriminator from the test pulse 50% value crossing time (i.e., 17.5 ns from time zero). The threshold voltage was placed at 8 mV from the baseline of the pre-amplifier (i.e., 6 keV at 1.4 mV/keV gain). The dependency of the time response of the front-end with the amplitude of the pulse is due to two main delays: the first delay is the intrinsic time-walk of the output pulse of the pre-amplifier (i.e., for a given collection time, dV/dt of the output pulse depends on the amplitude of the injected charge). The second and major delay is due to the limited gain and bandwidth of the discriminator for pulses with peak amplitude above but very close to the threshold. Note that by increasing the power budget of the discriminator the absolute delay of the front-end will decrease in the low energy region of Fig. 9. The front-end time response will be characterized and calibrated off line since the value of the energy will be obtained with 10-bit resolution from the energy path of the analog front-end (i.e., preamplifier + shaper + peak and hold circuit + ADC).
Fig. 9.
Measured delay of the discriminator output versus injected test pulse amplitude.
Although the absolute value of the discriminator delay can be corrected, the jitter becomes the limiting factor on the time resolution of the system. Note that the jitter of the discriminator is mainly due to the amount of noise at the input of the discriminator and the dV/dt of the output pulse of the pre-amplifier such as that we expect higher jitter for low energies since the slope of the pulse is smaller than for high energies. Fig. 10 shows the measured jitter time of the discriminator extracted from the Gaussian fit for 50 test pulses per point measurement. Note that events with an energy deposition higher than 20 keV fulfill the requirement of 10 ns. As we can observe, for pulses with amplitude larger than 40% of full scale, the jitter remains below 1 ns.
Fig. 10.
Measured discriminator jitter versus injected test pulse amplitude.
B. ADC Characterization
The 10-bit ADC ASIC has been tested using an input voltage ramp with steps of 250 μV generated by a 16-bit external DAC with adjustable full range. The conversion clock frequency used for all measurements was 1 MHz and the conversion range was 900 mV centered at 1.25 V. A DC offset of +8 mV and a gain error of 30 ppm were measured. After DC offset correction, the linearity of the ADC was analyzed. The differential non-linearity (DNL) and the integral non-linearity (INL) of the SAR ADC are shown in Fig. 11. The behavior of the ADC is linear within a standard deviation of 0.2 LSB. In particular, the distribution of the DNL is centered at 0 with a standard deviation of 0.2 LSB, and the distribution of the INL has a mean of 0.09 LSB with a standard deviation of 0.16 LSB.
Fig. 11.
Measured Integral Non-Linearity and Differential Non-Linearity of the 10-bit ADC.
C. Analog Front-End Plus ADC Characterization
The output of the analog front-end ASIC, (i.e., the output of the peak and hold circuit) has been connected to the input of the ADC ASIC on the PCB to characterize the electronics of the full energy path. With 1000 test pulses per measurement, the linearity and the output noise have been measured for nominal operating conditions such as 40 mV/fC (or 1.4 mV/keV) gain of the preamplifier, 100 μs baseline restore time of the preamplifier, 10 μs shaper peak time, 1 MHz ADC conversion clock frequency, and 900 mV ADC conversion range.
Fig. 12 shows the mean values of the linearity curve of the complete energy path and a normalized measured output voltage versus expected voltage as a function of the amplitude of the injected test pulse for positive polarity and negative polarity. As expected from simulations, the linearity curve shows non-linear behavior due to the optimization of the MOS resistors used in the shaper. By using n-well based resistors instead of active MOS transistors the response of the front-end is linear in all range. Nevertheless, due to their small resistivity, the values of the shaper capacitors are of the order of 10 pF. Such a large capacitor decreases the bandwidth of the preamplifier and makes the use of n-well resistors not suitable for low consumption.
Fig. 12.
Measured linearity curve of the analog front-end connected to the ADC on the PCB.
The non-linear gain observed in Fig. 12 reduces the resolution at low energy range but since every pixel is characterized and calibrated off-line, practically it does not affect the overall performance of the complete front-end.
Fig. 13 shows the value of the standard deviation, considering Gaussian distribution, of the 1000 measurements for every mean value of Fig. 12. The RMS output noise of the pixel readout electronics extracted from Fig. 13 is of the order of 0.7 ADC counts for positive polarity and 0.8 ADC counts for negative one. Considering a 40 mV/fC gain, the equivalent noise charge (ENC) at the input of the preamplifier is 98 e− RMS for positive polarity and 107 e− RMS for negative polarity.
Fig. 13.
Sigma of the measured energy from Fig. 12 obtained with 1000 points fit per test pulse step.
Fig. 14 shows the measured ENC and the simulated noise performance of the front-end as a function of the detector capacitance at room temperature. The front-end was simulated including all loading IOs such as stray capacitances, ESD diodes, and package parasitic. The extracted capacitance at the input transistor was 600 fF. Such a high value was due to loading of the bonding pad since all I/O pads are realized by stacking all metal layers plus polysilicon layer. The case of connecting the front-end to the detector via bump-bonding, (i.e., avoiding current extra capacitance and couplings and just having 80 fF as detector capacitance) was also simulated. Circles and stars correspond to the measuring conditions and squares and triangles to the case of direct connection to the CdTe detector via bump-bonding.
Fig. 14.
Simulated and measured noise performance of the front-end electronics.
The discrepancy from measured noise and simulated one at minimum detector capacitance is lower than 5%. Considering positive and negative polarities, the calculation of chi square results in just 0.133. Therefore, as can be observed from Fig. 14, we can expect an ENC of 65 e− RMS for positive polarity when the front-end is connected directly to the detector minimizing the parasitic capacitances from the actual testing ASIC.
Table II summarizes the measured performance of the analog front-end and the ADC of the pixel electronics.
TABLE II.
Measured Performance of the Analog Front-End Plus ADC
| Input charge dynamic range | +/− 17 fC to +/− 70 fC |
| Gain for both polarities | 10, 16, 20, and 40 mV/fC |
| Shaper peak time | 4 to 16 μs |
| Peak-and-hold circuit discharge rate | 160 μV/ms |
| Detector leakage compensation | up to 10 nA per pixel |
| Minimum threshold | 6 keV |
| ENC @ 40 mV/fC (Pos/Neg Polarity) | 98 e− RMS /107 e− RMS |
| Discriminator j itter | < 10 ns for E > 20 keV |
| Supply Voltage | 2.5 V |
| Preamplifier/Shaper | 75 μW/20 μW |
| Peak and hold/Discriminator | 20 μW/35 μW |
| ADC/Total Power consumption | 50 μW/200 μW |
| ADC conversion clock frequency | 1 MHz |
| Analog front-end area | 300 μm × 400 μm |
| ADC area | 400 μm × 400 μm |
V. Conclusion
We presented the architecture of a readout integrated circuit based on an array of 100 independent and smart pixels as a solution for high density voxel imaging systems such as next generation PET scanners or Compton gamma cameras based on pixelated CdTe detector challenge designers to optimize gamma-ray detector’s front-end electronics in terms of noise and time response. We introduced the architecture of the pixel electronics and we fabricated and characterized the two main blocks of the pixel: the analog front-end and the analog to digital converter. We tested the performance of both chips individually and together using charge injection through an on-chip test pulse capacitor.
Results show promising noise and timing performance with power consumption of 200 μW/channel. The measured noise of the energy path is 98 e− RMS for positive polarity and 107 e− RMS for negative polarity and the jitter of the discriminator is below 10 ns for energies above 20 keV. Once the pixel is integrated into a full 10×10 pixel ASIC and is connected to the CdTe detector via bump-bonding technique, we expect lower noise in the measurement of the energy and also lower discriminator jitter since both are dominated by the noise of the preamplifier.
The results represent the first successful steps towards the full integration of the 100 pixels ROIC for the VIP pathfinder project and pixelated CdTe detectors for PET applications.
Acknowledgment
The authors would like to thank Thomas Moore for realizing the layout of most of the VIP-PIX readout integrated circuit.
Footnotes
The Voxel Imaging PET pathfinder project is supported by the European 7th Framework Program ERC Advanced Grant 250207.
Contributor Information
Jose-Gabriel Macias-Montero, Institut de Fisica d’Altes Energies (IFAE), Barcelona E-08193, Spain (jgmacias@ifae.es).
Maher Sarraj, Texas Instruments Incorporated, Dallas, TX 75266 USA (m-sarraj1@ti.com).
Mokhtar Chmeissani, Institut de Fisica d’Altes Energies (IFAE), Barcelona E-08193, Spain (mokhtar@ifae.es).
Carles Puigdengoles, Institut de Fisica d’Altes Energies (IFAE), Barcelona E-08193, Spain (cpuig@ifae.es).
Gianluca De Lorenzo, Institut de Fisica d’Altes Energies (IFAE), Barcelona E-08193, Spain (gdl@ifae.es).
Ricardo Martínez, Instituto de Microelectronica de Barcelona (IMB-CNM), Barcelona E-08193, Spain (ricardo.martinez@imb-cnm.csic.es).
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